Texas Instruments TMS320F28016PZS, TMS320F2809 Datasheet

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

Data Manual

Literature Number: SPRS230I

October 2003 – Revised May 2007

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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Contents

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

Revision History ........................................................................................................................... 9

1 F280x, F2801x, C280x DSPs ................................................................................................. 11

1.1 Features ..................................................................................................................... 11

1.2 Getting Started .............................................................................................................. 12

2 Introduction ....................................................................................................................... 13

2.1 Pin Assignments ............................................................................................................ 15

2.2 Signal Descriptions ......................................................................................................... 21

3 Functional Overview ........................................................................................................... 27

3.1 Memory Maps ............................................................................................................... 28

3.2 Brief Descriptions ........................................................................................................... 36

3.2.1 C28x CPU ....................................................................................................... 36

3.2.2 Memory Bus (Harvard Bus Architecture) .................................................................... 36

3.2.3 Peripheral Bus .................................................................................................. 36

3.2.4 Real-Time JTAG and Analysis ................................................................................ 36

3.2.5 Flash .............................................................................................................. 37

3.2.6 ROM ............................................................................................................... 37

3.2.7 M0, M1 SARAMs ............................................................................................... 37

3.2.8 L0, L1, H0 SARAMs ............................................................................................ 37

3.2.9 Boot ROM ........................................................................................................ 37

3.2.10 Security .......................................................................................................... 39

3.2.11 Peripheral Interrupt Expansion (PIE) Block .................................................................. 40

3.2.12 External Interrupts (XINT1, XINT2, XNMI) ................................................................... 40

3.2.13 Oscillator and PLL .............................................................................................. 40

3.2.14 Watchdog ........................................................................................................ 40

3.2.15 Peripheral Clocking ............................................................................................. 40

3.2.16 Low-Power Modes .............................................................................................. 40

3.2.17 Peripheral Frames 0, 1, 2 (PFn) .............................................................................. 41

3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 41

3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 41

3.2.20 Control Peripherals ............................................................................................. 41

3.2.21 Serial Port Peripherals ......................................................................................... 42

3.3 Register Map ................................................................................................................ 42

3.4 Device Emulation Registers ............................................................................................... 44

3.5 Interrupts .................................................................................................................... 45

3.5.1 External Interrupts .............................................................................................. 47

3.6 System Control ............................................................................................................. 48

3.6.1 OSC and PLL Block ............................................................................................ 49

3.6.2 Watchdog Block ................................................................................................. 52

3.7 Low-Power Modes Block .................................................................................................. 53

4 Peripherals ........................................................................................................................ 54

4.1 32-Bit CPU-Timers 0/1/2 .................................................................................................. 54

4.2 Enhanced PWM Modules (ePWM1/2/3/4/5/6) .......................................................................... 56

4.3 Hi-Resolution PWM (HRPWM) ........................................................................................... 58

4.4 Enhanced CAP Modules (eCAP1/2/3/4) ................................................................................ 59

4.5 Enhanced QEP Modules (eQEP1/2) ..................................................................................... 61

4.6 Enhanced Analog-to-Digital Converter (ADC) Module ................................................................ 63

4.6.1 ADC Connections if the ADC Is Not Used ................................................................... 66

4.6.2 ADC Registers ................................................................................................... 67

4.7 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) ..................................... 68

4.8 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B) .................................................... 73

Contents 2 Submit Documentation Feedback

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

4.9 Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D) ........................................... 76

4.10 Inter-Integrated Circuit (I

2

C) ............................................................................................... 80

4.11 GPIO MUX .................................................................................................................. 82

5 Device Support .................................................................................................................. 86

5.1 Device and Development Support Tool Nomenclature ................................................................ 86

5.2 Documentation Support ................................................................................................... 88

6 Electrical Specifications ...................................................................................................... 91

6.1 Absolute Maximum Ratings ............................................................................................... 91

6.2 Recommended Operating Conditions ................................................................................... 92

6.3 Electrical Characteristics ................................................................................................. 92

6.4 Current Consumption ..................................................................................................... 93

6.4.1 Reducing Current Consumption .............................................................................. 97

6.4.2 Current Consumption Graphs .................................................................................. 98

6.5 Emulator Connection Without Signal Buffering for the DSP .......................................................... 99

6.6 Timing Parameter Symbology ........................................................................................... 100

6.6.1 General Notes on Timing Parameters ....................................................................... 100

6.6.2 Test Load Circuit .............................................................................................. 101

6.6.3 Device Clock Table ........................................................................................... 101

6.7 Clock Requirements and Characteristics ............................................................................. 103

6.8 Power Sequencing ........................................................................................................ 104

6.8.1 Power Management and Supervisory Circuit Solutions ................................................... 104

6.9 General-Purpose Input/Output (GPIO) ................................................................................. 107

6.9.1 GPIO - Output Timing ......................................................................................... 107

6.9.2 GPIO - Input Timing ........................................................................................... 108

6.9.3 Sampling Window Width for Input Signals .................................................................. 109

6.9.4 Low-Power Mode Wakeup Timing ........................................................................... 110

6.10 Enhanced Control Peripherals .......................................................................................... 113

6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing ........................................................ 113

6.10.2 Trip-Zone Input Timing ........................................................................................ 113

6.10.3 External Interrupt Timing ...................................................................................... 115

6.10.4 I

2

C Electrical Specification and Timing ...................................................................... 116

6.10.5 Serial Peripheral Interface (SPI) Master Mode Timing .................................................... 116

6.10.6 SPI Slave Mode Timing ....................................................................................... 120

6.10.7 On-Chip Analog-to-Digital Converter ........................................................................ 123

6.11 Detailed Descriptions .................................................................................................... 128

6.12 Flash Timing ............................................................................................................... 129

6.13 ROM Timing (C280x only) ............................................................................................... 130

7 Migrating From F280x Devices to C280x Devices .................................................................. 131

7.1 Migration Issues ........................................................................................................... 131

8 Mechanical Data ............................................................................................................... 132

Contents 3

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

List of Figures

2-1 TMS320F2809, TMS320F2808 100-Pin PZ LQFP (Top View) ............................................................. 16

2-2 TMS320F2806 100-Pin PZ LQFP (Top View) ................................................................................. 17

2-3 TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP

(Top View) ......................................................................................................................... 18

2-4 TMS320F2801x 100-Pin PZ LQFP

(Top View) ......................................................................................................................... 19

2-5 TMS320F2809, TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801,

TMS320C2802, TMS320C2801 100-Ball GGM and ZGM MicroStar BGA™ (Bottom View) ........................... 20

3-1 Functional Block Diagram ........................................................................................................ 27

3-2 F2809 Memory Map .............................................................................................................. 28

3-3 F2808 Memory Map .............................................................................................................. 29

3-4 F2806 Memory Map .............................................................................................................. 30

3-5 F2802, C2802 Memory Map ..................................................................................................... 31

3-6 F2801, F28015, F28016, C2801 Memory Map ............................................................................... 32

3-7 External and PIE Interrupt Sources ............................................................................................. 45

3-8 Multiplexing of Interrupts Using the PIE Block ................................................................................ 46

3-9 Clock and Reset Domains ....................................................................................................... 48

3-10 OSC and PLL Block Diagram ................................................................................................... 49

3-11 Using a 3.3-V External Oscillator ............................................................................................... 49

3-12 Using a 1.8-V External Oscillator ............................................................................................... 50

3-13 Using the Internal Oscillator ..................................................................................................... 50

3-14 Watchdog Module ................................................................................................................. 52

4-1 CPU-Timers ........................................................................................................................ 54

4-2 CPU-Timer Interrupt Signals and Output Signal .............................................................................. 55

4-3 Multiple PWM Modules in a 280x System ..................................................................................... 56

4-4 ePWM Sub-Modules Showing Critical Internal Signal Interconnections ................................................... 58

4-5 eCAP Functional Block Diagram ................................................................................................ 59

4-6 eQEP Functional Block Diagram ................................................................................................ 61

4-7 Block Diagram of the ADC Module ............................................................................................. 64

4-8 ADC Pin Connections With Internal Reference ............................................................................... 65

4-9 ADC Pin Connections With External Reference .............................................................................. 66

4-10 eCAN Block Diagram and Interface Circuit .................................................................................... 69

4-11 eCAN-A Memory Map ............................................................................................................ 70

4-12 eCAN-B Memory Map ............................................................................................................ 71

4-13 Serial Communications Interface (SCI) Module Block Diagram ............................................................ 75

4-14 SPI Module Block Diagram (Slave Mode) ..................................................................................... 79

4-15 I

2

C Peripheral Module Interfaces ............................................................................................... 81

4-16 GPIO MUX Block Diagram ....................................................................................................... 82

4-17 Qualification Using Sampling Window .......................................................................................... 85

5-1 Example of TMS320x280x Device Nomenclature ............................................................................ 87

6-1 Typical Operational Current Versus Frequency (F2808) .................................................................... 98

List of Figures4 Submit Documentation Feedback

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

6-2 Typical Operational Power Versus Frequency (F2808) ...................................................................... 98

6-3 Emulator Connection Without Signal Buffering for the DSP ................................................................. 99

6-4 3.3-V Test Load Circuit ......................................................................................................... 101

6-5 Clock Timing ..................................................................................................................... 104

6-6 Power-on Reset .................................................................................................................. 105

6-7 Warm Reset ...................................................................................................................... 106

6-8 Example of Effect of Writing Into PLLCR Register .......................................................................... 107

6-9 General-Purpose Output Timing ............................................................................................... 107

6-10 Sampling Mode .................................................................................................................. 108

6-11 General-Purpose Input Timing ................................................................................................. 109

6-12 IDLE Entry and Exit Timing .................................................................................................... 110

6-13 STANDBY Entry and Exit Timing Diagram ................................................................................... 111

6-14 HALT Wake-Up Using GPIOn ................................................................................................. 112

6-15 PWM Hi-Z Characteristics ...................................................................................................... 113

6-16 ADCSOCAO or ADCSOCBO Timing ......................................................................................... 115

6-17 External Interrupt Timing ....................................................................................................... 115

6-18 SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 118

6-19 SPI Master Mode External Timing (Clock Phase = 1) ...................................................................... 120

6-20 SPI Slave Mode External Timing (Clock Phase = 0) ........................................................................ 121

6-21 SPI Slave Mode External Timing (Clock Phase = 1) ........................................................................ 122

6-22 ADC Power-Up Control Bit Timing ............................................................................................ 124

6-23 ADC Analog Input Impedance Model ......................................................................................... 125

6-24 Sequential Sampling Mode (Single-Channel) Timing ....................................................................... 126

6-25 Simultaneous Sampling Mode Timing ........................................................................................ 127

List of Figures 5

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

List of Tables

2-1 Hardware Features (100-MHz Devices) ........................................................................................ 14

2-2 Hardware Features (60-MHz Devices) ......................................................................................... 15

2-3 Signal Descriptions ............................................................................................................... 21

3-1 Addresses of Flash Sectors in F2809 .......................................................................................... 33

3-2 Addresses of Flash Sectors in F2808 .......................................................................................... 33

3-3 Addresses of Flash Sectors in F2806, F2802 ................................................................................. 33

3-4 Addresses of Flash Sectors in F2801, F28015, F28016 ..................................................................... 34

3-5 Impact of Using the Code Security Module .................................................................................... 34

3-6 Wait-states ......................................................................................................................... 35

3-7 Boot Mode Selection .............................................................................................................. 38

3-8 Peripheral Frame 0 Registers ................................................................................................... 43

3-9 Peripheral Frame 1 Registers ................................................................................................... 43

3-10 Peripheral Frame 2 Registers ................................................................................................... 44

3-11 Device Emulation Registers ..................................................................................................... 44

3-12 PIE Peripheral Interrupts ......................................................................................................... 46

3-13 PIE Configuration and Control Registers ...................................................................................... 47

3-14 External Interrupt Registers ...................................................................................................... 47

3-15 PLL, Clocking, Watchdog, and Low-Power Mode Registers ................................................................ 49

3-16 PLLCR Register Bit Definitions .................................................................................................. 50

3-17 Possible PLL Configuration Modes ............................................................................................. 51

3-18 Low-Power Modes ................................................................................................................ 53

4-1 CPU-Timers 0, 1, 2 Configuration and Control Registers ................................................................... 55

4-2 ePWM Control and Status Registers ........................................................................................... 57

4-3 eCAP Control and Status Registers ............................................................................................ 60

4-4 eQEP Control and Status Registers ............................................................................................ 62

4-5 ADC Registers ..................................................................................................................... 67

4-6 3.3-V eCAN Transceivers ....................................................................................................... 69

4-7 CAN Register Map ................................................................................................................ 72

4-8 SCI-A Registers ................................................................................................................... 74

4-9 SCI-B Registers ................................................................................................................... 74

4-10 SPI-A Registers ................................................................................................................... 77

4-11 SPI-B Registers ................................................................................................................... 77

4-12 SPI-C Registers ................................................................................................................... 78

4-13 SPI-D Registers ................................................................................................................... 78

4-14 I

2

C-A Registers .................................................................................................................... 81

4-15 GPIO Registers ................................................................................................................... 83

4-16 F2808 GPIO MUX Table ......................................................................................................... 84

6-1 TMS320F2809, TMS320F2808 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT ............ 93

6-2 TMS320F2806 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT .............................. 94

List of Tables6 Submit Documentation Feedback

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

6-3 TMS320F2802, TMS320F2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT ............ 95

6-4 TMS320C2802, TMS320C2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT ........... 96

6-5 Typical Current Consumption by Various Peripherals (at 100 MHz) ....................................................... 97

6-6 TMS320x280x Clock Table and Nomenclature (100-MHz Devices) ...................................................... 101

6-7 TMS320x280x Clock Table and Nomenclature (60-MHz Devices) ....................................................... 102

6-8 Input Clock Frequency .......................................................................................................... 103

6-9 XCLKIN Timing Requirements - PLL Enabled ............................................................................... 103

6-10 XCLKIN Timing Requirements - PLL Disabled .............................................................................. 103

6-11 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ....................................................... 103

6-12 Power Management and Supervisory Circuit Solutions .................................................................... 104

6-13 Reset ( XRS) Timing Requirements ........................................................................................... 106

6-14 General-Purpose Output Switching Characteristics ......................................................................... 107

6-15 General-Purpose Input Timing Requirements ............................................................................... 108

6-16 IDLE Mode Timing Requirements ............................................................................................. 110

6-17 IDLE Mode Switching Characteristics ......................................................................................... 110

6-18 STANDBY Mode Timing Requirements ...................................................................................... 110

6-19 STANDBY Mode Switching Characteristics ................................................................................. 111

6-20 HALT Mode Timing Requirements ............................................................................................ 111

6-21 HALT Mode Switching Characteristics ....................................................................................... 112

6-22 ePWM Timing Requirements................................................................................................... 113

6-23 ePWM Switching Characteristics .............................................................................................. 113

6-24 Trip-Zone input Timing Requirements ........................................................................................ 113

6-25 High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz) .............................................. 114

6-26 Enhanced Capture (eCAP) Timing Requirement ............................................................................ 114

6-27 eCAP Switching Characteristics ............................................................................................... 114

6-28 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements .................................................... 114

6-29 eQEP Switching Characteristics ............................................................................................... 114

6-30 External ADC Start-of-Conversion Switching Characteristics .............................................................. 115

6-31 External Interrupt Timing Requirements ...................................................................................... 115

6-32 External Interrupt Switching Characteristics ................................................................................. 115

6-33 I

2

C Timing ........................................................................................................................ 116

6-34 SPI Master Mode External Timing (Clock Phase = 0) ...................................................................... 117

6-35 SPI Master Mode External Timing (Clock Phase = 1) ...................................................................... 119

6-36 SPI Slave Mode External Timing (Clock Phase = 0)........................................................................ 120

6-37 SPI Slave Mode External Timing (Clock Phase = 1)........................................................................ 121

6-38 ADC Electrical Characteristics (over recommended operating conditions) .............................................. 123

6-39 ADC Power-Up Delays .......................................................................................................... 124

6-40 Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK) ....................................... 124

6-41 Sequential Sampling Mode Timing ............................................................................................ 126

6-42 Simultaneous Sampling Mode Timing ........................................................................................ 127

6-43 Flash Endurance ................................................................................................................. 129

List of Tables 7

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

6-44 Flash Parameters at 100-MHz SYSCLKOUT ................................................................................ 129

6-45 Flash/OTP Access Timing ...................................................................................................... 129

6-46 Minimum Required Flash/OTP Wait-States at Different Frequencies .................................................... 130

6-47 ROM/OTP Access Timing ...................................................................................................... 130

6-48 ROM/ROM (OTP area) Minimum Required Wait-States at Different Frequencies ..................................... 130

8-1 F280x Thermal Model 100-pin GGM Results ................................................................................ 132

8-2 F280x Thermal Model 100-pin PZ Results ................................................................................... 132

8-3 C280x Thermal Model 100-pin GGM Results ................................................................................ 132

8-4 C280x Thermal Model 100-pin PZ Results ................................................................................... 132

8-5 F2809 Thermal Model 100-pin GGM Results ............................................................................... 132

8-6 F2809 Thermal Model 100-pin PZ Results .................................................................................. 133

List of Tables8 Submit Documentation Feedback

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Revision History

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

This data manual was revised from SPRS230H to SPRS230I.
Scope: TMS320F2809 is now a production device.
The UCD9501 device was removed because TMS320F2801 is the identical replacement for the UCD9501

device.
This document has been reviewed for technical accuracy; the technical content is up to date as of the

specified release date with the following changes:

Technical Changes Made for Revision I

Location Additions, Deletions, Changes

Section 1.2 Added Getting Started section
Table 2-2 Added GGM and ZGM packages to devices in hardware table
Figure 2-3 Modified pinout and added another pinout to clarify 2801x pin mapping
Figure 3-6 Modified F2801, F28015, F28016, C2801 Memory Map
Table 3-5 Modified note and added table on handling certain memory locations
Section 3.2.5 Added F2809 and F2802 to text in Flash section
Table 3-11 Added F2809 to Device Emulation Registers table
Table 4-2 Added HRCNFG register locations for F2809 devices with footnote in ePWM Control and Status

Registers table and added footnote to HRCNFG to show it as EALLOW protected

Section 4.6.1 Added subsection on pins if ADC is not used
Section 4.7 Modified note following features list in eCAN Module section
Section 6.2 Added 60-MHz values for device clock frequency in the Recommended Operating Conditions table
Section 5.2 Updated the document list in Documentation Support
Section 6.4.1 Added a note in the section on reducing current consumption, following Table 6-5
Figure 6-2 Modified Note following Typical Operational Power Versus Frequency (F2808) figure
Table 6-7 Changed 100 MHz to 60 MHz in TMS320x280x Clock Table and Nomenclature (60-MHz devices)

table note

Table 6-29 Changed symbol in eQEP Switching Characteristics table from t

d(PCSOUT)QEP

to t

d(PCS-OUT)QEP

Table 6-36 Modified values in last two rows of table
Table 6-37 Modified values in last two rows of table
Section 7.1 Added two bullets to the section on migration issues

Revision History 9

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

Revision History10 Submit Documentation Feedback

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1 F280x, F2801x, C280x DSPs

1.1 Features

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

• High-Performance Static CMOS Technology • Enhanced Control Peripherals

– 100 MHz (10-ns Cycle Time) – Up to 16 PWM Outputs
– 60 MHz (16.67-ns Cycle Time) – Up to 6 HRPWM Outputs With 150 ps MEP

Resolution

– Low-Power (1.8-V Core, 3.3-V I/O) Design

– Up to Four Capture Inputs

• JTAG Boundary Scan Support

(1)

– Up to Two Quadrature Encoder Interfaces

• High-Performance 32-Bit CPU (TMS320C28x)

– Up to Six 32-bit/Six 16-bit Timers

– 16 x 16 and 32 x 32 MAC Operations

• Serial Port Peripherals

– 16 x 16 Dual MAC

– Up to 4 SPI Modules

– Harvard Bus Architecture

– Up to 2 SCI (UART) Modules

– Atomic Operations

– Up to 2 CAN Modules

– Fast Interrupt Response and Processing

– One Inter-Integrated-Circuit (I2C) Bus

– Unified Memory Programming Model

• 12-Bit ADC, 16 Channels

– Code-Efficient (in C/C++ and Assembly)

– 2 x 8 Channel Input Multiplexer

• On-Chip Memory

– Two Sample-and-Hold

– F2809: 128K X 16 Flash, 18K X 16 SARAM

– Single/Simultaneous Conversions

F2808: 64K X 16 Flash, 18K X 16 SARAM
F2806: 32K X 16 Flash, 10K X 16 SARAM

– Fast Conversion Rate:

F2802: 32K X 16 Flash, 6K X 16 SARAM

80 ns - 12.5 MSPS (F2809 only)

F2801: 16K X 16 Flash, 6K X 16 SARAM

160 ns - 6.25 MSPS (280x)

F2801x: 16K X 16 Flash, 6K X 16 SARAM

267 ns - 3.75 MSPS (F2801x)

– 1K x 16 OTP ROM (Flash Devices Only)

– Internal or External Reference

– C2802: 32K X 16 ROM, 6K X 16 SARAM

• Up to 35 Individually Programmable,

C2801: 16K X 16 ROM, 6K X 16 SARAM

Multiplexed GPIO Pins With Input Filtering

• Boot ROM (4K x 16)

• Advanced Emulation Features

– With Software Boot Modes (via SCI, SPI,

– Analysis and Breakpoint Functions

CAN, I2C, and Parallel I/O)

– Real-Time Debug via Hardware

– Standard Math Tables

• Development Support Includes

• Clock and System Control

– ANSI C/C++ Compiler/Assembler/Linker

– Dynamic PLL Ratio Changes Supported

– Code Composer Studio™ IDE

– On-Chip Oscillator

– DSP/BIOS™

– Watchdog Timer Module

– Digital Motor Control and Digital Power

• Any GPIO A Pin Can Be Connected to One of

Software Libraries

the Three External Core Interrupts

• Low-Power Modes and Power Savings

• Peripheral Interrupt Expansion (PIE) Block

– IDLE, STANDBY, HALT Modes Supported

That Supports All 43 Peripheral Interrupts

– Disable Individual Peripheral Clocks

• 128-Bit Security Key/Lock

• Package Options

– Protects Flash/OTP/L0/L1 Blocks

– Thin Quad Flatpack (PZ)

– Prevents Firmware Reverse Engineering

– MicroStar BGA™ (GGM, ZGM)

• Three 32-Bit CPU Timers

• Temperature Options:

– A: -40°C to 85°C (PZ, GGM, ZGM)
– S: -40°C to 125°C (PZ, GGM, ZGM)
– Q: -40°C to 125°C (PZ)

(1) IEEE Standard 1149.1-1990 Standard Test Access Port and

Boundary Scan Architecture

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.

Code Composer Studio, DSP/BIOS, MicroStar BGA, TMS320C28x, C28x, TMS320C2000 are trademarks of Texas Instruments.
eZdsp is a trademark of Spectrum Digital.

PRODUCTION DATA information is current as of publication date.

Copyright © 2003–2007, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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1.2 Getting Started

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

This section gives a brief overview of the steps to take when first developing for a C28x device. For more
detail on each of these steps, see the following:

• Getting Started With TMS320C28x™ Digital Signal Controllers (literature number SPRAAM0 ).

• C2000 Getting Started Website (http://www.ti.com/c2000getstarted)

Step 1. Acquire the appropriate development tools

The quickest way to begin working with a C28x device is to acquire an eZdsp™ kit for initial
development, which, in one package, includes:

• On-board JTAG emulation via USB or parallel port

• Appropriate emulation driver

• Code Composer Studio™ IDE for eZdsp

Once you have become familiar with the device and begin developing on your own
hardware, purchase Code Composer Studio™ IDE separately for software development and
a JTAG emulation tool to get started on your project.

Step 2. Download starter software

To simplify programming for C28x devices, it is recommended that users download and use
the C/C++ Header Files and Example(s) to begin developing software for the C28x devices
and their various peripherals.

After downloading the appropriate header file package for your device, refer to the following
resources for step-by-step instructions on how to run the peripheral examples and use the
header file structure for your own software

• The Quick Start Readme in the /doc directory to run your first application.

• Programming TMS320x28xx and 28xxx Peripherals in C/C++ Application Report

(literature number SPRAA85 )

Step 3. Download flash programming software

Many C28x devices include on-chip flash memory and tools that allow you to program the
flash with your software IP.

• Flash Tools: C28x Flash Tools

• TMS320F281x Flash Programming Solutions (literature number SPRB169 )

• Running an Application from Internal Flash Memory on the TMS320F28xx DSP (literature

number SPRA958 )

Step 4. Move on to more advanced topics

For more application software and other advanced topics, visit the TI website at

http://www.ti.com or http://www.ti.com/c2000getstarted .

12 F280x, F2801x, C280x DSPs Submit Documentation Feedback

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2 Introduction

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320F28015,
TMS320F28016, TMS320C2802, and TMS320C2801, devices, members of the TMS320C28x™ DSP
generation, are highly integrated, high-performance solutions for demanding control applications.

Throughout this document, TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802,
TMS320F2801, TMS320C2802, TMS320C2801, TMS320F28015, and TMS32028016 are abbreviated as
F2809, F2808, F2806, F2802, F2801, F28015, F28016, C2802, and C2801, respectively. TMS320F28015
and TMS320F28016 are abbreviated as F2801x. Table 2-1 provides a summary of features for each
device.

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

Table 2-1. Hardware Features (100-MHz Devices)

FEATURE F2809 F2808 F2806 F2802 F2801 C2802 C2801

Instruction cycle (at 100 MHz) 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns

18K 18K

10K 6K 6K 6K 6K

Single-access RAM (SARAM) (16-bit word) (L0, L1, M0, M1, (L0, L1, M0, M1,

(L0, L1, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1)

H0) H0)

3.3-V on-chip flash (16-bit word) 128K 64K 32K 32K 16K – –
On-chip ROM (16-bit word) – – – – – 32K 16K
Code security for on-chip flash/SARAM/OTP blocks Yes Yes Yes Yes Yes Yes Yes
Boot ROM (4K X16) Yes Yes Yes Yes Yes Yes Yes
One-time programmable (OTP) ROM

1K 1K 1K 1K 1K – –

(16-bit word)
PWM outputs ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3/4/5/6 ePWM1/2/3 ePWM1/2/3 ePWM1/2/3 ePWM1/2/3

ePWM1A/2A/3A/ ePWM1A/2A/ ePWM1A/2A/

HRPWM channels ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A

4A/5A/6A 3A/4A 3A/4A
32-bit CAPTURE inputs or auxiliary PWM outputs eCAP1/2/3/4 eCAP1/2/3/4 eCAP1/2/3/4 eCAP1/2 eCAP1/2 eCAP1/2 eCAP1/2
32-bit QEP channels (four inputs/channel) eQEP1/2 eQEP1/2 eQEP1/2 eQEP1 eQEP1 eQEP1 eQEP1
Watchdog timer Yes Yes Yes Yes Yes Yes Yes
12-Bit, 16-channel ADC conversion time 80 ns 160 ns 160 ns 160 ns 160 ns 160 ns 160 ns
32-Bit CPU timers 3 3 3 3 3 3 3
Serial Peripheral Interface (SPI) SPI-A/B/C/D SPI-A/B/C/D SPI-A/B/C/D SPI-A/B SPI-A/B SPI-A/B SPI-A/B
Serial Communications Interface (SCI) SCI-A/B SCI-A/B SCI-A/B SCI-A SCI-A SCI-A SCI-A
Enhanced Controller Area Network (eCAN) eCAN-A/B eCAN-A/B eCAN-A eCAN-A eCAN-A eCAN-A eCAN-A
Inter-Integrated Circuit (I2C) I2C-A I2C-A I2C-A I2C-A I2C-A I2C-A I2C-A
Digital I/O pins (shared) 35 35 35 35 35 35 35
External interrupts 3 3 3 3 3 3 3
Supply voltage 1.8-V Core, 3.3-V I/O Yes Yes Yes Yes Yes Yes Yes

100-Pin PZ Yes Yes Yes Yes Yes Yes Yes

Packaging

100-Ball GGM, ZGM Yes Yes Yes Yes Yes Yes Yes
A: -40 ° C to 85 ° C (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)

Temperature options S: -40 ° C to 125 ° C (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)

Q: -40 ° C to 125 ° C (PZ) (PZ) (PZ) (PZ) (PZ) (PZ) (PZ)

Product status

(1)

TMS TMS TMS TMS TMS TMS TMS

(1) See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages.

14 Introduction Submit Documentation Feedback

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2.1 Pin Assignments

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

Table 2-2. Hardware Features (60-MHz Devices)

FEATURE F2802-60 F2801-60 F28016 F28015

Instruction cycle (at 60 MHz) 16.67 ns 16.67 ns 16.67 ns 16.67 ns

6K 6K 6K 6K

Single-access RAM (SARAM) (16-bit word)

(L0, M0, M1) (L0, M0, M1) (L0, M0, M1) (L0, M0, M1)

3.3-V on-chip flash (16-bit word) 32K 16K 16K 16K
On-chip ROM (16-bit word) – – – –
Code security for on-chip flash/SARAM/OTP

Yes Yes Yes Yes

blocks
Boot ROM (4K X16) Yes Yes Yes Yes
One-time programmable (OTP) ROM

1K 1K 1K 1K

(16-bit word)
PWM outputs ePWM1/2/3 ePWM1/2/3 ePWM1/2/3/4 ePWM1/2/3/4
HRPWM channels ePWM1A/2A/3A ePWM1A/2A/3A ePWM1A/2A/3A/4A ePWM1A/2A/3A/4A
32-bit CAPTURE inputs or auxiliary PWM

eCAP1/2 eCAP1/2 eCAP1/2 eCAP1/2

outputs
32-bit QEP channels (four inputs/channel) eQEP1 eQEP1 - ­Watchdog timer Yes Yes Yes Yes

No. of channels 16 16 16 16

12-Bit ADC MSPS 3.75 3.75 3.75 3.75

Conversion time 267 ns 267 ns 267 ns 267 ns
32-Bit CPU timers 3 3 3 3
Serial Peripheral Interface (SPI) SPI-A/B SPI-A/B SPI-A SPI-A
Serial Communications Interface (SCI) SCI-A SCI-A SCI-A SCI-A
Enhanced Controller Area Network (eCAN) eCAN-A eCAN-A eCAN-A ­Inter-Integrated Circuit (I2C) I2C-A I2C-A I2C-A I2C-A
Digital I/O pins (shared) 35 35 35 35
External interrupts 3 3 3 3

1.8-V Core, 1.8-V Core, 1.8-V Core, 1.8-V Core,

Supply voltage

3.3-V I/O 3.3-V I/O 3.3-V I/O 3.3-V I/O

100-Pin PZ Yes Yes Yes Yes
Packaging

100-Ball GGM, ZGM Yes Yes Yes Yes

A: -40 ° C to 85 ° C (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)
Temperature options S: -40 ° C to 125 ° C (PZ GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM) (PZ, GGM, ZGM)

Q: -40 ° C to 125 ° C (PZ) (PZ) (PZ) (PZ)
Product status

(1)

TMS TMS TMS TMS

(1) See Section 5.1, Device and Development Support Nomenclature for descriptions of device stages.

The TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802,
TMS320C2801, TMS320F28015, and TMS320F28016 100-pin PZ low-profile quad flatpack (LQFP) pin
assignments are shown in Figure 2-1 , Figure 2-2 , Figure 2-3 , and Figure 2-4 . The F2801-60 and F2802-60
are available only in the PZ package. The TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801,
TMS320C2802, and TMS320C2801 100-ball GGM and ZGM ball grid array (BGA) terminal assignments
are shown in Figure 2-5 . Table 2-3 describes the function(s) of each pin.

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33
32
31
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28
27
26

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77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

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72

71

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69

68

67

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51

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

GPIO0/EPWM1A

TCK

TMS

TDI

GPIO23/EQEP1I/SPISTEC/SCIRXDB

GPIO22/EQEP1S/SPICLKC/SCITXDB

GPIO11/EPWM6B/SCIRXDB/ECAP4

GPIO21/EQEP1B/SPISOMIC/CANRXB

XCLKOUT

GPIO20/EQEP1A/SPISIMOC/CANTXB

GPIO9/EPWM5B/SCITXDB/ECAP3

GPIO7/EPWM4B/SPISTED/ECAP2

GPIO19/SPISTEA/SCIRXDB

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO18/SPICLKA/SCITXDB

GPIO5/EPWM3B/SPICLKD/ECAP1

GPIO4/EPWM3A

XRS

TRST

V

SS

V

DD

V

DDIO

GPIO10/EPWM6A/CANRXB/ADCSOCBO

V

SS

GPIO8/EPWM5A/CANTXB/ADCSOCAO

V

DD

V

SS

GPIO17/SPISOMIA/CANRXB/TZ6

V

SS

V

SS

V

DD

V

DDIO

GPIO16/SPISIMOA/CANTXB/TZ5

V

DD2A18

V

SS2AGND

V

DDAIO

GPIO12/TZ1/CANTXB/SPISIMOB

V

SS

V

DDIO

GPIO29/SCITXDA/TZ6

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

GPIO14/TZ3/SCITXDB/SPICLKB

V

SS

V

DD

V

DD1A18

V

SS1AGND

V

SSA2

V

DDA2

GPIO15/TZ4/SCIRXDB/SPISTEB

V

SSAIO

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO13/TZ2/CANRXB/SPISOMIB

V

DD3VFL

V

SS

V

DD

GPIO28/SCIRXDA/TZ5

V

SS

V

SS

V

DD

V

SS

V

DDIO

GPIO26/ECAP3/EQEP2I/SPICLKB

TEST2

TEST1

GPIO25/ECAP2/EQEP2B/SPISOMIB

XCLKIN

X1

X2

EMU1

EMU0

GPIO24/ECAP1/EQEP2A/SPISIMOB

GPIO27/ECAP4/EQEP2S/SPISTEB

TDO

GPIO30/CANRXA

GPIO31/CANTXA

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCLO

ADCINB0

ADCINB1

ADCINB2

ADCINB3

ADCINB4

ADCINB5

ADCINB6

ADCINB7

ADCREFIN

ADCREFM

ADCREFP

ADCRESEXT

GPIO34

GPIO1/EPWM1B/SPISIMOD

GPIO2/EPWM2A

GPIO3/EPWM2B/SPISOMID

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

Figure 2-1. TMS320F2809, TMS320F2808 100-Pin PZ LQFP (Top View)

Introduction 16 Submit Documentation Feedback

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99

100

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2

3

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5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

GPIO3/EPWM2B/SPISOMID
GPIO0/EPWM1A

GPIO2/EPWM2A
GPIO1/EPWM1B/SPISIMOD

GPIO34

ADCRESEXT
ADCREFP
ADCREFM
ADCREFIN
ADCINB7
ADCINB6
ADCINB5
ADCINB4
ADCINB3
ADCINB2
ADCINB1
ADCINB0

TCK

TMS

TDI

GPIO23/EQEP1I/SPISTEC/SCIRXDB

GPIO22/EQEP1S/SPICLKC/SCITXDB

XCLKOUT

GPIO20/EQEP1A/SPISIMOC

GPIO9/EPWM5B/SCITXDB/ECAP3

GPIO7/EPWM4B/SPISTED/ECAP2

GPIO19/SPISTEA/SCIRXDB

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO18/SPICLKA/SCITXDB

GPIO5/EPWM3B/SPICLKD/ECAP1

GPIO4/EPWM3A

GPIO30/CANRXA

GPIO31/CANTXA

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCLO

XRS

TRST

GPIO11/EPWM6B/SCIRXDB/ECAP4

GPIO21/EQEP1B/SPISOMIC

V

SS

V

SS

V

DD

V

DDIO

GPIO16/SPISIMOA/TZ5

V

DD2A18

V

SS2AGND

V

DDAIO

V

SS

V

DD

V

DDIO

GPIO10/EPWM6A/ADCSOCBO

V

SS

GPIO8/EPWM5A/ADCSOCAO

V

DD

V

SS

GPIO17/SPISOMIA/TZ6

V

DD3VFL

V

SS

V

DD

GPIO28/SCIRXDA/TZ5

V

SS

V

SS

V

DD

V

SS

V

DDIO

GPIO13/TZ2/SPISOMIB

GPIO12/TZ1/SPISIMOB

GPIO29/SCITXDA/TZ6

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

GPIO14/TZ3/SCITXDB/SPICLKB

V

DD

V

DD1A18

V

SS1AGND

V

SSA2

V

DDA2

GPIO15/TZ4/SCIRXDB/SPISTEB

V

SSAIO

V

SS

V

DDIO

GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

GPIO26/ECAP3/EQEP2I/SPICLKB

TEST2

TEST1

GPIO25/ECAP2/EQEP2B/SPISOMIB

XCLKIN

X1

X2

GPIO24/ECAP1/EQEP2A/SPISIMOB

EMU1

EMU0

GPIO27/ECAP4/EQEP2S/SPISTEB

TDO

V

SS

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

Figure 2-2. TMS320F2806 100-Pin PZ LQFP (Top View)

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7

8

9

101112

13

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19

20

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25

GPIO0/EPWM1A

GPIO2/EPWM2A
GPIO1/EPWM1B

GPIO34

ADCRESEXT

ADCREFP

ADCREFM

ADCREFIN
ADCINB7

ADCINB6

ADCINB5

ADCINB4

ADCINB3
ADCINB2

ADCINB1

ADCINB0

TCK

TMS

TDI

X

CLKOUT

GPIO30/CANRXA

GPIO31/CANTXA

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCL

O

XRS

TRST

GPIO12/TZ1

V

SS

V

DDIO

GPIO29/SCITXDA/TZ6

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

V

SS

V

DD

V

DD1A18

V

SS1AGND

V

SSA2

V

DDA2

GPIO32/SDAA/EPWMSYNCI/ADSOCAO

GPIO13/TZ2

V

DD3VFL

(A)

V

SS

V

DD

GPIO28/SCIRXDA/TZ5

V

SS

V

SS

V

DD

GPIO21/EQEP1B

V

SSVDD

GPIO23/EQEP1I

GPIO22/EQEP1S

V

DDIO

GPIO10/ADC

SOCBO

GPIO20/EQEP1A

V

SS

GPIO9

GPIO8/ADCSOCAO

V

DD

GPIO7/ECAP2

GPIO19/SPISTEA

GPIO6/EPWMSYNCI/EPWMSYNCO

GPIO1

1

V

SS

GPIO18/SPICLKA

GPIO5/EPWM3B/ECAP1

GPIO17/SPISOMIA/TZ6

GPIO4/EPWM3A

V

SS

V

SS

V

DD

V

DDIO

GPIO16/SPISIMOA/TZ5

GPIO3/EPWM2B

V

DD2A18

V

SS2AGND

V

DDAIO

GPIO14/TZ3

GPIO15/TZ4

V

SS

GPIO27

V

DDIO

GPIO24/ECAP1

V

SSAIO

GPIO25/ECAP2/SPISOMIB

GPIO26

TEST2

TEST1

XCLKIN

X1

X2

EMU1

EMU0

TDO

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

A. On the C280x devices, the V

DD3VFL

pin is V

DDIO

.

Figure 2-3. TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP

(Top View)

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2

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4

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6

7

8

9

101112

13

14

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16

17

18

19

20

21

22

23

24

25

GPIO0/EPWM1A

GPIO2/EPWM2A
GPIO1/EPWM1B

GPIO34

ADCRESEXT

ADCREFP

ADCREFM

ADCREFIN
ADCINB7

ADCINB6

ADCINB5

ADCINB4

ADCINB3
ADCINB2

ADCINB1

ADCINB0

TCK

TMS

TDI

X

CLKOUT

GPIO30/CANRXA

GPIO31/CANTXA

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCL

O

XRS

TRST

GPIO12/TZ1

V

SS

V

DDIO

GPIO29/SCITXDA/TZ6

GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

GPIO14/TZ3

V

SS

V

DD

V

DD1A18

V

SS1AGND

V

SSA2

V

DDA2

GPIO32/SDAA/EPWMSYNCI/ADSOCAO

GPIO13/TZ2

V

DD3VFL

(A)

V

SS

V

DD

GPIO28/SCIRXDA/TZ5

V

SS

V

SS

V

DD

GPIO21

V

SS

V

DD

GPIO23

GPIO22

V

DDIO

GPIO10/ADC

SOCBO

GPIO20

V

SS

GPIO9

GPIO8/ADCSOCAO

V

DD

GPIO7/EPWM4B/ECAP2

GPIO19/SPISTEA

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO11

V

SS

GPIO18/SPICLKA

GPIO5/EPWM3B/ECAP1

GPIO17/SPISOMIA/TZ6

GPIO4/EPWM3A

V

SS

V

SS

V

DD

V

DDIO

GPIO16/SPISIMOA/TZ5

GPIO3/EPWM2B

V

DD2A18

V

SS2AGND

V

DDAIO

GPIO15/TZ4

V

SS

GPIO27

V

DDIO

GPIO24/ECAP1

V

SSAIO

GPIO25/ECAP2

GPIO26

TEST2

TEST1

XCLKIN

X1

X2

EMU1

EMU0

TDO

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

A. CANTXA (pin 7) and CANRXA (pin 6) pins are not applicable for the TMS320F28015.

Figure 2-4. TMS320F2801x 100-Pin PZ LQFP

(Top View)

Submit Documentation Feedback Introduction 19

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4

C

B

A

D

E

21 3

K

F

G

H

J

5 76 98 10

Bottom View

TRST TCK

TDI

TDO TMS

EMU0

EMU1

V

DD3VFL

TEST1

TEST2

XCLKOUT

XCLKIN

X1

X2

XRS

GPIO0

GPIO1

GPIO2 GPIO3 GPIO4

GPIO5

GPIO6GPIO7

GPIO9 GPIO8

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

GPIO20

GPIO21

GPIO22

GPIO23GPIO24GPIO25

GPIO26

GPIO27

GPIO28

GPIO29

GPIO30

GPIO31

GPIO32

GPIO33

GPIO34

V

DDA2

V

DD1A18

V

SS1AGND

V

DD

V

DDIO

VSSAIO

V

DDAIO

VSSA2

ADCINA7

V

SS2AGND

V

DD2A18

V

DD

V

DD

V

DD

V

DD

V

DD

V

DDIO

V

DDIO

V

DDIO

VSS

V

SS

V

SS

V

SS

V

SS

VSS

V

SS

V

SS

V

SS

V

SS

V

SS

ADCINB2

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCINB7

ADCINB1

ADCINB0

ADCLO

ADCRESEXT

ADCREFIN

ADCREFP

ADCREFM

ADCINB3

ADCINB5

ADCINB4

ADCINB6

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

Figure 2-5. TMS320F2809, TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801,
TMS320C2802, TMS320C2801 100-Ball GGM and ZGM MicroStar BGA™ (Bottom View)

20 Introduction Submit Documentation Feedback

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2.2 Signal Descriptions

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

Table 2-3 describes the signals on the 280x devices. All digital inputs are TTL-compatible. All outputs are

3.3 V with CMOS levels. Inputs are not 5-V tolerant.

Table 2-3. Signal Descriptions

PIN NO.

GGM/

NAME DESCRIPTION

(1)

PZ

ZGM

PIN #

BALL #

JTAG

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal pull-down device. TRST is an active
high test pin and must be maintained low at all times during normal device operation. In a low-noise

TRST 84 A6

environment, TRST may be left floating. In other instances, an external pulldown resistor is highly
recommended. The value of this resistor should be based on drive strength of the debugger pods
applicable to the design. A 2.2-k Ω resistor generally offers adequate protection. Since this is
application-specific, it is recommended that each target board be validated for proper operation of
the debugger and the application. (I, ↓ )

TCK 75 A10 JTAG test clock with internal pullup (I, ↑ )

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP

TMS 74 B10

controller on the rising edge of TCK. (I, ↑ )
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction

TDI 73 C9

or data) on a rising edge of TCK. (I, ↑ )
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)

TDO 76 B9

are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator

system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

EMU0 80 A8 (I/O/Z, 8 mA drive ↑ )

NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-k Ω to 4.7-k Ω
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.

Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

EMU1 81 B7 (I/O/Z, 8 mA drive ↑ )

NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-k Ω to 4.7-k Ω
resistor is generally adequate. Since this is application-specific, it is recommended that each target
board be validated for proper operation of the debugger and the application.

FLASH

3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times. On the ROM

V

DD3VFL

96 C4

parts (C280x), this pin should be connected to V

DDIO

.
TEST1 97 A3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
TEST2 98 B3 Test Pin. Reserved for TI. Must be left unconnected. (I/O)

CLOCK

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by the bits 1, 0

XCLKOUT 66 E8 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal

can be turned off by setting XCLKOUTDIV to 3. Unlike other GPIO pins, the XCLKOUT pin is not
placed in high-impedance state during a reset. (O/Z, 8 mA drive).

External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case,

XCLKIN 90 B5 the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.8-V oscillator is

used to feed clock to X1 pin), this pin must be tied to GND. (I)

(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

Table 2-3. Signal Descriptions (continued)

PIN NO.

GGM/

NAME DESCRIPTION

(1)

PZ

ZGM

PIN #

BALL #

Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic
resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.8-V core digital

X1 88 E6 power supply. A 1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN

pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must
be tied to GND. (I)

Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and

X2 86 C6

X2. If X2 is not used it must be left unconnected. (O)

RESET

Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs.

XRS 78 B8

During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑ )
The output buffer of this pin is an open-drain with an internal pullup (100 µ A, typical). It is
recommended that this pin be driven by an open-drain device.

ADC SIGNALS

ADCINA7 16 F3 ADC Group A, Channel 7 input (I)
ADCINA6 17 F4 ADC Group A, Channel 6 input (I)
ADCINA5 18 G4 ADC Group A, Channel 5 input (I)
ADCINA4 19 G1 ADC Group A, Channel 4 input (I)
ADCINA3 20 G2 ADC Group A, Channel 3 input (I)
ADCINA2 21 G3 ADC Group A, Channel 2 input (I)
ADCINA1 22 H1 ADC Group A, Channel 1 input (I)
ADCINA0 23 H2 ADC Group A, Channel 0 input (I)
ADCINB7 34 K5 ADC Group B, Channel 7 input (I)
ADCINB6 33 H4 ADC Group B, Channel 6 input (I)
ADCINB5 32 K4 ADC Group B, Channel 5 input (I)
ADCINB4 31 J4 ADC Group B, Channel 4 input (I)
ADCINB3 30 K3 ADC Group B, Channel 3 input (I)
ADCINB2 29 H3 ADC Group B, Channel 2 input (I)
ADCINB1 28 J3 ADC Group B, Channel 1 input (I)
ADCINB0 27 K2 ADC Group B, Channel 0 input (I)
ADCLO 24 J1 Low Reference (connect to analog ground) (I)
ADCRESEXT 38 F5 ADC External Current Bias Resistor. Connect a 22-k Ω resistor to analog ground.
ADCREFIN 35 J5 External reference input (I)

Internal Reference Positive Output. Requires a low ESR (50 m Ω - 1.5 Ω ) ceramic bypass capacitor

ADCREFP 37 G5

of 2.2 µ F to analog ground. (O)
Internal Reference Medium Output. Requires a low ESR (50 m Ω - 1.5 Ω ) ceramic bypass capacitor

ADCREFM 36 H5

of 2.2 µ F to analog ground. (O)

CPU AND I/O POWER PINS

V

DDA2

15 F2 ADC Analog Power Pin (3.3 V)

V

SSA2

14 F1 ADC Analog Ground Pin

V

DDAIO

26 J2 ADC Analog I/O Power Pin (3.3 V)

V

SSAIO

25 K1 ADC Analog I/O Ground Pin

V

DD1A18

12 E4 ADC Analog Power Pin (1.8 V)

V

SS1AGND

13 E5 ADC Analog Ground Pin

V

DD2A18

40 J6 ADC Analog Power Pin (1.8 V)

V

SS2AGND

39 K6 ADC Analog Ground Pin

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

Table 2-3. Signal Descriptions (continued)

PIN NO.

GGM/

NAME DESCRIPTION

(1)

PZ

ZGM

PIN #

BALL #

V

DD

10 E2

V

DD

42 G6

V

DD

59 F10

CPU and Logic Digital Power Pins (1.8 V)

V

DD

68 D7

V

DD

85 B6

V

DD

93 D4

V

DDIO

3 C2

V

DDIO

46 H7

Digital I/O Power Pin (3.3 V)

V

DDIO

65 E9

V

DDIO

82 A7

V

SS

2 B1

V

SS

11 E3

V

SS

41 H6

V

SS

49 K9

V

SS

55 H10

V

SS

62 F7 Digital Ground Pins

V

SS

69 D10

V

SS

77 A9

V

SS

87 D6

V

SS

89 A5

V

SS

94 A4

GPIOA AND PERIPHERAL SIGNALS

(2) (3)

GPIO0 General purpose input/output 0 (I/O/Z)

(4)

EPWM1A Enhanced PWM1 Output A and HRPWM channel (O)

47 K8

- -

- ­GPIO1 General purpose input/output 1 (I/O/Z)

(4)

EPWM1B Enhanced PWM1 Output B (O)

44 K7

SPISIMOD SPI-D slave in, master out (I/O) (not available on 2801, 2802)

- ­GPIO2 General purpose input/output 2 (I/O/Z)

(4)

EPWM2A Enhanced PWM2 Output A and HRPWM channel (O)

45 J7

- -

- ­GPIO3 General purpose input/output 3 (I/O/Z)

(4)

EPWM2B Enhanced PWM2 Output B (O)

48 J8

SPISOMID SPI-D slave out, master in (I/O) (not available on 2801, 2802)

- ­GPIO4 General purpose input/output 4 (I/O/Z)

(4)

EPWM3A Enhanced PWM3 output A and HRPWM channel (O)

51 J9

- -

- ­GPIO5 General purpose input/output 5 (I/O/Z)

(4)

EPWM3B Enhanced PWM3 output B (O)

53 H9

SPICLKD SPI-D clock (I/O) (not available on 2801, 2802)
ECAP1 Enhanced capture input/output 1 (I/O)

(2) Some peripheral functions may not be available in TMS320F2801x devices. See Table 2-2 for details.
(3) All GPIO pins are I/O/Z, 4-mA drive typical (unless otherwise indicated), and have an internal pullup, which can be selectively

enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The GPIO function (shown in Italics) is the default at
reset. The peripheral signals that are listed under them are alternate functions.

(4) The pullups on GPIO0-GPIO11 pins are not enabled at reset.

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

Table 2-3. Signal Descriptions (continued)

PIN NO.

GGM/

NAME DESCRIPTION

(1)

PZ

ZGM

PIN #

BALL #

GPIO6 General purpose input/output 6 (I/O/Z)

(4)

EPWM4A Enhanced PWM4 output A and HRPWM channel (not available on 2801, 2802) (O)

56 G9

EPWMSYNCI External ePWM sync pulse input (I)
EPWMSYNCO External ePWM sync pulse output (O)

GPIO7 General purpose input/output 7 (I/O/Z)

(4)

EPWM4B Enhanced PWM4 output B (not available on 2801, 2802) (O)

58 G8

SPISTED SPI-D slave transmit enable (not available on 2801, 2802) (I/O)
ECAP2 Enhanced capture input/output 2 (I/O)

GPIO8 General purpose input/output 8 (I/O/Z)

(4)

EPWM5A Enhanced PWM5 output A (not available on 2801, 2802) (O)

60 F9

CANTXB Enhanced CAN-B transmit (not available on 2801, 2802, F2806) (O)
ADCSOCAO ADC start-of-conversion A (O)

GPIO9 General purpose input/output 9 (I/O/Z)

(4)

EPWM5B Enhanced PWM5 output B (not available on 2801, 2802) (O)

61 F8

SCITXDB SCI-B transmit data (not available on 2801, 2802) (O)
ECAP3 Enhanced capture input/output 3 (not available on 2801, 2802) (I/O)

GPIO10 General purpose input/output 10 (I/O/Z)

(4)

EPWM6A Enhanced PWM6 output A (not available on 2801, 2802) (O)

64 E10

CANRXB Enhanced CAN-B receive (not available on 2801, 2802, F2806) (I)
ADCSOCBO ADC start-of-conversion B (O)

GPIO11 General purpose input/output 11 (I/O/Z)

(4)

EPWM6B Enhanced PWM6 output B (not available on 2801, 2802) (O)

70 D9

SCIRXDB SCI-B receive data (not available on 2801, 2802) (I)
ECAP4 Enhanced CAP Input/Output 4 (not available on 2801, 2802) (I/O)

GPIO12 General purpose input/output 12 (I/O/Z)

(5)

TZ1 Trip Zone input 1 (I)

1 B2

CANTXB Enhanced CAN-B transmit (not available on 2801, 2802, F2806) (O)
SPISIMOB SPI-B Slave in, Master out (I/O)

GPIO13 General purpose input/output 13 (I/O/Z)

(5)

TZ2 Trip zone input 2 (I)

95 B4

CANRXB Enhanced CAN-B receive (not available on 2801, 2802, F2806) (I)
SPISOMIB SPI-B slave out, master in (I/O)

GPIO14 General purpose input/output 14 (I/O/Z)

(5)

TZ3 Trip zone input 3 (I)

8 D3

SCITXDB SCI-B transmit (not available on 2801, 2802) (O)
SPICLKB SPI-B clock input/output (I/O)

GPIO15 General purpose input/output 15 (I/O/Z)

(5)

TZ4 Trip zone input (I)

9 E1

SCIRXDB SCI-B receive (not available on 2801, 2802) (I)
SPISTEB SPI-B slave transmit enable (I/O)

GPIO16 General purpose input/output 16 (I/O/Z)

(5)

SPISIMOA SPI-A slave in, master out (I/O)

50 K10

CANTXB Enhanced CAN-B transmit (not available on 2801, 2802, F2806) (O)
TZ5 Trip zone input 5 (I)

GPIO17 General purpose input/output 17 (I/O/Z)

(5)

SPISOMIA SPI-A slave out, master in (I/O)

52 J10

CANRXB Enhanced CAN-B receive (not available on 2801, 2802, F2806) (I)
TZ6 Trip zone input 6(I)

GPIO18 General purpose input/output 18 (I/O/Z)

(5)

SPICLKA SPI-A clock input/output (I/O)
SCITXDB 54 H8 SCI-B transmit (not available on 2801, 2802) (O)

- -

- ­GPIO19 General purpose input/output 19 (I/O/Z)

(5)

SPISTEA SPI-A slave transmit enable input/output (I/O)
SCIRXDB 57 G10 SCI-B receive (not available on 2801, 2802) (I)

- -

- -

(5) The pullups on GPIO12-GPIO34 are enabled upon reset.

Introduction 24 Submit Documentation Feedback

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

Table 2-3. Signal Descriptions (continued)

PIN NO.

GGM/

NAME DESCRIPTION

(1)

PZ

ZGM

PIN #

BALL #

GPIO20 General purpose input/output 20 (I/O/Z)

(5)

EQEP1A Enhanced QEP1 input A (I)

63 F6

SPISIMOC SPI-C slave in, master out (not available on 2801, 2802) (I/O)
CANTXB Enhanced CAN-B transmit (not available on 2801, 2802, F2806) (O)

GPIO21 General purpose input/output 21 (I/O/Z)

(5)

EQEP1B Enhanced QEP1 input A (I)

67 E7

SPISOMIC SPI-C master in, slave out (not available on 2801, 2802) (I/O)
CANRXB Enhanced CAN-B receive (not available on 2801, 2802, F2806) (I)

GPIO22 General purpose input/output 22 (I/O/Z)

(5)

EQEP1S Enhanced QEP1 strobe (I/O)

71 D8

SPICLKC SPI-C clock (not available on 2801, 2802) (I/O)
SCITXDB SCI-B transmit (not available on 2801, 2802) (O)

GPIO23 General purpose input/output 23 (I/O/Z)

(5)

EQEP1I Enhanced QEP1 index (I/O)

72 C10

SPISTEC SPI-C slave transmit enable (not available on 2801, 2802) (I/O)
SCIRXDB SCI-B receive (I) (not available on 2801, 2802)

GPIO24 General purpose input/output 24 (I/O/Z)

(5)

ECAP1 Enhanced capture 1 (I/O)

83 C7

EQEP2A Enhanced QEP2 input A (I) (not available on 2801, 2802)
SPISIMOB SPI-B slave in, master out (I/O)

GPIO25 General purpose input/output 25 (I/O/Z)

(5)

ECAP2 Enhanced capture 2 (I/O)

91 C5

EQEP2B Enhanced QEP2 input B (I) (not available on 2801, 2802)
SPISOMIB SPI-B master in, slave out (I/O)

GPIO26 General purpose input/output 26 (I/O/Z)

(5)

ECAP3 Enhanced capture 3 (I/O) (not available on 2801, 2802)

99 A2

EQEP2I Enhanced QEP2 index (I/O) (not available on 2801, 2802)
SPICLKB SPI-B clock (I/O)

GPIO27 General purpose input/output 27 (I/O/Z)

(5)

ECAP4 Enhanced capture 4 (I/O) (not available on 2801, 2802)

79 C8

EQEP2S Enhanced QEP2 strobe (I/O) (not available on 2801, 2802)
SPISTEB SPI-B slave transmit enable (I/O)

GPIO28 General purpose input/output 28. This pin has an 8-mA (typical) output buffer. (I/O/Z)

(5)

SCIRXDA SCI receive data (I)

92 D5

- ­TZ5 Trip zone input 5 (I)

GPIO29 General purpose input/output 29. This pin has an 8-mA (typical) output buffer. (I/O/Z)

(5)

SCITXDA SCI transmit data (O)

4 C3

- ­TZ6 Trip zone 6 input (I)

GPIO30 General purpose input/output 30. This pin has an 8-mA (typical) output buffer. (I/O/Z)

(5)

CANRXA Enhanced CAN-A receive data (I)

6 D2

- -

- ­GPIO31 General purpose input/output 31. This pin has an 8-mA (typical) output buffer. (I/O/Z)

(5)

CANTXA Enhanced CAN-A transmit data (O)

7 D1

- -

- ­GPIO32 General purpose input/output 32 (I/O/Z)

(5)

SDAA I2C data open-drain bidirectional port (I/OD)

100 A1

EPWMSYNCI Enhanced PWM external sync pulse input (I)
ADCSOCAO ADC start-of-conversion (O)

Submit Documentation Feedback Introduction 25

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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

Table 2-3. Signal Descriptions (continued)

PIN NO.

GGM/

NAME DESCRIPTION

(1)

PZ

ZGM

PIN #

BALL #

GPIO33 General-Purpose Input/Output 33 (I/O/Z)

(1)

SCLA I2C clock open-drain bidirectional port (I/OD)

5 C1

EPWMSYNCO Enhanced PWM external synch pulse output (O)
ADCSOCBO ADC start-of-conversion (O)

GPIO34 General-Purpose Input/Output 34 (I/O/Z)

(1)

- -

43 G7

- -

- -

(1) The pullups on GPIO12-GPIO34 are enabled upon reset.

NOTE

Some peripheral functions may not be available in TMS320F2801x devices. See

Table 2-2 for details.

26 Introduction Submit Documentation Feedback

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3 Functional Overview

INT[12:1]

Real-TimeJTAG

(TDI,TDO,TRST

,TCK,

TMS,EMU0,EMU1)

C28xCPU
(100MHz)

NMI,INT13

MemoryBus

BootROM

4K 16

(1-waitstate)

FLASH

128Kx16(F2809)

64Kx16(F2808)
32Kx16(F2806)
32Kx16(F2802)
16Kx16(F2801)

16Kx16(F2801x)

H0SARAM

(C)

8K 16

(0-wait)

L1SARAM

(B)

4K 16

(0-wait)

L0SARAM

4K 16

(0-wait)

M0SARAM

1K 16

M1SARAM

1K 16

INT14

32-bitCPUTIMER0

32-bitCPUTIMER1

32-bitCPUTIMER2

SYSCLKOUT

RS

CLKIN

12-BitADC

ADCSOCA/B

SOCA/B

16Channels

12

6

32

XCLKOUT

XRS

XCLKIN

X1
X2

32

SystemControl

(Oscillator,PLL,

PeripheralClocking,

LowPowerModes,

WatchDog)

ePWM1/2/3/4/5/6

(12PWMoutputs,

6tripzones,

6timers16-bit)

eCAP1/2/3/4

(4timers32-bit)

eQEP1/2

eCAN-A/B(32mbox)

ExternalInterrupt

Control

PIE

(96Interrupts)

(A)

FIFO

FIFO

FIFO

SCI-A/B

SPI-A/B/C/D

I2C-A

4

8

4

2

16

4

GPIOMUX

GPIOs

(35)

TINT0

TINT1

TINT2

7

OTP

(D)

1K 16

PeripheralBus

Protected bythecode-securitymodule.

ROM

32K x16(C2802)

16Kx16(C2801)

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

A. 43 of the possible 96 interrupts are used on the devices.
B. Not available in F2802, F2801, C2802, and C2801.
C. Not available in F2806, F2802, F2801, C2802, and C2801.
D. The 1K x 16 OTP has been replaced with 1K x 16 ROM for C280x devices.

Figure 3-1. Functional Block Diagram

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3.1 Memory Maps

0x00 0000

Block Start

Address

Data Space

Prog Space

M0 SARAM (1 K y 16)

M1 SARAM (1 K y 16)

0x00 0400

Peripheral Frame 0

0x00 0800

0x00 0D00

Peripheral Frame 1

(protected)

0x00 6000

Peripheral Frame 2

(protected)

0x00 7000

L0 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x00 8000

L1 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x00 9000

H0 SARAM (0-wait)

(8 k y 16, Dual Mapped)

0x00 A000

0x00 C000

OTP

(1 k y 16, Secure Zone)

0x3D 7800

0x3D 7C00

FLASH

(128 k y 16, Secure Zone)

0x3D 8000

0x3F 7FF8

128-bit Password

L0 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x3F 8000

L1 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x3F 9000

H0 SARAM (0-wait)

(8 k y 16, Dual Mapped)

0x3F A000

0x3F F000

Boot ROM (4 k y 16)

Vectors (32 y 32)

(enabled if VMAP = 1, ENPIE = 0)

0x3F FFC0

Low 64K [0000 − FFFF]

(24x/240x equivalent data space)

High 64K [3F0000 − 3FFFFF]

(24x/240x equivalent program space)

Reserved

PIE Vector − RAM

(256 x 16)

(Enabled if ENPIE = 1)

0x00 0E00

0x3F C000

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

A. Memory blocks are not to scale.
B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

User program cannot access these memory maps in program space.
C. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.

Figure 3-2. F2809 Memory Map

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0x00 0000

Block Start

Address

Data Space

Prog Space

M0 SARAM (1 K y 16)

M1 SARAM (1 K y 16)

0x00 0400

Peripheral Frame 0

0x00 0800

0x00 0D00

Peripheral Frame 1

(protected)

0x00 6000

Peripheral Frame 2

(protected)

0x00 7000

L0 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x00 8000

L1 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x00 9000

H0 SARAM (0-wait)

(8 k y 16, Dual Mapped)

0x00 A000

0x00 C000

OTP

(1 k y 16, Secure Zone)

0x3D 7800

0x3D 7C00

FLASH

(64 k y 16, Secure Zone)

0x3E 8000

0x3F 7FF8

128-bit Password

L0 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x3F 8000

L1 SARAM (0-wait)

(4 k y 16, Secure Zone, Dual Mapped)

0x3F 9000

H0 SARAM (0-wait)

(8 k y 16, Dual Mapped)

0x3F A000

0x3F F000

Boot ROM (4 k y 16)

Vectors (32 y 32)

(enabled if VMAP = 1, ENPIE = 0)

0x3F FFC0

Low 64K [0000 − FFFF]

(24x/240x equivalent data space)

High 64K [3F0000 − 3FFFFF]

(24x/240x equivalent program space)

Reserved

PIE Vector − RAM

(256 x 16)

(Enabled if ENPIE = 1)

0x00 0E00

0x3F C000

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801

TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

A. Memory blocks are not to scale.
B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

User program cannot access these memory maps in program space.
C. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.

Figure 3-3. F2808 Memory Map

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0x00 0000

Block Start

Address

Data Space

M0 SARAM (1K y 16)

0x00 0400

0x00 0800

0x00 0D00

0x00 6000

0x00 7000

0x00 8000

0x00 9000

0x00 A000

0x3D 7800

0x3D 7C00

0x3F 7FF8
0x3F 8000

0x3F 9000

0x3F A000

0x3F F000

0x3F FFC0

OTP

(1 K y 16, Secure Zone)

FLASH

(32 K y 16, Secure Zone)

Boot ROM (4 K y 16)

Low 64K [0000−FFFF]

(24x/240x equivalent data space)

High 64K [3F0000 −3FFFF]

(24x/240x equivalent program space)

Reserved

M1 SARAM (1K y 16)

L0 SARAM (0-wait)

(4k y 16, Secure Zone, Dual Mapped)

L1 SARAM (0-wait)

(4k y 16, Secure Zone, Dual Mapped)

L0 SARAM (0-wait) (4k y 16,
Secure Zone, Dual Mapped)

L1 SARAM (0-wait) (4k y 16,
Secure Zone, Dual Mapped)

128-bit Password

0x3F 0000

Prog Space

Peripheral Frame 0

Peripheral Frame 1

(protected)

Peripheral Frame 2

(protected)

PIE Vector − RAM

(256 x 16)

(Enabled if ENPIE = 1)

Vectors (32 y 32)

(enabled if VMAP = 1, ENPIE = 0)

0x00 0E00

TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801
TMS320C2802, TMS320C2801, and TMS320F2801x DSPs

SPRS230I – OCTOBER 2003 – REVISED MAY 2007

A. Memory blocks are not to scale.
B. Peripheral Frame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.

User program cannot access these memory maps in program space.
C. Protected means the order of Write followed by Read operations is preserved rather than the pipeline order.
D. Certain memory ranges are EALLOW protected against spurious writes after configuration.

Figure 3-4. F2806 Memory Map

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