TEXAS INSTRUMENTS TMS320DM814x Technical data

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1 高性能片上系统 (SoC)

1.1 特性

123

• 高性能Davinci 数字媒体处理器 – 高达 1GHz 的 ARM® Cortex™-A8 RISC MPU – 高达 2000 ARM®Cortex™-A8 MIPS – 高达 750MHz C674x™ VLIW DSP – 6000 / 4500 C674x™ MIPS/ MFLOPS – 与C67x+™、C64x+™ 具有完全的软件兼容性

• ARM® Cortex™-A8 内核 – ARMv7 架构

• 顺序 (In-Order)、双发射 (Dual-Issue)、超标

量微处理器内核

• NEON™ 多媒体架构

• 支持整数和浮点

• Jazelle® RCT 执行环境

• ARM® Cortex™-A8 内存架构 – 32k 字节指令及数据高速缓存 – 512 k 字节 L2 高速缓存 – 64k 字节 RAM、48k 字节引导 ROM

• TMS320C674x™ 浮点 VLIW DSP – 64 个通用寄存器（32 位） – 6 个 ALU（32 / 40位）功能单元

• 支持 32 位整数、SP （IEEE 单精度 / 32

位）和 DP （IEEE 双精度 / 64 位）浮点

• 每个时钟支持多达 4 个 SP 加法，每两个时钟支持 4 个 DP 加法

• 每个周期支持多达两个浮点（SP 或 DP）倒数逼近或平方根运算

– 两个乘法功能单元

• 所支持的混合精度 IEEE 浮点乘法高达：

• C674x 两级内存架构

– 每个时钟 2 SP x SP -> SP – 每两个时钟 2 SP x SP -> DP – 每三个时钟 2 SP x DP -> DP – 每四个时钟 2 DP x DP -> DP

• 定点乘法支持每个时钟周期 2个 32 x 32 位乘

法运算、4 个 16 x 16 位乘法运算（包括复数乘法）或 8 个 8 x 8 位乘法运算

– 具有 EDC 的 32k 字节 L1P RAM / 高速缓存 – 32k 字节 L1D RAM / 高速缓存 – 采用 ECC 的 256k 字节 L2 统一映射 RAM / 高

ZHCS057–MARCH 2011

TMS320DM814x DaVinci™

数字媒体处理器

查询样品: TMS320DM8148, TMS320DM8147

速缓存

• DSP / EDMA 内存管理单元 (DEMMU) – 将 C674x DSP 和 EDMA TC 内存存取映射至系

统地址

• 128k 字节片上内存控制器 (OCMC) RAM

• 成像子系统 (ISS) – 摄像机传感器连接

• 用于素材（高达 16 位）及 BT.656/BT.1120

（8 / 16 位）的并行连接

– 用于处理来自摄像机传感器的图像/视频数据的图

像传感器接口 (ISIF)

– 图像尺寸调节器 (Resizer)

• 将图像/视频尺寸从 1/16x 重设为 8x

• 同时生成两个不同的变尺寸输出

• 可编程高分辨率视频图像协处理 (HDVICP v2) 引擎 – 编码、解码、代码转换操作 – H.264、MPEG2、VC1、MPEG4、SP /

ASP、JPEG / MJPEG

• 媒体控制器 – 用于控制 HDVPSS、HDVICP2 和 ISS

• SGX530 3D 图形引擎 – 可提供高达 18 MPoly/sec 的多边形生成速率 – 通用型可扩缩渲染引擎 – 具有 Direct3D Mobile、OpenGL ES 1.1 和

2.0、OpenVG 1.0、OpenMax API支持能力

– 高级几何 DMA 驱动型操作 – 可编程 HQ 图像抗混叠处理

• 字节序 (Endianness) – ARM / DSP 指令/数据——小端 (Little Endian)

• HD 视频处理子系统 (HDVPSS) – 两个148.5MHz HD 视频捕获输入

• 一个 16 / 24 位输入，可拆分为两个 8 位 SD

捕获端口

• 一个8 / 16 /24 位输入

• 仅一个 8位输入

– 两个148.5MHz HD 视频显示输出

• 一个 16 / 24 / 30位输出和一个 16 / 24 位输出 – 复合或 S 视频模拟输出 – 可支持MacroVision®

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2DSP/BIOS, XDS are trademarks of Texas Instruments. 3All other trademarks are the property of their respective owners.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right English Data Sheet: SPRS647 to change or discontinue these products without notice.

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– 数字 – 高级视频处理功能，例如：扫描/格式/速率转换 • 双控制器局域网 (DCAN) 模块 – 3 个图形层及组合器 – CAN Version 2 Part A、B

• 双 32 位 LPDDR / DDR2 / DDR3 SDRAM 接口 • 4 个集成电路间 (I2C BUS™) 端口 – 支持高达 LPDDR-400、DDR2-667 和 • 6 个多通道音频串行端口 (McASP)

– 总共有多达 8 个 x8 器件 2 GB的总地址空间 – 动态内存管理器 (DMM)

• 通用内存控制器 (GPMC) – 8 / 16 位多路复用地址/数据总线 – 512M 字节的总地址空间在多达 8 条片选线之间

– 至 NOR 闪存、NADN 闪存（具有 BCH / 汉明

– 位于 GPMC 外部的错误定位器模块 (ELM) 负责

– 灵活的异步协议控制，用于至

• 增强型直接存储器存取 (EDMA) 控制器 – 4 个传输控制器 – 64 / 8 个独立的 DMA / QDMA 通道

• 具有双 10/100/1000 Mbps 外部接口 (I/F) 的以太网

开关 (EMAC SW)

– 符合 IEEE 802.3 标准（仅 3.3V I/O） – MII / RMII / GMII / RGMII 媒体独立接口 (I/F) – 管理数据 I/O (MDIO) 模块 – 复位隔离 – IEEE-1588 时间戳和工业以太网协议

• 具有集成型 PHY 的双 USB 2.0 端口 – USB 2.0 高速/全速客户机 – UCB 2.0 高速/全速/低速主机，或 OTG – 支持端点 0-15

• 一个具有集成型 PHY 的 PCI Express 2.0 端口 – 具有一条 5.0 GT/s 线道的单端口 – 可配置为根联合体 (root complex) 或端点

• 8 个 32 位通用定时器（定时器 1～8）

• 1 个系统看门狗定时器 (WDT 0)

• 6 个可配置的 UART / IrDA / CIR 模块 – 具有调制解调器控制信号的 UART0 – 支持高达 3.6864Mbps 的 UART0 / 1 / 2 – 支持高达 12Mbps 的 UART3 / 4 / 5 – SIR、MIR、FIR (4.0 MBAUD) 及CIR

• 4 个串行外设接口 (SPI) [高达 48MHz] – 各具有 4 条片选线

• 3 个 MMC / SD / SDIO 串行接口 [高达48MHz]

HDMI 1.3 发送器 – 3 个接口支持高达1 / 4 / 8 位模式

DDR3-667 的内存

• 可编程多区内存映射及交错

• 实现了高效 2D 成组存取 (Block Accesses)

• 支持 0°、90°、180° 或 270° 取向的平铺对象

和镜像

• 优化了交错存取

进行分配

误码检测功能）、SRAM 和伪 SRAM 的无缝接口

提供用于 NAND 的高达 16 位 / 512 字节的硬件ECC

FPGA、CPLD、ASIC 等的接口

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– 两个 10 通道串化器发送/接收端口 – 四个 4 通道串化器发送/接收端口 – 具有用于 S/PDIF 的 DIT 能力（所有端口）

• 多通道缓冲串行端口 (McBSP) – 高达 48MHz 的发送/接收时钟 – 两个时钟区和两个串行数据引脚 – 支持 TDM、I2S 及相似的格式

• 具有集成型 PHY 的串行 ATA (SATA) 3.0 Gbps 控

制器

– 至一个硬盘驱动器的直接接口 – 来自多达 32 个入口的硬件辅助本机命令排队

(NCQ)

– 支持端口乘法器和基于命令的交换

• 实时时钟 (RTC) – 一次性或周期性中断发生

• 多达 128 个通用 I/O (GPIO) 引脚

• 一个具有 128 个硬件信号标志 (Hardware

Semaphores) 的自旋锁模块 (Spin Lock Module)

• 一个具有 12 个邮箱的邮箱模块

• 片上 ARM ROM 引导加载程序 (RBL)

• 电源、复位和时钟管理 – SmartReflex™ 技术 (Level 2b) – 多个独立的内核电源域 (power domain) – 多个独立的内核电压域 (voltage domain) – 每个电压域可支持 3 个工作点 (OPP120 / 100 /

50)

– 针对子系统及外设的时钟启用/停用控制

• 用于调试的 32KB 嵌入式跟踪缓冲器 (Embedded Trace Buffer™ [ETB™] ) 和 5 引脚跟踪接口

• 可兼容 IEEE-1149.1 (JTAG)

• 684 引脚无铅型 BGA 封装（CYE 后缀），0.8mm

焊球间距，并采用 Via Channel™ 技术来降低PCB 成本

• 45nm CMOS 工艺技术

• 适合通用 I/O 的1.8V / 3.3V 双电压缓冲器

• 应用： – HD 会议电视——Skype 端点 – 视频监控 DVR、IP 网络摄像机 – 数字标牌 – 媒体播放器/适配器 – 移动医疗成像 – 网络投影机 – 家用音频/视频设备

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1.2 说明

TMS320DM814xDaVinci™ 数字媒体处理器是高度集成的可编程平台，它利用 TI 的DaVinci技术来满足下列应用的处理要求：HD 会议电视——Skype 端点、视频监控DVR、IP 网络摄像机、数字标牌、媒体播放器/ 适配器、移动医疗成像、网络投影机以及家用音频/视频设备，等等。

凭借全集成化混合处理器解决方案所具有的极大灵活性，该器件使得原始设备制造商 (OEM) 和原始设计制造商 (ODM) 能够将拥有稳健的操作系统支持、丰富的用户界面以及高处理性能的设备迅速投放市场。另外，这款器件还将可编程视频及音频处理与高度集成的外设集 (peripheral set) 组合在了一起。

TMS320DM814x DaVinci™ 数字媒体处理器还使 OEM 和 ODM 拥有了新的处理器可扩缩性及软件重用性水平。对于在设计中使用 AM387x、并发现有机会制作一款具有附加功能的相似产品的 OEM 或 ODM 而言，他们可以升级 (scale up) 为采用由德州仪器 (TI) 提供的引脚兼容和软件兼容的TMS320C6A814x 或 TMS320DM814x 处理器。 TMS320C6A814x Integra™ DSP+ARM 处理器给 AM38x 上的硬件增添了一个强大的 C674x™ DSP 内核，而 TMS320DM814x DaVinci™ 数字媒体处理器则将一个视频编码器/解码器添加至TMS320C6A814x 上已有的硬件。此外，对于已经使用了AM387x、C6A814x 或 DM814x，并发现需要速度更快的 ARM 和/或 DSP内核性能的 OEM 或 ODM 来说，他们可以升级至具有较高内核速度且软件兼容的 AM389x、TMS320C6A816x 或 TMS320DM816x 器件。

可编程性由一个具有 Neon™ 扩展的 ARM Cortex™ A8 RISC CPU、TI C674x VLIW 浮点 DSP 内核、及高分辨率视频/成像协处理器提供。 ARM 使得开发人员能够将控制功能与在 DSP 和协处理器上进行编程的

A/V 算法分离开来，从而降低了系统软件的复杂程度。具有 Neon™ 浮点扩展的 ARM Cortex A8 32 位 RISC 微处理器包括： 32K 字节 (KB) 的指令高速缓存； 32KB 的数据高速缓存； 512KB 的 L2 高速缓存；48KB 的引导 ROM；和 64KB 的 RAM。

ZHCS057–MARCH 2011

丰富的外设集提供了控制外围设备以及与外部处理器进行通信的能力。如需了解每个外设的详细信息，请参见本文件中的有关章节以及相关联的外设参考指南。外设集包括：HD 视频处理子系统；具有 MII / RMII / GMII / RGMII 和 MDIO 接口的双端口千兆位以太网 MAC (10/100/1000 Mbps)，可支持 IEEE-1588 时间戳和工业以太网协议；两个具有集成型 2.0 PHY 的 USB 端口； PCIe x1 GEN2 兼容型接口；两个10 通道串化器 McASP 音频串行端口（具有 DIT 模式）； 4 个四通道串化器 McASP 音频串行端口（具有 DIT 模式）；一个 McBSP 多通道缓冲串行端口；6 个可支持 IrDA 和 CIR 的 UART； 4 个 SPI 串行接口；3 个

MMC / SD / SDIO 串行接口；4 个 I2C 主/从接口；1 个并行相机接口 (CAM)；多达 128 个通用 IO (GPIO)； 8 个 32 位通用定时器；系统看门狗定时器；双 LPDDR / DDR2 /DDR3 SDRAM 接口；灵活的 8 / 16位异步存储器接口；2 个控制器局域网 (DCAN) 模块； 1 个自旋锁；邮箱；以及串行硬盘驱动器接口 (SATA 300)。

TMS320DM814x DaVinci™ 数字媒体处理器还包括一个高分辨率视频/成像协处理器 2 (HDVICP2) 和一个 SGX530 3D 图形引擎（以分担许多原本由 DSP 内核所承担的视频和成像处理任务），从而使得能够将更多

的 DSP 处理性能用于通用视频及成像算法。此外，它还拥有一整套用于 ARM 及 DSP 的开发工具。这些开发工具包括 C 语言编译器、用于简化程序设计和调度的 DSP 汇编优化器以及旨在将可视性引入源代码执行的 Microsoft® Windows™ 调试程序界面。

C674x DSP 内核是 TMS320C6000™ DSP 平台中的新型高性能浮点 DSP 系列。 C674x 浮点 DSP 处理器采用具有 EDC 的 32KB L1 程序内存和 32KB 的 L1 数据内存。多达 32KB 的 L1P 可被配置为程序高速缓存。剩余的是不可高速缓存的无等待状态程序内存。多达 32KB 的 L1P 可被配置为程序高速缓存。剩余的是不可高速缓存的无等待状态程序内存。 DSP 具有带 ECC 的 256KB L2 RAM，它可被规定为 SRAM、L2 高速缓存或此二者的某种组合。所有的 C674x L3 及片存储器存取均通过一个 MMU 来选定路由。

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DSP Subsystem

C674x

TM

DSP CPU

32KB

L1 Pgm

32 KB

L1 Data

256 KB L2 Cache

Video Processing

Subsystem

Video Capture

Display Processing

HD OSD SD OSD

HD VENC SD VENC

HDMI Xmt

SD DACs

AET

ICE Crusher

DSP/EDMA MMU

McASP

(6)

McBSP

(m)DDR2/3

32-bit

(2)

GPMC

+

ELM

EDMA

EMAC

(R)(G)MII

(2)

MDIO

USB 2.0

Ctlr/PHY

(2)

PCIe 2.0 (One x1

Port)

UART

(6)

SPI

(4)

I

2

C

(4)

System Control

Serial Interfaces

Program/Data Storage

Connectivity

Peripherals

System Interconnect

GP Timer

(8)

Watchdog

Timer

Real-Time

Clock

PRCM

JTAG

128 KB On-Chip RAM

High Definition Video Image

Coprocessor (HDVICP)

Media Controller

Imaging

Subsystem

Parallel Cam Input

CSI2 Serial Input

IPIPE

Resizer

H3A

MMC/SD/

SDIO

(3)

DCAN

(2)

ARM Subsystem

Cortex

TM

-A8

CPU

32 KB

I-Cache

32 KB

D-Cache

256 KB L2 Cache

Boot ROM

48 KB

RAM

64 KB

NEON

FPU

Spin Lock

Mailbox

Face Detect (FD)

TMS320DM8148, TMS320DM8147

ZHCS057–MARCH 2011

1.3 功能框图

图 1-1 shows the functional block diagram of the device.

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图 1-1. TMS320DM814x DaVinci™ Digital Media Processors Functional Block Diagram

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1 高性能片上系统 (SoC) ................................... 1

1.1 特性 .................................................. 1 7.2 Power .............................................. 166

1.2 说明 .................................................. 3

1.3 功能框图 ............................................. 4

2 Device Overview ........................................ 6

2.1 Device Comparison .................................. 6

2.2 Device Characteristics ............................... 6

2.3 Device Compatibility ................................. 8

2.4 ARM® Cortex™-A8 Microprocessor Unit (MPU)

Subsystem Overview ................................ 8

2.5 C674x™ DSP Overview ............................ 10

2.6 DSP/EDMA Memory Management Unit (MMU) .... 14

2.7 Media Controller Overview ......................... 15

2.8 HDVICP2 Overview ................................. 15

2.9 SGX530 Overview .................................. 16

2.10 Spinlock Module Overview ......................... 16

2.11 Mailbox Module Overview .......................... 17

2.12 Memory Map Summary ............................. 18

3 Device Pins ............................................. 26

3.1 Pin Maps ............................................ 26

3.2 Terminal Functions ................................. 35

4 Device Configurations .............................. 144

4.1 Control Module Registers ......................... 144

4.2 Boot Modes ....................................... 144 8.17 Peripheral Component Interconnect Express (PCIe)

4.3 Pin Multiplexing Control ........................... 145

4.4 Handling Unused Pins ............................ 155

4.5 DeBugging Considerations ........................ 155

5 System Interconnect ................................ 157

6 Device Operating Conditions ...................... 161

6.1 Absolute Maximum Ratings Over Operating Case Temperature Range

(Unless Otherwise Noted) ......................... 161

6.2 Recommended Operating Conditions ............. 162

6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating

Temperature (Unless Otherwise Noted) .......... 164

7 Power, Reset, Clocking, and Interrupts ......... 166

7.1 Power, Reset and Clock Management (PRCM)

ZHCS057–MARCH 2011

Module ............................................ 166

7.3 Reset .............................................. 173

7.4 Clocking ........................................... 181

7.5 Interrupts .......................................... 196

8 Peripheral Information and Timings ............. 203

8.1 Parameter Information ............................ 203

8.2 Recommended Clock and Control Signal Transition

Behavior ........................................... 204

8.3 Controller Area Network Interface (DCAN) ....... 204

8.4 EDMA ............................................. 206

8.5 Emulation Features and Capability ............... 209

8.6 Ethernet MAC Switch (EMAC SW) ................ 213

8.7 General-Purpose Input/Output (GPIO) ............ 225

8.8 General-Purpose Memory Controller (GPMC) and

Error Location Module (ELM) ..................... 228

8.9 High-Definition Multimedia Interface (HDMI) ...... 245

8.10 High-Definition Video Processing Subsystem

(HDVPSS) ......................................... 248

8.11 Inter-Integrated Circuit (I2C) ...................... 254

8.12 Imaging Subsystem (ISS) ......................... 258

8.13 LPDDR/DDR2/DDR3 Memory Controller ......... 261

8.14 Multichannel Audio Serial Port (McASP) .......... 294

8.15 Multichannel Buffered Serial Port (McBSP) ....... 302

8.16 MultiMedia Card/Secure Digital/Secure Digital Input

Output (MMC/SD/SDIO) ........................... 307

..................................................... 310

8.18 Serial ATA Controller (SATA) ..................... 315

8.19 Serial Peripheral Interface (SPI) .................. 319

8.20 Timers ............................................. 326

8.21 Universal Asynchronous Receiver/Transmitter

(UART) ............................................ 328

8.22 Universal Serial Bus (USB2.0) .................... 330

9 Device and Documentation Support ............. 338

9.1 Device Support .................................... 338

9.2 Documentation Support ........................... 339

9.3 Community Resources ............................ 339

10 Mechanical ............................................ 340

10.1 Thermal Data for CYE ............................. 340

10.2 Packaging Information ............................ 340

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2 Device Overview

2.1 Device Comparison

Table 2-1 shows a comparison between devices, highlighting the differences.

FEATURES

SGX530 YES (1) NONE

2.2 Device Characteristics

Table 2-2 provides an overview of the TMS320DM814x DaVinci™ Digital Media Processors, which

includes significant features of the device, including the capacity of on-chip RAM, peripherals, and the package type with pin count.

HARDWARE FEATURES DM841x

Peripherals Not all peripherals pins

are available at the same time (for more details, see the Device Configurations section).

HD Video Processing Subsystem (HDVPSS) and

Imaging Subsystem (ISS) LPDDR/DDR2/3 Memory Controller 2 (32-bit Bus Widths) GPMC + ELM

EDMA 10/100/1000 Ethernet MAC Switch with Management

Data Input/Output (MDIO) USB 2.0 PCI Express 2.0 1 Port (1 5.0GT/s lane)

Timers and

UART control)

SPI 4 (Supports 4 slave devices)

MMC/SD/SDIO

I2C 4 (Master/Slave) Media Controller Controls HDVPSS, HDVICP2, and ISS

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Table 2-1. DM814x Device Comparison

DEVICES

TMS320DM8148 TMS320DM8147

Table 2-2. Characteristics of the Processor

1 16-/24-bit HD Capture Port or

2 8-bit SD Capture Ports

and

1 8/16/24-bit HD Capture Port

and

1 8-bit SD Capture Port

1 16-/24-/30-bit HD Display Port or

1 HDMI 1.3 Transmitter

and

1 16-/24-bit HD Display Port

and

2 SD Video DACs

1 Parallel Camera Input for Raw (up to 16-bit)

and BT.656/BT.1120 (8/16-bit)

Asynchronous (8-/16-bit bus width)

RAM, NOR, NAND

64 Independent Channels

8 QDMA Channels

1 (with 2 MII/RMII/GMII/RGMII Interfaces)

2 (Supports High- and Full-Speed as a Device and

High-, Full-, and Low-Speed as a Host, or OTG)

8 (32-bit General purpose)

1 (System Watchdog)

6 (with SIR, MIR, FIR, CIR support and RTS/CTS flow

(UART0 Supports Modem Interface)

1 (1-bit or 4-bit or 8-bit modes)

and

1 (8-bit mode) or

2 (1-bit or 4-bit modes)

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Table 2-2. Characteristics of the Processor (continued)

HARDWARE FEATURES DM841x

McASP McBSP 1 (2 Data Pins, Transmit/Receive)

Controller Area Network (DCAN) 2 Serial ATA (SATA) 3.0 Gbps 1 (Supports 1 Hard Disk Drive) RTC 1 GPIO Up to 128 pins Parallel Camera Interface (CAM) 1 Spin Lock Module 1 (up to 128 H/W Semaphores) Mailbox Module 1 (with 12 Mailboxes) Size (Bytes) 1120KB RAM, 48KB ROM

On-Chip Memory Organization 48KB Boot ROM

CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x1401 C674x Megamodule

Revision JTAG BSDL ID DEVICE_ID Register (address location: 0x4814_0600)

CPU Frequency MHz

Cycle Time ns

Voltage

Package 23 x 23 mm 684-Pin BGA (CYE) [with Via Channel™ Technology] Process Technology μm 0.045 μm

Product Status

(1)

(1) PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

Revision ID Register (MM_REVID[15:0]) 0x0000

Core Logic (V) 0.83V – 1.2V I/O (V) 1.5 V, 1.8 V, 3.3 V

Product Preview (PP), Advance Information (AI), PP or Production Data (PD)

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6 (10/10/4/4/4/4 Serializers, Each with

Transmit/Receive and DIT capability)

ARM

32KB I-cache

32KB D-cache

512KB L2 Cache

DSP

32KB L1 Program (L1P)/Cache (up to 32KB) with EDC

32KB L1 Data (L1D)/Cache (up to 32KB)

256KB Unified Mapped RAM/Cache (L2) with ECC

ADDITIONAL SHARED MEMORY

128KB On-chip RAM

see Section 8.5.3.1, JTAG ID (JTAGID) Register

Description

ARM® Cortex™-A8 720 MHZ

DSP 600 MHz

ARM® Cortex™ -A8 1.39 ns

DSP 1.66 ns

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Arbiter

128

ICECrusher

Trace

Debug

48KB ROM

64KB RAM

ARM Cortex-A8

Interrupt Controller

(AINTC)

L3

DMM

128

64

128 128

128

PLL_ARM

128

System Events

32

128

ARM Cortex-A8

NEONETM

512KB L2$

32KB L1I$ 32KB L1D$

DEVOSC

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2.3 Device Compatibility

2.4 ARM® Cortex™-A8 Microprocessor Unit (MPU) Subsystem Overview

The ARM® Cortex™-A8 Subsystem is designed to give the ARM Cortex-A8 Master control of the device. In general, the ARM Cortex-A8 is responsible for configuration and control of the various subsystems, peripherals, and external memories.

The ARM Cortex-A8 Subsystem includes the following features:

• ARM Cortex-A8 RISC processor: – ARMv7 ISA plus Thumb2™, JazelleX™, and Media Extensions – Neon™ Floating-Point Unit – Enhanced Memory Management Unit (MMU) – Little Endian – 32KB L1 Instruction Cache – 32KB L1 Data Cache – 512KB L2 Cache

• CoreSight Embedded Trace Module (ETM)

• ARM Cortex-A8 Interrupt Controller (AINTC)

• Embedded PLL Controller (PLL_ARM)

• 64KB Internal RAM

• 48KB Internal Public ROM

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Figure 2-1 shows the ARM Cortex-A8 Subsystem for the device.

For more detailed information on the ARM Cortex-A8 Subsystem, see the ARM Cortex-A8 Subsystem User's Guide (Literature Number: TBD).

2.4.1 ARM Cortex-A8 RISC Processor

The ARM Cortex-A8 Subsystem integrates the ARM Cortex-A8 processor. The ARM Cortex-A8 processor is a member of ARM Cortex family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM Cortex-A8 processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM Cortex-A8 processor has a Harvard architecture and provides a complete high-performance subsystem, including:

• ARM Cortex-A8 Integer Core

• Superscalar ARMv7 Instruction Set

• Thumb-2 Instruction Set

Figure 2-1. ARM Cortex-A8 Subsystem

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• Jazelle RCT Acceleration

• CP14 Debug Coprocessor

• CP15 System Control Coprocessor

• NEON™ 64-/128-bit Hybrid SIMD Engine for Multimedia

• Enhanced VFPv3 Floating-Point Coprocessor

• Enhanced Memory Management Unit (MMU)

• Separate Level-1 Instruction and Data Caches

• Integrated Level-2 Cache

• 128-bit Interconnector-to-System Memories and Peripherals

• Embedded Trace Module (ETM).

2.4.2 Embedded Trace Module (ETM)

To support real-time trace, the ARM Cortex-A8 processor provides an interface to enable connection of an embedded trace module (ETM). The ETM consists of two parts:

• The Trace port which provides real-time trace capability for the ARM Cortex-A8.

• Triggering facilities that provide trigger resources, which include address and data comparators,

counter, and sequencers.

The ARM Cortex-A8 trace port is not pinned out and is, instead, only connected to the system-level Embedded Trace Buffer (ETB). The ETB has a 32KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data.

ZHCS057–MARCH 2011

For more details on the ETM, see Section 8.5.2, Trace.

2.4.3 ARM Cortex-A8 Interrupt Controller (AINTC)

The ARM Cortex-A8 subsystem contains an interrupt controller (AINTC) that prioritizes all service requests from the system peripherals and generates either IRQ or FIQ to the ARM Cortex-A8 processor. For more details on the AINTC, see Section 7.5.1, ARM Cortex-A8 Interrupts.

2.4.4 ARM Cortex-A8 PLL (PLL_ARM)

The ARM Cortex-A8 subsystem contains an embedded PLL Controller (PLL_ARM) for generating the subsystem’s clocks from the DEV Clock input. For more details on the PLL_ARM, see Section 7.4, Clocking.

2.4.5 ARM MPU Interconnect

The ARM Cortex-A8 processor is connected through the arbiter to both an L3 interconnect port and a DMM port. The DMM port is 128-bits wide and provides the ARM Cortex-A8 direct access to the DDR memories, while the L3 interconnect port is 64-bits wide and provides access to the remaining device modules.

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Instruction Fetch

C674x

Fixed/Floating Point CPU

Register

File A

Register

File B

Cache Control

Memory Protect

Bandwidth Mgmt

L1P

256

Cache Control

Memory Protect

Bandwidth Mgmt

L1D

64 64

8 x 32

32K Bytes L1D RAM/

Cache

32K Bytes L1P RAM/

Cache

w/EDC

256

Cache Control

Memory Protect

Bandwidth Mgmt

L2

256K Bytes

L2 RAM

w/ ECC

256

HDVICP2 Host

SL2 Port

256

CFG

MDMA SDMA

EMC

Power Down

Interrupt

Controller

IDMA

256

128

L3 (Fast)

Interconnect

128

32

L3 (Fast)

Interconnect

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2.5 C674x™ DSP Overview

The DSP Subsystem includes the following features:

• C674x DSP CPU

• 32KB L1 Program (L1P)/Cache (up to 32KB) with Error Detection Circuitry (EDC)

• 32KB L1 Data (L1D)/Cache (up to 32KB)

• 256KB Unified Mapped RAM/Cache (L2) with Error Correction Circuitry (ECC)

• Direct Connection to the HDVICP2 Host SL2 Port

• Little Endian

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For more details on the C674x DSP, see the C674x DSP Subsystem User's Guide (Literature Number: TBD).

Figure 2-2. C674x Megamodule Block Diagram

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2.5.1 C674x DSP CPU Description

The C674x central processing unit (CPU) consists of eight functional units, two register files, and two data paths as shown in Figure 2-2. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.

The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the C67x+ core.

Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x 32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four 16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The 32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on a variety of signed and unsigned 32-bit data types.

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The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.

The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2 comparisons were only available on the .L units. On the C674x core they are also available on the .S unit which increases the performance of algorithms that do searching and sorting. Finally, to increase data packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack instructions return parallel results to output precision including saturation support.

Other new features include:

• SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.

• Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x compiler can restrict the code to use certain registers in the register file. This compression is performed by the code generation tools.

• Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field multiplication.

• Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and from system events (such as a watchdog time expiration).

• Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with read, write, and execute permissions.

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•

Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.

For more details on the C674x CPU and its enhancements over the C64x architecture, see the following documents:

• TMS320C674x DSP CPU and Instruction Set User's Guide (literature number SPRUFE8)

• TMS320C674x DSP Megamodule Reference Guide (literature number SPRUFK5)

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src2

.D1

.M1

.S1

.L1

long src

odd dst

src2

src1

even dst

odd dst

dst1

dst

src2

long src

DA1

ST1b

LD1b

LD1a

ST1a

Data path A

Odd

register

file A

(A1, A3,

A5...A31)

Odd

register

file B

(B1, B3,

B5...B31)

.D2

src1

dst

src2

DA2

LD2a LD2b

src2

.M2

src1

dst1

.S2

src1

even dst

long src

odd dst

ST2a

ST2b

long src

.L2

even dst

odd dst

src1

Data path B

Control Register

32 MSB

32 LSB

dst2

32 MSB

32 LSB

2x

1x

32 LSB

32 MSB

32 LSB

32 MSB

dst2

8

32

Even

register

file A

(A0, A2,

A4...A30)

Even

register

file B

(B0, B2,

B4...B30)

(D)

A. .M unit, is 32 MSB. B On .M unit, is 32 LSB. C. On C64x CPU .M unit, is 32 bits; on C64x+ CPU .M unit, is 64 bits. D. On .L and .S units, connects to odd register files and even connects to even register files

dst2

dst1

src2 src2

odd dst dst

(D)

(A) (B)

(C)

(B)

(A)

(D)

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Figure 2-3. TMS320C674x CPU (DSP Core) Data Paths

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2.6 DSP/EDMA Memory Management Unit (MMU)

All C674x accesses through its MDMA port will be directed through the DSP/EDMA MMU module where they are remapped to physical system addresses. This protects the ARM Cortex-A8 memory regions from accidental corruption by C674x code and allows for direct allocation of buffers in user space without the need for translation between ARM and DSP applications.

In addition, accesses by the EDMA TC0 and TC1 may optionally be routed through the DSP/EDMA MMU. This allows EDMA Channels 0 and 1 to be used by the DSP to perform transfers using only the known virtual addresses of the associated buffers. The MMU_CFG register in the Control Module is used to enable/disable use of the DSP/EDMA MMU by the EDMA TCs.

For more details on the DSP/EDMA MMU features, see the TBD Memory Management Unit (MMU) User's Guide (Literature Number: TBD).

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2.7 Media Controller Overview

The Media Controller has the responsibility of managing the HDVPSS, HDVICP2, and ISS modules. For more details on the Media Controller, see the TBD Subsystem User's Guide (Literature Number:

TBD).

2.8 HDVICP2 Overview

The HDVICP2 is a Video Encoder/Decoder hardware accelerator supporting a range of encode, decode, and transcode operations for most major video codec standards. The main video Codec standards supported in hardware are MPEG1/2/4 ASP/SP, H.264 BL/MP/HP, VC-1 SP/MP/AP, RV9/10, AVS-1.0, and ON2 VP6.2/VP7.

The HDVICP2 hardware accelerator is composed of the following elements:

• Motion estimation acceleration engine

• Loop filter acceleration engine

• Sequencer, including its memories and an interrupt controller

• Intra-prediction estimation engine

• Calculation engine

• Motion compensation engine

• Entropy coder/decoder

• Video Direct Memory Access (DMA)

• Synchronization boxes

• Shared L2 controller

• Local interconnect

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For more details on the HDVICP2 see the HDVICP2 User's Guide (Literature Number: TBD).

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2.9 SGX530 Overview

The SGX530 is a vector/3D graphics accelerator for vector and 3-dimensional (3D) graphics applications. The SGX530 graphics accelerator efficiently processes a number of various multimedia data types concurrently:

• Pixel data

• Vertex data

• Video data

This is achieved using a multi-threaded architecture using two levels of scheduling and data partitioning enabling zero overhead task switching.

The SGX530 has the following major features:

• Vector graphics and 3D graphics

• Tile-based architecture

• Universal Scalable Shader Engine (USSE™) - multi-threaded engine incorporating pixel and vertex

shader functionality

• Advanced shader feature set - in excess of Microsoft VS3.0, PS3.0, and OpenGL2.0

• Industry standard API support - OpenGL ES 1.1 and 2.0, OpenVG v1.1

• Fine-grained task switching, load balancing, and power management

• Advanced geometry DMA driven operation for minimum CPU interaction

• Programmable high-quality image anti-aliasing

• POWERVR SGX core MMU for address translation from the core virtual address to the external

physical address (up to 4GB address range)

• Fully-virtualized memory addressing for OS operation in a unified memory architecture

• Advanced and standard 2D operations [e.g., vector graphics, block level transfers (BLTs), raster

operations (ROPs)]

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For more details on the SSM, see the ARM Cortex-A8 Subsystem User's Guide (Literature Number: TBD).

2.10 Spinlock Module Overview

The Spinlock module provides hardware assistance for synchronizing the processes running on multiple processors in the device:

• ARM Cortex-A8 processor

• C674x DSP

• Media Controller .

The Spinlock module implements 128 spinlocks (or hardware semaphores) that provide an efficient way to perform a lock operation of a device resource using a single read-access, avoiding the need for a read-modify-write bus transfer of which the programmable cores are not capable.

For more detailed information on the Spinlock Module, see the TBD User's Guide (Literature Number: TBD).

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Mailbox Mailbox Mailbox Mailbox Mailbox Mailbox

L4

Interconnect

Interrupt Interrupt Interrupt Interrupt

Mailbox Module

ARM Cortex-A8 C674x+ DSP Media Controller

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2.11 Mailbox Module Overview

The device Mailbox module facilitates communication between the ARM Cortex-A8, C674x DSP, and the Media Controller. It consists of twelve mailboxes, each supporting a 1-way communication between two of the above processors. The sender sends information to the receiver by writing a message to the mailbox registers. Interrupt signaling is used to notify the receiver that a message has been queued or to notify the sender about an overflow situation.

The Mailbox module supports the following features (see Figure 2-4):

• 12 mailboxes

• Flexible mailbox-to-processor assignment scheme

• Four-message FIFO depth for each message queue

• 32-bit message width

• Message reception and queue-not-full notification using interrupts

• Four interrupts (one to ARM Cortex-A8, one to C674x, and two to Media Controller)

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For more detailed information on the Mailbox Module, see the TBD User's Guide (Literature Number: TBD).

Figure 2-4. Mailbox Module Block Diagram

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2.12 Memory Map Summary

The device has multiple on-chip memories associated with its two processors and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters.

2.12.1 L3 Memory Map

Table 2-3 shows the L3 memory map for all system masters (including Cortex-A8), except for the C674x

DSP. Table 2-4 shows the memory map for the C674x DSP. For more details on the interconnect topology and connectivity across the L3 and L4 interconnects, see

Section 5, System Interconnect.

START ADDRESS END ADDRESS

(HEX) (HEX)

0x0000_0000 0x1FFF_FFFF 512MB GPMC 0x2000_0000 0x2FFF_FFFF 256MB PCIe 0x3000_0000 0x3FFF_FFFF 256MB Reserved 0x4000_0000 0x4001_FFFF 128KB Reserved

0x4002_0000 0x4002_BFFF 48K 0x4002_C000 0x402E_FFFF 2832K Reserved 0x402F_0000 0x402F_FFFF 64KB

0x4030_0000 0x4031_FFFF 128KB OCMC SRAM

0x4032_0000 0x407F_FFFF 4992KB Reserved

0x4080_0000 0x4083_FFFF 256KB C674x™ L2 RAM

0x4084_0000 0x40DF_FFFF 5888KB Reserved 0x40E0_0000 0x40E0_7FFF 32KB C674x L1P Cache/RAM 0x40E0_8000 0x40EF_FFFF 992KB Reserved 0x40F0_0000 0x40F0_7FFF 32KB C674x L1D Cache/RAM 0x40F0_8000 0x40FF_FFFF 992KB Reserved

0x4100_0000 0x41FF_FFFF 16MB Reserved

0x4200_0000 0x43FF_FFFF 32MB Reserved

0x4400_0000 0x443F_FFFF 4MB L3 Fast configuration registers

0x4440_0000 0x447F_FFFF 4MB L3 Mid configuration registers

0x4480_0000 0x44BF_FFFF 4MB L3 Slow configuration registers 0x44C0_0000 0x45FF_FFFF 20MB Reserved

0x4600_0000 0x463F_FFFF 4MB McASP0 Data Peripheral Registers

0x4640_0000 0x467F_FFFF 4MB McASP1 Data Peripheral Registers

0x4680_0000 0x46BF_FFFF 4MB McASP2 Data Peripheral Registers 0x46C0_0000 0x46FF_FFFF 4MB HDMI

0x4700_0000 0x473F_FFFF 4MB McBSP

0x4740_0000 0x477F_FFFF 4MB USB

0x4780_0000 0x4780_FFFF 64KB Reserved

0x4781_0000 0x4781_1FFF 8KB MMCSD2

0x4781_2000 0x47BF_FFFF 4MB - 72KB Reserved 0x47C0_0000 0x47FF FFFF 4MB Reserved

0x4800_0000 0x48FF_FFFF 16MB L4 Slow Peripheral Domain

0x4900_0000 0x490F_FFFF 1MB EDMA TPCC Registers

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Table 2-3. L3 Memory Map

SIZE DESCRIPTION

ARM Cortex-A8 ROM (Accessible by ARM Cortex-A8 only)

ARM Cortex-A8 RAM (Accessible by ARM Cortex-A8 only)

(see Table 2-6)

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Table 2-3. L3 Memory Map (continued)

START ADDRESS END ADDRESS

(HEX) (HEX)

0x4910_0000 0x497F_FFFF 7MB Reserved

0x4980_0000 0x498F_FFFF 1MB EDMA TPTC0 Registers

0x4990_0000 0x499F_FFFF 1MB EDMA TPTC1 Registers 0x49A0_0000 0x49AF_FFFF 1MB EDMA TPTC2 Registers 0x49B0_0000 0x49BF_FFFF 1MB EDMA TPTC3 Registers 0x49C0_0000 0x49FF_FFFF 4MB Reserved 0x4A00_0000 0x4AFF_FFFF 16MB L4 Fast Peripheral Domain

0x4B00_0000 0x4BFF_FFFF 16MB Emulation Subsystem 0x4C00_0000 0x4CFF_FFFF 16MB DDR0 Registers 0x4D00_0000 0x4DFF_FFFF 16MB DDR1 Registers 0x4E00_0000 0x4FFF_FFFF 32MB DDR DMM Registers

0x5000_0000 0x50FF_FFFF 16MB GPMC Registers

0x5100_0000 0x51FF_FFFF 16MB PCIE Registers

0x5200_0000 0x54FF_FFFF 48MB Reserved

0x5500_0000 0x55FF_FFFF 16MB Media Controller

0x5600_0000 0x56FF_FFFF 16MB SGX530

0x5700_0000 0x57FF_FFFF 16MB Reserved

0x5800_0000 0x58FF_FFFF 16MB HDVICP2 Configuration

0x5900_0000 0x59FF_FFFF 16MB HDVICP SL2 0x5A00_0000 0x5BFF_FFFF 32MB Reserved 0x5C00_0000 0x5DFF_FFFF 32MB ISS 0x5E00_0000 0x5FFF_FFFF 32MB Reserved

0x6000_0000 0x7FFF_FFFF 512MB DDR DMM Tiler Window (see Table 2-7)

0x8000_0000 0xFFFF_FFFF 2GB DDR

0x1 0000 0000 0x1 FFFF FFFF 4GB DDR DMM Tiler Extended Address Map

SIZE DESCRIPTION

(see Table 2-5)

(ISS and HDVPSS only) [see Table 2-7]

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2.12.2 C674x Memory Map

Table 2-4 shows the memory map for the C674x DSP.

START ADDRESS END ADDRESS

(HEX) (HEX)

0x0000_0000 0x003F_FFFF 4MB Reserved 0x0040_0000 0x0043_FFFF 256KB HDVICP SL2 0x0044_0000 0x007F_FFFF 3840KB Reserved 0x0080_0000 0x0083_FFFF 256KB C674x™ L2 RAM

0x0084_0000 0x00DF_FFFF 5888KB Reserved 0x00E0_0000 0x00E0_7FFF 32KB C674x L1P Cache/RAM 0x00E0_8000 0x00EF_FFFF 992KB Reserved 0x00F0_0000 0x00F0_7FFF 32KB C674x L1D Cache/RAM 0x00F0_8000 0x017F_FFFF 9184KB Reserved 0x0180_0000 0x01BF_FFFF 4MB C674x Internal CFG registers 0x01C0_0000 0x07FF_FFFF 100MB Reserved 0x0800_0000 0x08FF_FFFF 16MB L4 Slow Peripheral Domain

0x0900_0000 0x090F_FFFF 1MB EDMA TPCC Registers 0x0910_0000 0x097F_FFFF 7MB Reserved 0x0980_0000 0x098F_FFFF 1MB EDMA TPTC0 Registers

(1) Addresses 0x1000_0000 to 0x10FF_FFFF are mapped to C674x internal addresses 0x0000_0000 to 0x00FF_FFFF. (2) For more details on the DSP/EDMA MMU, see the TMS320DM814x DMSoC Memory Management Units (MMU) User's Guide

0x0990_0000 0x099F_FFFF 1MB EDMA TPTC1 Registers 0x09A0_0000 0x09AF_FFFF 1MB EDMA TPTC2 Registers 0x09B0_0000 0x09BF_FFFF 1MB EDMA TPTC3 Registers 0x09C0_0000 0x09FF_FFFF 4MB Reserved 0x0A00_0000 0x0AFF_FFFF 16MB L4 Fast Peripheral Domain

0x0B00_0000 0x0FFF_FFFF 80MB Reserved 0x1000_0000 0x10FF_FFFF 16MB C674x Internal Global Address 0x1100_0000 0xFFFF_FFFF 3824MB DEMMU Mapped L3 Regions

(Literature Number: TBD).

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Table 2-4. C674x Memory Map

SIZE DESCRIPTION

(see Table 2-6)

(see Table 2-5)

(1)

(2)

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2.12.3 L4 Memory Map

The L4 Fast Peripheral Domain, L4 Slow Peripheral Domain regions of the memory maps above are broken out into Table 2-5 and Table 2-6.

For more details on the interconnect topology and connectivity across the L3 and L4 interconnects, see

Section 5, System Interconnect.

2.12.3.1 L4 Fast Peripheral Memory Map

Cortex-A8 and L3 Masters C674x DSP

START START

ADDRESS ADDRESS

(HEX) (HEX)

0x4A00_0000 0x4A00_07FF 0x0A00_0000 0x0A00_07FF 2KB L4 Fast Configuration - Address/Protection

0x4A00_0800 0x4A00_0FFF 0x0A00_0800 0x0A00_0FFF 2KB L4 Fast Configuration - Link Agent (LA) 0x4A00_1000 0x4A00_13FF 0x0A00_1000 0x0A00_13FF 1KB L4 Fast Configuration - Initiator Port (IP0) 0x4A00_1400 0x4A00_17FF 0x0A00_1400 0x0A00_17FF 1KB L4 Fast Configuration - Initiator Port (IP1) 0x4A00_1800 0x4A00_1FFF 0x0A00_1800 0x0A00_1FFF 2KB Reserved 0x4A00_2000 0x4A07_FFFF 0x0A00_2000 0x0A07_FFFF 504KB Reserved 0x4A08_0000 0x4A0F_FFFF 0x0A08_0000 0x0A0F_FFFF 512KB Reserved 0x4A10_0000 0x4A10_7FFF 0x0A10_0000 0x0A10_7FFF 32KB EMAC SW Peripheral Registers 0x4A10_8000 0x4A10_8FFF 0x0A10_8000 0x0A10_8FFF 4KB EMAC SW Support Registers 0x4A14_0000 0x4A14_FFFF 0x0A14_0000 0x0A14_FFFF 64KB SATA Peripheral Registers 0x4A15_0000 0x4A15_0FFF 0x0A15_0000 0x0A15_0FFF 4KB SATA Support Registers 0x4A15_1000 0x4A17_FFFF 0x0A15_1000 0x0A17_FFFF 188KB Reserved 0x4A18_0000 0x4A1A_1FFF 0x0A18_0000 0x0A1A_1FFF 136KB Reserved 0x4A1A_2000 0x4A1A_3FFF 0x0A1A_2000 0x0A1A_3FFF 8KB McASP3 Configuration Peripheral Registers 0x4A1A_4000 0x4A1A_4FFF 0x0A1A_4000 0x0A1A_4FFF 4KB McASP3 Configuration Support Registers 0x4A1A_5000 0x4A1A_5FFF 0x0A1A_5000 0x0A1A_5FFF 4KB McASP3 Data Peripheral Registers 0x4A1A_6000 0x4A1A_6FFF 0x0A1A_6000 0x0A1A_6FFF 4KB McASP3 Data Support Registers

0x4A1A7000 0x4A1A7FFF 0x0A1A_7000 0x0A1A_7FFF 4KB Reserved

0x4A1A_8000 0x4A1A_9FFF 0x0A1A_8000 0x0A1A_9FFF 8KB McASP4 Configuration Peripheral Registers 0x4A1A_A000 0x4A1A_AFFF 0x0A1A_A000 0x0A1A_AFFF 4KB McASP4 Configuration Support Registers 0x4A1A_B000 0x4A1A_BFFF 0x0A1A_B000 0x0A1A_BFFF 4KB McASP4 Data Peripheral Registers 0x4A1A_C000 0x4A1A_CFFF 0x0A1A_C000 0x0A1A_CFFF 4KB McASP4 Data Support Registers 0x4A1A_D000 0x4A1A_DFFF 0x0A1A_D000 0x0A1A_DFFF 4KB Reserved 0x4A1A_E000 0x4A1A_FFFF 0x0A1A_E000 0x0A1A_FFFF 8KB McASP5 Configuration Peripheral Registers 0x4A1B_0000 0x4A1B_0FFF 0x0A1B_0000 0x0A1B_0FFF 4KB McASP5 Configuration Support Registers 0x4A1B_1000 0x4A1B_1FFF 0x0A1B_1000 0x0A1B_1FFF 4KB McASP5 Data Peripheral Registers 0x4A1B_2000 0x4A1B_2FFF 0x0A1B_2000 0x0A1B_2FFF 4KB McASP5 Data Support Registers 0x4A1B_3000 0x4A1B_5FFF 0x0A1B_3000 0x0A1B_5FFF 12KB Reserved 0x4A1B_6000 0x4A1B_6FFF 0x0A1B_6000 0x0A1B_6FFF 4KB Reserved 0x4A1B_4000 0x4AFF_FFFF 0x0A1B_4000 0x0AFF_FFFF 14632KB Reserved

END ADDRESS END ADDRESS

(HEX) (HEX)

ZHCS057–MARCH 2011

Table 2-5. L4 Fast Peripheral Memory Map

SIZE DEVICE NAME

(AP)

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2.12.3.2 L4 Slow Peripheral Memory Map

Cortex-A8 and L3 Masters C674x DSP START

ADDRESS

(HEX)

0x4800_0000 0x4800_07FF 0x0800_0000 0x0800_07FF 2KB L4 Slow Configuration –

0x4800_0800 0x4800_0FFF 0x0800_0800 0x0800_0FFF 2KB L4 Slow Configuration – Link Agent

0x4800_1000 0x4800_13FF 0x0800_1000 0x0800_13FF 1KB L4 Slow Configuration – Initiator Port

0x4800_1400 0x4800_17FF 0x0800_1400 0x0800_17FF 1KB L4 Slow Configuration – Initiator Port

0x4800_1800 0x4800_1FFF 0x0800_1800 0x0800_1FFF 2KB Reserved 0x4800_2000 0x4800_7FFF 0x0800_2000 0x0800_7FFF 24KB Reserved 0x4800_8000 0x4800_8FFF 0x0800_8000 0x0800_8FFF 32KB Reserved 0x4801_0000 0x4801_0FFF 0x0801_0000 0x0801_0FFF 4KB DEMMU Peripheral Registers 0x4801_1000 0x4801_1FFF 0x0801_1000 0x0801_1FFF 4KB DEMMU Support Registers 0x4801_2000 0x4801_FFFF 0x0801_2000 0x0801_FFFF 56KB Reserved 0x4802_0000 0x4802_0FFF 0x0802_0000 0x0802_0FFF 4KB UART0 Peripheral Registers 0x4802_1000 0x4802_1FFF 0x0802_1000 0x0802_1FFF 4KB UART0 Support Registers 0x4802_2000 0x4802_2FFF 0x0802_2000 0x0802_2FFF 4KB UART1 Peripheral Registers 0x4802_3000 0x4802_3FFF 0x0802_3000 0x0802_3FFF 4KB UART1 Support Registers 0x4802_4000 0x4802_4FFF 0x0802_4000 0x0802_4FFF 4KB UART2 Peripheral Registers 0x4802_5000 0x4802_5FFF 0x0802_5000 0x0802_5FFF 4KB UART2 Support Registers 0x4802_6000 0x4802_7FFF 0x0802_6000 0x0802_7FFF 8KB Reserved 0x4802_8000 0x4802_8FFF 0x0802_8000 0x0802_8FFF 4KB I2C0 Peripheral Registers

0x4802_9000 0x4802_9FFF 0x0802_9000 0x0802_9FFF 4KB I2C0 Support Registers 0x4802_A000 0x4802_AFFF 0x0802_A000 0x0802_AFFF 4KB I2C1 Peripheral Registers 0x4802_B000 0x4802_BFFF 0x0802_B000 0x0802_BFFF 4KB I2C1 Support Registers 0x4802_C000 0x4802_DFFF 0x0802_C000 0x0802_DFFF 8KB Reserved 0x4802_E000 0x4802_EFFF 0x0802_E000 0x0802_EFFF 4KB TIMER1 Peripheral Registers 0x4802_F000 0x4802_FFFF 0x0802_F000 0x0802_FFFF 4KB TIMER1 Support Registers

0x4803_0000 0x4803_0FFF 0x0803_0000 0x0803_0FFF 4KB SPI0 Peripheral Registers

0x4803_1000 0x4803_1FFF 0x0803_1000 0x0803_1FFF 4KB SPI0 Support Registers

0x4803_2000 0x4803_2FFF 0x0803_2000 0x0803_2FFF 4KB GPIO0 Peripheral Registers

0x4803_3000 0x4803_3FFF 0x0803_3000 0x0803_3FFF 4KB GPIO0 Support Registers

0x4803_4000 0x4803_7FFF 0x0803_4000 0x0803_7FFF 16KB Reserved

0x4803_8000 0x4803_9FFF 0x0803_8000 0x0803_9FFF 8KB McASP0 CFG Peripheral Registers 0x4803_A000 0x4803_AFFF 0x0803_A000 0x0803_AFFF 4KB McASP0 CFG Support Registers 0x4803_B000 0x4803_BFFF 0x0803_B000 0x0803_BFFF 4KB Reserved 0x4803_C000 0x4803_DFFF 0x0803_C000 0x0803_DFFF 8KB McASP1 CFG Peripheral Registers 0x4803_E000 0x4803_EFFF 0x0803_E000 0x0803_EFFF 4KB McASP1 CFG Support Registers 0x4803_F000 0x4803_FFFF 0x0803_F000 0x0803_FFFF 4KB Reserved

0x4804_0000 0x4804_0FFF 0x0804_0000 0x0804_0FFF 4KB TIMER2 Peripheral Registers

0x4804_1000 0x4804_1FFF 0x0804_1000 0x0804_1FFF 4KB TIMER2 Support Registers

0x4804_2000 0x4804_2FFF 0x0804_2000 0x0804_2FFF 4KB TIMER3 Peripheral Registers

0x4804_3000 0x4804_3FFF 0x0804_3000 0x0804_3FFF 4KB TIMER3 Support Registers

0x4804_4000 0x4804_4FFF 0x0804_4000 0x0804_4FFF 4KB TIMER4 Peripheral Registers

END ADDRESS START END ADDRESS

(HEX) ADDRESS (HEX) (HEX)

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Table 2-6. L4 Slow Peripheral Memory Map

SIZE DEVICE NAME

Address/Protection (AP)

(LA)

(IP0)

(IP1)

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Table 2-6. L4 Slow Peripheral Memory Map (continued)

Cortex-A8 and L3 Masters C674x DSP START

ADDRESS

(HEX)

0x4804_5000 0x4804_5FFF 0x0804_5000 0x0804_5FFF 4KB TIMER4 Support Registers

0x4804_6000 0x4804_6FFF 0x0804_6000 0x0804_6FFF 4KB TIMER5 Peripheral Registers

0x4804_7000 0x4804_7FFF 0x0804_7000 0x0804_7FFF 4KB TIMER5 Support Registers

0x4804_8000 0x4804_8FFF 0x0804_8000 0x0804_8FFF 4KB TIMER6 Peripheral Registers

0x4804_9000 0x4804_9FFF 0x0804_9000 0x0804_9FFF 4KB TIMER6 Support Registers 0x4804_A000 0x4804_AFFF 0x0804_A000 0x0804_AFFF 4KB TIMER7 Peripheral Registers 0x4804_B000 0x4804_BFFF 0x0804_B000 0x0804_BFFF 4KB TIMER7 Support Registers 0x4804_C000 0x4804_CFFF 0x0804_C000 0x0804_CFFF 4KB GPIO1 Peripheral Registers 0x4804_D000 0x4804_DFFF 0x0804_D000 0x0804_DFFF 4KB GPIO1 Support Registers 0x4804_E000 0x4804_FFFF 0x0804_E000 0x0804_FFFF 8KB Reserved

0x4805_0000 0x4805_1FFF 0x0805_0000 0x0805_1FFF 8KB McASP2 CFG Peripheral Registers

0x4805_2000 0x4805_2FFF 0x0805_2000 0x0805_2FFF 4KB McASP2 CFG Support Registers

0x4805_3000 0x4805_FFFF 0x0805_3000 0x0805_FFFF 52KB Reserved

0x4806_0000 0x4806_FFFF 0x0806_0000 0x0806_FFFF 64KB MMC/SD/SDIO Peripheral Registers

0x4807_0000 0x4807_0FFF 0x0807_0000 0x0807_0FFF 4KB MMC/SD/SDIO Support Registers

0x4807_1000 0x4807_FFFF 0x0807_1000 0x0807_FFFF 60KB Reserved

0x4808_0000 0x4808_FFFF 0x0808_0000 0x0808_FFFF 64KB ELM Peripheral Registers

0x4809_0000 0x4809_0FFF 0x0809_0000 0x0809_0FFF 4KB ELM Support Registers

0x4809_1000 0x4809_FFFF 0x0809_1000 0x0809_FFFF 60KB Reserved 0x480A_0000 0x480A_FFFF 0x080A_0000 0x080A_FFFF 64KB Reserved 0x480B_0000 0x480B_0FFF 0x080B_0000 0x080B_0FFF 4KB Reserved 0x480B_1000 0x480B_FFFF 0x080B_1000 0x080B_FFFF 60KB Reserved 0x480C_0000 0x480C_0FFF 0x080C_0000 0x080C_0FFF 4KB RTC Peripheral Registers 0x480C_1000 0x480C_1FFF 0x080C_1000 0x080C_1FFF 4KB RTC Support Registers 0x480C_2000 0x480C_3FFF 0x080C_2000 0x080C_3FFF 8KB Reserved 0x480C_4000 0x480C_7FFF 0x080C_4000 0x080C_7FFF 16KB Reserved 0x480C_8000 0x480C_8FFF 0x080C_8000 0x080C_8FFF 4KB Mailbox Peripheral Registers 0x480C_9000 0x480C_9FFF 0x080C_9000 0x080C_9FFF 4KB Mailbox Support Registers 0x480C_A000 0x480C_AFFF 0x080C_A000 0x080C_AFFF 4KB Spinlock Peripheral Registers 0x480C_B000 0x480C_BFFF 0x080C_B000 0x080C_BFFF 4KB Spinlock Support Registers 0x480C_C000 0x480F_FFFF 0x080C_C000 0x080F_FFFF 208KB Reserved

0x4810_0000 0x4811_FFFF 0x0810_0000 0x0811_FFFF 128KB HDVPSS Peripheral Registers

0x4812_0000 0x4812_0FFF 0x0812_0000 0x0812_0FFF 4KB HDVPSS Support Registers

0x4812_1000 0x4812_1FFF 0x0812_1000 0x0812_1FFF 4KB Reserved

0x4812_2000 0x4812_2FFF 0x0812_2000 0x0812_2FFF 4KB HDMI Peripheral Registers

0x4812_3000 0x4812_3FFF 0x0812_3000 0x0812_3FFF 4KB HDMI Support Registers

0x4812_4000 0x4813_FFFF 0x0812_4000 0x0813_FFFF 112KB Reserved

0x4814_0000 0x4815_FFFF 0x0814_0000 0x0815_FFFF 128KB Control Module Peripheral Registers

0x4816_0000 0x4816_0FFF 0x0816_0000 0x0816_0FFF 4KB Control Module Support Registers

0x4816_1000 0x4817_FFFF 0x0816_1000 0x0817_FFFF 124KB Reserved

0x4818_0000 0x4818_2FFF 0x0818_0000 0x0818_2FFF 12KB PRCM Peripheral Registers

0x4818_3000 0x4818_3FFF 0x0818_3000 0x0818_3FFF 4KB PRCM Support Registers

0x4818_4000 0x4818_7FFF 0x0818_4000 0x0818_7FFF 16KB Reserved

0x4818_8000 0x4818_8FFF 0x0818_8000 0x0818_8FFF 4KB SmartReflex0 Peripheral Registers

0x4818_9000 0x4818_9FFF 0x0818_9000 0x0818_9FFF 4KB SmartReflex0 Support Registers

END ADDRESS START END ADDRESS

(HEX) ADDRESS (HEX) (HEX)

ZHCS057–MARCH 2011

SIZE DEVICE NAME

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Cortex-A8 and L3 Masters C674x DSP START

ADDRESS

(HEX)

0x4818_A000 0x4818_AFFF 0x0818_A000 0x0818_AFFF 4KB SmartReflex1 Peripheral Registers 0x4818_B000 0x4818_BFFF 0x0818_B000 0x0818_BFFF 4KB SmartReflex1 Support Registers 0x4818_C000 0x4818_CFFF 0x0818_C000 0x0818_CFFF 4KB OCP Watchpoint Peripheral Registers 0x4818_D000 0x4818_DFFF 0x0818_D000 0x0818_DFFF 4KB OCP Watchpoint Support Registers 0x4818_E000 0x4818_EFFF 0x0818_E000 0x0818_EFFF 4KB Reserved 0x4818_F000 0x4818_FFFF 0x0818_F000 0x0818_FFFF 4KB Reserved

0x4819_0000 0x4819_0FFF 0x0819_0000 0x0819_0FFF 4KB SmartReflex2 Peripheral Registers

0x4819_1000 0x4819_1FFF 0x0819_1000 0x0819_1FFF 4KB SmartReflex2 Support Registers

0x4819_2000 0x4819_2FFF 0x0819_2000 0x0819_2FFF 4KB SmartReflex3 Peripheral Registers

0x4819_3000 0x4819_3FFF 0x0819_3000 0x0819_3FFF 4KB SmartReflex3 Support Registers

0x4819_4000 0x4819_BFFF 0x0819_4000 0x0819_BFFF 32KB Reserved 0x4819_C000 0x481F_FFFF 0x0819_C000 0x081F_FFFF 400KB Reserved 0x4819_C000 0x4819_CFFF 0x0819_C000 0x0819_CFFF 4KB I2C2 Peripheral Registers 0x4819_D000 0x4819_DFFF 0x0819_D000 0x0819_DFFF 4KB I2C2 Support Registers 0x4819_E000 0x4819_EFFF 0x0819_E000 0x0819_EFFF 4KB I2C3 Peripheral Registers 0x4819_F000 0x4819_FFFF 0x0819_F000 0x0819_FFFF 4KB I2C3 Support Registers 0x481A_0000 0x481A_0FFF 0x081A_0000 0x081A_0FFF 4KB SPI1 Peripheral Registers 0x481A_1000 0x481A_1FFF 0x081A_1000 0x081A_1FFF 4KB SPI1 Support Registers 0x481A_2000 0x481A_2FFF 0x081A_2000 0x081A_2FFF 4KB SPI2 Peripheral Registers 0x481A_3000 0x481A_3FFF 0x081A_3000 0x081A_3FFF 4KB SPI2 Support Registers 0x481A_4000 0x481A_4FFF 0x081A_4000 0x081A_4FFF 4KB SPI3 Peripheral Registers 0x481A_5000 0x481A_5FFF 0x081A_5000 0x081A_5FFF 4KB SPI3 Support Registers 0x481A_6000 0x481A_6FFF 0x081A_6000 0x081A_6FFF 4KB UART3 Peripheral Registers 0x481A_7000 0x481A_7FFF 0x081A_7000 0x081A_7FFF 4KB UART3 Support Registers 0x481A_8000 0x481A_8FFF 0x081A_8000 0x081A_8FFF 4KB UART4 Peripheral Registers 0x481A_9000 0x481A_9FFF 0x081A_9000 0x081A_9FFF 4KB UART4 Support Registers 0x481A_A000 0x481A_AFFF 0x081A_A000 0x081A_AFFF 4KB UART5 Peripheral Registers 0x481A_B000 0x481A_BFFF 0x081A_B000 0x081A_BFFF 4KB UART5 Support Registers 0x481A_C000 0x481A_CFFF 0x081A_C000 0x081A_CFFF 4KB GPIO2 Peripheral Registers 0x481A_D000 0x481A_DFFF 0x081A_D000 0x081A_DFFF 4KB GPIO2 Support Registers 0x481A_E000 0x481A_EFFF 0x081A_E000 0x081A_EFFF 4KB GPIO3 Peripheral Registers 0x481A_F000 0x481A_FFFF 0x081A_F000 0x081A_FFFF 4KB GPIO3 Support Registers 0x481B_0000 0x481B_FFFF 0x081B_0000 0x081B_FFFF 64KB Reserved 0x481C_0000 0x481C_0FFF 0x081C_0000 0x081C_0FFF 4KB Reserved 0x481C_1000 0x481C_1FFF 0x081C_1000 0x081C_1FFF 4KB TIMER8 Peripheral Registers 0x481C_2000 0x481C_2FFF 0x081C_2000 0x081C_2FFF 4KB TIMER8 Support Registers 0x481C_3000 0x481C_3FFF 0x081C_3000 0x081C_3FFF 4KB SYNCTIMER32K Peripheral Registers 0x481C_4000 0x481C_4FFF 0x081C_4000 0x081C_4FFF 4KB SYNCTIMER32K Support Registers 0x481C_5000 0x481C_5FFF 0x081C_5000 0x081C_5FFF 4KB PLLSS Peripheral Registers 0x481C_6000 0x481C_6FFF 0x081C_6000 0x081C_6FFF 4KB PLLSS 0x481C_7000 0x481C_7FFF 0x081C_7000 0x081C_7FFF 4KB WDT0 Peripheral Registers 0x481C_8000 0x481C_8FFF 0x081C_8000 0x081C_8FFF 4KB WDT0 Support Registers 0x481C_9000 0x481C_9FFF 0x081C_9000 0x081C_9FFF 8KB Reserved 0x481C_A000 0x481C_BFFF 0x081C_A000 0x081C_BFFF 8KB Reserved 0x481C_C000 0x481C_DFFF 0x081C_C000 0x081C_DFFF 8KB DCAN0 Peripheral Registers

END ADDRESS START END ADDRESS

(HEX) ADDRESS (HEX) (HEX)

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Table 2-6. L4 Slow Peripheral Memory Map (continued)

SIZE DEVICE NAME

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Table 2-6. L4 Slow Peripheral Memory Map (continued)

Cortex-A8 and L3 Masters C674x DSP START

ADDRESS

(HEX)

0x481C_E000 0x481C_FFFF 0x081C_E000 0x081C_FFFF 8KB DCAN0 Support Registers 0x481D_0000 0x481D_1FFF 0x081D_0000 0x081D_1FFF 8KB DCAN1 Peripheral Registers 0x481D_2000 0x481D_3FFF 0x081D_2000 0x081D_3FFF 8KB DCAN1 Support Registers 0x481D_4000 0x481D_5FFF 0x081D_4000 0x081D_5FFF 8KB Reserved 0x481D_6000 0x481D_6FFF 0x081D_6000 0x081D_6FFF 4KB Reserved 0x481D_7000 0x481D_7FFF 0x081D_7000 0x081D_7FFF 4KB Reserved 0x481D_8000 0x481E_7FFF 0x081D_8000 0x081E_7FFF 64KB MMC/SD/SDIO1 Peripheral Registers 0x481E_8000 0x481E_8FFF 0x081E_8000 0x081E_8FFF 4KB MMC/SD/SDIO1 Support Registers 0x481E_9000 0x481F_FFFF 0x081E_9000 0x081F_FFFF 52KB Reserved

0x4820_0000 0x4820_0FFF 0x0820_0000 0x0820_0FFF 4KB Interrupt controller

0x4820_1000 0x4823_FFFF 0x0820_1000 0x0823_FFFF 252KB Reserved

0x4824_0000 0x4824_0FFF 0x0824_0000 0x0824_0FFF 4KB MPUSS config register

0x4824_1000 0x4827_FFFF 0x0824_1000 0x0827_FFFF 252KB Reserved

0x4828_0000 0x4828_0FFF 0x0828_0000 0x0828_0FFF 4KB SSM

0x4828_1000 0x482F_FFFF 0x0828_1000 0x082F_FFFF 508KB Reserved

0x4830_0000 0x48FF_FFFF 0x0830_0000 0x08FF_FFFF 13MB Reserved

(1) These regions decoded internally by the Cortex™-A8 Subsystem and are not physically part of the L4 Slow. They are included here only

for reference when considering the Cortex™-A8 Memory Map. For Masters other than the Cortex-A8 these regions are reserved.

(2) These regions decoded internally by the Cortex™-A8 Subsystem and are not physically part of the L4 Slow. They are included here only

for reference when considering the Cortex™-A8 Memory Map. For Masters other than the Cortex-A8 these regions are reserved.

END ADDRESS START END ADDRESS

(HEX) ADDRESS (HEX) (HEX)

SIZE DEVICE NAME

(1)

(2)

2.12.4 DDR DMM TILER Extended Addressing Map

The Tiler includes an additional 4-GBytes of addressing range, enabled by a 33rd address bit, to access the frame buffer in rotated and mirrored views. shows the details of the Tiler Extended Address Mapping. This entirety of this additional range is only accessible to the HDVPSS and ISS subsystems. However, other masters can access any one single view through the 512-MB Tiler region in the base 4GByte address memory map.

Table 2-7. DDR DMM TILER Extended Address Mapping

BLOCK NAME SIZE DESCRIPTION

Tiler View 0 0x1 0000_0000 0x1 1FFF_FFFF 512MB Natural 0° View Tiler View 1 0x1 2000_0000 0x1 3FFF_FFFF 512MB 0° with Vertical Mirror

Tiler View 2 0x1 4000_0000 0x1 5FFF_FFFF 512MB 0° with Horizontal Mirror

Tiler View 3 0x1 6000_0000 0x1 7FFF_FFFF 512MB 180° View Tiler View 4 0x1 8000_0000 0x1 9FFF_FFFF 512MB 90° with Vertical Mirror

Tiler View 5 0x1 A000_0000 0x1 BFFF_FFFF 512MB 270° View Tiler View 6 0x1 C000_0000 0x1 DFFF_FFFF 512MB 90° View Tiler View 7 0x1 E000_0000 0x1 FFFF_FFFF 512MB 90° with Horizontal Mirror

START ADDRESS END ADDRESS

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View

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3 Device Pins

3.1 Pin Maps

Figure 3-1 through Figure 3-8 show the bottom view of the package pin assignments in eight pin maps (A,

B, C, D, E, F, G, and H).

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VDDA_1P8

P

N

M

A

B

C

D

E

F

G

H

J

K

L

1 2

3

4

5

6

7

MCA[3]_AXR[0]/

TIM4_IO/

GP0[18]

MCA[3]_AXR[1]/

TIM5_IO/

GP0[19]

AUD_CLKIN2/

MCA[0]_AXR[9]/

MCA[2]_AHCLKX/

MCA[5]_ACHCLKX/

EDMA_EVT2/

TIM3_IO/

GP0[9]

AUD_CLKIN0/

MCA[0]_AXR[7]/

MCA[0]_AHCLKX/

MCA[3]_AHCLKX]/

USB1_DRVVBUS

MCA[0]_AXR[1]/

I2C[3]_SCL

MCA[0]_AXR[3]

MCA[0]_AFSR/

MCA[5]_AXR[3]

MCA[0]_AXR[7]/

MCB_DX

MCA[0]_AFSX

MCA[1]_AFSR/ MCA[1]_AXR[5]

MCA[0]_AXR[5]/ MCA[1]_AXR[9]

SD0_CMD/ SD1_CMD/

GP0[2]

MCA[2]_AXR[0]/

SD0_DAT[6]/

UART5_RXD

GP0[12]

SD1_CMD/

GP0[0]

SD1_DAT[2]_SDRW

SD1_CLK SD1_DAT[1]_SDIRQ

SD1_DAT[3] DVDD_SD

MCA[1]_AXR[3]/

MCB_CLKR

DVDD

MCA[0]_AXR[9]/

MCB_CLKX/ MCB_CLKR

CLKIN32/

CLKOUT0/

TIM3_IO/

GP3[31]

NMI

MCA[5]_AXR[0]/ MCA[4]_AXR[2]/

GP0[27]

MCA[4]_ACLKX/

GP0[21]

MCA[0]_AXR[6]/

MCB_DR

MCA[1]_ACLKR/

MCA[1]_AXR[4]

SD1_DAT[0]

MCA[0]_ACLKR/

MCA[5]_AXR[2]

MCA[0]_AXR[8]/

MCB_FSX/

MCB_FSR

MCA[5]_ACLKX/

GP0[25]

MCA[5]_AXR[1]/ MCA[4]_AXR[3]/

TIM7_IO/ GP0[28]

RSTOUT_WD_OUT

MCA[4]_AFSX/

GP0[22]

MCA[4]_AXR[1]/

TIM6_IO/

GP0[24]

MCA[3]_AFSX/

GP0[17]

RESET

MCA[2]_AXR[3]/ MCA[1]_AXR[7]/

TIM3_IO/

GP0[15]

MCA[3]_AXR[3]/

MCA[1]_AXR[9]

MCA[4]_AXR[0]/

GP0[23]

MCA[3]_AXR[2]/ MCA[1]_AXR[8]/

GP0[20]

POR

DDR[1]_D[2]DDR[1]_D[3]

DDR[1]_DQS[0]

DDR[1]_D[8]

DDR[1]_D[7]

DDR[1]_DQM[1]

DDR[1]_VTP

DDR[1]_D[11]VSS

DDR[1]_DQM[0]

DDR[1]_D[1]

DDR[1]_D[5]DDR[1]_D[0]

DDR[1]_D[13]DDR[1]_D[10]

DDR[1]_D[12]DDR[1]_DQS[1]

DDR[1]_D[14]

DDR[1]_DQS[1]

DDR[1]_D[22]DDR[1]_D[9]

DDR[1]_D[20]DDR[1]_D[18]

DDR[1]_DQS[2]

DDR[1]_D[19]

DDR[1]_DQS[2]DDR[1]_D[15]

DDR[1]_D[6]

MCA[3]_ACLKX/

GP0[16]

DDR[1]_D[4]

DDR[1]_D[17]

DDR[1]_D[21]

DDR[1]_D[23]

DDR[1]_D[27]

MCA[5]_AFSX/

GP0[26]

MCA[0]_AXR[0]

MCA[0]_AXR[2]/

I2C[3]_SDA

A B C D

E F G H

TMS320DM8148, TMS320DM8147

www.ti.com.cn

ZHCS057–MARCH 2011

Figure 3-1. Pin Map A

Product Folder Link(s): TMS320DM8148 TMS320DM8147

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P

N

M

A

B

C

D

E

F

G

H

J

K

L

8

9

10

11

12

13 14

DDR[1]_DQM[2] DDR[1]_DQM[3]

DDR[1]_D[16]

CVDD

VSS CVDD_DSP

DVDD VSS

VSS

CVDD_DSP

DVDD DVDD_SD LDOCAP_DSP VDDA_DSPPLL_1P8 CVDD VSS CVDD

CVDD_HDVICP CVDD_HDVICP

VSS

DVDD_DDR[1]

CVDD_HDVICP

VSS

CVDD_DSP

LDOCAP_DSPRAM

CVDD_DSP

CVDD_DSP VSS

VSS

DVDD_DDR[1]

DDR[1]_ODT[0]

DVDD_DDR[1]

DDR[1]_CKE

VSS

DVDD_DDR[1]

DVDD_DDR[1]DDR[1]_D[25]

DDR[1]_D[24]DDR[1]_D[26]

DVDD_DDR[1]DVDD_DDR[1]

VSSDDR[1]_D[29]

DDR[1]_D[28]DDR[1]_D[30]

DDR[1]_D[31]DDR[1]_DQS[3]

DDR[1]_A[7]

DDR[1]_DQS[3]

DDR[1]_ODT[1]DDR[1]_A[1]

DDR[1]_A[13]

DDR[1]_A[2]

DDR[1]_A[0]DDR[1]_A[12]

DDR[1]_A[11]

DDR[1]_BA[1]

DDR[1]_A[6]

DDR[1]_BA[2]

DDR[1]_A[9]

DDR[1]_RAS

DDR[1]_CLKDDR[1]_A[5]

DDR[1]_CLKVSS

DVDD_DDR[1]

DDR[1]_A[10] DDR[1]_BA[0]

DDR[1]_A[8]

DDR[1]_A[4]

DDR[1]_A[3]

CVDD_DSP VSS CVDD

LDOCAP_HDVICP LDOCAP_HDVICPRAM VSS

DDR[1]_A[14]

VREFSSTL_DDR[1]

DDR[1]_RST DDR[1]_CS[1]

DDR[1]_CS[0]

DDR[1]_WE

DDR[1]_CAS

A B C D

E F G H

TMS320DM8148, TMS320DM8147

ZHCS057–MARCH 2011

www.ti.com.cn

Figure 3-2. Pin Map B

Product Folder Link(s): TMS320DM8148 TMS320DM8147

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15

16

17

18

19

20 21

VREFSSTL_DDR[0] DVDD_DDR[0]

VDDA_DDRPLL_1P8

DVDD_DDR[0] DVDD_DDR[0]

VSS VSS

CVDD VSS

VSS CVDD

VSS

VSS CVDD VSS LDOCAP_RAM0 VSS DVDD_GPMC VSS

VSS VSS

DVDD_GPMC VSS

DDR[0]_D[18]

DVDD_GPMC

VSS

CVDD

LDOCAP_RAM2

VSS

CVDD VDDA_1P8

DVDD_GPMC

DVDD_DDR[0]

DDR[0]_CKE

VSS

DDR[0]_ODT[1] DDR[0]_D[24]DVDD_DDR[0]

DDR[0]_A[14]DDR[0]_BA[0]

DDR[0]_A[12]DDR[0]_A[3]

DDR[0]_A[11]DDR[0]_A[4]

DDR[0]_WE

DDR[0]_A[9]

DDR[0]_CLK

DDR[0]_A[8]

DDR[0]_CLK

DDR[0]_A[6]

DDR[0]_CS[0]

DDR[0]_A[13]

DDR[0]_A[7]

DDR[0]_CAS

DDR[0]_RASDDR[0]_A[5]

DDR[0]_BA[2]VSS

DDR[0]_D[30]

DDR[0]_D[29]

DDR[0]_D[31]DDR[0]_A[0]

DDR[0]_BA[1]DDR[0]_A[10]

DDR[0]_D[26]

DDR[0]_A[1] DDR[0]_D[25]

DVDD_DDR[0]

DDR[0]_DQS[3]

VSS CVDD VSS

CVDD VDDA_L3PLL_1P8 CVDD

DDR[0]_A[2]

DDR[0]_D[19]DDR[0]_CS[1]

DDR[0]_ODT[0]

DDR[0]_RST

P

N

M

A

B

C

D

E

F

G

H

J

K

L

VSS

DDR[0]_D[28]

DDR[0]_DQM[3]

DVDD_DDR[0]

A B C D

E F G H

TMS320DM8148, TMS320DM8147

www.ti.com.cn

ZHCS057–MARCH 2011

Figure 3-3. Pin Map C

Product Folder Link(s): TMS320DM8148 TMS320DM8147

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P

N

M

A

B

C

D

E

F

G

H

J

K

L

22

23

24

25

26

27

28

EMAC[0]_MRXD[0]/

VIN[1]B_D[5]/

EMAC[0]_RMTXD[0]/

GP3[28]

EMAC[0]_RGTXD[0]/

EMAC[0]_MTXD[4]/

EMAC[1]_RMRXER/

GPMC_A[11]/

EMAC[1]_RGTXD[2]/

UART4_RTS

EMAC[0]_MTXD[2]/

EMAC[1]_RMRXD[0]/

GPMC_A[9]/

UART4_TXD

EMAC[1]_RGTXCTL/

EMAC[0]_MTXD[6]/

EMAC[1]_RMTXD[0]/

GPMC_A[13]/ UART1_TXD

EMAC[1]_RGRXD[0]/

EMAC[0]_MTXEN/

EMAC[1]_RMTXEN/

GPMC_A[15]/

EMAC[1]_RGRXD[2]/

UART1_RTS

EMAC[0]_MRXDV/

GPMC_A[5]/

SPI[2]_SCLK

EMAC[1]_RGRXD[1]/

EMAC[0]_GMTCLK/

GPMC_A[6]/

SPI[2]_D[1]

EMAC[1]_RGRXC/

VSS

EMAC[0]_MCOL/

VIN[1]B_D[1]/

EMAC[0]_RMRXD[0]/

GP3[24]

EMAC[0]_RGRXCTL/

VDDA_1P8

SD2_SCLK/

GP1[15]

VSS

SD2_DAT[6]/ GPMC_A[25]/ GPMC_A[21]/ UART2_TXD/

GP1[20]

SD2_DAT[5]/ GPMC_A[26]/ GPMC_A[22]/

TIM6_IO/

GP1[21]

EMAC[0]_MRXD[1]/

VIN[1]B_D[6]/

EMAC[0]_RMTXD[1]/

GP3[29]

EMAC[0]_RGRXD[0]/

MDIO/

GP1[12]

GPMC_CS[4]/

SD2_CMD/

GP1[8]

GPMC_CS[3]

SPI[2]_SCS[0]

/

VIN[1]B_CLK/

/

GP1[26]

RSV13 RSV12

RSV11 RSV10

RSV8 RSV9

SD2_DAT[3]/ GPMC_A[1]/

GP2[5]

MDCLK/ GP1[11]

RSV7

GPMC_CS[1]/

GPMC_A[25]/

GP1[24]

SD2_DAT[1]_ /

GPMC_A[3]/

GP1[13]

SDIRQ

EMAC[0]_MTCLK/

VIN[1]B_D[0]/

/

I2C[2]_SDA/

GP3[23]

EMAC[0]_RGRXC/

SPI[3]_SCS[3]

GPMC_CS[2]/ GPMC_A[24]/

GP1[25]

SD2_DAT[7]/ GPMC_A[24]/ GPMC_A[20]/ UART2_RXD/

GP1[19]

GPMC_ _ALE/

/

TIM5_IO/

GP1[28]

ADV

GPMC_CS[6]

SD2_DAT[0]/ GPMC_A[4]/

GP1[14]

RSV6

SD2_DAT[2]_SDR /

GPMC_A[2]/

GP2[6]

W

EMAC[0]_MTXD[0]/

GPMC_A[7]/

SPI[2]_D[0]

EMAC[1]_RGRXD[3]/

EMAC[0]_MTXD[7]/

EMAC[1]_RMTXD[0]/

GPMC_A[14]/

EMAC[1]_RGTXD[3]/

UART1_CTS

EMAC[0]_MRXD[3]/

GPMC_A[27]/ GPMC_A[26]/

GPMC_A[0]/ UART5_RXD

EMAC[1]_RGRXCTL/

EMAC[0]_MTXD[1]/

GPMC_A[8]/ UART4_RXD

EMAC[1]_RGTXD[1]/

EMAC[0]_MRXER/

VIN[1]B_D[3]/

EMAC[0]_RMRXER/

GP3[26]

EMAC[0]_RGTXCTL/

EMAC[0]_MRXD[5]/

GPMC_A[2]/

EMAC[0]_RGTXD[3]/

UART5_CTS

EMAC_RMREFCLK/

TIM2_IO/

GP1[10]

EMAC[0]_MRCLK/

VIN[1]B_D[4]/

EMAC[0]_RMCRSDV/

/

GP3[27]

EMAC[0]_RGTXC/

SPI[3]_SCS[2]

EMAC[0]_MTXD[3]/

EMAC[1]_RMRXD[1]/

GPMC_A[10]/

EMAC[1]_RGTXD[0]/

UART4_CTS

EMAC[0]_MTXD[5]/

EMAC[1]_RMCRSDV/

GPMC_A[12]/ UART1_RXD

EMAC[1]_RGTXC/

DDR[0]_D[17]

DDR[0]_D[21] DDR[0]_DQM[0]

DDR[0]_D[20]

DDR[0]_DQS[0]

DDR[0]_D[22]

DDR[0]_D[7]

DDR[0]_DQS[2]

DDR[0]_D[23]

DDR[0]_DQS[2]

DDR[0]_D[27]

DDR[0]_D[3]DDR[0]_D[4]

DDR[0]_D[5] DDR[0]_D[2]

DDR[0]_D[9]DDR[0]_DQM[2]

DDR[0]_D[12]DDR[0]_D[16]

DDR[0]_D[14]DDR[0]_D[15]

DDR[0]_DQS[0]

DDR[0]_D[6]

DDR[0]_D[8]DDR[0]_D[10]

DDR[0]_VTPDDR[0]_DQS[1]

DDR[0]_D[11]DDR[0]_DQS[1]

DDR[0]_D[13]

EMAC[0]_MRXD[7]/

GPMC_A[4]/

EMAC[0]_RGTXD[1]/

SPI[2]_SCS[3]

DDR[0]_D[1]

EMAC[0]_MRXD[6]/

GPMC_A[3]/

EMAC[0]_RGTXD[2]/

UART5_RTS

DDR[0]_D[0]

DDR[0]_DQM[1]

VSS

A B C D

E F G H

TMS320DM8148, TMS320DM8147

ZHCS057–MARCH 2011

www.ti.com.cn

Figure 3-4. Pin Map D

Product Folder Link(s): TMS320DM8148 TMS320DM8147

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AH

AG

AF

R

T

U

V

W

Y

AA

AB

AC

AD

AE

1 2

3

4

5

6 7

SATA_RXP0

SATA_RXN0

SATA_TXN0

PCIE_RXN0 PCIE_RXP0

PCIE_TXN0 PCIE_TXP0

VSS VSS

SERDES_CLKP

SERDES_CLKN

VSS

UART0_DTR UART3_CTS// UART1_TXD/

GP1[4]

VSS

DEVOSC_MXO

UART0_DCD

SPI[0]_SCS[3]

/

UART3_RXD/

/ I2C[2]_SCL/ SD1_POW/

GP1[2]

UART0_RXD

DCAN0_TX/

UART2_TXD/

I2C[3]_SDA/

GP1[0]

VOUT[0]_G_Y_YC[2]/

EMU3/

GP2[24]

DCAN0_RX/

UART2_RXD/

I2C[3]_SCL/

GP1[1]

VOUT[0]_B_CB_C[2]

EMU2/

GP2[22]

VOUT[0]_R_CR[6]/

SPI[0]_SCLK

SPI[0]_D[1]

SPI[0]_D[0]

UART0_RIN/

/

UART1_RXD/

GP1[5]

UART3_RTS

UART0_RTS/ UART4_TXD/ DCAN1_RX/

SPI[1]_SCS[2]/

SD2_SDCD

SPI[0]_SCS[1]/

SD1_SDCD/

SATA_ACT0_LED/

EDMA_EVT1/

TIM4_IO/

GP1[6]

UART0_CTS

SPI[1]_SCS[3]

/

UART4_RXD/

DCAN1_TX/

/

SD0_SDCD

SPI[0]_SCS[0]

SPI[1]_SCLK/

GP1[17]

I2C[0]_SCL TDO

I2C[0]_SDA

SATA_TXP0

VSSVSS

GP1[8]

GP1[7]

GP1[10]GP1[9]

RSV17RSV16

TCLKIN/ GP0[30]

AUXOSC_MXO

VSSA_AUXOSC

AUXOSC_MXI/

AUX_CLKIN

SD0_DAT[3]/ SD1_DAT[7]/

GP0[6]

SD0_DAT[2]_SDR /

SD1_DAT[6]/

GP0[5]

W

UART2_RXD/

GP0[29]

UART2_TXD/

GP0[31]

MCA[0]_ACLKX

MCA[1]_AXR[2]/

MCB_FSR

MCA[2]_AXR[1]/

SD0_DAT[7]/

UART5_TXD/

GP0[13]

MCA[2]_AXR[2]/ MCA[1]_AXR[6]/

TIM2_IO/

GP0[14]

MCA[2]_ACLKX//

GP0[10]

MCA[1]_ACLKX

MCA[1]_AXR[1]/

SD0_DAT[5]

MCA[0]_AXR[4]/ MCA[1]_AXR[8]

AUD_CLKIN1/

MCA[0]_AXR[8]/ MCA[1]_AHCLKX/ MCA[4]_AHCLKX/

EDMA_EVT3/

TIM2_IO/

GP0[8]

MCA[1]_AFSX

SPI[1]_D[0]/

GP1[26]

SD0_DAT[1]_ /

SD1_DAT[5]/

GP0[4]

SDIRQ

TDI

DEVOSC_WAKE/

/

TIM5_IO/

GP1[7]

SPI[1]_SCS[1]

DVDD

SD0_DAT[0]/ SD1_DAT[4]/

GP0[3]

VSSA_DEVOSC

UART0_DSR

SPI[0]_SCS[2]

/

UART3_TXD/

/ I2C[2]_SDA/ SD1_SDWP/

GP1[3]

UART0_TXD

SPI[1]_SCS[0]/

GP1[16]

RTCK

TRST

SPI[1]_D[1]/

GP1[18]

MCA[2]_AFSX/

GP0[11]

TMS

SD0_CLK/

GP0[1]

TCLK

VSS

VDDA_1P8

MCA[1]_AXR[0]/

SD0_DAT[4]

A B C D

E F G H

DEVOSC_MXI/

DEV_CLKIN

TMS320DM8148, TMS320DM8147

www.ti.com.cn

ZHCS057–MARCH 2011

Product Folder Link(s): TMS320DM8148 TMS320DM8147

Figure 3-5. Pin Map E

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AH

AG

AF

R

T

U

V

W

Y

AA

AB

AC

AD

AE

8

9

10

11

12

13

14

VOUT[0]_G_Y_YC[6] VOUT[0]_R_CR[4]

VOUT[0]_G_Y_YC[4]

RSV5

VIN[0]A_D[2]/

GP2[7]

RSV1

VOUT[0]_R_CR[2]/

EMU4/

GP2[26]

VOUT[0]_R_CR[8] VSS

VOUT[0]_R_CR[5]

VIN[0]A_D[0]/

GP1[11]

EMU0

VIN[0]A_D[9]_BD[1]/

GP2[14]

VIN[0]A_D[4]/

GP2[9]

VIN[0]A_D[10]_BD[2]/

GP2[15]

USB0_CE USB0_DM USB1_ID USB1_DM USB1_CE

USB1_DP USB1_VBUSIN

VOUT[0]_G_Y_YC[9]

VIN[0]A_D[15]_BD[7]/

CAM_SHUTTER/

GP2[20]

DVDD

VOUT[0]_G_Y_YC[8]

VOUT[0]_G_Y_YC[7]

USB0_DRVVBUS/

GP0[7]

EMU1

VOUT[0]_R_CR[7]

VIN[0]A_D[3]/

GP2[8]

VOUT[0]_B_CB_C[6]

VOUT[0]_B_CB_C[7]

VOUT[0]_HSYNC

VIN[0]A_D[1]/

GP1[12]

VIN[0]A_D[14]_BD[6]/

CAM_STROBE/

GP2[19]

VOUT[0]_G_Y_YC[5]

VOUT[0]_R_CR[9]

VOUT[0]_VSYNC

VOUT[0]_R_CR[3]/

GP2[27]

VDDA_PCIE_1P8

VSSRSV3

VDDA_SATA_1P8RSV2

VSSVSS

DVDDVSS

CVDD

LDOCAP_SERDESCLKLDOCAP_SGX

LDOCAP_RAM1DVDD_M

LDOCAP_ARMRAM

VSSA_USB

VSS

VSSCVDD

VDDA_ARMPLL_1P8VSS

VDDA_USB_3P3

VSS RSV4

LDOCAP_ARM

CVDD_ARM

VSS

VOUT[0]_B_CB_C[4] VOUT[0]_CLK

USB0_ID USB0_DP USB0_VBUSIN

VSS

VOUT[0]_AVID/

VOUT[0]_FLD/

SPI[3]_SCLK/

TIM7_IO/

GP2[21]

VIN[0]A_D[7]/

GP2[12]

VDDA_USB0_1P8

VSS

VDDA_1P8

VDDA_PCIE_1P8

VDDA_SATA_1P8

VDDA_1P8

VSSA_USB

CVDD

VDDA_USB1_1P8

A B C D

E F G H

TMS320DM8148, TMS320DM8147

ZHCS057–MARCH 2011

www.ti.com.cn

Figure 3-6. Pin Map F

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15

16

17

18

19

20

21

DVDD VSS

VIN[0]A_D[8]_BD[0]/

GP2[13]

VIN[0]B_DE/

CAM_D[6]/

GP0[19]

VIN[0]A_D[23]/

CAM_D[15]/

EMAC[1]_RMTXEN/

SPI[3]_D[0]/

GP0[17]

VOUT[0]_B_CB_C[5]

VOUT[0]_B_CB_C[3]/

GP2[23]

VOUT[0]_B_CB_C[8]

VOUT[0]_B_CB_C[9]

VIN[0]A_D[5]/

GP2[10]

VOUT[0]_G_Y_YC[3]/

GP2[25]

VIN[0]A_D[6]/

GP2[11]

VIN[0]A_D[11]_BD[3]/

/

GP2[16]

CAM_WE

HDMI_CLKN HDMI_DN0 HDMI_DN1 HDMI_DN2

HDMI_DP1 HDMI_DP2

VIN[0]A_D[18]/

CAM_D[10]/

EMAC[1]_RMRXD[1]/

I2C[3]_SCL/

GP0[12]

VIN[0]A_D[19]/

CAM_D[11]/

EMAC[1]_RMRXD[0]/

I2C[3]_SDA/

GP0[13]

VIN[0]A_D[22]/

CAM_D[14]/

EMAC[1]_RMTXD[1]/

SPI[3]_D[1]/

GP0[16]

VIN[0]A_D[17]/

CAM_D[9]/

EMAC[1]_RMRXER/

GP0[11]

VIN[0]A_DE/

VIN[0]B_HSYNC/

UART5_TXD/

I2C[2]_SDA/

GP2[0]

VSS

VIN[0]A_D[13]_BD[5]/

CAM_RESET/

GP2[18]

VIN[0]B_CLK/

CLKOUT0/

GP1[9]

VOUT[0]_FLD/

CAM_PCLK/

GPMC_A[12]/

/

GP2[2]

UART2_RTS

VIN[0]A_D[21]/

CAM_D[13]/

EMAC[1]_RMTXD[0]/

/

GP0[15]

SPI[3]_SCLK

VSS

VIN[0]A_VSYNC/

/

GP2[4]

UART5_CTS

VIN[0]A_D[20]/

CAM_D[12]/

EMAC[1]_RMCRSDV/

/

GP0[14]

SPI[3]_SCS[0]

VIN[0]A_DE/

CAM_D[7]/

GP0[18]

VOUT[1]_G_Y_YC[0]/

CAM_D[2]/

GPMC_A[6]/

UART4_TXD/

GP0[23]

VDDA_VID0PLL_1P8

VOUT[1]_R_CR[1]/

CAM_D[1]/

GPMC_A[7]/

/

GP0[24]

UART4_CTS

VDDA_VDAC_1P8

VIN[0]A_HSYNC/

/

GP2[3]

UART5_RTS

VIN[0]A_CLK/

GP2[2]

DVDD

DVDDVSS

VSSVDDA_1P8

VSSCVDD_ARM

CVDDCVDD_ARM

CVDD_ARMCVDD_ARM

VSSCVDD

VSSVSS

VDDA_HDMI_1P8

VSS

VSSVSS

VDDA_AUDIOPLL_1P8CVDD

VSS

DVDD

DVDD_GPMCVSS

VDDA_1P8CVDD

VIN[0]A_FLD/

VIN[0]B_VSYNC/

UART5_RXD/

I2C[2]_SCL/

GP2[1]

VSS

VIN[0]B_FLD/

CAM_D[4]/

GP0[21]

VOUT[1]_G_Y_YC[1]/

CAM_D[3]/

GPMC_A[5]/

UART4_RXD/

GP0[22]

VIN[0]A_D[12]_BD[4]/

CLKOUT1/

GP2[17]

HDMI_CLKP HDMI_DP0

VSSA_HDMI

VIN[0]A_D[16]/

CAM_D[8]/

I2C[2]_SCL/

GP0[10]

DVDD VDDA_VID1PLL_1P8 VSSA_VDAC

AH

AG

AF

R

T

U

V

W

Y

AA

AB

AC

AD

AE

DVDD

VSS

DVDD_CVSS

CVDD_ARM

VSS

CVDD

DVDD_C

A B C D

E F G H

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AH

AG

AF

R

T

U

V

W

Y

AA

AB

AC

AD

AE

22

23

24

25

26

27 28

GPMC_D[5]/ BTMODE[5]

VOUT[1]_VSYNC/

EMAC[1]_MCRS/

VIN[1]A_FLD/

VIN[1]A_DE/ SPI[3]_D[0]/

/

GP2[30]

UART3_CTS

VIN[0]A_FLD/

CAM_D[5]/

GP0[20]

VOUT[1]_B_CB_C[0]/

CAM_VS/ GPMC_A[10]/ UART2_TXD/

GP0[27]

VOUT[1]_B_CB_C[1]/

CAM_HS/

GPMC_A[9]/

UART2_RXD/

GP0[26]

VSS

TV_VFB1 TV_VFB0

TV_OUT1 TV_RSET TV_OUT0

VOUT[1]_B_CB_C[3]/

EMAC[1]_MRCLK/

VIN[1]A_D[0]/

/

GP3[0]

UART4_CTS

VOUT[1]_B_CB_C[8]/

EMAC[1]_MRXD[4]/

VIN[1]A_D[5]/

I2C[3]_SCL/

GP3[5]

VOUT[1]_G_Y_YC[6]/

EMAC[1]_GMTCLK/

VIN[1]A_D[11]/

GP3[10]

VSS

VOUT[1]_R_CR[4]/

EMAC[1]_MTXD[3]/

VIN[1]A_D[15]/

/

GP3[14]

SPI[3]_SCS[1]

VOUT[1]_R_CR[3]/

GPMC_A[14]/

VIN[1]A_D[22]/

HDMI_SDA/

SPI[2]_SCLK/

I2C[2]_SDA

GP3[21]

VOUT[1]_G_Y_YC[2]/

GPMC_A[13]/

VIN[1]A_D[21]/

HDMI_SCL/

SPI[2]_SCS[2]/

I2C[2]_SCL/

GP3[20]

VOUT[1]_B_CB_C[2]/

GPMC_A[0]/

VIN[1]A_D[7]/

HDMI_CEC/ SPI[2]_D[0]/

GP3[30]

GPMC_A[21]/

SPI[2]_D[0]/

GP1[16]

GPMC_D[9]/ BTMODE[9]

GPMC_A[18]/

TIM2_IO/ GP1[13]

GPMC_A[20]/

]/

GP1[15]

SPI[2]_SCS[1

I2C[1]_SCL/

HDMI_SCL

VOUT[1]_CLK/

EMAC[1]_MTCLK/

VIN[1]A_HSYNC/

GP2[28]

VOUT[1]_B_CB_C[5]/

EMAC[1]_MRXD[1]/

VIN[1]A_D[2]/ UART4_TXD/

GP3[2]

VOUT[1]_G_Y_YC[7]/

EMAC[1]_MTXD[0]/

VIN[1]A_D[12]/

GP3[11]

VOUT[1]_G_Y_YC[8]/

EMAC[1]_MTXD[1]/

VIN[1]A_D[13]/

GP3[12]

VOUT[1]_R_CR[2]/

GPMC_A[15]/ VIN[1]A_D[23]/ HDMI_HPDET/

SPI[2]_D[1]/

GP3[22]

GPMC_A[16]/

GP2[5]

VOUT[1]_HSYNC/

EMAC[1]_MCOL/ VIN[1]A_VSYNC/

SPI[3]_D[1]/

/

GP2[29]

UART3_RTS

VOUT[1]_B_CB_C[7]/

EMAC[1]_MRXD[3]/

VIN[1]A_D[4]/ UART3_TXD/

GP3[4]

VOUT[1]_R_CR[5]/ EMAC[1]_MTXD[4]/

VIN[1]A_D[16]/

SPI[3]_SCLK/

GP3[15]

GPMC_A[19]/

TIM3_IO/

GP1[14]

GPMC_A[22]/

SPI[2]_D[1]/ HDMI_CEC/

TIM4_IO/

GP1[17]

VOUT[1]_FLD/

CAM_FLD/

/

GPMC_A[11]/

/

GP0[28]

CAM_WE

UART2_CTS

GPMC_D[8]/

BTMODE[8]

VOUT[1]_AVID/

EMAC[1]_MRXER/

VIN[1]A_CLK/

/

TIM6_IO/

GP2[31]

UART4_RTS

VOUT[1]_R_CR[8]/

EMAC[1]_MTXD[7]/

VIN[1]A_D[19]/

UART5_RXD/

GP3[18]

GPMC_WAIT[0]/

GPMC_A[26]/

EDMA_EVT0/

GP1[31]

GPMC_A[17]/

GP2[6]

GPMC_BE[1]/

GPMC_A[24]/

EDMA_EVT1/

TIM7_IO/

GP1[30]

GPMC_D[13]/

BTMODE[13]

GPMC_WE

EMAC[0]_MRXD[4]/

GPMC_A[1]/

UART5_TXD

EMAC[0]_RGRXD[3]/

VSS

EMAC[0]_MRXD[2]/

VIN[1]B_D[7]/

EMAC[0]_RMTXEN/

GP3[30]

EMAC[0]_RGRXD[1]/

VSS

GPMC_D[15]/

BTMODE[15]

VOUT[1]_R_CR[9]/

EMAC[1]_MTXEN/

VIN[1]A_D[20]/

UART5_TXD/

GP3[19]

GPMC_D[6]/

BTMODE[6]

GPMC_D[12]/

BTMODE[12]

EMAC[0]_MCRS/

VIN[1]B_D[2]/

EMAC[0]_RMRXD[1]/

GP3[25]

EMAC[0]_RGRXD[2]/

SD2_DAT[4]/ GPMC_A[27]/ GPMC_A[23]/

/

EDMA_EVT0/

TIM7_IO/

GP1[22]

GPMC_CS[7]

GPMC_D[2]/

BTMODE[2]

GPMC_D[4]/ BTMODE[4]

GPMC_ _CLE/

GPMC_A[25]/

EDMA_EVT2/

TIM6_IO/

GP1[29]

BE[0]

GPMC_D[0]/ BTMODE[0]

GPMC_OE_RE

RSV14

GPMC_CLK/

/

GPMC_WAIT[1]/

CLKOUT1/

EDMA_EVT3/

TIM4_IO/

GP1[27]

GPMC_CS[5]

GPMC_D[14]/

BTMODE[14]

GPMC_D[11]/

BTMODE[11]

GPMC_D[10]/ BTMODE[10]

GPMC_D[1]/ BTMODE[1]

GPMC_D[3]/

BTMODE[3]

GPMC_CS[0]/

GP1[23]

RSV15

I2C[1]_SDA/

HDMI_SDA

VOUT[1]_B_CB_C[4]/

EMAC[1]_MRXD[0]/

VIN[1]A_D[1]/ UART4_RXD/

GP3[1]

VOUT[1]_G_Y_YC[5]/

EMAC[1]_MRXDV/

VIN[1]A_D[10]/

GP3[9]

VOUT[1]_B_CB_C[6 ]/

EMAC[1]_MRXD[2]/

VIN[1]A_D[3]/

UART3_RXD/

GP3[3]

VOUT[1]_G_Y_YC[9]/

EMAC[1]_MTXD[2]/

VIN[1]A_D[14]/

GP3[13]

VOUT[1]_R_CR[6]/ EMAC[1]_MTXD[5]/

VIN[1]A_D[17]/

SPI[3]_D[1]/

GP3[16]

VOUT[1]_B_CB_C[9]/

EMAC[1]_MRXD[5]/

VIN[1]A_D[6]/

I2C[3]_SDA/

GP3[6]

GPMC_A[23]/ SPI[2]_SCLK/

HDMI_HPDET/

TIM5_IO/

GP1[18]

VOUT[1]_R_CR[0]/

CAM_D[0]/

GPMC_A[8]/

/

GP0[25]

UART4_RTS

VOUT[1]_G_Y_YC[3]/

EMAC[1]_MRXD[6]/

VIN[1]A_D[8]/

GP3[7]

VOUT[1]_G_Y_YC[4]/

EMAC[1]_MRXD[7]/

VIN[1]A_D[9]/

GP3[8]

VOUT[1]_R_CR[7]/

EMAC[1]_MTXD[6]/

VIN[1]A_D[18]/

SPI[3]_D[0]/

GP3[17]

DVDD

GPMC_D[7]/

BTMODE[7]

A B C D

E F G H

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3.2 Terminal Functions

The terminal functions tables identify the external signal names and their pin multiplexing, the associated pin (ball) numbers along with the mechanical package designator, the pin type (e.g., I, O, Z, S, A, or GND), whether the pin has any internal pullup or pulldown resistors (e.g., IPU, IPD, or DIS), the supply voltage source, and describe the a function(s) of the pin. The MUXED column in the tables also identifies all peripheral pin functions multiplexed on a pin, the pin control register (PINCNTLx) that controls which peripheral pin function is selected for that particular pin, and indicates the state driven on the peripheral input (logic "0", logic "1", or "PIN" level) when the peripheral pin function is not selected (i.e., the de-selected input state [DSIS]), and the Multi-Muxed [MM] option for that peripheral pin function). For more detailed information on device configuration, boot mode order, peripheral selection, and multiplexed/shared pin control, etc., see Section 4, Device Configurations of this data manual.

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3.2.1 Boot Configuration

SIGNAL

NAME NO.

GPMC_D[15]/ DIS BTMODE[15] DVDD_GPMC

GPMC_D[14]/ DIS BTMODE[14] DVDD_GPMC

GPMC_D[13]/ DIS BTMODE[13] DVDD_GPMC

Y25 I PINCNTL104

V24 I PINCNTL103 input. These pins are multiplexed between ARM

U23 I PINCNTL102

GPMC_D[12]/ DIS BTMODE[12] DVDD_GPMC

GPMC_D[11]/ DIS BTMODE[11] DVDD_GPMC

U24 I PINCNTL101

AA27 I PINCNTL100

Table 3-1. Boot Configuration Terminal Functions

TYPE

(1)

OTHER

(2) (3)

MUXED DESCRIPTION

BOOT

GPMC CS0 default GPMC_Wait enable input. This pin is multiplexed between ARM Cortex-A8 boot mode and General-Purpose Memory Controller (GPMC) peripheral

GPMC

DSIS: PIN

GPMC GPMC CS0 default Address/Data multiplexing mode

DSIS: PIN Cortex-A8 boot mode and General-Purpose Memory

GPMC

DSIS: PIN

GPMC

DSIS: PIN

GPMC

DSIS: PIN

functions. At reset, BOOT[15] is sampled to determine the GPMC CS0 Wait enable:

• 0 = Wait disabled

• 1 = Wait enabled

After reset, this pin functions as GPMC multiplexed data/address pin 15 (GPMC_D[15]).

Controller (GPMC) peripheral functions. At reset, BOOT[14:13] are sampled to determine the GPMC CS0 Address/Data multiplexing:

• 00 = Not muxed

• 01 = A/A/D muxed

• 10 = A/D muxed

• 11 = Reserved

After reset, this pin functions as GPMC multiplexed data/address pins 14 through 13 (GPMC_D[14:13]).

GPMC CS0 default Data Bus Width input. This pin is multiplexed between ARM Cortex-A8 boot mode and General-Purpose Memory Controller (GPMC) peripheral functions. At reset, BOOT[12] is sampled to determine the GPMC CS0 bus width:

• 0 = 8-bit data bus

• 1 = 16-bit data bus

After reset, this pin functions as GPMC multiplexed data/address pin 12 (GPMC_D[12]).

RSTOUT_WD_OUT Configuration. This pin is multiplexed between ARM Cortex-A8 boot mode and General-Purpose Memory Controller (GPMC) peripheral functions. At reset, BOOT[11] is sampled to determine the function of the RSTOUT_WD_OUT pin:

• 0 = RSTOUT is asserted when a Watchdog Timer reset, POR, RESET, or Emulation/Software-Global Cold/Warm reset occurs

• 1 = RSTOUT_WD_OUT is asserted only when a Watchdog Timer reset occurs

After reset, this pin functions as GPMC multiplexed data/address pin 11 (GPMC_D[11]).

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DESCRIPTION

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.

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Table 3-1. Boot Configuration Terminal Functions (continued)

SIGNAL

NAME NO.

GPMC_D[10]/ DIS BTMODE[10] DVDD_GPMC

GPMC_D[9]/ DIS

BTMODE[9] DVDD_GPMC

GPMC_D[8]/ DIS

BTMODE[8] DVDD_GPMC

GPMC_D[7]/ DIS

BTMODE[7] DVDD_GPMC

GPMC_D[6]/ DIS

BTMODE[6] DVDD_GPMC

GPMC_D[5]/ DIS

BTMODE[5] DVDD_GPMC

GPMC_D[4]/ DIS

BTMODE[4] DVDD_GPMC

GPMC_D[3]/ DIS

BTMODE[3] DVDD_GPMC

GPMC_D[2]/ DIS more details on the types of boot modes supported, see

BTMODE[2] DVDD_GPMC Section 4.2, Boot Modes of this document along with the

GPMC_D[1]/ DIS

BTMODE[1] DVDD_GPMC

GPMC_D[0]/ DIS

BTMODE[0] DVDD_GPMC

Y26 I PINCNTL99

AB28 I PINCNTL98

Y27 I PINCNTL97

V25 I PINCNTL96

U25 I PINCNTL95

AA28 I PINCNTL94

V26 I PINCNTL93

W27 I PINCNTL92

V27 I PINCNTL91

Y28 I PINCNTL90

U26 I PINCNTL89

TYPE

(1)

OTHER

(2) (3)

MUXED DESCRIPTION

GPMC

DSIS: PIN

GPMC

DSIS: PIN

GPMC

DSIS: PIN

GPMC

DSIS: PIN

GPMC

DSIS: PIN

GPMC

DSIS: PIN

GPMC

DSIS: PIN

GPMC

DSIS: PIN

GPMC

DSIS: PIN

GPMC

DSIS: PIN

GPMC

DSIS: PIN

Reserved Boot Pins. These pins are multiplexed between ARM Cortex-A8 boot mode and General-Purpose Memory Controller (GPMC) peripheral functions.

For proper device operation at reset, these pins should be externally pulled low.

After reset, these pins function as GPMC multiplexed data/address pins 10 through 5 (GPMC_D[10:5]).

ARM Cortex-A8 Boot Mode Configuration Bits. These pins are multiplexed between ARM Cortex-A8 boot mode and the General-Purpose Memory Controller (GPMC) peripheral functions.

At reset, the boot mode inputs BTMODE[4:0] are sampled to determine the ARM boot configuration. For

TMS320DM814x ROM Code Memory and Peripheral Booting Section of the TMS320DM814x DaVinci™ Digital Media Processors Technical Reference Manual

(Literature Number: SPRUGZ8). After reset, these pins function as GPMC multiplexed

data/address pins 4 through 0 (GPMC_D[4:0]).

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3.2.2 Camera Interface (I/F)

SIGNAL

NAME NO.

VOUT[0]_FLD/ CAM_PCLK/ GPMC_A[12]/ AF18 I Camera Pixel Clock. UART2_RTS/ GP2[2]

VIN[0]A_D[23]/ CAM_D[15]/ EMAC[1]_RMTXEN/ AC16 I SPI[3]_D[0]/ GP0[17]

VIN[0]A_D[22]/ CAM_D[14]/ EMAC[1]_RMTXD[1]/ AC21 I SPI[3]_D[1]/ GP0[16]

VIN[0]A_D[21]/ CAM_D[13]/ EMAC[1]_RMTXD[0]/ AE18 I SPI[3]_SCLK/ GP0[15]

VIN[0]A_D[20]/ CAM_D[12]/ EMAC[1]_RMCRSDV/ AC17 I SPI[3]_SCS[0]/ GP0[14]

VIN[0]A_D[19]/ CAM_D[11]/ EMAC[1]_RMRXD[0]/ AF21 I I2C[3]_SDA/ GP0[13]

VIN[0]A_D[18]/ CAM_D[10]/ EMAC[1]_RMRXD[1]/ AF20 I I2C[3]_SCL/ GP0[12]

VIN[0]A_D[17]/ VIN[0]A, EMAC[1]_RM, CAM_D[9]/ IPD GP0 EMAC[1]_RMRXER/ DVDD_C PINCNTL157 GP0[11] DSIS: PIN

VIN[0]A_D[16]/ CAM_D[8]/ IPU I2C[2]_SCL/ DVDD_C GP0[10]

AB21 I

AA21 I PINCNTL156

Table 3-2. Camera I/F Terminal Functions

TYPE

(1)

(2) (3)

OTHER

VOUT[0], GPMC, UART2,

IPD GP2

DVDD_C PINCNTL175

VIN[0]A, EMAC[1], SPI[3],

IPD GP0

DVDD_C PINCNTL163

IPD SPI[3], GP0

DVDD_C PINCNTL162

IPD SPI[3], GP0

DVDD_C PINCNTL161

IPD SPI[3], GP0

DVDD_C PINCNTL160

IPU I2C[3], GP0

DVDD_C PINCNTL159

IPU I2C[3], GP0

DVDD_C PINCNTL158

MUXED DESCRIPTION

CAMERA I/F

DSIS: 0

DSIS: PIN

VIN[0]A, EMAC[1]_RM,

DSIS: PIN

VIN[0]A, EMAC[1]_RM,

DSIS: PIN

VIN[0]A, EMAC[1]_RM,

DSIS: PIN

VIN[0]A, EMAC[1]_RM,

DSIS: PIN

VIN[0]A, EMAC[1]_RM,

DSIS: PIN

VIN[0]A, I2C[2], GP0

DSIS: PIN

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Camera data inputs

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.

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Table 3-2. Camera I/F Terminal Functions (continued)

SIGNAL

NAME NO.

VIN[0]A_DE/ VIN[0]A, GP0 CAM_D[7]/ AB17 I PINCNTL164 GP0[18] DSIS: PIN

VIN[0]B_DE/ VIN[0]A, GP0 CAM_D[6]/ AC15 I PINCNTL165 GP0[19] DSIS: PIN

VIN[0]A_FLD/ VIN[0]A, GP0 CAM_D[5]/ AC22 I PINCNTL166 GP0[20] DSIS: PIN

VIN[0]B_FLD/ VIN[0]B, GP0 CAM_D[4]/ AD17 I PINCNTL167 GP0[21] DSIS: PIN

VOUT[1]_G_Y_YC[1]/ CAM_D[3]/ GPMC_A[5]/ AD18 I UART4_RXD/ GP0[22]

VOUT[1]_G_Y_YC[0]/ CAM_D[2]/ GPMC_A[6]/ AC18 I UART4_TXD/ GP0[23]

VOUT[1]_R_CR[1]/ CAM_D[1]/ GPMC_A[7]/ AC19 I UART4_CTS/ GP0[24]

VOUT[1]_R_CR[0]/ CAM_D[0]/ GPMC_A[8]/ AA22 I UART4_RTS/ GP0[25]

VOUT[1]_B_CB_C[1]/ CAM_HS/ GPMC_A[9]/ AE23 I/O Camera Horizontal Synchronization UART2_RXD/ GP0[26]

VOUT[1]_B_CB_C[0]/ CAM_VS/ GPMC_A[10]/ AD23 I/O Camera Vertical Synchronization UART2_TXD/ GP0[27]

VIN[0]A_D[13]_BD[5]/ VIN[0]AB, GP2 CAM_RESET/ AF17 I/O PINCNTL153 Camera Reset. Used for Strobe Synchronization GP2[18] DSIS: 0

VIN[0]A_D[11]_BD[3]/ CAM_WE/ AH17 I GP2[16]

VOUT[1]_FLD/ CAM_FLD/ CAM_WE/ IPD GPMC_A[11]/ DVDD_C UART2_CTS/ GP0[28]

VOUT[1]_FLD/ CAM_FLD/ VOUT[1], CAMERA_I/F, CAM_WE/ IPD GPMC, UART2, GP0 GPMC_A[11]/ DVDD_C PINCNTL174 UART2_CTS/ DSIS: 0 GP0[28]

AB23 I PINCNTL174

AB23 I/O Camera Field Identification input

TYPE

(1)

(2) (3)

OTHER

IPU

DVDD_C

IPU

DVDD_C

IPU

DVDD_C

IPU

DVDD_C

IPU GP0

DVDD_C PINCNTL168

IPD GP0

DVDD_C PINCNTL169

IPD GP0

DVDD_C PINCNTL170

IPD GP0

DVDD_C PINCNTL171

IPD GP0

DVDD_C PINCNTL172

IPU GP0

DVDD_C PINCNTL173

IPD

DVDD

IPD PINCNTL151

DVDD DSIS: 0

VOUT[1], GPMC, UART4,

VOUT[1], GPMC, UART2,

VOUT[1], CAMERA_I/F,

GPMC, UART2, GP0

MUXED DESCRIPTION

DSIS: PIN

DSIS: 0

VIN[0]AB. GP2

MM: MUX1

DSIS: 0

MM: MUX0

Camera data inputs

Camera Write Enable

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Table 3-2. Camera I/F Terminal Functions (continued)

SIGNAL

NAME NO.

VIN[0]A_D[14]_BD[6]/ VIN[0]AB, GP2 CAM_STROBE/ AC12 O PINCNTL154 Camera Flash Strobe Control Signal GP2[19] DSIS: N/A

VIN[0]A_D[15]_BD[7]/ VIN[0]AB, GP2 CAM_SHUTTER/ AC14 O PINCNTL155 Camera Mechanical Shutter Control Signal GP2[20] DSIS: N/A

TYPE

(1)

OTHER

IPD

DVDD

IPD

DVDD

(2) (3)

MUXED DESCRIPTION

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3.2.3 Controller Area Network (DCAN) Modules (DCAN0, DCAN1)

Table 3-3. DCAN Terminal Functions

SIGNAL

NAME NO.

DCAN0_RX/

UART2_RXD/ IPU I2C[3]_SCL/ DVDD GP1[1]

DCAN0_TX/ UART2_TXD/ IPU I2C[3]_SDA/ DVDD GP1[0]

UART0_RTS/ UART4_TXD/ DCAN1_RX/ AF5 I/O DCAN1 receive data pin. SPI[1]_SCS[2]/ SD2_SDCD

UART0_CTS/ UART4_RXD/ DCAN1_TX/ AE6 I/O DCAN1 transmit data pin. SPI[1]_SCS[3]/ SD0_SDCD

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.

(3) Specifies the operating I/O supply voltage for each signal

AG6 I/O PINCNTL69 DCAN0 receive data pin.

AH6 I/O PINCNTL68 DCAN0 transmit data pin.

TYPE

(1)

(2) (3)

OTHER

IPU SD2

DVDD PINCNTL73

IPU SD0

DVDD PINCNTL72

MUXED DESCRIPTION

DCAN0

UART2, I2C[3], GP1

DSIS: 1

UART2, I2C[3], GP1

DSIS: 1

DCAN1

UART0, UART4, SPI[1],

DSIS: 1

UART0, UART4, SPI[1],

DSIS: 1

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3.2.4 LPDDR/DDR2/DDR3 Memory Controller

Table 3-4. LPDDR/DDR2/DDR3 Memory Controller 0 Terminal Functions

SIGNAL

NAME NO.

DDR[0]_CLK B16 O The internal pulldown (IPD) is enabled for this pin when the device is

DDR[0]_CLK A16 O The internal pullup (IPU) is enabled for this pin when the device is in

DDR[0]_CKE H18 O DDR[0] Clock Enable

DDR[0]_WE C17 O The internal pullup (IPU) is enabled for this pin when the device is in

DDR[0]_CS[0] F18 O The internal pullup (IPU) is enabled for this pin when the device is in

DDR[0]_CS[1] G17 O The internal pullup (IPU) is enabled for this pin when the device is in

DDR[0]_RAS B18 O The internal pullup (IPU) is enabled for this pin when the device is in

DDR[0]_CAS C18 O The internal pullup (IPU) is enabled for this pin when the device is in

DDR[0]_DQM[3] F20 O

DDR[0]_DQM[2] C24 O

DDR[0]_DQM[1] B28 O

DDR[0]_DQM[0] E28 O

DDR[0]_DQS[3] B21 I/O

DDR[0]_DQS[2] B23 I/O

DDR[0]_DQS[1] B26 I/O

DDR[0]_DQS[0] D28 I/O

DDR[0]_DQS[3] A21 I/O

DDR[0]_DQS[2] A23 I/O

DDR[0]_DQS[1] A26 I/O

DDR[0]_DQS[0] D27 I/O

(1)

TYPE

LPDDR/DDR2/DDR3 Memory Controller 0 (DDR[0])

DVDD_DDR[0]

OTHER

IPD/DIS

IPU/DIS

IPD

IPU/DIS

IPU

IPD

IPU

(2) (3)

DDR[0] Clock in reset and the IPD is disabled (DIS) when reset is released.

DDR[0] Negative Clock reset and the IPU is disabled (DIS) when reset is released.

DDR[0] Write Enable reset and the IPU is disabled (DIS) when reset is released.

DDR[0] Chip Select 0 reset and the IPU is disabled (DIS) when reset is released.

DDR[0] Chip Select 1 reset and the IPU is disabled (DIS) when reset is released.

DDR[0] Row Address Strobe output reset and the IPU is disabled (DIS) when reset is released.

DDR[0] Column Address Strobe output reset and the IPU is disabled (DIS) when reset is released.

DDR[0] Data Mask outputs DDR[0]_DQM[3]: For upper byte data bus DDR[0]_D[31:24] DDR[0]_DQM[2]: For DDR[0]_D[23:16] DDR[0]_DQM[1]: For DDR[0]_D[15:8] DDR[0]_DQM[0]: For lower byte data bus DDR[0]_D[7:0]

The internal pullup (IPU) is enabled for these pins when the device is in reset and switches to an IPD enabled when reset is released.

Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[0] memory when writing and inputs when reading. They are used to synchronize the data transfers. DDR[0]_DQS[3]: For upper byte data bus DDR[0]_D[31:24] DDR[0]_DQS[2]: For DDR[0]_D[23:16] DDR[0]_DQS[1]: For DDR[0]_D[15:8] DDR[0]_DQS[0]: For lower byte data bus DDR[0]_D[7:0]

Complimentary data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[0] memory when writing and inputs when reading. They are used to synchronize the data transfers. DDR[0]_DQS[3]: For upper byte data bus DDR[0]_D[31:24] DDR[0]_DQS[2]: For DDR[0]_D[23:16] DDR[0]_DQS[1]: For DDR[0]_D[15:8] DDR[0]_DQS[0]: For lower byte data bus DDR[0]_D[7:0]

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DESCRIPTION

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.

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Table 3-4. LPDDR/DDR2/DDR3 Memory Controller 0 Terminal Functions (continued)

SIGNAL

NAME NO.

DDR[0]_ODT[0] G18 O The internal pulldown (IPD) is enabled for this pin when the device is

DDR[0]_ODT[1] H19 O The internal pulldown (IPD) is enabled for this pin when the device is

DDR[0]_RST G19 O

DDR[0]_BA[2] A18 O

DDR[0]_BA[1] A20 O

DDR[0]_BA[0] F15 O

DDR[0]_A[14] F16 O

DDR[0]_A[13] F17 O

DDR[0]_A[12] E17 O

DDR[0]_A[11] D17 O

DDR[0]_A[10] A19 O

DDR[0]_A[9] C15 O

DDR[0]_A[8] B15 O

DDR[0]_A[7] E18 O

DDR[0]_A[6] A15 O

DDR[0]_A[5] B17 O

DDR[0]_A[4] D15 O

DDR[0]_A[3] E15 O

DDR[0]_A[2] D18 O

DDR[0]_A[1] F19 O

DDR[0]_A[0] B19 O

TYPE

(1)

(2) (3)

OTHER

IPD/DIS

DVDD_DDR[0]

IPD/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

IPU/DIS

DVDD_DDR[0]

ZHCS057–MARCH 2011

DESCRIPTION

DDR[0] On-Die Termination for Chip Select 0. in reset and the IPD is disabled (DIS) when reset is released.

DDR[0] On-Die Termination for Chip Select 1. in reset and the IPD is disabled (DIS) when reset is released.

DDR[0] Reset output The internal pullup (IPU) is enabled for this pin when the device is in

reset and the IPU is disabled (DIS) when reset is released.

DDR[0] Bank Address outputs The internal pullup (IPU) is enabled for these pins when the device is

in reset and the IPU is disabled (DIS) when reset is released.

DDR[0] Address Bus The internal pullup (IPU) is enabled for these pins when the device is

in reset and the IPU is disabled (DIS) when reset is released.

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Table 3-4. LPDDR/DDR2/DDR3 Memory Controller 0 Terminal Functions (continued)

SIGNAL

NAME NO.

DDR[0]_D[31] B20 I/O

DDR[0]_D[30] D21 I/O

DDR[0]_D[29] C21 I/O

DDR[0]_D[28] C20 I/O

DDR[0]_D[27] A22 I/O

DDR[0]_D[26] G20 I/O

DDR[0]_D[25] F21 I/O

DDR[0]_D[24] H20 I/O

DDR[0]_D[23] B22 I/O

DDR[0]_D[22] C23 I/O

DDR[0]_D[21] E23 I/O

DDR[0]_D[20] D23 I/O

DDR[0]_D[19] G21 I/O

DDR[0]_D[18] H21 I/O

DDR[0]_D[17] F22 I/O

DDR[0]_D[16] B24 I/O

TYPE

(1)

(2) (3)

OTHER

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

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DESCRIPTION

DDR[0] Data Bus

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Table 3-4. LPDDR/DDR2/DDR3 Memory Controller 0 Terminal Functions (continued)

SIGNAL

NAME NO.

DDR[0]_D[15] A24 I/O

DDR[0]_D[14] A25 I/O

DDR[0]_D[13] D24 I/O

DDR[0]_D[12] B25 I/O

DDR[0]_D[11] A27 I/O

DDR[0]_D[10] C26 I/O

DDR[0]_D[9] C25 I/O

DDR[0]_D[8] C27 I/O

DDR[0]_D[7] C28 I/O

DDR[0]_D[6] D26 I/O

DDR[0]_D[5] E25 I/O

DDR[0]_D[4] F24 I/O

DDR[0]_D[3] F25 I/O

DDR[0]_D[2] E26 I/O

DDR[0]_D[1] F26 I/O

DDR[0]_D[0] E27 I/O

DDR[0]_VTP B27 I DDR VTP Compensation Resistor Connection

TYPE

(1)

(2) (3)

OTHER

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

IPD

DVDD_DDR[0]

–

DVDD_DDR[0]

DESCRIPTION

DDR[0] Data Bus

ZHCS057–MARCH 2011

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Table 3-5. LPDDR/DDR2/DDR3 Memory Controller 1 Terminal Functions

SIGNAL

NAME NO.

DDR[1]_CLK B13 O The internal pulldown (IPD) is enabled for this pin when the device is

DDR[1]_CLK A13 O The internal pullup (IPU) is enabled for this pin when the device is in

DDR[1]_CKE H11 O DDR[1] Clock Enable

DDR[1]_WE E12 O The internal pullup (IPU) is enabled for this pin when the device is in

DDR[1]_CS[0] G12 O The internal pullup (IPU) is enabled for this pin when the device is in

DDR[1]_CS[1] G11 O The internal pullup (IPU) is enabled for this pin when the device is in

DDR[1]_RAS C12 O The internal pullup (IPU) is enabled for this pin when the device is in

DDR[1]_CAS F13 O The internal pullup (IPU) is enabled for this pin when the device is in

DDR[1]_DQM[3] G9 O

DDR[1]_DQM[2] G8 O

DDR[1]_DQM[1] B2 O

DDR[1]_DQM[0] F4 O

DDR[1]_DQS[3] B8 I/O

DDR[1]_DQS[2] A6 I/O

DDR[1]_DQS[1] B3 I/O

DDR[1]_DQS[0] D1 I/O

DDR[1]_DQS[3] A8 I/O

DDR[1]_DQS[2] B6 I/O

DDR[1]_DQS[1] A3 I/O

DDR[1]_DQS[0] D2 I/O

DDR[1]_ODT[0] H10 O The internal pulldown (IPD) is enabled for this pin when the device is

(1)

TYPE

LPDDR/DDR2/DDR3 Memory Controller 1 (DDR[1])

DVDD_DDR[1]

DVDD_DDR[1] data bus. They are outputs to the DDR[1] memory when writing and

DVDD_DDR[1]

(2) (3)

OTHER

IPD/DIS

IPU/DIS

IPD

IPU/DIS

IPU/IPD

IPD

IPU/IPD Complimentary data strobe input/outputs for each byte of the 32-bit

IPU/IPD

IPD/DIS

DDR[1] Clock in reset and the IPD is disabled (DIS) when reset is released.

DDR[1] Negative Clock reset and the IPU is disabled (DIS) when reset is released.

DDR[1] Write Enable reset and the IPU is disabled (DIS) when reset is released.

DDR[1] Chip Select 0 reset and the IPU is disabled (DIS) when reset is released.

DDR[1] Chip Select 1 reset and the IPU is disabled (DIS) when reset is released.

DDR[1] Row Address Strobe output reset and the IPU is disabled (DIS) when reset is released.

DDR[1] Column Address Strobe output reset and the IPU is disabled (DIS) when reset is released.

DDR[1] Data Mask outputs DDR[1]_DQM[3]: For upper byte data bus DDR[1]_D[31:24] DDR[1]_DQM[2]: For DDR[1]_D[23:16] DDR[1]_DQM[1]: For DDR[1]_D[15:8] DDR[1]_DQM[0]: For lower byte data bus DDR[1]_D[7:0]

The internal pullup (IPU) is enabled for these pins when the device is in reset and switches to an IPD enabled when reset is released.

Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[1] memory when writing and inputs when reading. They are used to synchronize the data transfers. DDR[1]_DQS[3]: For upper byte data bus DDR[1]_D[31:24] DDR[1]_DQS[2]: For DDR[1]_D[23:16] DDR[1]_DQS[1]: For DDR[1]_D[15:8] DDR[1]_DQS[0]: For lower byte data bus DDR[1]_D[7:0]

inputs when reading. They are used to synchronize the data transfers. DDR[1]_DQS[3]: For upper byte data bus DDR[1]_D[31:24] DDR[1]_DQS[2]: For DDR[1]_D[23:16] DDR[1]_DQS[1]: For DDR[1]_D[15:8] DDR[1]_DQS[0]: For lower byte data bus DDR[1]_D[7:0]

The internal pullup (IPU) is enabled for these pins when the device is in reset and switches to an IPD enabled when reset is released.

DDR[1] On-Die Termination for Chip Select 0. in reset and the IPD is disabled (DIS) when reset is released.

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DESCRIPTION

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.

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Table 3-5. LPDDR/DDR2/DDR3 Memory Controller 1 Terminal Functions (continued)

SIGNAL

NAME NO.

DDR[1]_ODT[1] F11 O The internal pulldown (IPD) is enabled for this pin when the device is

DDR[1]_RST G10 O The internal pullup (IPU) is enabled for this pin when the device is in

DDR[1]_BA[2] D12 O

DDR[1]_BA[1] A10 O

DDR[1]_BA[0] F14 O

DDR[1]_A[14] D11 O

DDR[1]_A[13] E11 O

DDR[1]_A[12] B10 O

DDR[1]_A[11] A11 O

DDR[1]_A[10] F12 O

DDR[1]_A[9] C14 O

DDR[1]_A[8] E14 O

DDR[1]_A[7] A9 O

DDR[1]_A[6] D14 O

DDR[1]_A[5] B12 O

DDR[1]_A[4] B14 O

DDR[1]_A[3] A14 O

DDR[1]_A[2] C11 O

DDR[1]_A[1] F10 O

DDR[1]_A[0] B11 O

TYPE

(1)

OTHER

DVDD_DDR[1]

(2) (3)

IPD/DIS

IPU/DIS

ZHCS057–MARCH 2011

DESCRIPTION

DDR[1] On-Die Termination for Chip Select 1. in reset and the IPD is disabled (DIS) when reset is released.

DDR[1] Reset output. reset and the IPU is disabled (DIS) when reset is released.

DDR[1] Bank Address outputs The internal pullup (IPU) is enabled for these pins when the device is

in reset and the IPU is disabled (DIS) when reset is released.

DDR[1] Address Bus The internal pullup (IPU) is enabled for these pins when the device is

in reset and the IPU is disabled (DIS) when reset is released.

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Table 3-5. LPDDR/DDR2/DDR3 Memory Controller 1 Terminal Functions (continued)

SIGNAL

NAME NO.

DDR[1]_D[31] B9 I/O

DDR[1]_D[30] C8 I/O

DDR[1]_D[29] D8 I/O

DDR[1]_D[28] C9 I/O

DDR[1]_D[27] A7 I/O

DDR[1]_D[26] F8 I/O

DDR[1]_D[25] H9 I/O

DDR[1]_D[24] F9 I/O

DDR[1]_D[23] B7 I/O

DDR[1]_D[22] D6 I/O

DDR[1]_D[21] E6 I/O

DDR[1]_D[20] C6 I/O

DDR[1]_D[19] B5 I/O

DDR[1]_D[18] C5 I/O

DDR[1]_D[17] F7 I/O

DDR[1]_D[16] H8 I/O

TYPE

(1)

OTHER

DVDD_DDR[1]

IPD

(2) (3)

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DESCRIPTION

DDR[1] Data Bus

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Table 3-5. LPDDR/DDR2/DDR3 Memory Controller 1 Terminal Functions (continued)

SIGNAL

NAME NO.

DDR[1]_D[15] A5 I/O

DDR[1]_D[14] A4 I/O

DDR[1]_D[13] C4 I/O

DDR[1]_D[12] B4 I/O

DDR[1]_D[11] A2 I/O

DDR[1]_D[10] C3 I/O

DDR[1]_D[9] D5 I/O

DDR[1]_D[8] C2 I/O

DDR[1]_D[7] C1 I/O

DDR[1]_D[6] D3 I/O

DDR[1]_D[5] E4 I/O

DDR[1]_D[4] F5 I/O

DDR[1]_D[3] E1 I/O

DDR[1]_D[2] E2 I/O

DDR[1]_D[1] F3 I/O

DDR[1]_D[0] E3 I/O

DDR[1]_VTP B1 I DDR[1] VTP Compensation Resistor Connection

TYPE

(1)

OTHER

DVDD_DDR[1]

IPD

–

(2) (3)

DESCRIPTION

DDR[1] Data Bus

ZHCS057–MARCH 2011

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3.2.5 EDMA

SIGNAL

NAME NO.

AUD_CLKIN1/ AUD_CLKIN1, MCA[0]_AXR[8]/ MCA[0], MCA[1], MCA[1]_AHCLKX/ MCA[4], TIMER2, MCA[4]_AHCLKX/ R5 I GP0 EDMA_EVT3/ PINCNTL15 TIM2_IO/ DSIS: PIN GP0[8] MM: MUX1

GPMC_CLK/ GPMC_CS[5]/ GPMC, CLKOUT1, GPMC_WAIT[1]/ TIMER4, GP1 CLKOUT1/ R26 I PINCNTL127 EDMA_EVT3/ DSIS: PIN TIM4_IO/ MM: MUX0 GP1[27]

AUD_CLKIN2/ AUD_CLKIN2, MCA[0]_AXR[9]/ MCA[0], MCA[2]. MCA[2]_AHCLKX/ MCA[5], TIMER3, MCA[5]_AHCLKX/ H1 I GP0 EDMA_EVT2/ PINCNTL16 TIM3_IO/ DSIS: PIN GP0[9] MM: MUX1

GPMC_BE[0]_CLE/ GPMC, TIMER6, GPMC_A[25]/ GP1 EDMA_EVT2/ U27 I PINCNTL131 TIM6_IO/ DSIS: PIN GP1[29] MM: MUX0

SPI[0]_SCS[1]/ SPI[0], SD1, SD1_SDCD/ SATA, TIMER4, SATA_ACT0_LED/ IPU GP1 EDMA_EVT1/ DVDD PINCNTL80 TIM4_IO/ DSIS: PIN GP1[6] MM: MUX1

GPMC_BE[1]/ GPMC, TIMER7, GPMC_A[24]/ GP1 EDMA_EVT1/ V28 I PINCNTL132 TIM7_IO/ DSIS: PIN GP1[30] MM: MUX0

SD2_DAT[4]/ GPMC_A[27]/ SD2, GPMC, GPMC_A[23]/ TIMER7, GP1 GPMC_CS[7]/ R24 I PINCNTL116 EDMA_EVT0/ DSIS: PIN TIM7_IO/ MM: MUX1 GP1[22]

GPMC_WAIT[0]/ GPMC, GP1 GPMC_A[26]/ IPU PINCNTL133 EDMA_EVT0/ DVDD_GPMC DSIS: PIN GP1[31] MM: MUX0

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and the , Pin Behaviors at Reset.

(3) Specifies the operating I/O supply voltage for each signal

AE5 I

W28 I

TYPE

Table 3-6. EDMA Terminal Functions

(1)

DVDD_GPMC

OTHER

IPD

DVDD

IPU

IPD

DVDD

IPD

IPU

(2) (3)

MUXED DESCRIPTION

EDMA

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External EDMA Event 3

External EDMA Event 2

External EDMA Event 1

External EDMA Event 0

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ZHCS057–MARCH 2011

3.2.6 EMAC [(R)(G)MII Modes] and MDIO

Table 3-7. EMAC[0] Terminal Functions [(R)(G)MII]

SIGNAL

NAME NO.

TBD These pin functions are available only when GMII or MII modes are selected.

EMAC[0]_MCOL/ EMAC[0]_RGRXCTL/ VIN[1]B_D[1]/ L23 I [G]MII Collision Detect (Sense) input EMAC[0]_RMRXD[0]/ GP3[24]

EMAC[0]_MCRS/ EMAC[0]_RGRXD[2]/ VIN[1]B_D[2]/ R25 I [G]MII Carrier Sense input EMAC[0]_RMRXD[1]/ GP3[25]

EMAC[0]_GMTCLK/ EMAC[1], EMAC[1]_RGRXC/ IPD GPMC, SPI[2] GPMC_A[6]/ DVDD_GPMC PINCNTL249 SPI[2]_D[1] DSIS: N/A

EMAC[0]_MRCLK/ EMAC[0]_RGTXC/ VIN[1]B_D[4]/ IPD EMAC[0]_RMCRSDV/ DVDD_GPMC SPI[3]_SCS[2]/ GP3[27]

K23 O GMII Source Asynchronous Transmit Clock

H27 I GP3 [G]MII Receive Clock

TYPE

(1)

DVDD_GPMC PINCNTL236

DVDD_GPMC PINCNTL237

(2) (3)

OTHER

EMAC[0] (G)MII Mode

IPD VIN[1]B, GP3

VIN[1]B, SPI[3],

PINCNTL239

MUXED DESCRIPTION

EMAC[0],

DSIS: 0

EMAC[0],

DSIS: 0

EMAC[0],

DSIS: 0

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.

(3) Specifies the operating I/O supply voltage for each signal

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Table 3-7. EMAC[0] Terminal Functions [(R)(G)MII] (continued)

SIGNAL

NAME NO.

EMAC[0]_MRXD[7]/ EMAC[0],

EMAC[0]_RGTXD[1]/ GPMC, SPI[2] GPMC_A[4]/ PINCNTL247 SPI[2]_SCS[3] DSIS: PIN

EMAC[0]_MRXD[6]/ EMAC[0], EMAC[0]_RGTXD[2]/ GPMC, UART5 GPMC_A[3]/ PINCNTL246 UART5_RTS DSIS: PIN

EMAC[0]_MRXD[5]/ EMAC[0], EMAC[0]_RGTXD[3]/ GPMC, UART5 GPMC_A[2]/ PINCNTL245 UART5_CTS DSIS: PIN

EMAC[0]_MRXD[4]/ EMAC[0], EMAC[0]_RGRXD[3]/ GPMC, UART5 GPMC_A[1]/ PINCNTL244 UART5_TXD DSIS: PIN

EMAC[0]_MRXD[3]/ EMAC[1]_RGRXCTL/ EMAC[1], GPMC_A[27]/ GPMC, UART5 GPMC_A[26]/ PINCNTL243 GPMC_A[0]/ DSIS: PIN UART5_RXD

EMAC[0]_MRXD[2]/ EMAC[0]_RGRXD[1]/ VIN[1]B_D[7]/ R23 EMAC[0]_RMTXEN/ GP3[30]

EMAC[0]_MRXD[1]/ EMAC[0]_RGRXD[0]/ VIN[1]B_D[6]/ P23 EMAC[0]_RMTXD[1]/ GP3[29]

EMAC[0]_MRXD[0]/ EMAC[0]_RGTXD[0]/ VIN[1]B_D[5]/ G28 EMAC[0]_RMTXD[0]/ GP3[28]

EMAC[0]_MRXDV/ EMAC[1], EMAC[1]_RGRXD[1]/ IPD GPMC, SPI[2] GPMC_A[5]/ DVDD_GPMC PINCNTL248 SPI[2]_SCLK DSIS: 0

EMAC[0]_MRXER/ EMAC[0]_RGTXCTL/ VIN[1]B_D[3]/ J26 I [G]MII Receive Data Error input EMAC[0]_RMRXER/ GP3[26]

EMAC[0]_MTCLK/ EMAC[0]_RGRXC/ VIN[1]B_D[0]/ IPD SPI[3]_SCS[3]/ DVDD_GPMC I2C[2]_SDA/ GP3[23]

(1)

TYPE

G27

F28

H26

T23

I

J25

K22 I [G]MII Receive Data Valid input

L24 I I2C[2], GP3 [G]MII Transmit Clock input

DVDD_GPMC EMAC MII operation, only EMAC[0]_RXD[3:0] are

DVDD_GPMC PINCNTL238

(2) (3)

OTHER

IPD operation, EMAC[0]_RXD[7:0] are used. For 10/100

IPD VIN[1]B, GP3

MUXED DESCRIPTION

[G]MII Receive Data [7:0]. For 1000 EMAC GMII

used.

EMAC[0],

VIN[1]B, GP3

PINCNTL242

DSIS: PIN

EMAC[0],

VIN[1]B, GP3

PINCNTL241

DSIS: PIN

EMAC[0],

VIN[1]B, GP3

PINCNTL240

DSIS: PIN

EMAC[0],

DSIS: 0

EMAC[0],

VIN[1]B, SPI[3],

PINCNTL235

DSIS: 0

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Table 3-7. EMAC[0] Terminal Functions [(R)(G)MII] (continued)

SIGNAL

NAME NO.

EMAC[0]_MTXD[7]/

EMAC[1]_RGTXD[3]/ EMAC[1]_RMTXD[1]/ H24 GPMC_A[14]/ UART1_CTS

EMAC[0]_MTXD[6]/ EMAC[1]_RGRXD[0]/ EMAC[1]_RMTXD[0]/ J22 GPMC_A[13]/ UART1_TXD

EMAC[0]_MTXD[5]/ EMAC[1]_RGTXC/ EMAC[1]_RMCRSDV/ F27 GPMC_A[12]/ UART1_RXD

EMAC[0]_MTXD[4]/ EMAC[1]_RGTXD[2]/ EMAC[1]_RMRXER/ G23 GPMC_A[11]/ UART4_RTS

EMAC[0]_MTXD[3]/ EMAC[1]_RGTXD[0]/ EMAC[1]_RMRXD[1]/ H23 GPMC_A[10]/ UART4_CTS

EMAC[0]_MTXD[2]/ EMAC[1]_RGTXCTL/ EMAC[1]_RMRXD[0]/ H22 GPMC_A[9]/ UART4_TXD

EMAC[0]_MTXD[1]/ EMAC[1], EMAC[1]_RGTXD[1]/ GPMC, UART4 GPMC_A[8]/ PINCNTL251 UART4_RXD DSIS: N/A

EMAC[0]_MTXD[0]/ EMAC[1], EMAC[1]_RGRXD[3]/ GPMC, UART4 GPMC_A[7]/ PINCNTL250 SPI[2]_D[0] DSIS: N/A

EMAC[0]_MTXEN/ EMAC[1]_RGRXD[2]/ EMAC[1]_RMTXEN/ J23 O [G]MII Transmit Data Enable output GPMC_A[15]/ UART1_RTS

H25

J24

TBD These pin functions are available only when RMII mode is selected.

EMAC_RMREFCLK/ TIMER2, GP1 TIM2_IO/ J27 I/O PINCNTL232 GP1[10] DSIS: PIN

EMAC[0]_MRCLK/ EMAC[0]_RGTXC/ VIN[1]B_D[4]/ IPD EMAC[0]_RMCRSDV/ DVDD_GPMC SPI[3]_SCS[2]/ GP3[27]

H27 I GP3 RMII Carrier Sense input

TYPE

O

ZHCS057–MARCH 2011

(1)

DVDD_GPMC EMAC MII operation, only EMAC[0]_TXD[3:0] are

DVDD_GPMC PINCNTL258

DVDD_GPMC mode)

(2) (3)

OTHER

IPD operation, EMAC[0]_TXD[7:0] are used. For 10/100

IPD GPMC, UART4

EMAC[0] RMII Mode

IPD RMII Reference Clock (EMAC[0] and EMAC[1] RMII

MUXED DESCRIPTION

EMAC[1],

GPMC, UART1

PINCNTL257

DSIS: N/A

EMAC[1],

GPMC, UART1

PINCNTL256

DSIS: N/A

EMAC[1],

GPMC, UART1

PINCNTL255

DSIS: N/A

EMAC[1],

GPMC, UART4

PINCNTL254

DSIS: N/A

EMAC[1],

GPMC, UART4

PINCNTL253

DSIS: N/A

EMAC[1],

GPMC, UART4

PINCNTL252

DSIS: N/A

EMAC[1],

DSIS: N/A

EMAC[0],

VIN[1]B, SPI[3],

PINCNTL239

DSIS: 0

[G]MII Transmit Data [7:0]. For 1000 EMAC GMII

used.

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Table 3-7. EMAC[0] Terminal Functions [(R)(G)MII] (continued)

SIGNAL

NAME NO.

EMAC[0]_MCRS/ EMAC[0], EMAC[0]_RGRXD[2]/ VIN[1]B, SPI[3], VIN[1]B_D[2]/ R25 I GPI3 EMAC[0]_RMRXD[1]/ PINCNTL237 GP3[25] DSIS: PIN

EMAC[0]_MCOL/ EMAC[0]_RGRXCTL/ VIN[1]B_D[1]/ L23 I EMAC[0]_RMRXD[0]/ GP3[24]

EMAC[0]_MRXER/ EMAC[0]_RGTXCTL/ VIN[1]B_D[3]/ J26 I RMII Receive Data Error input EMAC[0]_RMRXER/ GP3[26]

EMAC[0]_MRXD[1]/ EMAC[0]_RGRXD[0]/ VIN[1]B_D[6]/ P23 O EMAC[0]_RMTXD[1]/ GP3[29]

EMAC[0]_MRXD[0]/ EMAC[0]_RGTXD[0]/ VIN[1]B_D[5]/ G28 O EMAC[0]_RMTXD[0]/ GP3[28]

EMAC[0]_MRXD[2]/ EMAC[0]_RGRXD[1]/ VIN[1]B_D[7]/ R23 O RMII Transmit Data Enable output EMAC[0]_RMTXEN/ GP3[30]

TBD These pin functions are available only when RGMII mode is selected.

EMAC[0]_MTCLK/ EMAC[0]_RGRXC/ VIN[1]B_D[0]/ IPD SPI[3]_SCS[3]/ DVDD_GPMC I2C[2]_SDA/ GP3[23]

EMAC[0]_MCOL/ EMAC[0]_RGRXCTL/ VIN[1]B_D[1]/ L23 I RGMII Receive Control EMAC[0]_RMRXD[0]/ GP3[24]

(1)

TYPE

DVDD_GPMC

DVDD_GPMC PINCNTL236

DVDD_GPMC PINCNTL238

DVDD_GPMC PINCNTL241

DVDD_GPMC PINCNTL240

DVDD_GPMC PINCNTL242

L24 I I2C[2], GP3 RGMII Receive Clock

DVDD_GPMC PINCNTL236

(2) (3)

OTHER

IPD

IPD VIN[1]B, GP3

EMAC[0] RGMII Mode

VIN[1]B, SPI[3],

PINCNTL235

IPD VIN[1]B, GP3

MUXED DESCRIPTION

RMII Receive Data [1:0]. For 10/100 EMAC RMII

EMAC[0],

DSIS: PIN

EMAC[0],

DSIS: 0

EMAC[0],

DSIS: N/A

EMAC[0],

DSIS: N/A

EMAC[0],

DSIS: N/A

EMAC[0],

DSIS: PIN

EMAC[0],

DSIS: PIN

operation, EMAC[0]_RMRXD[1:0] are used.

RMII Transmit Data [7:0]. For 10/100 EMAC RMII operation, EMAC[0]_RMTXD[1:0] are used.

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Table 3-7. EMAC[0] Terminal Functions [(R)(G)MII] (continued)

SIGNAL

NAME NO.

EMAC[0]_MRXD[4]/ EMAC[0], EMAC[0]_RGRXD[3]/ IPD GPMC, UART5 GPMC_A[1]/ DVDD_GPMC PINCNTL244 UART5_TXD DSIS: PIN

EMAC[0]_MCRS/ EMAC[0]_RGRXD[2]/ VIN[1]B_D[2]/ R25 I EMAC[0]_RMRXD[1]/ GP3[25]

EMAC[0]_MRXD[2]/ EMAC[0]_RGRXD[1]/ VIN[1]B_D[7]/ R23 I EMAC[0]_RMTXEN/ GP3[30]

EMAC[0]_MRXD[1]/ EMAC[0]_RGRXD[0]/ VIN[1]B_D[6]/ P23 I EMAC[0]_RMTXD[1]/ GP3[29]

EMAC[0]_MRCLK/ EMAC[0]_RGTXC/ VIN[1]B_D[4]/ IPD EMAC[0]_RMCRSDV/ DVDD_GPMC SPI[3]_SCS[2]/ GP3[27]

EMAC[0]_MRXER/ EMAC[0]_RGTXCTL/ VIN[1]B_D[3]/ J26 O RGMII Transmit Enable EMAC[0]_RMRXER/ GP3[26]

EMAC[0]_MRXD[5]/ EMAC[0], EMAC[0]_RGTXD[3]/ IPD GPMC, UART5 GPMC_A[2]/ DVDD_GPMC PINCNTL245 UART5_CTS DSIS: N/A

EMAC[0]_MRXD[6]/ EMAC[0], EMAC[0]_RGTXD[2]/ IPD GPMC, UART5 GPMC_A[3]/ DVDD_GPMC PINCNTL246 UART5_RTS DSIS: N/A

EMAC[0]_MRXD[7]/ EMAC[0], EMAC[0]_RGTXD[1]/ IPD GPMC, SPI[2] GPMC_A[4]/ DVDD_GPMC PINCNTL247 SPI[2]_SCS[3] DSIS: N/A

EMAC[0]_MRXD[0]/ EMAC[0]_RGTXD[0]/ VIN[1]B_D[5]/ G28 O EMAC[0]_RMTXD[0]/ GP3[28]

T23 I

H27 O GP3 RGMII Transmit Clock

H26 O

F28 O

G27 O

TYPE

(1)

DVDD_GPMC PINCNTL237

DVDD_GPMC PINCNTL242

DVDD_GPMC PINCNTL241

DVDD_GPMC PINCNTL238

DVDD_GPMC PINCNTL240

(2) (3)

OTHER

IPD VIN[1]B, GP3

VIN[1]B, SPI[3],

PINCNTL239

IPD VIN[1]B, GP3

MUXED DESCRIPTION

EMAC[0],

DSIS: PIN

EMAC[0],

DSIS: PIN

EMAC[0],

DSIS: PIN

EMAC[0],

DSIS: N/A

EMAC[0],

DSIS: N/A

EMAC[0],

DSIS: N/A

RGMII Receive Data [3:0]

RGMII Transmit Data [3:0]

ZHCS057–MARCH 2011

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SIGNAL

NAME NO.

TBD These pin functions are available only when GMII and MII modes are selected.

VOUT[1]_HSYNC/ EMAC[1]_MCOL/ VIN[1]A_VSYNC/ IPD SPI[3]_D[1]/ DVDD UART3_RTS/ GP2[29]

VOUT[1]_VSYNC/ EMAC[1]_MCRS/ VOUT[1], VIN[1]A_FLD/ VIN[1]A, SPI[3], VIN[1]A_DE/ AA23 I UART3, GP2 [G]MII Carrier Sense input SPI[3]_D[0]/ PINCNTL206 UART3_CTS/ DSIS: 0 GP2[30]

VOUT[1]_G_Y_YC[6]/ VOUT[1], EMAC[1]_GMTCLK/ IPD VIN[1]A, GP3 VIN[1]A_D[11]/ DVDD PINCNTL218 GP3[10] DSIS: N/A

VOUT[1]_B_CB_C[3]/ VOUT[1], EMAC[1]_MRCLK/ VIN[1]A, VIN[1]A_D[0]/ AH25 I UART4, GP3 [G]MII Receive Clock UART4_CTS/ PINCNTL208 GP3[0] DSIS: 0

AC24 I UART3, GP2 [G]MII Collision Detect (Sense) input

AH27 O GMII Source Asynchronous Transmit Clock

Table 3-8. EMAC[1] Terminal Functions [(R)(G)MII]

TYPE

(1)

(2) (3)

OTHER

EMAC[1] (G)MII Mode

IPD

DVDD

IPD

DVDD

MUXED DESCRIPTION

VOUT[1],

VIN[1]A, SPI[3],

PINCNTL205

DSIS: 0

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(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and the , Pin Behaviors at Reset.

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Table 3-8. EMAC[1] Terminal Functions [(R)(G)MII] (continued)

SIGNAL

NAME NO.

VOUT[1]_G_Y_YC[4]/ VOUT[1], EMAC[1]_MRXD[7]/ VIN[1]A, GP3 VIN[1]A_D[9]/ PINCNTL216 GP3[8] DSIS: PIN

VOUT[1]_G_Y_YC[3]/ VOUT[1], EMAC[1]_MRXD[6]/ VIN[1]A, GP3 VIN[1]A_D[8]/ PINCNTL215 GP3[7] DSIS: PIN

VOUT[1]_B_CB_C[9]/ VOUT[1], EMAC[1]_MRXD[5]/ VIN[1]A, I2C[3], VIN[1]A_D[6]/ AA24 GP3 I2C[3]_SDA/ PINCNTL214 GP3[6] DSIS: PIN

VOUT[1]_B_CB_C[8]/ VOUT[1], EMAC[1]_MRXD[4]/ VIN[1]A, I2C[3], VIN[1]A_D[5]/ AH26 GP3 I2C[3]_SCL/ PINCNTL213 GP3[5] DSIS: PIN

VOUT[1]_B_CB_C[7]/ VOUT[1], EMAC[1]_MRXD[3]/ VIN[1]A, VIN[1]A_D[4]/ AC25 UART3, GP3 UART3_TXD/ PINCNTL212 GP3[4] DSIS: PIN

VOUT[1]_B_CB_C[6]/ VOUT[1], EMAC[1]_MRXD[2]/ VIN[1]A, VIN[1]A_D[3]/ AD25 UART3, GP3 UART3_RXD/ PINCNTL211 GP3[3] DSIS: PIN

VOUT[1]_B_CB_C[5]/ VOUT[1], EMAC[1]_MRXD[1]/ VIN[1]A, VIN[1]A_D[2]/ AF25 UART4, GP3 UART4_TXD/ PINCNTL210 GP3[2] DSIS: PIN

VOUT[1]_B_CB_C[4]/ VOUT[1], EMAC[1]_MRXD[0]/ VIN[1]A, VIN[1]A_D[1]/ AG25 UART4, GP3 UART4_RXD/ PINCNTL209 GP3[1] DSIS: PIN

VOUT[1]_G_Y_YC[5]/ VOUT[1], EMAC[1]_MRXDV/ IPD VIN[1]A, GP3 VIN[1]A_D[10]/ DVDD PINCNTL217 GP3[9] DSIS: 0

VOUT[1]_AVID/ VOUT[1], EMAC[1]_MRXER/ VIN[1]A, VIN[1]A_CLK/ IPD UART4, TIMER UART4_RTS/ DVDD 6, GP2 TIM6_IO/ PINCNTL207 GP2[31] DSIS: 0

VOUT[1]_CLK/ VOUT[1], EMAC[1]_MTCLK/ IPD VIN[1]A, GP2 VIN[1]A_HSYNC/ DVDD PINCNTL204 GP2[28] DSIS: 0

W22

Y23

AG26 I [G]MII Receive Data Valid input

Y22 I [G]MII Receive Data Error input

AE24 I [G]MII Transmit Clock input

TYPE

I

ZHCS057–MARCH 2011

(1)

(2) (3)

OTHER

IPD operation, EMAC[0]_RXD[7:0] are used. For 10/100

DVDD EMAC MII operation, only EMAC[0]_RXD[3:0] are

MUXED DESCRIPTION

[G]MII Receive Data [7:0]. For 1000 EMAC GMII

used.

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Table 3-8. EMAC[1] Terminal Functions [(R)(G)MII] (continued)

SIGNAL

NAME NO.

VOUT[1]_R_CR[8]/ VOUT[1], EMAC[1]_MTXD[7]/ VIN[1]A, VIN[1]A_D[19]/ W23 UART5, GP3 UART5_RXD/ PINCNTL226 GP3[18] DSIS: N/A

VOUT[1]_R_CR[7]/ VOUT[1], EMAC[1]_MTXD[6]/ VIN[1]A, SPI[3], VIN[1]A_D[18]/ V22 GP3 SPI[3]_D[0]/ PINCNTL225 GP3[17] DSIS: N/A

VOUT[1]_R_CR[6]/ VOUT[1], EMAC[1]_MTXD[5]/ VIN[1]A, SPI[3], VIN[1]A_D[17]/ AA25 GP3 SPI[3]_D[1]/ PINCNTL224 GP3[16] DSIS: N/A

VOUT[1]_R_CR[5]/ VOUT[1], EMAC[1]_MTXD[4]/ VIN[1]A, SPI[3], VIN[1]A_D[16]/ AC26 GP3 SPI[3]_SCLK/ PINCNTL223 GP3[15] DSIS: N/A

VOUT[1]_R_CR[4]/ VOUT[1], EMAC]1]_MTXD[3]/ VIN[1]A, SPI[3], VIN]1]A_D[15]/ AG27 GP3 SPI[3]_SCS[1]/ PINCNTL222 GP3[14] DSIS: N/A

VOUT[1]_G_Y_YC[9]/ VOUT[1], EMAC[1]_MTXD[2]/ VIN[1]A, GP3 VIN[1]A_D[14]/ PINCNTL221 GP3[13] DSIS: N/A

VOUT[1]_G_Y_YC[8]/ VOUT[1], EMAC[1]_MTXD[1]/ VIN[1]A, GP3 VIN[1]A_D[13]/ PINCNTL220 GP3[12] DSIS: N/A

VOUT[1]_G_Y_YC[7]/ VOUT[1], EMAC[1]_MTXD[0]/ VIN[1]A, GP3 VIN[1]A_D[12]/ PINCNTL219 GP3[11] DSIS: N/A

VOUT[1]_R_CR[9]/ VOUT[1], EMAC[1]_MTXEN/ VIN[1]A, VIN[1]A_D[20]/ Y24 O UART5, GP3 [G]MII Transmit Data Enable output UART5_TXD/ PINCNTL227 GP3[19] DSIS: N/A

TBD These pin functions are available only when RMII mode is selected.

EMAC_RMREFCLK/ TIMER2, GP1 TIM2_IO/ J27 I/O PINCNTL232 GP1[10] DSIS: PIN

VIN[0]A_D[20]/ CAM_D[12]/ EMAC[1]_RMCRSDV/ AC17 I SPI[3]_SCS[0]/ GP0[14]

EMAC[0]_MTXD[5]/ EMAC[1]_RGTXC/ EMAC[1]_RMCRSDV/ F27 I GPMC_A[12]/ UART1_RXD

AD26

AE26

AF26

TYPE

O

(1)

DVDD_GPMC mode)

DVDD_GPMC PINCNTL255

(2) (3)

OTHER

IPD operation, EMAC[0]_TXD[7:0] are used. For 10/100

DVDD EMAC MII operation, only EMAC[0]_TXD[3:0] are

IPD

DVDD

EMAC[1] RMII Mode

IPD RMII Reference Clock (EMAC[0] and EMAC[1] RMII

IPD SPI[3], GP0

DVDD_C PINCNTL160

IPD GPMC, UART1

MUXED DESCRIPTION

VIN[0]A,

CAMERA_I/F,

DSIS: 0

MM: MUX1

EMAC[0], EMAC[1],

DSIS: 0

MM: MUX0

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[G]MII Transmit Data [7:0]. For 1000 EMAC GMII

used.

RMII Carrier Sense input

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Table 3-8. EMAC[1] Terminal Functions [(R)(G)MII] (continued)

SIGNAL

NAME NO.

VIN[0]A_D[18]/ CAM_D[10]/ EMAC[1]_RMRXD[1]/ AF20 I I2C[3]_SCL/ GP0[12]

EMAC[0]_MTXD[3]/ EMAC[1]_RGTXD[0]/ EMAC[1]_RMRXD[1]/ H23 I GPMC_A[10]/ UART4_CTS

VIN[0]A_D[19]/ CAM_D[11]/ EMAC[1]_RMRXD[0]/ AF21 I I2C[3]_SDA/ GP0[13]

EMAC[0]_MTXD[2]/ EMAC[1]_RGTXCTL/ EMAC[1]_RMRXD[0]/ H22 I GPMC_A[9]/ UART4_TXD

VIN[0]A_D[17]/ CAMERA_I/F, CAM_D[9]/ IPD SPI[3], GP0 EMAC[1]_RMRXER/ DVDD_C PINCNTL157 GP0[11] DSIS: 0

EMAC[0]_MTXD[4]/ EMAC[1]_RGTXD[2]/ EMAC[1]_RMRXER/ G23 I GPMC_A[11]/ UART4_RTS

VIN[0]A_D[22]/ CAM_D[14]/ EMAC[1]_RMTXD[1]/ AC21 O SPI[3]_D[1]/ GP0[16]

EMAC[0]_MTXD[7]/ EMAC[0], EMAC[1]_RGTXD[3]/ GPMC, UART1 EMAC[1]_RMTXD[1]/ H24 O PINCNTL257 GPMC_A[14]/ DSIS: N/A UART1_CTS MM: MUX0

VIN[0]A_D[21]/ CAM_D[13]/ EMAC[1]_RMTXD[0]/ AE18 O SPI[3]_SCLK/ GP0[15]

EMAC[0]_MTXD[6]/ EMAC[1]_RGRXD[0]/ EMAC[1]_RMTXD[0]/ J22 O GPMC_A[13]/ UART1_TXD

AB21 I

TYPE

(1)

DVDD_GPMC PINCNTL253

DVDD_GPMC PINCNTL252

DVDD_GPMC PINCNTL254

DVDD_GPMC

DVDD_GPMC PINCNTL256

(2) (3)

OTHER

IPU I2C[3], GP0

DVDD_C PINCNTL158

IPD GPMC, UART4

IPU I2C[3], GP0

DVDD_C PINCNTL159

IPD GPMC, UART4

IPD GPMC, UART1

IPD SPI[3], GP0

DVDD_C PINCNTL162

IPD

IPD SPI[3], GP0

DVDD_C PINCNTL161

IPD GPMC, UART1

CAMERA_I/F,

MUXED DESCRIPTION

VIN[0]A,

DSIS: PIN

MM: MUX1

EMAC[0], EMAC[1],

DSIS: PIN

MM: MUX0

VIN[0]A,

DSIS: PIN

MM: MUX1

EMAC[0], EMAC[1],

DSIS: PIN

MM: MUX0

VIN[0]A,

MM: MUX1

EMAC[0], EMAC[1],

DSIS: 0

MM: MUX0

VIN[0]A,

DSIS: N/A

MM: MUX1

VIN[0]A

DSIS: N/A

MM: MUX1

EMAC[0], EMAC[1],

DSIS: N/A

MM: MUX0

RMII Receive Data [1:0].

RMII Receive Data Error input

RMII Transmit Data [1:0].

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Table 3-8. EMAC[1] Terminal Functions [(R)(G)MII] (continued)

SIGNAL

NAME NO.

VIN[0]A_D[23]/ CAM_D[15]/ EMAC[1]_RMTXEN/ AC16 O SPI[3]_D[0]/ GP0[17]

EMAC[0]_MTXEN/ EMAC[1]_RGRXD[2]/ EMAC[1]_RMTXEN/ J23 O GPMC_A[15]/ UART1_RTS

TBD These pin functions are available only when RGMII mode is selected.

EMAC[0]_GMTCLK/ EMAC[0], EMAC[1]_RGRXC/ IPD GPMC, SPI[2] GPMC_A[6]/ DVDD_GPMC PINCNTL249 SPI[2]_D[1] DSIS: PIN

EMAC[0]_MRXD[3]/ EMAC[1]_RGRXCTL/ EMAC[0], GPMC_A[27]/ IPD GPMC, UART5 GPMC_A[26]/ DVDD_GPMC PINCNTL243 GPMC_A[0]/ DSIS: PIN UART5_RXD

EMAC[0]_MTXD[0]/ EMAC[0], EMAC[1]_RGRXD[3]/ IPD GPMC, UART4 GPMC_A[7]/ DVDD_GPMC PINCNTL250 SPI[2]_D[0] DSIS: PIN

EMAC[0]_MTXEN/ EMAC[1]_RGRXD[2]/ EMAC[1]_RMTXEN/ J23 I GPMC_A[15]/ UART1_RTS

EMAC[0]_MRXDV/ EMAC[0], EMAC[1]_RGRXD[1]/ IPD GPMC, SPI[2] GPMC_A[5]/ DVDD_GPMC PINCNTL248 SPI[2]_SCLK DSIS: PIN

EMAC[0]_MTXD[6]/ EMAC[1]_RGRXD[0]/ EMAC[1]_RMTXD[0]/ J22 I GPMC_A[13]/ UART1_TXD

EMAC[0]_MTXD[5]/ EMAC[1]_RGTXC/ EMAC[1]_RMCRSDV/ F27 O RGMII Transmit Clock GPMC_A[12]/ UART1_RXD

EMAC[0]_MTXD[2]/ EMAC[1]_RGTXCTL/ EMAC[1]_RMRXD[0]/ H22 O RGMII Transmit Enable GPMC_A[9]/ UART4_TXD

(1)

TYPE

DVDD_GPMC PINCNTL258

K23 I RGMII Receive Clock

J25 I RGMII Receive Control

J24 I

DVDD_GPMC PINCNTL258

K22 I

DVDD_GPMC PINCNTL256

DVDD_GPMC PINCNTL255

DVDD_GPMC PINCNTL252

(2) (3)

OTHER

IPD SPI[3], GP0

DVDD_C PINCNTL163

IPD GPMC, UART1

EMAC[1] RGMII MODE

IPD GPMC, UART4

IPD GPMC, UART1

IPD GPMC, UART4

MUXED DESCRIPTION

VIN[0]A,

CAMERA_I/F,

DSIS: N/A

MM: MUX1

EMAC[0], EMAC[1],

DSIS: N/A

MM: MUX0

EMAC[0],

DSIS: PIN

EMAC[0],

DSIS: PIN

EMAC[0],

DSIS: N/A

EMAC[0],

DSIS: N/A

RMII Transmit Data Enable output

RGMII Receive Data [3:0]

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Table 3-8. EMAC[1] Terminal Functions [(R)(G)MII] (continued)

SIGNAL

NAME NO.

EMAC[0]_MTXD[7]/ EMAC[1]_RGTXD[3]/ EMAC[1]_RMTXD[1]/ H24 O GPMC_A[14]/ UART1_CTS

EMAC[0]_MTXD[4]/ EMAC[1]_RGTXD[2]/ EMAC[1]_RMRXER/ G23 O GPMC_A[11]/ UART4_RTS

EMAC[0]_MTXD[1]/ EMAC[0], EMAC[1]_RGTXD[1]/ IPD GPMC, UART4 GPMC_A[8]/ DVDD_GPMC PINCNTL251 UART4_RXD DSIS: N/A

EMAC[0]_MTXD[3]/ EMAC[0], EMAC[1]_RGTXD[0]/ EMAC[1], EMAC[1]_RMRXD[1]/ H23 O GPMC, UART4 GPMC_A[10]/ PINCNTL253 UART4_CTS DSIS: N/A

H25 O

TYPE

(1)

DVDD_GPMC PINCNTL257

DVDD_GPMC PINCNTL254

DVDD_GPMC

(2) (3)

OTHER

IPD GPMC, UART1

IPD GPMC, UART4

IPD

MUXED DESCRIPTION

EMAC[0],

DSIS: N/A

EMAC[0],

DSIS: N/A

RGMII Transmit Data [3:0]

Table 3-9. MDIO Terminal Functions

SIGNAL

NAME NO.

MDCLK/ IPU

GP1[11] DVDD_GPMC

MDIO/ IPU GP1[12] DVDD_GPMC

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.

(3) Specifies the operating I/O supply voltage for each signal

H28 O PINCNTL233 Management Data Serial Clock output

P24 I/O PINCNTL234 Management Data I/O

TYPE

(1)

OTHER

(2) (3)

MUXED DESCRIPTION

MDIO

GP1

DSIS: N/A

GP1

DSIS: 1

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3.2.7 General-Purpose Input/Outputs (GPIOs)

SIGNAL

NAME NO.

Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.

UART2_TXD/ IPD GP0[31] DVDD

TCLKIN/ IPD GP0[30] DVDD

UART2_RXD/ IPD GP0[29] DVDD

MCA[5]_AXR[1]/ MCA[4]_AXR[3]/ IPD TIM7_IO/ DVDD

GP0[28]

VOUT[1]_FLD/ VOUT[1], CAM_FLD/ CAMERA_I/F, CAM_WE/ IPD GPMC, UART2 GPMC_A[11]/ DVDD_C PINCNTL174 UART2_CTS/ DSIS: PIN GP0[28] MM: MUX0

MCA[5]_AXR[0]/ MCA[4]_AXR[2]/ L7 I/O

GP0[27]

VOUT[1]_B_CB_C[0]/ CAM_VS/ GPMC_A[10]/ AD23 I/O UART2_TXD/

GP0[27]

MCA[5]_AFSX/ IPD PINCNTL56 GP0[26] DVDD DSIS: PIN

VOUT[1]_B_CB_C[1]/ CAM_HS/ GPMC_A[9]/ AE23 I/O UART2_RXD/

GP0[26]

MCA[5]_ACLKX/ IPD PINCNTL55 GP0[25] DVDD DSIS: PIN

VOUT[1]_R_CR[0]/ CAM_D[0]/ GPMC_A[8]/ AA22 I/O UART4_RTS/

GP0[25]

U3 I/O PINCNTL61 General-Purpose Input/Output (I/O) 0 [GP0] pin 31.

T2 I/O PINCNTL60 General-Purpose Input/Output (I/O) 0 [GP0] pin 30.

U4 I/O PINCNTL59 General-Purpose Input/Output (I/O) 0 [GP0] pin 29.

L6 I/O PINCNTL58

AB23 I/O

H5 I/O

J3 I/O

TYPE

Table 3-10. GP0 Terminal Functions

(1)

(2) (3)

OTHER

IPD PINCNTL57

DVDD DSIS: PIN

IPU GPMC, UART2

DVDD_C PINCNTL173

IPD GPMC, UART2

DVDD_C PINCNTL172

IPD GPMC, UART4

DVDD_C PINCNTL171

MUXED DESCRIPTION

GPIO0

UART2

DSIS: PIN

TCLKIN

DSIS: PIN

UART2

DSIS: PIN

MCA[5], MCA[4],

TIMER7

DSIS: PIN

MM: MUX1

MCA[5], MCA[4]

MM: MUX1

VOUT[1],

CAMERA_I/F,

DSIS: PIN

MM: MUX0

MCA[5]

MM: MUX1

VOUT[1],

CAMERA_I/F,

DSIS: PIN

MM: MUX0

MCA[5]

MM: MUX1

VOUT[1],

CAMERA_I/F,

DSIS: PIN

MM: MUX0

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General-Purpose Input/Output (I/O) 0 [GP0] pin 28.

General-Purpose Input/Output (I/O) 0 [GP0] pin 27.

General-Purpose Input/Output (I/O) 0 [GP0] pin 26.

General-Purpose Input/Output (I/O) 0 [GP0] pin 25.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.

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SIGNAL

NAME NO.

MCA[4]_AXR[1]/ TIM6_IO/ J4 I/O

GP0[24]

VOUT[1]_R_CR[1]/ CAM_D[1]/ GPMC_A[7]/ AC19 I/O UART4_CTS/

GP0[24]

MCA[4]_AXR[0]/ IPD PINCNTL53 GP0[23] DVDD DSIS: PIN

VOUT[1]_G_Y_YC[0]/ CAM_D[2]/ GPMC_A[6]/ AC18 I/O UART4_TXD/

GP0[23]

MCA[4]_AFSX/ IPD PINCNTL52 GP0[22] DVDD DSIS: PIN

VOUT[1]_G_Y_YC[1]/ CAM_D[3]/ GPMC_A[5]/ AD18 I/O UART4_RXD/

GP0[22]

MCA[4]_ACLKX/ IPD PINCNTL51 GP0[21] DVDD DSIS: PIN

VIN[0]B_FLD/ CAMERA_I/F CAM_D[4]/ AD17 I/O PINCNTL167 GP0[21] DSIS: PIN

MCA[3]_AXR[2]/ MCA[1]_AXR[8]/ F2 I/O

GP0[20]

VIN[0]A_FLD/ CAMERA_I/F CAM_D[5]/ AC22 I/O PINCNTL166 GP0[20] DSIS: PIN

MCA[3]_AXR[1]/ TIM5_IO/ G2 I/O

GP0[19]

VIN[0]B_DE/ CAMERA_I/F CAM_D[6]/ AC15 I/O PINCNTL165

GP0[19] DSIS: PIN

TYPE

H6 I/O

H3 I/O

K7 I/O

Table 3-10. GP0 Terminal Functions (continued)

(1)

(2) (3)

OTHER

IPD PINCNTL54

DVDD DSIS: PIN

IPD GPMC, UART4

DVDD_C PINCNTL170

IPD GPMC, UART4

DVDD_C PINCNTL169

IPU GPMC, UART4

DVDD_C PINCNTL168

IPU

DVDD_C

IPD PINCNTL49

DVDD DSIS: PIN

IPU

DVDD_C

IPD PINCNTL48

DVDD DSIS: PIN

IPU

DVDD_C

MUXED DESCRIPTION

MCA[4], TIMER6

MM: MUX1

VOUT[1],

CAMERA_I/F,

DSIS: PIN

MM: MUX0

MCA[4]

MM: MUX1

VOUT[1],

CAMERA_I/F,

DSIS: PIN

MM: MUX0

MCA[4]

MM: MUX1

VOUT[1],

CAMERA_I/F,

DSIS: PIN

MM: MUX0

MCA[4]

MM: MUX1

VIN[0]B,

MM: MUX0

MCA[3], MCA[1]

MM: MUX1

VIN[0]A,

MM: MUX0

MCA[3], TIMER5

MM: MUX1

VIN[0]B,

MM: MUX0

General-Purpose Input/Output (I/O) 0 [GP0] pin 24.

General-Purpose Input/Output (I/O) 0 [GP0] pin 23.

General-Purpose Input/Output (I/O) 0 [GP0] pin 22.

General-Purpose Input/Output (I/O) 0 [GP0] pin 21.

General-Purpose Input/Output (I/O) 0 [GP0] pin 20.

General-Purpose Input/Output (I/O) 0 [GP0] pin 19.

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SIGNAL

NAME NO.

MCA[3]_AXR[0]/ TIM4_IO/ G1 I/O

GP0[18]

VIN[0]A_DE/ CAMERA_I/F CAM_D[7]/ AB17 I/O PINCNTL164 GP0[18] DSIS: PIN

MCA[3]_AFSX/ IPD PINCNTL46 GP0[17] DVDD DSIS: PIN

VIN[0]A_D[23]/ CAMERA_I/F, CAM_D[15]/ EMAC[1]_RM, EMAC[1]_RMTXEN/ AC16 I/O SPI[3] SPI[3]_D[0]/ PINCNTL163 GP0[17] DSIS: PIN

MCA[3]_ACLKX/ IPD PINCNTL45 GP0[16] DVDD DSIS: PIN

VIN[0]A_D[22]/ CAMERA_I/F, CAM_D[14]/ EMAC[1]_RM, EMAC[1]_RMTXD[1]/ AC21 I/O SPI[3] SPI[3]_D[1]/ PINCNTL162 GP0[16] DSIS: PIN

MCA[2]_AXR[3]/ MCA[1]_AXR[7]/ IPD TIM3_IO/ DVDD

GP0[15]

VIN[0]A_D[21]/ CAMERA_I/F, CAM_D[13]/ EMAC[1]_RM, EMAC[1]_RMTXD[0]/ AE18 I/O SPI[3] SPI[3]_SCLK/ PINCNTL161 GP0[15] DSIS: PIN

MCA[2]_AXR[2]/ MCA[1]_AXR[6]/ IPD TIM2_IO/ DVDD

GP0[14]

VIN[0]A_D[20]/ CAMERA_I/F, CAM_D[12]/ EMAC[1]_RM, EMAC[1]_RMCRSDV/ AC17 I/O SPI[3] SPI[3]_SCS[0]/ PINCNTL160 GP0[14] DSIS: PIN

H4 I/O

G6 I/O

H2 I/O PINCNTL44

V5 I/O PINCNTL43

Table 3-10. GP0 Terminal Functions (continued)

TYPE

(1)

(2) (3)

OTHER

IPD PINCNTL47

DVDD DSIS: PIN

IPU

DVDD_C

IPD

DVDD_C

IPD

DVDD_C

IPD

DVDD_C

IPD

DVDD_C

MUXED DESCRIPTION

MCA[3], TIMER4

MM: MUX1

VIN[0]A,

MM: MUX0

MM: MUX1

VIN[0]A,

MM: MUX0

MM: MUX1

VIN[0]A,

MM: MUX0

MCA[2], MCA[1],

TIMER3

DSIS: PIN

MM: MUX1

VIN[0]A,

MM: MUX0

MCA[2], MCA[1],

TIMER2

DSIS: PIN

MM: MUX1

VIN[0]A,

MM: MUX0

General-Purpose Input/Output (I/O) 0 [GP0] pin 18.

MCA[3]

General-Purpose Input/Output (I/O) 0 [GP0] pin 17.

MCA[3]

General-Purpose Input/Output (I/O) 0 [GP0] pin 16.

General-Purpose Input/Output (I/O) 0 [GP0] pin 15.

General-Purpose Input/Output (I/O) 0 [GP0] pin 14.

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SIGNAL

NAME NO.

MCA[2]_AXR[1]/ SD0_DAT[7]/ IPU UART5_TXD/ DVDD

GP0[13]

VIN[0]A_D[19]/ CAMERA_I/F, CAM_D[11]/ EMAC[1]_RM, EMAC[1]_RMRXD[0]/ AF21 I/O I2C[3] I2C[3]_SDA/ PINCNTL159 GP0[13] DSIS: PIN

MCA[2]_AXR[0]/ SD0_DAT[6]/ IPU UART5_RXD/ DVDD

GP0[12]

VIN[0]A_D[18]/ CAMERA_I/F, CAM_D[10]/ EMAC[1]_RM, EMAC[1]_RMRXD[1]/ AF20 I/O I2C[3] I2C[3]_SCL/ PINCNTL158 GP0[12] DSIS: PIN

MCA[2]_AFSX/ IPU PINCNTL40 GP0[11] DVDD DSIS: PIN

VIN[0]A_D[17]/ CAMERA_I/F, CAM_D[9]/ IPD EMAC[1]_RM EMAC[1]_RMRXER/ DVDD_C PINCNTL157 GP0[11] DSIS: PIN

MCA[2]_ACLKX/ IPU PINCNTL39 GP0[10] DVDD DSIS: PIN

VIN[0]A_D[16]/ CAMERA_I/F, CAM_D[8]/ IPU I2C[2] I2C[2]_SCL/ DVDD_C PINCNTL156 GP0[10] DSIS: PIN

AUD_CLKIN2/ MCA[0]_AXR[9]/ MCA[2]_AHCLKX/ MCA[5]_AHCLKX/ H1 I/O General-Purpose Input/Output (I/O) 0 [GP0] pin 9. EDMA_EVT2/ TIM3_IO/

GP0[9]

AUD_CLKIN1/ MCA[0]_AXR[8]/ MCA[1]_AHCLKX/ MCA[4]_AHCLKX/ R5 I/O General-Purpose Input/Output (I/O) 0 [GP0] pin 8. EDMA_EVT3/ TIM2_IO/

GP0[8]

USB0_DRVVBUS/ IPD GP0[7] DVDD

AA5 I/O

AB21 I/O

AA21 I/O

AF11 I/O PINCNTL270 General-Purpose Input/Output (I/O) 0 [GP0] pin 7.

TYPE

V6 I/O PINCNTL42

N2 I/O PINCNTL41

U6 I/O

Table 3-10. GP0 Terminal Functions (continued)

(1)

(2) (3)

OTHER

IPU

DVDD_C

IPU

DVDD_C

IPD MCA[5], EDMA,

DVDD TIMER3

IPD MCA[4], EDMA,

DVDD TIMER2

MUXED DESCRIPTION

MCA[2], SD0,

DSIS: PIN

MM: MUX1

VIN[0]A,

MM: MUX0

MCA[2], SD0,

DSIS: PIN

MM: MUX1

VIN[0]A,

MM: MUX0

MCA[2]

MM: MUX1

VIN[0]A,

MM: MUX0

MCA[2]

MM: MUX1

VIN[0]A,

MM: MUX0

AUD_CLKIN2,

MCA[0], MCA[2],

PINCNTL16

DSIS: PIN

AUD_CLKIN1,

MCA[0], MCA[1],

PINCNTL15

DSIS: PIN

UART5

General-Purpose Input/Output (I/O) 0 [GP0] pin 13.

UART5

General-Purpose Input/Output (I/O) 0 [GP0] pin 12.

General-Purpose Input/Output (I/O) 0 [GP0] pin 11.

General-Purpose Input/Output (I/O) 0 [GP0] pin 10.

USB0

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Table 3-10. GP0 Terminal Functions (continued)

SIGNAL

NAME NO.

SD0_DAT[3]/ SD0, SD1 SD1_DAT[7]/ Y4 I/O PINCNTL13 General-Purpose Input/Output (I/O) 0 [GP0] pin 6. GP0[6] DSIS: PIN

SD0_DAT[2]_SDRW/ SD0, SD1 SD1_DAT[6]/ Y3 I/O PINCNTL12 General-Purpose Input/Output (I/O) 0 [GP0] pin 5. GP0[5] DSIS: PIN

SD0_DAT[1]_SDIRQ/ SD0, SD1 SD1_DAT[5]/ Y5 I/O PINCNTL11 General-Purpose Input/Output (I/O) 0 [GP0] pin 4. GP0[4] DSIS: PIN

SD0_DAT[0]/ SD0, SD1 SD1_DAT[4]/ R7 I/O PINCNTL10 General-Purpose Input/Output (I/O) 0 [GP0] pin 3. GP0[3] DSIS: PIN

SD0_CMD/ SD0, SD1 SD1_CMD/ N1 I/O PINCNTL9 General-Purpose Input/Output (I/O) 0 [GP0] pin 2. GP0[2] DSIS: PIN

SD0_CLK/ IPU GP0[1] DVDD_SD

SD1_CMD/ IPU GP0[0] DVDD_SD

Y6 I/O PINCNTL8 General-Purpose Input/Output (I/O) 0 [GP0] pin 1.

P2 I/O PINCNTL2 General-Purpose Input/Output (I/O) 0 [GP0] pin 0.

TYPE

(1)

OTHER

IPU

DVDD_SD

IPU

DVDD_SD

IPU

DVDD_SD

IPU

DVDD_SD

IPU

DVDD_SD

(2) (3)

MUXED DESCRIPTION

SD0

DSIS: PIN

SD1

DSIS: PIN

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SIGNAL

NAME NO.

Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.

GPMC_WAIT[0]/ GPMC_A[26]/ EDMA_EVT0/

GP1[31]

GPMC_BE[1]/ GPMC_A[24]/ IPD EDMA_EVT1/ V28 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 30. TIM7_IO/ MC

GP1[30]

GPMC_BE[0]_CLE/ GPMC_A[25]/ IPD EDMA_EVT2/ U27 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 29. TIM6_IO/ MC

GP1[29]

GPMC_ADV_ALE/ GPMC_CS[6]/ TIM5_IO/

GP1[28]

GPMC_CLK/ GPMC_CS[5]/ GPMC_WAIT[1]/ IPU CLKOUT1/ R26 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 27. EDMA_EVT3/ MC TIM4_IO/

GP1[27]

SPI[1]_D[0]/ IPU PINCNTL88 GP1[26] DVDD DSIS: PIN

GPMC_CS[3]/ VIN[1]B_CLK/ SPI[2]_SCS[0]/

GP1[26]

GPMC_CS[2]/ IPU GPMC GPMC_A[24]/ M25 I/O DVDD_GP PINCNTL124 General-Purpose Input/Output (I/O) 1 [GP1] pin 25. GP1[25] MC DSIS: PIN

GPMC_CS[1]/ IPU GPMC GPMC_A[25]/ K28 I/O DVDD_GP PINCNTL123 General-Purpose Input/Output (I/O) 1 [GP1] pin 24. GP1[24] MC DSIS: PIN

GPMC_CS[0]/

GP1[23]

SD2_DAT[4]/ GPMC_A[27]/ GPMC_A[23]/ IPU GPMC_CS[7]/ R24 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 22. EDMA_EVT0/ MC TIM7_IO/

GP1[22]

W28 I/O DVDD_GP PINCNTL133 General-Purpose Input/Output (I/O) 1 [GP1] pin 31.

M26 I/O DVDD_GP PINCNTL128 General-Purpose Input/Output (I/O) 1 [GP1] pin 28.

AA6 I/O

TYPE

P26 I/O DVDD_GP PINCNTL125

T28 I/O DVDD_GP PINCNTL122 General-Purpose Input/Output (I/O) 1 [GP1] pin 23.

Table 3-11. GP1 Terminal Functions

(2)

OTHER

(1)

(3)

IPU GPMC, EDMA MC DSIS: PIN

IPU GPMC, TIMER5 MC DSIS: PIN

IPU SPI[2] MC DSIS: PIN

IPU GPMC MC DSIS: PIN

MUXED DESCRIPTION

GPIO1

GPMC, EDMA,

TIMER7

PINCNTL132

DSIS: PIN

GPMC, EDMA,

TIMER6

PINCNTL131

DSIS: PIN

GPMC, CLKOUT1,

EDMA, TIMER4

PINCNTL127

DSIS: PIN

SPI[1]

MM: MUX1

GPMC, VIN[1]B,

MM: MUX0

SD2, GPMC,

EDMA, TIMER7

PINCNTL116

DSIS: PIN

ZHCS057–MARCH 2011

General-Purpose Input/Output (I/O) 1 [GP1] pin 26.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.

(3) Specifies the operating I/O supply voltage for each signal

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ZHCS057–MARCH 2011

SIGNAL

NAME NO.

SD2_DAT[5]/ GPMC_A[26]/ IPU GPMC_A[22]/ P22 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 21. TIM6_IO/ MC

GP1[21]

SD2_DAT[6]/ GPMC_A[25]/ IPU GPMC_A[21]/ N23 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 20. UART2_TXD/ MC

GP1[20]

SD2_DAT[7]/ GPMC_A[24]/ IPU GPMC_A[20]/ L25 I/O DVDD_GP General-Purpose Input/Output (I/O) 1 [GP1] pin 19. UART2_RXD/ MC

GP1[19]

SPI[1]_D[1]/ IPU PINCNTL87 GP1[18] DVDD DSIS: PIN

GPMC_A[23]/ GPMC, SPI[2], SPI[2]_SCLK/ IPD HDMI, TIMER5 HDMI_HPDET/ AA26 I/O DVDD_GP PINCNTL112 TIM5_IO/ MC DSIS: PIN GP1[18] MM: MUX0

SPI[1]_SCLK/ IPU PINCNTL86 GP1[17] DVDD DSIS: PIN

GPMC_A[22]/ GPMC, SPI[2], SPI[2]_D[1]/ IPU HDMI, TIMER4 HDMI_CEC/ AB27 I/O DVDD_GP PINCNTL111 TIM4_IO/ MC DSIS: PIN GP1[17] MM: MUX0

SPI[1]_SCS[0]/ IPU PINCNTL85 GP1[16] DVDD DSIS: PIN

GPMC_A[21]/ IPD SPI[2]_D[0]/ AC28 I/O DVDD_GP GP1[16] MC

SD2_SCLK/ PINCNTL121 GP1[15] DSIS: PIN

GPMC_A[20]/ IPU SPI[2]_SCS[1]/ AD28 I/O DVDD_GP GP1[15] MC

SD2_DAT[0]/ IPU GPMC_A[4]/ L26 I/O DVDD_GP GP1[14] MC

GPMC_A[19]/ IPD TIM3_IO/ AC27 I/O DVDD_GP GP1[14] MC

AA3 I/O

AC3 I/O

AD3 I/O

M23 I/O DVDD_GP

Table 3-11. GP1 Terminal Functions (continued)

(2)

OTHER

(1)

TYPE

(3)

IPU MC

MUXED DESCRIPTION

SD2, GPMC,

TIMER6

PINCNTL115

DSIS: PIN

SD2, GPMC,

UART2

PINCNTL114

DSIS: PIN

SD2, GPMC,

UART2

PINCNTL113

DSIS: PIN

SPI[1]

MM: MUX1

General-Purpose Input/Output (I/O) 1 [GP1] pin 18.

SPI[1]

MM: MUX1

General-Purpose Input/Output (I/O) 1 [GP1] pin 17.

SPI[1]

MM: MUX1

GPMC, SPI[2]

PINCNTL110

DSIS: PIN

MM: MUX0

SD2

MM: MUX1

GPMC, SPI[2]

PINCNTL109

DSIS: PIN

MM: MUX0

SD2, GPMC

PINCNTL120

DSIS: PIN

MM: MUX1

GPMC, TIMER3

PINCNTL108

DSIS: PIN

MM: MUX0

General-Purpose Input/Output (I/O) 1 [GP1] pin 16.

General-Purpose Input/Output (I/O) 1 [GP1] pin 15.

General-Purpose Input/Output (I/O) 1 [GP1] pin 14.

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SIGNAL

NAME NO.

SD2_DAT[1]_SDIRQ SD2, GPMC / PINCNTL119 GPMC_A[3]/ DSIS: PIN GP1[13] MM: MUX1

GPMC_A[18]/ IPD TIM2_IO/ AE28 I/O DVDD_GP GP1[13] MC

VIN[0]A_D[1]/ IPD PINCNTL141 GP1[12] DVDD DSIS: PIN

MDIO/ PINCNTL234 GP1[12] DSIS: PIN

VIN[0]A_D[0]/ IPD PINCNTL140 GP1[11] DVDD DSIS: PIN

MDCLK/ PINCNTL233

GP1[11] DSIS: PIN

GP1[10] V2 I/O DSIS: PIN

EMAC_RMREFCLK/ IPD TIM2_IO/ J27 I/O DVDD_GP

GP1[10] MC

GP1[9] V1 I/O DSIS: PIN

VIN[0]B_CLK/ CLKOUT0/ AE17 I/O

GP1[9]

GP1[8] W2 I/O DSIS: PIN

GPMC_CS[4]/ IPU SD2_CMD/ P25 I/O DVDD_GP

GP1[8] MC

GP1[7] W1 I/O DSIS: PIN

DEVOSC_WAKE/ SPI[1]_SCS[1]/ IPU TIM5_IO/ DVDD_SD

GP1[7]

SPI[0]_SCS[1]/ SD1_SDCD/ SPI[0], SD1, SATA, SATA_ACT0_LED/ IPU EDMA, TIMER4 EDMA_EVT1/ DVDD PINCNTL80 TIM4_IO/ DSIS: PIN

GP1[6]

M24 I/O DVDD_GP

AB11 I/O

AF9 I/O

H28 I/O DVDD_GP

AE5 I/O General-Purpose Input/Output (I/O) 1 [GP1] pin 6.

TYPE

P24 I/O DVDD_GP

W6 I/O PINCNTL7

Table 3-11. GP1 Terminal Functions (continued)

(2)

OTHER

(1)

(3)

IPU MC

IPU

DVDD_M

IPD

DVDD_M

IPD PINCNTL134

DVDD DSIS: PIN

IPU

DVDD_M

IPD

DVDD_M

MUXED DESCRIPTION

GPMC, TIMER2

PINCNTL107

DSIS: PIN

MM: MUX0

VIN[0]A

MM: MUX1

MDIO

MM: MUX0

VIN[0]A

MM: MUX1

MDIO

MM: MUX0

PINCNTL65

MM: MUX1

EMAC, TIMER2

PINCNTL232

DSIS: PIN

MM: MUX0

PINCNTL64

MM: MUX1

VIN[0]B, CLKOUT0

MM: MUX0

PINCNTL63

MM: MUX1

GPMC, SD2

PINCNTL126

DSIS: PIN

MM: MUX0

PINCNTL62

MM: MUX1

DEVOSC, SPI[1],

TIMER5

DSIS: PIN

MM: MUX0

General-Purpose Input/Output (I/O) 1 [GP1] pin 13.

General-Purpose Input/Output (I/O) 1 [GP1] pin 12.

General-Purpose Input/Output (I/O) 1 [GP1] pin 11.

General-Purpose Input/Output (I/O) 1 [GP1] pin 10.

General-Purpose Input/Output (I/O) 1 [GP1] pin 9.

General-Purpose Input/Output (I/O) 1 [GP1] pin 8.

General-Purpose Input/Output (I/O) 1 [GP1] pin 7.

ZHCS057–MARCH 2011

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ZHCS057–MARCH 2011

SIGNAL

NAME NO.

UART0_RIN/ UART0, UART3, UART3_RTS/ IPU UART1 UART1_RXD/ DVDD PINCNTL77 GP1[5] DSIS: PIN

UART0_DTR/ UART0, UART3, UART3_CTS/ IPU UART1 UART1_TXD/ DVDD PINCNTL76 GP1[4] DSIS: PIN

UART0_DSR/ UART3_TXD/ UART0, UART3, SPI[0]_SCS[2]/ IPU SPI[0], I2C[2], SD1 I2C[2]_SDA/ DVDD PINCNTL75 SD1_SDWP/ DSIS: PIN

GP1[3]

UART0_DCD/ UART3_RXD/ UART0, UART3, SPI[0]_SCS[3]/ IPU SPI[0], I2C[2], SD1 I2C[2]_SCL/ DVDD PINCNTL74 SD1_POW/ DSIS: PIN

GP1[2]

DCAN0_RX/ DCAN0, UART2, UART2_RXD/ IPU I2C[3] I2C[3]_SCL/ DVDD PINCNTL69 GP1[1] DSIS: PIN

DCAN0_TX/ DCAN0, UART2, UART2_TXD/ IPU I2C[3] I2C[3]_SDA/ DVDD PINCNTL68 GP1[0] DSIS: PIN

AF4 I/O General-Purpose Input/Output (I/O) 1 [GP1] pin 5.

AG2 I/O General-Purpose Input/Output (I/O) 1 [GP1] pin 4.

AG4 I/O General-Purpose Input/Output (I/O) 1 [GP1] pin 3.

AH4 I/O General-Purpose Input/Output (I/O) 1 [GP1] pin 2.

AG6 I/O General-Purpose Input/Output (I/O) 1 [GP1] pin 1.

AH6 I/O General-Purpose Input/Output (I/O) 1 [GP1] pin 0.

Table 3-11. GP1 Terminal Functions (continued)

(2)

OTHER

(1)

TYPE

(3)

MUXED DESCRIPTION

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SIGNAL

NAME NO.

Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.

VOUT[1]_AVID/ EMAC[1]_MRXER/ VIN[1]A_CLK/ IPD UART4_RTS/ DVDD TIM6_IO/

GP2[31]

VOUT[1]_VSYNC/ EMAC[1]_MCRS/ VOUT[1], EMAC[1], VIN[1]A_FLD/ VIN[1]A, SPI[3], VIN[1]A_DE/ AA23 I/O UART3 General-Purpose Input/Output (I/O) 2 [GP2] pin 30. SPI[3]_D[0]/ PINCNTL206 UART3_CTS/ DSIS: PIN

GP2[30]

VOUT[1]_HSYNC/ EMAC[1]_MCOL/ VIN[1]A_VSYNC/ IPD SPI[3]_D[1]/ DVDD UART3_RTS/

GP2[29]

VOUT[1]_CLK/ VOUT[1], EMAC[1], EMAC[1]_MTCLK/ IPD VIN[1]A VIN[1]A_HSYNC/ DVDD PINCNTL204 GP2[28] DSIS: PIN

VOUT[0]_R_CR[3]/ IPD GP2[27] DVDD

VOUT[0]_R_CR[2]/ VOUT[0], EMU EMU4/ AD9 I/O PINCNTL196 General-Purpose Input/Output (I/O) 2 [GP2] pin 26. GP2[26] DSIS: PIN

VOUT[0]_G_Y_YC[3]/ IPD GP2[25] DVDD

VOUT[0]_G_Y_YC[2]/ VOUT[0], EMU EMU3/ AH7 I/O PINCNTL188 General-Purpose Input/Output (I/O) 2 [GP2] pin 24. GP2[24] DSIS: PIN

VOUT[0]_B_CB_C[3]/ IPD GP2[23] DVDD

VOUT[0]_B_CB_C[2]/ VOUT[0], EMU EMU2/ AG7 I/O PINCNTL180 General-Purpose Input/Output (I/O) 2 [GP2] pin 22. GP2[22] DSIS: PIN

VOUT[0]_AVID/ VOUT[0]_FLD/ SPI[3]_SCLK/ AA10 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 21. TIM7_IO/

GP2[21]

VIN[0]A_D[15]_BD[7]/ CAM_SHUTTER/ AC14 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 20.

GP2[20]

Y22 I/O TIMER6 General-Purpose Input/Output (I/O) 2 [GP2] pin 31.

AC24 I/O UART3 General-Purpose Input/Output (I/O) 2 [GP2] pin 29.

AE24 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 28.

AB9 I/O PINCNTL197 General-Purpose Input/Output (I/O) 2 [GP2] pin 27.

AH15 I/O PINCNTL189 General-Purpose Input/Output (I/O) 2 [GP2] pin 25.

AE15 I/O PINCNTL181 General-Purpose Input/Output (I/O) 2 [GP2] pin 23.

Table 3-12. GP2 Terminal Functions

(2)

OTHER

(1)

TYPE

(3)

IPD

DVDD

IPD

DVDD

IPD

DVDD

IPD

DVDD

IPD TIMER7

DVDD PINCNTL179

DIS CAMERA_I/F

DVDD PINCNTL155

MUXED DESCRIPTION

GPIO2

VOUT[1], EMAC[1],

VIN[1]A, UART4,

PINCNTL207

DSIS: PIN

VOUT[1], EMAC[1],

VIN[1]A, SPI[3],

PINCNTL205

DSIS: PIN

VOUT[0]

DSIS: PIN

VOUT[0]

DSIS: PIN

VOUT[0]

DSIS: PIN

VOUT[0], SPI[3],

DSIS: PIN VIN[0]AB,

DSIS: PIN

ZHCS057–MARCH 2011

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.

(3) Specifies the operating I/O supply voltage for each signal

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ZHCS057–MARCH 2011

SIGNAL

NAME NO.

VIN[0]A_D[14]_BD[6]/ CAM_STROBE/ AC12 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 19.

GP2[19]

VIN[0]A_D[13]_BD[5]/ CAM_RESET/ AF17 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 18.

GP2[18]

VIN[0]A_D[12]_BD[4]/ CLKOUT1/ AG17 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 17.

GP2[17]

VIN[0]A_D[11]_BD[3]/ CAM_WE/ AH17 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 16.

GP2[16]

VIN[0]A_D[10]_BD[2]/ IPD GP2[15] DVDD

VIN[0]A_D[9]_BD[1]/ IPD GP2[14] DVDD

VIN[0]A_D[8]_BD[0]/ IPD GP2[13] DVDD

VIN[0]A_D[7]/ IPD GP2[12] DVDD

VIN[0]A_D[6]/ IPD GP2[11] DVDD

VIN[0]A_D[5]/ IPD GP2[10] DVDD

VIN[0]A_D[4]/ IPD GP2[9] DVDD

VIN[0]A_D[3]/ IPD GP2[8] DVDD

VIN[0]A_D[2]/ IPD GP2[7] DVDD

SD2_DAT[2]_SDRW/ IPU GPMC_A[2]/ K27 I/O DVDD_GP GP2[6] MC

GPMC_A[17]/ PINCNTL106 GP2[6] DSIS: PIN

SD2_DAT[3]/ IPU GPMC_A[1]/ J28 I/O DVDD_GP GP2[5] MC

GPMC_A[16]/ PINCNTL105 GP2[5] DSIS: PIN

AH9 I/O PINCNTL150 General-Purpose Input/Output (I/O) 2 [GP2] pin 15.

AG9 I/O PINCNTL149 General-Purpose Input/Output (I/O) 2 [GP2] pin 14.

AB15 I/O PINCNTL148 General-Purpose Input/Output (I/O) 2 [GP2] pin 13.

AA11 I/O PINCNTL147 General-Purpose Input/Output (I/O) 2 [GP2] pin 12.

AH16 I/O PINCNTL146 General-Purpose Input/Output (I/O) 2 [GP2] pin 11.

AG16 I/O PINCNTL145 General-Purpose Input/Output (I/O) 2 [GP2] pin 10.

AH8 I/O PINCNTL144 General-Purpose Input/Output (I/O) 2 [GP2] pin 9.

AE12 I/O PINCNTL143 General-Purpose Input/Output (I/O) 2 [GP2] pin 8.

AC9 I/O PINCNTL142 General-Purpose Input/Output (I/O) 2 [GP2] pin 7.

V23 I/O DVDD_GP

AD27 I/O DVDD_GP

Table 3-12. GP2 Terminal Functions (continued)

(2)

OTHER

(1)

TYPE

(3)

IPD CAMERA_I/F

DVDD PINCNTL154

IPD CAMERA_I/F

DVDD PINCNTL153

IPD CLKOUT1

DVDD PINCNTL152

IPD CAMERA_I/F

DVDD PINCNTL151

IPD MC

MUXED DESCRIPTION

VIN[0]AB,

DSIS: PIN VIN[0]AB,

DSIS: PIN

VIN[0]AB

DSIS: PIN

VIN[0]AB

DSIS: PIN

VIN[0]AB

DSIS: PIN

VIN[0]A

DSIS: PIN

VIN[0]A

DSIS: PIN

VIN[0]A

DSIS: PIN

VIN[0]A

DSIS: PIN

VIN[0]A

DSIS: PIN

VIN[0]A

DSIS: PIN

SD2, GPMC

PINCNTL118

DSIS: PIN

MM: MUX1

GPMC

MM: MUX0

SD2, GPMC

PINCNTL117

DSIS: PIN

MM: MUX1

GPMC

MM: MUX0

General-Purpose Input/Output (I/O) 2 [GP2] pin 6.

General-Purpose Input/Output (I/O) 2 [GP2] pin 5.

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ZHCS057–MARCH 2011

Table 3-12. GP2 Terminal Functions (continued)

SIGNAL

NAME NO.

VIN[0]A_VSYNC/ VIN[0]A, UART5 UART5_CTS/ AD20 I/O PINCNTL139 General-Purpose Input/Output (I/O) 2 [GP2] pin 4. GP2[4] DSIS: PIN

VIN[0]A_HSYNC/ VIN[0]A, UART5 UART5_RTS/ AC20 I/O PINCNTL138 General-Purpose Input/Output (I/O) 2 [GP2] pin 3. GP2[3] DSIS: PIN

VIN[0]A_CLK/ IPD PINCNTL137 GP2[2] DVDD DSIS: PIN

VOUT[0]_FLD/ CAM_PCLK/ GPMC_A[12]/ AF18 I/O UART2_RTS/

GP2[2]

VIN[0]A_FLD/ VIN[0]B_VSYNC/ UART5_RXD/ AA20 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 1. I2C[2]_SCL/

GP2[1]

VIN[0]A_DE/ VIN[0]B_HSYNC/ UART5_TXD/ AE21 I/O General-Purpose Input/Output (I/O) 2 [GP2] pin 0. I2C[2]_SDA/

GP2[0]

AB20 I/O

TYPE

(1)

(2)

OTHER

(3)

IPU

DVDD

IPU

DVDD

IPD GPMC, UART2

DVDD_C PINCNTL175

IPU UART5, I2C[2]

DVDD PINCNTL136

IPU UART5, I2C[2]

DVDD PINCNTL135

MUXED DESCRIPTION

VIN[0]A

MM: MUX1

VOUT[0],

CAMERA_I/F,

DSIS: PIN

MM: MUX0

VIN[0]A, VIN[0]B,

DSIS: PIN

VIN[0]A, VIN[0]B,

DSIS: PIN

General-Purpose Input/Output (I/O) 2 [GP2] pin 2.

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ZHCS057–MARCH 2011

SIGNAL

NAME NO.

Note: General-Purpose Input/Output (I/O) pins can also serve as external interrupt inputs.

CLKIN32/ CLKOUT0/ IPD TIM3_IO/ DVDD

GP3[31]

VOUT[1]_B_CB_C[2]/ VOUT[1], GPMC, GPMC_A[0]/ VIN[1]A, HDMI, VIN[1]A_D[7]/ IPU SPI[2] HDMI_CEC/ DVDD PINCNTL231 SPI[2]_D[0]/ DSIS: PIN GP3[30] MM: MUX1

EMAC[0]_MRXD[2]/ EMAC[0]_RGRXD[1]/ VIN[1]B_D[7]/ R23 I/O EMAC[0]_RMTXEN/

GP3[30]

EMAC[0]_MRXD[1]/ EMAC[0]_RGRXD[0]/ EMAC[0], VIN[1]B VIN[1]B_D[6]/ P23 I/O PINCNTL241 General-Purpose Input/Output (I/O) 3 [GP3] pin 29. EMAC[0]_RMTXD[1]/ DSIS: PIN

GP3[29]

EMAC[0]_MRXD[0]/ EMAC[0]_RGTXD[0]/ EMAC[0], VIN[1]B VIN[1]B_D[5]/ G28 I/O PINCNTL240 General-Purpose Input/Output (I/O) 3 [GP3] pin 28. EMAC[0]_RMTXD[0]/ DSIS: PIN

GP3[28]

EMAC[0]_MRCLK/ EMAC[0]_RGTXC/ EMAC[0], VIN[1]B, VIN[1]B_D[4]/ IPD SPI[3] EMAC[0]_RMCRSDV/ DVDD_GPMC PINCNTL239 SPI[3]_SCS[2]/ DSIS: PIN

GP3[27]

EMAC[0]_MRXER/ EMAC[0]_RGTXCTL/ EMAC[0], VIN[1]B VIN[1]B_D[3]/ J26 I/O PINCNTL238 General-Purpose Input/Output (I/O) 3 [GP3] pin 26. EMAC[0]_RMRXER/ DSIS: PIN

GP3[26]

EMAC[0]_MCRS/ EMAC[0]_RGRXD[2]/ EMAC[0], VIN[1]B VIN[1]B_D[2]/ R25 I/O PINCNTL237 General-Purpose Input/Output (I/O) 3 [GP3] pin 25. EMAC[0]_RMRXD[1]/ DSIS: PIN

GP3[25]

EMAC[0]_MCOL/ EMAC[0]_RGRXCTL/ EMAC[0], VIN[1]B VIN[1]B_D[1]/ L23 I/O PINCNTL236 General-Purpose Input/Output (I/O) 3 [GP3] pin 24. EMAC[0]_RMRXD[0]/ DSIS: PIN

GP3[24]

EMAC[0]_MTCLK/ EMAC[0]_RGRXC/ EMAC[0], VIN[1]B, VIN[1]B_D[0]/ IPD SPI[3], I2C[2] SPI[3]_SCS[3]/ DVDD_GPMC PINCNTL235 I2C[2]_SDA/ DSIS: PIN

GP3[23]

J7 I/O TIMER3 General-Purpose Input/Output (I/O) 3 [GP3] pin 31.

AF28 I/O

H27 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 27.

L24 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 23.

TYPE

Table 3-13. GP3 Terminal Functions

(1)

DVDD_GPMC DSIS: PIN

DVDD_GPMC

(2) (3)

OTHER

GPIO3

CLKOUT0,

PINCNTL259

IPD PINCNTL242

IPD

EMAC[0], VIN[1]B

MM: MUX0

MUXED DESCRIPTION

CLKIN32,

DSIS: PIN

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General-Purpose Input/Output (I/O) 3 [GP3] pin 30.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.

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SIGNAL

NAME NO.

VOUT[1]_R_CR[2]/ GPMC_A[15]/ VIN[1]A_D[23]/ IPD HDMI_HPDET/ DVDD SPI[2]_D[1]/

GP3[22]

VOUT[1]_R_CR[3]/ GPMC_A[14]/ VOUT[1], GPMC, VIN[1]A_D[22]/ VIN[1]A, HDMI, HDMI_SDA/ AG28 I/O SPI[2], I2C[2] General-Purpose Input/Output (I/O) 3 [GP3] pin 21. SPI[2]_SCLK/ PINCNTL229 I2C[2]_SDA DSIS: PIN

GP3[21]

VOUT[1]_G_Y_YC[2]/ GPMC_A[13]/ VOUT[1], GPMC, VIN[1]A_D[21]/ VIN[1]A, HDMI, HDMI_SCL/ AF27 I/O SPI[2], I2C[2] General-Purpose Input/Output (I/O) 3 [GP3] pin 20. SPI[2]_SCS[2]/ PINCNTL228 I2C[2]_SCL/ DSIS: PIN

GP3[20]

VOUT[1]_R_CR[9]/ VOUT[1], EMAC[1]_MTXEN/ EMAC[1], VIN[1]A, VIN[1]A_D[20]/ Y24 I/O UART5 General-Purpose Input/Output (I/O) 3 [GP3] pin 19. UART5_TXD/ PINCNTL227 GP3[19] DSIS: PIN

VOUT[1]_R_CR[8]/ VOUT[1], EMAC[1]_MTXD[7]/ EMAC[1], VIN[1]A, VIN[1]A_D[19]/ W23 I/O UART5 General-Purpose Input/Output (I/O) 3 [GP3] pin 18. UART5_RXD/ PINCNTL226 GP3[18] DSIS: PIN

VOUT[1]_R_CR[7]/ VOUT[1], EMAC[1]_MTXD[6]/ EMAC[1], VIN[1]A, VIN[1]A_D[18]/ V22 I/O SPI[3] General-Purpose Input/Output (I/O) 3 [GP3] pin 17. SPI[3]_D[0]/ PINCNTL225 GP3[17] DSIS: PIN

VOUT[1]_R_CR[6]/ VOUT[1], EMAC[1]_MTXD[5]/ EMAC[1], VIN[1]A, VIN[1]A_D[17]/ AA25 I/O SPI[3] General-Purpose Input/Output (I/O) 3 [GP3] pin 16. SPI[3]_D[1]/ PINCNTL224 GP3[16] DSIS: PIN

VOUT[1]_R_CR[5]/ VOUT[1], EMAC[1]_MTXD[4]/ EMAC[1], VIN[1]A, VIN[1]A_D[16]/ AC26 I/O SPI[3] General-Purpose Input/Output (I/O) 3 [GP3] pin 15. SPI[3]_SCLK/ PINCNTL223 GP3[15] DSIS: PIN

VOUT[1]_R_CR[4]/ VOUT[1], EMAC[1]_MTXD[3]/ EMAC[1], VIN[1]A_D[15]/ AG27 I/O VIN[1]ASPI[3] General-Purpose Input/Output (I/O) 3 [GP3] pin 14. SPI[3]_SCS[1]/ PINCNTL222 GP3[14] DSIS: PIN

VOUT[1]_G_Y_YC[9]/ VOUT[1], EMAC[1]_MTXD[2]/ IPD EMAC[1], VIN[1]A VIN[1]A_D[14]/ DVDD PINCNTL221 GP3[13] DSIS: PIN

VOUT[1]_G_Y_YC[8]/ VOUT[1], EMAC[1]_MTXD[1]/ IPD EMAC[1], VIN[1]A VIN[1]A_D[13]/ DVDD PINCNTL220 GP3[12] DSIS: PIN

VOUT[1]_G_Y_YC[7]/ VOUT[1], EMAC[1]_MTXD[0]/ IPD EMAC[1], VIN[1]A VIN[1]A_D[12]/ DVDD PINCNTL219 GP3[11] DSIS: PIN

AE27 I/O SPI[2] General-Purpose Input/Output (I/O) 3 [GP3] pin 22.

AD26 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 13.

AE26 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 12.

AF26 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 11.

Table 3-13. GP3 Terminal Functions (continued)

TYPE

(1)

OTHER

IPU

DVDD

IPU

DVDD

IPD

DVDD

IPD

DVDD

IPD

DVDD

IPD

DVDD

IPD

DVDD

IPD

DVDD

(2) (3)

MUXED DESCRIPTION

VOUT[1], GPMC,

VIN[1]A, HDMI,

PINCNTL230

DSIS: PIN

ZHCS057–MARCH 2011

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SIGNAL

NAME NO.

VOUT[1]_G_Y_YC[6]/ VOUT[1], EMAC[1]_GMTCLK/ IPD EMAC[1], VIN[1]A VIN[1]A_D[11]/ DVDD PINCNTL218 GP3[10] DSIS: PIN

VOUT[1]_G_Y_YC[5]/ VOUT[1], EMAC[1]_MRXDV/ IPD EMAC[1], VIN[1]A VIN[1]A_D[10]/ DVDD PINCNTL217 GP3[9] DSIS: PIN

VOUT[1]_G_Y_YC[4]/ VOUT[1], EMAC[1]_MRXD[7]/ IPD EMAC[1], VIN[1]A VIN[1]A_D[9]/ DVDD PINCNTL216 GP3[8] DSIS: PIN

VOUT[1]_G_Y_YC[3]/ VOUT[1], EMAC[1]_MRXD[6]/ IPD EMAC[1], VIN[1]A VIN[1]A_D[8]/ DVDD PINCNTL215 GP3[7] DSIS: PIN

VOUT[1]_B_CB_C[9]/ VOUT[1], EMAC[1]_MRXD[5]/ EMAC[1], VIN[1]A, VIN[1]A_D[6]/ AA24 I/O I2C[3] General-Purpose Input/Output (I/O) 3 [GP3] pin 6. I2C[3]_SDA/ PINCNTL214 GP3[6] DSIS: PIN

VOUT[1]_B_CB_C[8]/ VOUT[1], EMAC[1]_MRXD[4]/ EMAC[1], VIN[1]A, VIN[1]A_D[5]/ AH26 I/O I2C[3] General-Purpose Input/Output (I/O) 3 [GP3] pin 5. I2C[3]_SCL/ PINCNTL213 GP3[5] DSIS: PIN

VOUT[1]_B_CB_C[7]/ VOUT[1], EMAC[1]_MRXD[3]/ EMAC[1], VIN[1]A, VIN[1]A_D[4]/ AC25 I/O UART3 General-Purpose Input/Output (I/O) 3 [GP3] pin 4. UART3_TXD/ PINCNTL212 GP3[4] DSIS: PIN

VOUT[1]_B_CB_C[6]/ VOUT[1], EMAC[1]_MRXD[2]/ EMAC[1], VIN[1]A, VIN[1]A_D[3]/ AD25 I/O UART3 General-Purpose Input/Output (I/O) 3 [GP3] pin 3. UART3_RXD/ PINCNTL211 GP3[3] DSIS: PIN

VOUT[1]_B_CB_C[5]/ VOUT[1], EMAC[1]_MRXD[1]/ EMAC[1], VIN[1]A, VIN[1]A_D[2]/ AF25 I/O UART4 General-Purpose Input/Output (I/O) 3 [GP3] pin 2. UART4_TXD/ PINCNTL210 GP3[2] DSIS: PIN

VOUT[1]_B_CB_C[4]/ VOUT[1], EMAC[1]_MRXD[0]/ EMAC[1], VIN[1]A, VIN[1]A_D[1]/ AG25 I/O UART4 General-Purpose Input/Output (I/O) 3 [GP3] pin 1. UART4_RXD/ PINCNTL209 GP3[1] DSIS: PIN

VOUT[1]_B_CB_C[3]/ VOUT[1], EMAC[1]_MRCLK/ EMAC[1], VIN[1]A, VIN[1]A_D[0]/ AH25 I/O UART4 General-Purpose Input/Output (I/O) 2 [GP2] pin 0. UART4_CTS/ PINCNTL208 GP3[0] DSIS: PIN

AH27 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 10.

AG26 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 9.

W22 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 8.

Y23 I/O General-Purpose Input/Output (I/O) 3 [GP3] pin 7.

Table 3-13. GP3 Terminal Functions (continued)

TYPE

(1)

OTHER

IPD

DVDD

IPD

DVDD

IPD

DVDD

IPD

DVDD

IPD

DVDD

IPD

DVDD

IPD

DVDD

(2) (3)

MUXED DESCRIPTION

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3.2.8 GPMC

SIGNAL

NAME NO.

GPMC_CLK/

GPMC_CS[5]/ GPMC, CLKOUT1, GPMC_WAIT[1]/ EDMA, TIMER4, CLKOUT1/ R26 O GP1 GPMC Clock output EDMA_EVT3/ PINCNTL127 TIM4_IO/ DSIS: 0 GP1[27]

SD2_DAT[4]/ GPMC_A[27]/ SD2, GPMC, GPMC_A[23]/ EDMA, TIMER7, GPMC_CS[7]/ R24 O GP1 GPMC Chip Select 7 EDMA_EVT0/ PINCNTL116 TIM7_IO/ DSIS: N/A GP1[22]

GPMC_ADV_ALE/ GPMC, TIMER5, GPMC_CS[6]/ IPU GP1 TIM5_IO/ DVDD_GPMC PINCNTL128 GP1[28] DSIS: N/A

GPMC_CLK/ GPMC_CS[5]/ GPMC, CLKOUT1, GPMC_WAIT[1]/ EDMA, TIMER4, CLKOUT1/ R26 O GP1 GPMC Chip Select 5 EDMA_EVT3/ PINCNTL127 TIM4_IO/ DSIS: N/A GP1[27]

GPMC_CS[4]/ SD2, GP1 SD2_CMD/ P25 O PINCNTL126 GPMC Chip Select 4 GP1[8] DSIS: N/A

GPMC_CS[3]/ VIN[1]B, SPI[2], VIN[1]B_CLK/ IPU GP1 SPI[2]_SCS[0]/ DVDD_GPMC PINCNTL125 GP1[26] DSIS: N/A

GPMC_CS[2]/ GPMC, GP1 GPMC_A[24]/ M25 O PINCNTL124 GPMC Chip Select 2 GP1[25] DSIS: N/A

GPMC_CS[1]/ GPMC, GP1 GPMC_A[25]/ K28 O PINCNTL123 GPMC Chip Select 1 GP1[24] DSIS: N/A

GPMC_CS[0]/ IPU GP1[23] DVDD_GPMC

M26 O GPMC Chip Select 6

P26 O GPMC Chip Select 3

T28 O PINCNTL122 GPMC Chip Select 0

TYPE

GPMC_WE U28 O PINCNTL130 GPMC Write Enable output

GPMC_OE_RE T27 O PINCNTL129 GPMC Output Enable output

GPMC_BE[1]/ GPMC_A[24]/ EDMA_EVT1/ V28 O GPMC Upper Byte Enable output TIM7_IO/ GP1[30]

Table 3-14. GPMC Terminal Functions

(1)

DVDD_GPMC

DVDD_GPMC PINCNTL132

(2) (3)

OTHER

IPU

DSIS: N/A

IPU

DSIS: N/A

IPU

DSIS: N/A

IPD TIMER7, GP1

GPMC, EDMA,

DSIS: N/A

MUXED DESCRIPTION

GP1

–

ZHCS057–MARCH 2011

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and the , Pin Behaviors at Reset.

(3) Specifies the operating I/O supply voltage for each signal

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SIGNAL

NAME NO.

GPMC_BE[0]_CLE/

GPMC_A[25]/ EDMA_EVT2/ U27 O TIM6_IO/ GP1[29]

GPMC_ADV_ALE/ GPMC, TIMER5, GPMC_CS[6]/ IPU GP1 GPMC Address Valid output or Address Latch Enable TIM5_IO/ DVDD_GPMC PINCNTL128 output GP1[28] DSIS: N/A

GPMC_CLK/ GPMC_CS[5]/ GPMC, CLKOUT1, GPMC_WAIT[1]/ EDMA, TIMER4, CLKOUT1/ R26 I GP1 GPMC Wait input 1 EDMA_EVT3/ PINCNTL127 TIM4_IO/ DSIS: 1 GP1[27]

GPMC_WAIT[0]/ GPMC, EDMA, GPMC_A[26]/ IPU GP1 EDMA_EVT0/ DVDD_GPMC PINCNTL133 GP1[31] DSIS: 1

EMAC[0]_MRXD[3]/ EMAC[0], EMAC[1]_RGRXCTL/ EMAC[1], GPMC, GPMC_A[27]/ IPD UART5 GPMC_A[26]/ DVDD_GPMC PINCNTL243 GPMC_A[0]/ DSIS: N/A UART5_RXD MM: MUX1

SD2_DAT[4]/ GPMC_A[27]/ GPMC_A[23]/ GPMC_CS[7]/ R24 O EDMA_EVT0/ TIM7_IO/ GP1[22]

GPMC_WAIT[0]/ GPMC_A[26]/ IPU EDMA_EVT0/ DVDD_GPMC GP1[31]

EMAC[0]_MRXD[3]/ EMAC[0], EMAC[1]_RGRXCTL/ EMAC[1], GPMC, GPMC_A[27]/ IPD UART5 GPMC_A[26]/ DVDD_GPMC PINCNTL243 GPMC_A[0]/ DSIS: N/A UART5_RXD MM: MUX1

SD2_DAT[5]/ SD2, GPMC, GPMC_A[26]/ TIMER6, GP1 GPMC_A[22]/ P22 O PINCNTL115 TIM6_IO/ DSIS: N/A GP1[21] MM: MUX0

M26 O

W28 I GPMC Wait input 0

J25 O

W28 O PINCNTL133

J25 O GPMC Address 26

Table 3-14. GPMC Terminal Functions (continued)

TYPE

(1)

DVDD_GPMC PINCNTL131 Enable output

DVDD_GPMC

DVDD_GPMC PINCNTL116

DVDD_GPMC

(2) (3)

OTHER

IPD TIMER6, GP1 GPMC Lower Byte Enable output or Command Latch

IPU

IPU GP1

IPU

MUXED DESCRIPTION

GPMC, EDMA,

DSIS: PIN

SD2, GPMC,

EDMA, TIMER7,

DSIS: N/A

MM: MUX0

GPMC, EDMA,

GP1

DSIS: N/A

MM: MUX2

GPMC Address 27

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SIGNAL

NAME NO.

GPMC_BE[0]_CLE/ GPMC, EDMA, GPMC_A[25]/ TIMER6, GP1 EDMA_EVT2/ U27 O PINCNTL131 TIM6_IO/ DSIS: N/A GP1[29] MM: MUX2

GPMC_CS[1]/ GPMC_A[25]/ K28 O GPMC Address 25 GP1[24]

SD2_DAT[6]/ SD2, GPMC, GPMC_A[25]/ UART2, GP1 GPMC_A[21]/ N23 O PINCNTL114 UART2_TXD/ DSIS: N/A GP1[20] MM: MUX0

GPMC_BE[1]/ GPMC, EDMA, GPMC_A[24]/ TIMER7, GP1 EDMA_EVT1/ V28 O PINCNTL132 TIM7_IO/ DSIS: N/A GP1[30] MM: MUX2

GPMC_CS[2]/ GPMC_A[24]/ M25 O GPMC Address 24 GP1[25]

SD2_DAT[7]/ SD2, GPMC, GPMC_A[24]/ UART2, GP1 GPMC_A[20]/ L25 O PINCNTL113 UART2_RXD/ DSIS: N/A GP1[19] MM: MUX0

SD2_DAT[4]/ GPMC_A[27]/ GPMC_A[23]/ GPMC_CS[7]/ R24 O EDMA_EVT0/ TIM7_IO/ GP1[22]

GPMC_A[23]/ SPI[2], HDMI, SPI[2]_SCLK/ TIMER5, GP1 HDMI_HPDET/ AA26 O PINCNTL112 TIM5_IO/ DSIS: N/A GP1[18] MM: MUX0

SD2_DAT[5]/ SD2, GPMC, GPMC_A[26]/ TIMER6, GP1 GPMC_A[22]/ P22 O PINCNTL115 TIM6_IO/ DSIS: N/A GP1[21] MM: MUX1

GPMC_A[22]/ SPI[2], HDMI, SPI[2]_D[1]/ TIMER4, GP1 HDMI_CEC/ AB27 O PINCNTL111 TIM4_IO/ DSIS: N/A GP1[17] MM: MUX0

SD2_DAT[6]/ SD2, GPMC, GPMC_A[25]/ UART2, GP1 GPMC_A[21]/ N23 O PINCNTL114 UART2_TXD/ DSIS: N/A GP1[20] MM: MUX1

GPMC_A[21]/ SPI[2]_D[0]/ AC28 O GP1[16]

TYPE

Table 3-14. GPMC Terminal Functions (continued)

(1)

DVDD_GPMC

DVDD_GPMC DSIS: N/A

DVDD_GPMC

DVDD_GPMC DSIS: N/A

DVDD_GPMC

DVDD_GPMC PINCNTL116

DVDD_GPMC

DVDD_GPMC DSIS: N/A

(2) (3)

OTHER

IPD

IPU PINCNTL123

IPU

IPD

IPU PINCNTL124

IPU

IPU GP1

IPD

IPU

IPD PINCNTL110

GPMC, GP1

MM: MUX1

GPMC, GP1

MM: MUX1

SD2, GPMC,

EDMA, TIMER5,

DSIS: N/A

MM: MUX1

SPI[2], GP1

MM: MUX0

MUXED DESCRIPTION

GPMC Address 23

GPMC Address 22

GPMC Address 21

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SIGNAL

NAME NO.

SD2_DAT[7]/ SD2,. GPMC, GPMC_A[24]/ UART2, GP1 GPMC_A[20]/ L25 O PINCNTL113 UART2_RXD/ DSIS: N/A GP1[19] MM: MUX1

GPMC_A[20]/ SPI[2]_SCS[1]/ AD28 O GP1[15]

GPMC_A[19]/ TIMER2, GP1 TIM3_IO/ AC27 O PINCNTL108 GPMC Address 19 GP1[14] DSIS: N/A

GPMC_A[18]/ TIMER2, GP1 TIM2_IO/ AE28 O PINCNTL107 GPMC Address 18 GP1[13] DSIS: N/A

GPMC_A[17]/ IPD GP2[6] DVDD_GPMC

GPMC_A[16]/ IPD GP2[5] DVDD_GPMC

VOUT[1]_R_CR[2]/ GPMC_A[15]/ VIN[1]A_D[23]/ IPD HDMI_HPDET/ DVDD SPI[2]_D[1]/ GP3[22]

EMAC[0]_MTXEN/ EMAC[0], EMAC[1]_RGRXD[2]/ EMAC[1], UART1 EMAC[1]_RMTXEN/ J23 O PINCNTL258 GPMC_A[15]/ DSIS: N/A UART1_RTS MM: MUX0

VOUT[1]_R_CR[3]/ GPMC_A[14]/ VIN[1]A_D[22]/ HDMI_SDA/ AG28 O SPI[2]_SCLK/ I2C[2]_SDA/ GP3[21]

EMAC[0]_MTXD[7]/ EMAC[0], EMAC[1]_RGTXD[3]/ EMAC[1], UART1 EMAC[1]_RMTXD[1]/ H24 O PINCNTL257 GPMC_A[14]/ DSIS: N/A UART1_CTS MM: MUX0

VOUT[1]_G_Y_YC[2]/ GPMC_A[13]/ VIN[1]A_D[21]/ HDMI_SCL/ AF27 O SPI[2]_SCS[2]/ I2C[2]_SCL/ GP3[20]

EMAC[0]_MTXD[6]/ EMACF[0], EMAC[1]_RGRXD[0]/ EMAC[1], UART1 EMAC[1]_RMTXD[0]/ J22 O PINCNTL256 GPMC_A[13]/ DSIS: N/A UART1_TXD MM: MUX0

V23 O PINCNTL106 GPMC Address 17

AD27 O PINCNTL105 GPMC Address 16

AE27 O PINCNTL230

Table 3-14. GPMC Terminal Functions (continued)

TYPE

(1)

DVDD_GPMC

DVDD_GPMC DSIS: N/A

DVDD_GPMC

(2) (3)

OTHER

IPU

IPU PINCNTL109

IPD

IPU I2C[2], GP3

DVDD PINCNTL229

IPD

IPU I2C[2], GP3

DVDD PINCNTL228

IPD

MUXED DESCRIPTION

SPI[2], GP1

MM: MUX0

DSIS: N/A

VOUT[1], VIN[1]A, HDMI, SPI[2],GP3

DSIS: N/A

MM: MUX1

VOUT[1], VIN[1]A,

HDMI, SPI[2],

DSIS: N/A

MM: MUX1

VOUT[1], VIN[1]A,

HDMI, SPI[2],

DSIS: N/A

MM: MUX1

GPMC Address 20

GP2

GPMC Address 15

GPMC Address 14

GPMC Address 13

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SIGNAL

NAME NO.

VOUT[0]_FLD/ CAM_PCLK/ GPMC_A[12]/ AF18 O UART2_RTS/ GP2[2]

EMAC[0]_MTXD[5]/ EMAC[0], EMAC[1]_RGTXC/ EMAC[1], UART1 EMAC[1]_RMCRSDV/ F27 O PINCNTL255 GPMC_A[12]/ DSIS: N/A UART1_RXD MM: MUX0

VOUT[1]_FLD/ VOUT[1], CAM_FLD/ CAMERA_I/F, CAM_WE/ IPD UART2, GP0 GPMC_A[11]/ DVDD_C PINCNTL174 UART2_CTS/ DSIS: N/A GP0[28] MM: MUX1

EMAC[0]_MTXD[4]/ EMAC[0], EMAC[1]_RGTXD[2]/ EMAC[1], UART4 EMAC[1]_RMRXER/ G23 O PINCNTL254 GPMC_A[11]/ DSIS: N/A UART4_RTS MM: MUX0

VOUT[1]_B_CB_C[0]/ CAM_VS/ GPMC_A[10]/ AD23 O UART2_TXD/ GP0[27]

EMAC[0]_MTXD[3]/ EMAC[0], EMAC[1]_RGTXD[0]/ EMAC[1], UART4 EMAC[1]_RMRXD[1]/ H23 O PINCNTL253 GPMC_A[10]/ DSIS: N/A UART4_CTS MM: MUX0

VOUT[1]_B_CB_C[1]/ CAM_HS/ GPMC_A[9]/ AE23 O UART2_RXD/ GP0[26]

EMAC[0]_MTXD[2]/ EMAC[0], EMAC[1]_RGTXCTL/ EMAC[1], UART4 EMAC[1]_RMRXD[0]/ H22 O PINCNTL252 GPMC_A[9]/ DSIS: N/A UART4_TXD MM: MUX0

VOUT[1]_R_CR[0]/ CAM_D[0]/ GPMC_A[8]/ AA22 O UART4_RTS/ GP0[25]

EMAC[0]_MTXD[1]/ EMAC[1]_RGTXD[1]/ IPD GPMC_A[8]/ DVDD_GPMC UART4_RXD

AB23 O

H25 O PINCNTL251

TYPE

Table 3-14. GPMC Terminal Functions (continued)

(1)

DVDD_GPMC

(2) (3)

OTHER

IPD UART2, GP2

DVDD_C PINCNTL175

IPD

IPU UART2, GP0

DVDD_C PINCNTL173

IPD

IPD UART2, GP0

DVDD_C PINCNTL172

IPD

IPD UART4, GP0

DVDD_C PINCNTL171

MUXED DESCRIPTION

VOUT[0],

CAMERA_I/F,

DSIS: N/A

MM: MUX1

VOUT[1],

CAMERA_I/F,

DSIS: N/A

MM: MUX1

VOUT[1],

CAMERA_I/F,

DSIS: N/A

MM: MUX1

VOUT[1],

CAMERA_I/F,

DSIS: N/A

MM: MUX1

EMAC[0],

EMAC[1], UART4

DSIS: N/A

MM: MUX0

GPMC Address 12

GPMC Address 11

GPMC Address 10

GPMC Address 9

GPMC Address 8

ZHCS057–MARCH 2011

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SIGNAL

NAME NO.

VOUT[1]_R_CR[1]/ CAM_D[1]/ GPMC_A[7]/ AC19 O UART4_CTS/ GP0[24]

EMAC[0]_MTXD[0]/ EMAC[1]_RGRXD[3]/ IPD GPMC_A[7]/ DVDD_GPMC SPI[2]_D[0]

VOUT[1]_G_Y_YC[0]/ CAM_D[2]/ GPMC_A[6]/ AC18 O UART4_TXD/ GP0[23]

EMAC[0]_GMTCLK/ EMAC[1]_RGRXC/ IPD GPMC_A[6]/ DVDD_GPMC SPI[2]_D[1]

VOUT[1]_G_Y_YC[1]/ CAM_D[3]/ GPMC_A[5]/ AD18 O UART4_RXD/ GP0[22]

EMAC[0]_MRXDV/ EMAC[1]_RGRXD[1]/ IPD GPMC_A[5]/ DVDD_GPMC SPI[2]_SCLK

SD2_DAT[0]/ GPMC_A[4]/ L26 O GP1[14]

EMAC[0]_MRXD[7]/ EMAC[0], SPI[2] EMAC[0]_RGTXD[1]/ IPD PINCNTL247 GPMC_A[4]/ DVDD_GPMC DSIS: N/A SPI[2]_SCS[3] MM: MUX0

SD2_DAT[1]_ SDIRQ/ GPMC_A[3]/ M24 O GP1[13]

EMAC[0]_MRXD[6]/ EMAC[0], UART5 EMAC[0]_RGTXD[2]/ IPD PINCNTL246 GPMC_A[3]/ DVDD_GPMC DSIS: N/A UART5_RTS MM: MUX0

SD2_DAT[2]_SDRW/ GPMC_A[2]/ K27 O GP2[6]

EMAC[0]_MRXD[5]/ EMAC[0], UART5 EMAC[0]_RGTXD[3]/ IPD PINCNTL245 GPMC_A[2]/ DVDD_GPMC DSIS: N/A UART5_CTS MM: MUX0

J24 O PINCNTL250

K23 O PINCNTL249

K22 O PINCNTL248

G27 O

F28 O

H26 O

Table 3-14. GPMC Terminal Functions (continued)

TYPE

(1)

DVDD_GPMC DSIS: N/A

(2) (3)

OTHER

IPD UART4, GP0

DVDD_C PINCNTL170

IPD UART4, GP0

DVDD_C PINCNTL169

IPU UART4, GP0

DVDD_C PINCNTL168

IPU PINCNTL120

IPU PINCNTL119

IPU PINCNTL118

MUXED DESCRIPTION

VOUT[1],

CAMERA_I/F,

DSIS: N/A

MM: MUX1

EMAC[0],

EMAC[1], SPI[2]

DSIS: N/A

MM: MUX0

VOUT[1],

CAMERA_I/F,

DSIS: N/A

MM: MUX1

EMAC[0],

EMAC[1], SPI[2]

DSIS: N/A

MM: MUX0

VOUT[1],

CAMERA_I/F,

DSIS: N/A

MM: MUX1

EMAC[0],

EMAC[1], SPI[2]

DSIS: N/A

MM: MUX0

SD2, GP1

MM: MUX1

SD2, GP1

MM: MUX1

SD2, GP2

MM: MUX1

GPMC Address 7

GPMC Address 6

GPMC Address 5

GPMC Address 4

GPMC Address 3

GPMC Address 2

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Table 3-14. GPMC Terminal Functions (continued)

SIGNAL

NAME NO.

SD2_DAT[3]/ GPMC_A[1]/ J28 O GP2[5]

EMAC[0]_MRXD[4]/ EMAC[0], UART5 EMAC[0]_RGRXD[3]/ IPD PINCNTL244 GPMC_A[1]/ DVDD_GPMC DSIS: N/A UART5_TXD MM: MUX0

VOUT[1]_B_CB_C[2]/ GPMC_A[0]/ VIN[1]A_D[7]/ IPU HDMI_CEC/ DVDD SPI[2]_D[0]/ GP3[30]

EMAC[0]_MRXD[3]/ EMAC[0], EMAC[1]_RGRXCTL/ EMAC[1], GPMC, GPMC_A[27]/ IPD UART5 GPMC_A[26]/ DVDD_GPMC PINCNTL243 GPMC_A[0]/ DSIS: N/A UART5_RXD MM: MUX0

T23 O

AF28 O PINCNTL231

J25 O

TYPE

(1)

DVDD_GPMC DSIS: N/A

(2) (3)

OTHER

IPU PINCNTL117

VOUT[1], VIN[1]A,

HDMI, SPI[2], GP3

MUXED DESCRIPTION

SD2, GP2

MM: MUX1

DSIS: N/A

MM: MUX1

ZHCS057–MARCH 2011

GPMC Address 1

GPMC Address 0

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SIGNAL

NAME NO.

GPMC_D[15]/ DIS

BTMODE[15] DVDD_GPMC

GPMC_D[14]/ DIS BTMODE[14] DVDD_GPMC

GPMC_D[13]/ DIS BTMODE[13] DVDD_GPMC

GPMC_D[12]/ DIS BTMODE[12] DVDD_GPMC

GPMC_D[11]/ DIS BTMODE[11] DVDD_GPMC

GPMC_D[10]/ DIS BTMODE[10] DVDD_GPMC

GPMC_D[9]/ DIS BTMODE[9] DVDD_GPMC

GPMC_D[8]/ DIS BTMODE[8] DVDD_GPMC

GPMC_D[7]/ DIS BTMODE[7] DVDD_GPMC

GPMC_D[6]/ DIS BTMODE[6] DVDD_GPMC

GPMC_D[5]/ DIS BTMODE[5] DVDD_GPMC

GPMC_D[4]/ DIS BTMODE[4] DVDD_GPMC

GPMC_D[3]/ DIS BTMODE[3] DVDD_GPMC

GPMC_D[2]/ DIS BTMODE[2] DVDD_GPMC

GPMC_D[1]/ DIS BTMODE[1] DVDD_GPMC

GPMC_D[0]/ DIS+ BTMODE[0] DVDD_GPMC

Y25 I/O PINCNTL104

V24 I/O PINCNTL103

U23 I/O PINCNTL102

U24 I/O PINCNTL101

AA27 I/O PINCNTL100

Y26 I/O PINCNTL99

AB28 I/O PINCNTL98

Y27 I/O PINCNTL97

V25 I/O PINCNTL96

U25 I/O PINCNTL95

AA28 I/O PINCNTL94

V26 I/O PINCNTL93

W27 I/O PINCNTL92

V27 I/O PINCNTL91

Y28 I/O PINCNTL90

U26 I/O PINCNTL89

Table 3-14. GPMC Terminal Functions (continued)

TYPE

(1)

OTHER

(2) (3)

MUXED DESCRIPTION

BTMODE

DSIS: PIN

BTMODE

DSIS: PIN

BTMODE

DSIS: PIN

BTMODE

DSIS: PIN

BTMODE

DSIS: PIN

BTMODE

DSIS: PIN

BTMODE

DSIS: PIN

BTMODE

DSIS: PIN

BTMODE

DSIS: PIN

BTMODE

DSIS: PIN

BTMODE

DSIS: PIN

BTMODE

DSIS: PIN

BTMODE

DSIS: PIN

BTMODE

DSIS: PIN

BTMODE

DSIS: PIN

BTMODE

DSIS: PIN

GPMC Multiplexed Data/Address I/Os.

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3.2.9 HDMI

SIGNAL

NAME NO.

HDMI_CLKP AG18 O VDDA_HDMI_ –

HDMI_CLKN AH18 O VDDA_HDMI_ –

HDMI_DN2 AH21 O VDDA_HDMI_ –

HDMI_DP2 AG21 O VDDA_HDMI_ –

HDMI_DN1 AH20 O VDDA_HDMI_ –

HDMI_DP1 AG20 O VDDA_HDMI_ –

HDMI_DN0 AH19 O VDDA_HDMI_ –

HDMI_DP0 AG19 O VDDA_HDMI_ –

VOUT[1]_G_Y_YC[2]/ GPMC_A[13]/ VIN[1]A_D[21]/ HDMI_SCL/ AF27 I/O SPI[2]_SCS[2]/ I2C[2]_SCL/ GP3[20]

I2C[1]_SCL/ PINCNTL78 HDMI_SCL DSIS: 1

VOUT[1]_R_CR[3]/ GPMC_A[14]/ VIN[1]A_D[22]/ HDMI_SDA/ AG28 I/O SPI[2]_SCLK/ I2C[2]_SDA/ GP3[21]

I2C[1]_SDA/ PINCNTL79 HDMI_SDA DSIS: 1

AF24 I/O DVDD

AG24 I/O DVDD

TYPE

Table 3-15. HDMI Terminal Functions

(1)

(2) (3)

OTHER

–

1P8

–

1P8

–

1P8

–

1P8

–

1P8

–

1P8

–

1P8

–

1P8

IPU I2C[2], GP3

DVDD PINCNTL228

IPU I2C[2], GP3

DVDD PINCNTL229

MUXED DESCRIPTION

VOUT[1], GPMC,

VIN[1]A, SPI[2],

DSIS: 1

MM: MUX1

I2C[1]

MM: MUX0

VOUT[1], GPMC,

VIN[1]A, SPI[2],

DSIS: 1

MM: MUX1

I2C[1]

MM: MUX0

ZHCS057–MARCH 2011

HDMI Clock Output. When the HDMI PHY is powered down, these pins

should be left unconnected.

HDMI Data 2 output. When the HDMI PHY is powered down, these pins

should be left unconnected.

HDMI Data 1 output. When the HDMI PHY is powered down, these pins

should be left unconnected.

HDMI Data 0 output. When the HDMI PHY is powered down, these pins

should be left unconnected.

HDMI I2C Serial Clock Output

HDMI I2C Serial Data I/O

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.

(3) Specifies the operating I/O supply voltage for each signal

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Table 3-15. HDMI Terminal Functions (continued)

SIGNAL

NAME NO.

VOUT[1]_B_CB_C[2]/ VOUT[1], GPMC, GPMC_A[0]/ VIN[1]A, SPI[2], VIN[1]A_D[7]/ IPU GP3 HDMI_CEC/ DVDD PINCNTL231 SPI[2]_D[0]/ DSIS: 1 GP3[30] MM: MUX1

GPMC_A[22]/ GPMC, SPI[2], SPI[2]_D[1]/ TIMER4, GP1 HDMI_CEC/ AB27 I/O PINCNTL111 TIM4_IO/ DSIS: 1 GP1[17] MM: MUX0

VOUT[1]_R_CR[2]/ VOUT[1], GPMC, GPMC_A[15]/ VIN[1]A, SPI[2], VIN[1]A_D[23]/ IPD GP3 HDMI_HPDET/ DVDD PINCNTL230 SPI[2]_D[1]/ DSIS: 0 GP3[22] MM: MUX1

GPMC_A[23]/ GPMC, SPI[2], SPI[2]_SCLK/ TIMER5, GP1 HDMI_HPDET/ AA26 I PINCNTL112 TIM5_IO/ DSIS: 0 GP1[18] MM: MUX0

AF28 I/O

AE27 I

TYPE

(1)

OTHER

DVDD_GPMC

IPU

IPD

(2) (3)

MUXED DESCRIPTION

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HDMI Consumer Electronics Control I/O

HDMI Hot Plug Detect Input. Signals the connection / removal of an HDMI cable at the connector.

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3.2.10 I2C

Table 3-16. I2C Terminal Functions

SIGNAL

NAME NO.

I2C[0]_SCL AC4 I/O DVDD

I2C[0]_SDA AB6 I/O DVDD

I2C[1]_SCL/ HDMI_SCL

I2C[1]_SDA/ HDMI_SDA

VIN[0]A_FLD/ VIN[0]A, VIN[0]B,UART5, VIN[0]B_VSYNC/ GP2 UART5_RXD/ AA20 I/O PINCNTL136 I2C[2]_SCL/ DSIS: 1 GP2[1] MM: MUX3

VOUT[1]_G_Y_YC[2]/ GPMC_A[13]/ VOUT[1], GPMC, VIN[1]A, VIN[1]A_D[21]/ HDMI, SPI[2], GP3 HDMI_SCL/ AF27 I/O PINCNTL228 SPI[2]_SCS[2]/ DSIS: 1 I2C[2]_SCL/ MM: MUX2 GP3[20]

VIN[0]A_D[16]/ VIN[0]A, CAM I/F, GP0 CAM_D[8]/ IPU PINCNTL156 I2C[2]_SCL/ DVDD_C DSIS: 1 GP0[10] MM: MUX1

UART0_DCD/ UART3_RXD/ SPI[0]_SCS[3]/ IPU I2C[2]_SCL/ DVDD SD1_POW/ GP1[2]

AF24 I/O DVDD PINCNTL78 I2C mode, this pin must be pulled up via

AG24 I/O DVDD PINCNTL79 I2C mode, this pin must be pulled up via

AA21 I/O

AH4 I/O PINCNTL74

TYPE

(1)

OTHER

IPU

DVDD

IPU

DVDD

(2) (3)

MUXED DESCRIPTION

I2C[0]

– I2C[0] Clock I/O. For proper device operation,

PINCNTL263 this pin must be pulled up via external resistor.

– I2C[0] Data I/O. For proper device operation,

PINCNTL264 this pin must be pulled up via external resistor.

I2C[1]

HDMI I2C[1] Clock I/O. For proper device operation in

DSIS: 1 external resistor.

HDMI I2C[1] Data I/O. For proper device operation in

DSIS: 1 external resistor.

I2C[2]

UART0, UART3, SPI[0],

SD1, GP1

DSIS: 1

MM: MUX0

ZHCS057–MARCH 2011

I2C[2] Clock I/O. For proper device operation in I2C mode, this pin must be pulled up via external resistor.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and the , Pin Behaviors at Reset.

(3) Specifies the operating I/O supply voltage for each signal

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SIGNAL

NAME NO.

EMAC[0]_MTCLK/ EMAC[0]_RGRXC/ VIN[1]B_D[0]/ IPD SPI[3]_SCS[3]/ DVDD_GPMC I2C[2]_SDA/ GP3[23]

VOUT[1]_R_CR[3]/ GPMC_A[14]/ VOUT[1], GPMC, VIN[1]A, VIN[1]A_D[22]/ HDMI, SPI[2], GP3 HDMI_SDA/ AG28 I/O PINCNTL229 SPI[2]_SCLK/ DSIS: 1 I2C[2]_SDA/ MM: MUX2 GP3[21]

VIN[0]A_DE/ VIN[0]A, VIN[0]B, UART5, VIN[0]B_HSYNC/ GP2 UART5_TXD/ AE21 I/O PINCNTL135 I2C[2]_SDA/ DSIS: 1 GP2[0] MM: MUX1

UART0_DSR/ UART3_TXD/ SPI[0]_SCS[2]/ IPU I2C[2]_SDA/ DVDD SD1_SDWP/ GP1[3]

VOUT[1]_B_CB_C[8]/ VOUT[1], EMAC[1], EMAC[1]_RMRXD[4]/ VIN[1]A, GP3 VIN[1]A_D[5]/ AH26 I/O PINCNTL213 I2C[3]_SCL/ DSIS: 1 GP3[5] MM: MUX3

VIN[0]A_D[18]/ VIN[0]A, CAM I/F, CAM_D[10]/ EMAC[1], GP0 EMAC[1]_RMRXD[1]/ AF20 I/O PINCNTL158 I2C[3]_SCL/ DSIS: 1 GP0[12] MM: MUX2

DCAN0_RX/ DCAN0, UART2, GP1 UART2_RXD/ IPU PINCNTL69 I2C[3]_SCL/ DVDD DSIS: 1 GP1[1] MM: MUX1

MCA[0]_AXR[1]/ IPU PINCNTL22 I2C[3]_SCL DVDD DSIS: 1

VOUT[1]_B_CB_C[9]/ VOUT[1], EMAC[1], EMAC[1]_MRXD[5]/ VIN[1]A, GP3 VIN[1]A_D[6]/ AA24 I/O PINCNTL214 I2C[3]_SDA/ DSIS: 1 GP3[6] MM: MUX3

VIN[0]A_D[19]/ VIN[0]A, CAM I/F, CAM_D[11]/ EMAC[1], GP0 EMAC[1]_RMRXD[0]/ AF21 I/O PINCNTL159 I2C[3]_SDA/ DSIS: 1 GP0[13] MM: MUX2

DCAN0_TX/ DCAN0, UART2, GP1 UART2_TXD/ IPU PINCNTL68 I2C[3]_SDA/ DVDD DSIS: 1 GP1[0] MM: MUX1

MCA[0]_AXR[2]/ IPU PINCNTL23 I2C[3]_SDA DVDD DSIS: 1

L24 I/O PINCNTL235

AG4 I/O PINCNTL75

AG6 I/O

J1 I/O

AH6 I/O

L4 I/O

Table 3-16. I2C Terminal Functions (continued)

TYPE

(1)

OTHER

IPU

DVDD

IPU

DVDD

IPD

DVDD

IPU

DVDD_C

IPD

DVDD

IPU

DVDD_C

(2) (3)

EMAC[0], VIN[1]B, SPI[3],

MM: MUX3

UART0, UART3, SPI[0],

MM: MUX0

I2C3

MM: MUX0

MUXED DESCRIPTION

GP3

DSIS: 1

I2C[2] Data I/O. For proper device operation in I2C mode, this pin must be pulled up via external resistor.

SD1, GP1

DSIS: 1

I2C3 Clock I/O. For proper device operation in I2C mode, this pin must be pulled up via external resistor.

MCA[0]

I2C3 Data I/O. For proper device operation in I2C mode, this pin must be pulled up via external resistor.

MCA[0]

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3.2.11 McASP

SIGNAL

NAME NO.

MCA[0]_ACLKR/ IPD

MCA[5]_AXR[2] DVDD

MCA[0]_AFSR/ IPD MCA[5]_AXR[3] DVDD

MCA[0]_ACLKX R4 I/O McASP0 Transmit Bit Clock I/O AUD_CLKIN0/ AUD_CLKIN0,

MCA[0]_AXR[7]/ MCA[0], MCA[3], MCA[0]_AHCLKX/ L5 I/O USB1 McASP0 Transmit High-Frequency Master Clock I/O MCA[3]_AHCLKX/ PINCNTL14 USB1_DRVVBUS DSIS: PIN

MCA[0]_AFSX L3 I/O McASP0 Transmit Frame Sync I/O AUD_CLKIN2/ AUD_CLKIN2,

MCA[0]_AXR[9]/ MCA[1], MCA[4], MCA[2]_AHCLKX/ EDMA, TIMER2, MCA[5]_AHCLKX/ H1 I/O GP0 EDMA_EVT2/ PINCNTL16 TIM3_IO/ DSIS: PIN GP0[9] MM: MUX1

MCA[0]_AXR[9]/ MCB_CLKX/ M6 I/O MCB_CLKR

AUD_CLKIN1/ AUD_CLKIN1, MCA[0]_AXR[8]/ MCA[1], MCA[4], MCA[1]_AHCLKX/ EDMA, TIMER2, MCA[4]_AHCLKX/ R5 I/O GP0 EDMA_EVT3/ PINCNTL15 TIM2_IO/ DSIS: PIN GP0[8] MM: MUX1

MCA[0]_AXR[8]/ MCB_FSX/ L1 I/O MCB_FSR

AUD_CLKIN0/ MCA[0]_AXR[7]/ MCA[0]_AHCLKX/ L5 I/O MCA[3]_AHCLKX/ USB1_DRVVBUS

MCA[0]_AXR[7]/ IPD PINCNTL28 MCB_DX DVDD DSIS: PIN

TYPE

K2 I/O PINCNTL19 McASP0 Receive Bit Clock I/O

K1 I/O PINCNTL20 McASP0 Receive Frame Sync I/O

L2 I/O

Table 3-17. McASP0 Terminal Functions

(2)

OTHER

(1)

(3)

IPD –

DVDD PINCNTL17

IPD

DVDD

IPD –

DVDD PINCNTL18

IPD

DVDD

IPD PINCNTL30

DVDD DSIS: PIN

IPD

DVDD

IPD PINCNTL29

DVDD DSIS: PIN

IPD USB1

DVDD PINCNTL14

MUXED DESCRIPTION

McASP0

MCA[5]

DSIS: 0

MCA[5]

DSIS: 0

MCB

MM: MUX0

McASP0 Transmit/Receive Data I/Os

MCB

MM: MUX0

AUD_CLKIN0,

MCA[0], MCA[3],

DSIS: PIN

MM: MUX1

MCB

MM: MUX0

ZHCS057–MARCH 2011

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors After Reset.

(3) Specifies the operating I/O supply voltage for each signal

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Table 3-17. McASP0 Terminal Functions (continued)

SIGNAL

NAME NO.

MCA[0]_AXR[6]/ IPD

MCB_DR DVDD

MCA[0]_AXR[5]/ IPD MCA[1]_AXR[9] DVDD

MCA[0]_AXR[4]/ IPD MCA[1]_AXR[8] DVDD

MCA[0]_AXR[3]/ M5 I/O

MCA[0]_AXR[2]/ IPU

I2C[3]_SDA DVDD

MCA[0]_AXR[1]/ IPU I2C[3]_SCL DVDD

MCA[0]_AXR[0] J2 I/O

TYPE

M4 I/O PINCNTL27

M3 I/O PINCNTL26

R6 I/O PINCNTL25

L4 I/O PINCNTL23

J1 I/O PINCNTL22

OTHER

(1)

(3)

IPD PINCNTL24 McASP0 Transmit/Receive Data I/Os

DVDD DSIS: PIN

IPD PINCNTL21

DVDD DSIS: PIN

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(2)

MUXED DESCRIPTION

MCB

DSIS: PIN

MCA[1]

DSIS: PIN

MCA[1]

DSIS: PIN

I2C[3]

DSIS: PIN

I2C[3]

DSIS: PIN

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SIGNAL

NAME NO.

MCA[1]_ACLKR/ IPD

MCA[1]_AXR[4] DVDD

MCA[1]_AFSR/ IPD MCA[1]_AXR[5] DVDD

MCA[1]_ACLKX U5 I/O McASP1 Transmit Bit Clock I/O AUD_CLKIN1/

MCA[0]_AXR[8]/ MCA[1]_AHCLKX/ MCA[4]_AHCLKX/ R5 I/O McASP1 Transmit High-Frequency Master Clock I/O EDMA_EVT3/ TIM2_IO/ GP0[8]

MCA[1]_AFSX V3 I/O McASP1 Transmit Frame Sync I/O

MCA[3]_AXR[3]/ IPD PINCNTL50 MCA[1]_AXR[9]/ DVDD DSIS: PIN

MCA[0]_AXR[5]/ IPD PINCNTL26 MCA[1]_AXR[9] DVDD DSIS: PIN

MCA[3]_AXR[2]/ MCA[1]_AXR[8]/ F2 I/O GP0[20]

MCA[0]_AXR[4]/ IPD PINCNTL25 MCA[1]_AXR[8] DVDD DSIS: PIN

MCA[2]_AXR[3]/ MCA[2], TIMER3, MCA[1]_AXR[7]/ IPD GP0 TIM3_IO/ DVDD PINCNTL44 GP0[15] DSIS: PIN

MCA[2]_AXR[2]/ MCA[2], TIMER2, MCA[1]_AXR[6]/ IPD GP0 TIM2_IO/ DVDD PINCNTL43 GP0[14] DSIS: PIN

MCA[1]_AFSR/ IPD MCA[1]_AXR[5] DVDD

MCA[1]_ACLKR/ IPD

MCA[1]_AXR[4] DVDD

MCA[1]_AXR[3]/ IPD

MCB_CLKR DVDD

MCA[1]_AXR[2]/ IPD MCB_FSR DVDD

TYPE

M1 I/O PINCNTL33 McASP1 Receive Bit Clock I/O

M2 I/O PINCNTL34 McASP1 Receive Frame Sync I/O

J6 I/O

M3 I/O

R6 I/O

H2 I/O

V5 I/O

M2 I/O PINCNTL34

M1 I/O PINCNTL33

N6 I/O PINCNTL38

R3 I/O PINCNTL37

Table 3-18. McASP1 Terminal Functions

(2)

OTHER

(1)

(3)

IPD –

DVDD PINCNTL31

IPD EDMA, TIMER2,

DVDD GP0

IPD –

DVDD PINCNTL32

IPD PINCNTL49

DVDD DSIS: PIN

MUXED DESCRIPTION

McASP1

MCA[1]

DSIS: 0

MCA[1]

DSIS: 0

AUD_CLKIN1,

MCA[0], MCA[4],

PINCNTL15

DSIS: PIN

MCA[3]

MM: MUX1

MCA[0]

MM: MUX0

MCA[3], GP0

MM: MUX1

MCA[0]

MM: MUX0

McASP1 Transmit/Receive Data I/Os

MCA[1]

DSIS: PIN

MCA[1]

DSIS: PIN

MCB

DSIS: PIN

MCB

DSIS: PIN

ZHCS057–MARCH 2011

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors After Reset.

(3) Specifies the operating I/O supply voltage for each signal

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Table 3-18. McASP1 Terminal Functions (continued)

SIGNAL

NAME NO.

MCA[1]_AXR[1]/ IPU

SD0_DAT[5]/ DVDD

MCA[1]_AXR[0]/ IPU SD0_DAT[4]/ DVDD

TYPE

T6 I/O PINCNTL36

V4 I/O PINCNTL35

OTHER

(1)

(3)

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(2)

MUXED DESCRIPTION

SD0

DSIS: PIN

SD0

DSIS: PIN

McASP1 Transmit/Receive Data I/Os

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Table 3-19. McASP2 Terminal Functions

SIGNAL

NAME NO.

MCA[2]_ACLKX/ IPU

GP0[10] DVDD AUD_CLKIN2/

MCA[0]_AXR[9]/ MCA[2]_AHCLKX/ MCA[5]_AHCLKX/ H1 I/O McASP2 Transmit High-Frequency Master Clock I/O EDMA_EVT2/ TIM3_OUT/ GP0[9]

MCA[2]_AFSX/ IPU GP0[11] DVDD

MCA[2]_AXR[3]/ MCA[1], TIMER3, MCA[1]_AXR[7]/ IPD GP0 TIM3_IO/ DVDD PINCNTL44 GP0[15] DSIS: PIN

MCA[2]_AXR[2]/ MCA[1], TIMER2, MCA[1]_AXR[6]/ IPD GP0 TIM2_IO/ DVDD PINCNTL43 GP0[14] DSIS: PIN

MCA[2]_AXR[1]/ SD0_DAT[7]/ IPU UART5_TXD/ DVDD GP0[13]

MCA[2]_AXR[0]/ SD0_DAT[6]/ IPU UART5_RXD/ DVDD GP0[12]

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and ,Pin Behaviors After Reset.

(3) Specifies the operating I/O supply voltage for each signal

U6 I/O PINCNTL39 McASP2 Transmit Bit Clock I/O

AA5 I/O PINCNTL40 McASP2 Transmit Frame Sync I/O

H2 I/O

V5 I/O

V6 I/O PINCNTL42

N2 I/O PINCNTL41

TYPE

(1)

(2)

OTHER

(3)

IPD EDMA, TIMER3,

DVDD GP0

MUXED DESCRIPTION

McASP2

GP0

DSIS: 0

AUD_CLKIN2,

MCA[0], MCA[5],

PINCNTL16

DSIS: PIN

GP0

DSIS: 0

SD0, UART5, GP0

DSIS: PIN

SD0, UART5, GP0

DSIS: PIN

McASP2 Transmit/Receive Data I/Os

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SIGNAL

NAME NO.

MCA[3]_ACLKX/ IPD

GP0[16] DVDD AUD_CLKIN0/

MCA[0]_AXR[7]/ MCA[0]_AHCLKX/ L5 I/O McASP3 Transmit High-Frequency Master Clock I/O MCA[3]_AHCLKX/U SB1_DRVVBUS

MCA[3]_AFSX/ IPD GP0[17] DVDD

MCA[3]_AXR[3]/ IPD MCA[1]_AXR[9]/ DVDD

MCA[3]_AXR[2]/ MCA[1], GP0 MCA[1]_AXR[8]/ F2 I/O PINCNTL49 GP0[20] DSIS: PIN

MCA[3]_AXR[1]/ TIMER5, GP0 TIM5_IO/ G2 I/O PINCNTL48 GP0[19] DSIS: PIN

MCA[3]_AXR[0]/ TIMER4, GP0 TIM4_IO/ G1 I/O PINCNTL47 GP0[18] DSIS: PIN

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull before after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors After Reset.

(3) Specifies the operating I/O supply voltage for each signal

G6 I/O PINCNTL45 McASP3 Transmit Bit Clock I/O

H4 I/O PINCNTL46 McASP3 Transmit Frame Sync I/O

J6 I/O PINCNTL50

TYPE

Table 3-20. McASP3 Terminal Functions

(2)

OTHER

(1)

(3)

IPD MCA[0], USB1

DVDD PINCNTL14

IPD

DVDD

IPD

DVDD

IPD

DVDD

MUXED DESCRIPTION

McASP3

GP0

DSIS: 0

AUD_CLKIN0,

DSIS: PIN

GP0

DSIS: 0 MCA[1]

DSIS: PIN

McASP3 Transmit/Receive Data I/Os

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ZHCS057–MARCH 2011

Table 3-21. McASP4 Terminal Functions

SIGNAL

NAME NO.

MCA[4]_ACLKX/ IPD

GP0[21] DVDD AUD_CLKIN1/

MCA[0]_AXR[8]/ MCA[1]_AHCLKX/ MCA[4]_AHCLKX/ R5 I/O McASP4 Transmit High-Frequency Master Clock I/O EDMA_EVT3/ TIM2_OUT/ GP0[8]

MCA[4]_AFSX/ IPD GP0[22] DVDD

MCA[5]_AXR[1]/ MCA[5], TIMER7, MCA[4]_AXR[3]/ IPD GP0 TIM7_IO/ DVDD PINCNTL58 GP0[28] DSIS: PIN

MCA[5]_AXR[0]/ MCA[5], GP0 MCA[4]_AXR[2]/ L7 I/O PINCNTL57 GP0[27] DSIS: PIN

MCA[4]_AXR[1]/ TIMER6, GP0 TIM6_IO/ J4 I/O PINCNTL54 GP0[24] DSIS: PIN

MCA[4]_AXR[0]/ IPD GP0[23] DVDD

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors After Reset.

(3) Specifies the operating I/O supply voltage for each signal

K7 I/O PINCNTL51 McASP4 Transmit Bit Clock I/O

H3 I/O PINCNTL52 McASP4 Transmit Frame Sync I/O

L6 I/O

H6 I/O PINCNTL53

TYPE

(1)

(2)

OTHER

(3)

IPD EDMA, TIMER2,

DVDD GP0

IPD

DVDD

IPD

DVDD

MUXED DESCRIPTION

McASP4

GP0

DSIS: 0

AUD_CLKIN1,

MCA[0], MCA[1],

PINCNTL15

DSIS: PIN

GP0

DSIS: 0

GP0

DSIS: PIN

McASP4 Transmit/Receive Data I/Os

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SIGNAL

NAME NO.

MCA[5]_ACLKX/ IPD

GP0[25] DVDD AUD_CLKIN2/

MCA[0]_AXR[9]/ MCA[2]_AHCLKX/ MCA[5]_AHCLKX/ H1 I/O McASP5 Transmit High-Frequency Master Clock I/O EDMA_EVT2/ TIM3_IO/ GP0[9]

MCA[5]_AFSX/ IPD GP0[26] DVDD

MCA[0]_AFSR/ IPD MCA[5]_AXR[3] DVDD

MCA[0]_ACLKR/ IPD

MCA[5]_AXR[2] DVDD MCA[5]_AXR[1]/ MCA[4], TIMER7,

MCA[4]_AXR[3]/ IPD GP0 TIM7_IO/ DVDD PINCNTL58 GP0[28] DSIS: PIN

MCA[5]_AXR[0]/ MCA[4], GP0 MCA[4]_AXR[2]/ L7 I/O PINCNTL57 GP0[27] DSIS: PIN

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors After Reset.

(3) Specifies the operating I/O supply voltage for each signal

J3 I/O PINCNTL55 McASP5 Transmit Bit Clock I/O

H5 I/O PINCNTL56 McASP5 Transmit Frame Sync I/O

K1 I/O PINCNTL20

K2 I/O PINCNTL19

L6 I/O

TYPE

Table 3-22. McASP5 Terminal Functions

(2)

OTHER

(1)

(3)

IPD EDMA, TIMER3,

DVDD GP0

IPD

DVDD

MUXED DESCRIPTION

McASP5

GP0

DSIS: 0

AUD_CLKIN2,

MCA[0], MCA[2],

PINCNTL16

DSIS: PIN

GP0

DSIS: 0 MCA[0]

DSIS: PIN

MCA[0]

DSIS: PIN

McASP5 Transmit/Receive Data I/Os

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3.2.12 McBSP

Table 3-23. McBSP Terminal Functions

SIGNAL

NAME NO.

MCA[0]_AXR[9]/ MCB_CLKX/ M6 I/O

MCB_CLKR

MCA[1]_AXR[3]/ IPD PINCNTL38 MCB_CLKR DVDD DSIS: PIN

MCA[0]_AXR[8]/ MCB_FSX/ L1 I/O

MCB_FSR

MCA[1]_AXR[2]/ IPD PINCNTL37 MCB_FSR DVDD DSIS: PIN

MCA[0]_AXR[6]/ IPD MCB_DR DVDD

MCA[0]_AXR[9]/ MCA[0], MCB MCB_CLKX/ M6 I/O PINCNTL30 McBSP Transmit Clock I/O MCB_CLKR DSIS: PIN

MCA[0]_AXR[8]/ MCA[0], MCB MCB_FSX/ L1 I/O PINCNTL29 McBSP Transmit Frame Sync I/O MCB_FSR DSIS: PIN

MCA[0]_AXR[7]/ IPD MCB_DX DVDD

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors After Reset.

(3) Specifies the operating I/O supply voltage for each signal

N6 I/O

R3 I/O

M4 I/O PINCNTL27 McBSP Receive Data Input

L2 I/O PINCNTL28 McBSP Transmit Data Output

TYPE

(1)

(2)

OTHER

(3)

IPD PINCNTL30

DVDD DSIS: PIN

IPD PINCNTL29

DVDD DSIS: PIN

IPD

DVDD

IPD

DVDD

MUXED DESCRIPTION

MCA[0], MCB

MM: MUX1

MCA[1]

MM: MUX0

MCA[0], MCB

MM: MUX1

MCA[1], MCB

MM: MUX0

MCA[0]

DSIS: PIN

MCA[0]

DSIS: PIN

McBSP

McBSP Receive Clock I/O

McBSP Receive Frame Sync I/O

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3.2.13 PCI Express (PCIe)

Table 3-24. PCI Express (PCIe) Terminal Functions

SIGNAL

NAME NO.

PCIE_TXP0 AD2 O PCIE Transmit Data Lane 0. PCIE_TXN0 AD1 O PCIE_RXP0 AC2 I PCIE Receive Data Lane 0. PCIE_RXN0 AC1 I

SERDES_CLKP AF1 I SERDES_CLK LDO

SERDES_CLKN AF2 I SERDES_CLK LDO

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.

(3) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

VDDA_PCIE_1P8

OTHER

(internal)

–

(2) (3)

DESCRIPTION

When the PCIe SERDES are powered down, these pins should be left unconnected.

PCIE Serdes Reference Clock Inputs and optional SATA Reference Clock Inputs. Shared between PCI Express and Serial ATA. When PCI Express is not used, and these pins are not used as optional SATA Reference Clock Inputs, these pins can be left unconnected.

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3.2.14 Reset, Interrupts, and JTAG Interface

Table 3-25. RESET, Interrupts, and JTAG Terminal Functions

SIGNAL

NAME NO.

RESET J5 I Device Reset input

POR F1 I – Power-On Reset input

RSTOUT_WD_OUT K6 O

NMI H7 I Non-Maskable Interrupt input

GP0[31:0] I/O

GP1[31:0] I/O

GP2[31:0] I/O

GP3[31:0] I/O

TCLK W7 I – JTAG test clock input

RTCK AD4 O – The internal pullup (IPU) is enabled for this pin when the device is

TDI Y7 I – JTAG test data input

TDO AC5 O – JTAG test port data output

TMS AA7 I –

TRST AA4 I – JTAG test port reset input VOUT[0]_R_CR[2]/ VOUT[0], GP2

EMU4/ AD9 I/O PINCNTL196 Emulator pin 4 GP2[26] DSIS: 1

VOUT[0]_G_Y_YC[2]/ VOUT[0], GP2 EMU3/ AH7 I/O PINCNTL188 Emulator pin 3 GP2[24] DSIS: 1

see see see NOTE: All pins are multiplexed with other pin functions. See

Table 3-10 NOTE Table 3-10 Table 3-10, GP0 Terminal Functions table for muxing and internal

see see see NOTE: All pins are multiplexed with other pin functions. See

Table 3-11 NOTE Table 3-11 Table 3-11, GP1 Terminal Functions table for muxing and internal

see see see NOTE: All pins are multiplexed with other pin functions. See

Table 3-12 NOTE Table 3-12 Table 3-12, GP2 Terminal Functions table for muxing and internal

see see see NOTE: All pins are multiplexed with other pin functions. See

Table 3-13 NOTE Table 3-13 Table 3-13, GP3 Terminal Functions table for muxing and internal

TYPE(OTHER

1) ) (3)

IPU –

DVDD PINCNTL260

–

DVDD

DIS –

DVDD PINCNTL262

IPU –

DVDD PINCNTL261

IPU

DVDD

IPU/DIS

DVDD

IPU

DVDD

IPU

DVDD

IPU JTAG test port mode select input. For proper operation, do not

DVDD oppose the IPU on this pin.

IPD

DVDD

IPD

DVDD

IPD

DVDD

(2

MUXED DESCRIPTION

RESET

Reset output (RSTOUT) or watchdog out (WD_OUT) For more detailed information on RSTOUT_WD_OUT pin

behavior, see Section 7.3.14, RSTOUT_WD_OUT Pin.

INTERRUPTS

Interrupt-capable general-purpose I/Os.

pullup/pulldown/disable details. Interrupt-capable general-purpose I/Os.

pullup/pulldown/disable details.

JTAG

JTAG return clock output in reset and the IPU is disabled (DIS) when reset is released.

ZHCS057–MARCH 2011

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS =

De-selected Input State

(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the

Internal Pull during and after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see , Pullup/Pulldown Resistors and , Pin Behaviors at Reset.

(3) Specifies the operating I/O supply voltage for each signal

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Table 3-25. RESET, Interrupts, and JTAG Terminal Functions (continued)

IPD

DVDD

IPU

DVDD

IPU

DVDD

(2

MUXED DESCRIPTION

SIGNAL

NAME NO.

VOUT[0]_B_CB_C[2]/ VOUT[0], GP0 EMU2/ AG7 I/O PINCNTL180 Emulator pin 2 GP2[22] DSIS: 1

EMU1 AE11 I/O – Emulator pin 1

EMU0 AG8 I/O – Emulator pin 0

TYPE(OTHER

1) ) (3)

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TEXAS INSTRUMENTS TMS320DM814x Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

1 高性能片上系统 (SoC)

1.1 特性

1.2 说明

1.3 功能框图

2 Device Overview

2.1 Device Comparison

2.2 Device Characteristics

2.3 Device Compatibility

2.4 ARM® Cortex™-A8 Microprocessor Unit (MPU) Subsystem Overview

2.4.1 ARM Cortex-A8 RISC Processor

2.4.2 Embedded Trace Module (ETM)

2.4.3 ARM Cortex-A8 Interrupt Controller (AINTC)

2.4.4 ARM Cortex-A8 PLL (PLL_ARM)

2.4.5 ARM MPU Interconnect

2.5 C674x™ DSP Overview

2.5.1 C674x DSP CPU Description

2.6 DSP/EDMA Memory Management Unit (MMU)

2.7 Media Controller Overview

2.8 HDVICP2 Overview

2.9 SGX530 Overview

2.10 Spinlock Module Overview

2.11 Mailbox Module Overview

2.12 Memory Map Summary

2.12.1 L3 Memory Map

2.12.2 C674x Memory Map

2.12.3 L4 Memory Map

2.12.3.1 L4 Fast Peripheral Memory Map

2.12.3.2 L4 Slow Peripheral Memory Map

2.12.4 DDR DMM TILER Extended Addressing Map

3 Device Pins

3.1 Pin Maps

3.2 Terminal Functions

3.2.1 Boot Configuration

3.2.2 Camera Interface (I/F)

3.2.3 Controller Area Network (DCAN) Modules (DCAN0, DCAN1)

3.2.4 LPDDR/DDR2/DDR3 Memory Controller

3.2.5 EDMA

3.2.6 EMAC [(R)(G)MII Modes] and MDIO

3.2.7 General-Purpose Input/Outputs (GPIOs)

3.2.8 GPMC

3.2.9 HDMI

3.2.10 I2C

3.2.11 McASP

3.2.12 McBSP

3.2.13 PCI Express (PCIe)

3.2.14 Reset, Interrupts, and JTAG Interface