•Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
•Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock• Embedded Trace Buffer™ (ETB11™) With 4KB
Cycle or Eight 8 x 8-Bit Multiplies (16-BitMemory for ARM9 Debug
Results) per Clock Cycle
– Load-Store Architecture With Non-Aligned
Support
– 64 32-Bit General-Purpose Registers
– Instruction Packing Reduces Code SizeTranscode Operations
– All Instructions Conditional•H.264, MPEG2, VC1, MPEG4 SP/ASP
– Additional C64x+™ Enhancements• 150-MHz Video Port Interface (VPIF)
•Protected Mode Operation– Two 8-Bit SD (BT.656), Single 16-Bit HD
•Exceptions Support for Error Detection
and Program Redirection
•Hardware Support for Modulo Loop
Operation
• C64x+ Instruction Set Features
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
– Additional Instructions to Support Complex
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testingof all parameters.
– 128K-Byte L2 Unified Mapped RAM/Cache
(Flexible RAM/Cache Allocation)
• ARM926EJ-S Core
– Support for 32-Bit and 16-Bit (Thumb®
Mode) Instruction Sets
– DSP Instruction Extensions and Single Cycle
MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ Logic for Real-Time
Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 8K-Byte Data Cache
– 32K-Byte RAM
– 8K-Byte ROM
• Endianness: Little Endian for ARM and DSP
• Dual Programmable High-Definition Video
Image Co-Processor (HDVICP) Engines
– Supports a Range of Encode, Decode, and
(BT.1120), or Single Raw (8-/10-/12-Bit) Video
Capture Channels
– Two 8-Bit SD (BT.656) or Single 16-Bit HD
(BT.1120) Video Display Channels
• Video Data Conversion Engine (VDCE)
– Horizontal and Vertical Downscaling
– Chroma Conversion (4:2:2↔4:2:0)
• Two Transport Stream Interface (TSIF) Modules
(One Parallel/Serial and One Serial Only)
– TSIF for MPEG Transport Stream
– Simultaneous Synchronous or
• External Memory Interfaces (EMIFs)– CIR With Programmable Data Encoding
– Up to 400-MHz 32-Bit DDR2 SDRAM Memory• One Serial Peripheral Interface (SPI) With Two
Controller With 512M-Byte Address SpaceChip-Selects
(1.8-V I/O)
• Applications:
– Video Encode/Decode/Transcode/Transrate
– Digital Media
– Networked Media Encode/Decode
– Video Imaging
– Video Infrastructure
– Video Conferencing
• Community Resources
– TI E2E Community
– TI Embedded Processors Wiki
The TMS320DM6467T (also referenced as DM6467T) leverages TI’s DaVinci™ technology to meet the
networked media encode and decode application processing needs of next-generation embedded devices.
The DM6467T enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, high processing performance, and long battery life through the
maximum flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the DM6467T provides benefits of both DSP and Reduced Instruction Set
Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an
ARM926EJ-S core.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core incorporates:
•A coprocessor 15 (CP15) and protection module
•Data and program Memory Management Units (MMUs) with table look-aside buffers.
•Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual
index virtual tag (VIVT).
The TMS320C64x+™DSPs arethe highest-performancefixed-point DSPgeneration inthe
TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation
high-performance, advanced very-long-instruction-word(VLIW) architecture developed byTexas
Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a
code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of
the C64x+ DSP with added functionality and an expanded instruction set.
SPRS605B–JULY 2009–REVISED JULY 2010
Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and
C64x+ CPU, respectively.
With performance of up to 8000 million instructions per second (MIPS) at a clock rate of 1 GHz, the C64x+
core offers solutions to high-performance DSP programming challenges. The DSP core possesses the
operational flexibility of high-speed controllers and the numerical capability of array processors. The
C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly
independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The
eight functional units include instructions to accelerate the performance in video and imaging applications.
The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 4000 million
MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 8000 MMACS. For more details
on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide
(literature number SPRU732).
The DM6467T also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000 DSP platform devices. The DM6467T core uses a two-level
cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the
Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2)
consists of an 512K-bit memory space that is shared between program and data space. L2 memory can
be configured as mapped memory, cache, or combinations of the two.
The peripheral set includes: a configurable video port; a 10/100/1000 Mb/s Ethernet MAC (EMAC) with a
Management Data Input/Output (MDIO) module; a 4-bit transfer/4-bit receive VLYNQ interface; an
inter-integrated circuit (I2C) Bus interface; a multichannel audio serial port (McASP0) with 4 serializers; a
secondary multichannel audio serial port (McASP1) with a single transmit serializer; 2 64-bit
general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a
configurable 32-bit host port interface (HPI); up to 33-pins of general-purpose input/output (GPIO) with
programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART/IrDA/CIR
interfaces with modem interface signals on UART0; 2 pulse width modulator (PWM) peripherals; an
ATA/ATAPI-6 interface; a 66-MHz peripheral component interface (PCI); and 2 external memory
interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a
higher speed synchronous memory interface for DDR2.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6467T and
the network. The DM6467T EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps)
and 100 Mbps in either half- or full-duplex mode; and 1000Base-TX (1 Gbps) in full-duplex mode with
hardware flow control and quality of service (QOS) support.
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the
MDIO module transparently monitors its link state by reading the PHY status register. Link change events
are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link
status of the device without continuously performing costly MDIO accesses.
The PCI, HPI, I2C, SPI, USB2.0, and VLYNQ ports allow the DM6467T to easily control peripheral
devices and/or communicate with host processors.
The DM6467T also includes a High-Definition Video/Imaging Co-processor (HDVICP) and Video Data
Conversion Engine (VDCE) to offload many video and imaging processing tasks from the DSP core,
making more DSP MIPS available for common video and imaging algorithms. For more information on the
HDVICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TI sales
representative.
www.ti.com
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The DM6467T has a complete set of development tools for both the ARM and DSP. These include C
compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™
debugger interface for visibility into source code execution.
This data manual revision history highlights the technical changes made to the SPRS605A
device-specific data manual to make it an SPRS605B revision.
Scope: Applicable updates to the DM646xT DMSoC device family, specifically relating to the
TMS320DM6467T device (Silicon Revision 3.0) which is now in the production data (PD) stage of
development have been incorporated.
•USB 2.0 is now supported on -1G devices.
•Added, for clarification, the DDR2 Memory Controller speed of 400 MHz
SEEADDITIONS/MODIFICATIONS/DELETIONS
Global
Section 3.1Table 3-1, Characteristics of the DM6467T Processor
Table 3-1 provides an overview of the TMS320DM6467T SoC. The table shows significant features of the
device, including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the
C64x+ DSP, and the package type with pin count.
Table 3-1. Characteristics of the DM6467T Processor
HARDWARE FEATURESDM6467T
DDR2 Memory ControllerDDR2 (Up to 400-MHz, 16/32-bit bus width)
Asynchronous EMIF (EMIFA)
The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.
The C64x+ DSP core is code-compatible with the C6000™ DSP platform and supports features of the
C64xT DSP family.
3.3ARM Subsystem
The ARM Subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In
general, the ARM is responsible for configuration and control of the device; including the DSP Subsystem,
the VPSS Subsystem, and a majority of the peripherals and external memories.
The ARM Subsystem includes the following features:
•8KB Internal ROM (ARM bootloader for non-EMIFA boot options)
•Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
•ARM Interrupt Controller
•PLL Controller
•Power and Sleep Controller (PSC)
•System Module
SPRS605B–JULY 2009–REVISED JULY 2010
3.3.1ARM926EJ-S RISC CPU
The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of
ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all important. The
ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,
providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code
overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a
complete high performance subsystem, including:
•ARM926EJ -S integer core
•CP15 system control coprocessor
•Memory Management Unit (MMU)
•Separate instruction and data Caches
•Write buffer
•Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces
•Separate instruction and data AHB bus interfaces
•Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available
at http://www.arm.com
3.3.2CP15
The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and
data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and other ARM
subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions,
when the ARM in a privileged mode such as supervisor or system mode.
3.3.3MMU
The ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux®,
Windows® CE, Ultron®, ThreadX®, etc. A single set of two level page tables stored in main memory is
used to control the address translation, permission checks and memory region attributes for both data and
instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the
information held in the page tables. The MMU features are:
•Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.
•Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
•Hardware page table walks
•Invalidate entire TLB, using CP15 register 8
•Invalidate TLB entry, selected by MVA, using CP15 register 8
•Lockdown of TLB entries, using CP15 register 10
www.ti.com
3.3.4Caches and Write Buffer
The size of the Instruction Cache is 16KB, Data cache is 8KB. Additionally, the Caches have the following
features:
•Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)
•Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with
two dirty bits in the Dcache
•Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables.
•Critical-word first cache refilling
•Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown, and controlling cache corruption
•Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG
RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
•Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of
the Dcache or Icache, and regions of virtual memory.
The write buffer is used for all writes to a noncachable bufferable region, write-through region and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a
four-address buffer. The Dcache write-back has eight data word entries and a single address entry.
ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt
Vector table. ARM internal ROM enables non-EMIFA boot options, such as NAND and UART. The RAM
and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that provides
for separate instruction and data bus connections. Since the ARM TCM does not allow instructions on the
D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and instructions can be
stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM from extra-ARM
sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA support for direct accesses to
the ARM internal memory from a non-ARM master. Because of the time-critical nature of the TCM link to
the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers.
Instruction and Data accesses are differentiated via accessing different memory map regions, with the
instruction region from 0x0000 through 0x7FFF and data from 0x10000 through 0x17FFF. The instruction
region at 0x0000 and data region at 0x10000 map to the same physical 32-KB TCM RAM. Placing the
instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000,
as required by the ARM architecture. The internal 32-KB RAM is split into two physical banks of 16KB
each, which allows simultaneous instruction and data accesses to be accomplished if the code and data
are in separate banks.
3.3.6Advanced High-Performance Bus (AHB)
The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and
the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the
Config Bus and the external memories bus.
SPRS605B–JULY 2009–REVISED JULY 2010
3.3.7Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an
Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in the DM6467T also includes the
Embedded Trace Buffer (ETB). The ETM consists of two parts:
•Trace Port provides real-time trace capability for the ARM9.
•Triggering facilities provide trigger resources, which include address and data comparators, counter,
and sequencers.
The DM6467T trace port is not pinned out and is instead only connected to the Embedded Trace Buffer.
The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured
trace data.
3.3.8ARM Memory Mapping
The ARM memory map is shown in Section 3.5, Memory Map Summary of this document. The ARM has
access to memories shown in the following sections.
3.3.8.1ARM Internal Memories
The ARM has access to the following ARM internal memories:
•32KB ARM Internal RAM on TCM interface, logically separated into two 16KB pages to allow
simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data
(D-TCM) to the different memory regions.
•8KB ARM Internal ROM
3.3.8.2External Memories
The ARM has access to the following external memories:
DM6467T ARM and DSP integration features are as follows:
•DSP visibility from ARM’s memory map, see Section 3.5, Memory Map Summary, for details
•Boot Modes for DSP - see Device Configurations section, Section 4.4.1, DSP Boot, for details
•ARM control of DSP boot / reset - see Device Configurations section, Section 4.4.2.4, ARM Boot, for
details
•ARM control of DSP isolation and powerdown / powerup - see Section 4, Device Configurations, for
details
•ARM & DSP Interrupts - see Section 7.8.1, ARM CPU Interrupts, and Section 7.8.2, DSP Interrupts, for
details
3.3.9Peripherals
The ARM9 has access to all of the peripherals on the DM6467T device.
www.ti.com
3.3.10 PLL Controller (PLLC)
The ARM Subsystem includes the PLL Controller. The PLL Controller contains a set of registers for
configuring DM6467T’s two internal PLLs (PLL1 and PLL2). The PLL Controller provides the following
configuration and control:
•PLL Bypass Mode
•Set PLL multiplier parameters
•Set PLL divider parameters
•PLL power down
•Oscillator power down
The PLLs are briefly described in this document in the Clocking section. For more detailed information on
the PLLs and PLL Controller register descriptions, see the TMS320DM646x DMSoC ARM Subsystem
Reference Guide (literature number SPRUEP9).
3.3.11 Power and Sleep Controller (PSC)
The ARM Subsystem includes the Power and Sleep Controller (PSC). Through register settings
accessible by the ARM9, the PSC provides two levels of power savings: peripheral/module clock gating
and power domain shut-off. Brief details on the PSC are given in Section 7.3, Power Supplies. For more
detailed information and complete register descriptions for the PSC, see the TMS320DM646x DMSoCARM Subsystem Reference Guide (literature number SPRUEP9).
3.3.12 ARM Interrupt Controller (AINTC)
The ARM Interrupt Controller (AINTC) accepts device interrupts and maps them to either the ARM’s IRQ
(interrupt request) or FIQ (fast interrupt request). The ARM Interrupt Controller is briefly described in this
document in the Interrupts section. For detailed information on the ARM Interrupt Controller, see the
TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number SPRUEP9).
The ARM Subsystem includes the System module. The System module consists of a set of registers for
configuring and controlling a variety of system functions. For details and register descriptions for the
System module, see Section 4, Device Configurations and see the TMS320DM646x DMSoC ARMSubsystem Reference Guide (literature number SPRUEP9).
3.3.14 Power Management
DM6467T has several means of managing power consumption. There is extensive use of clock gating,
which reduces the power used by global device clocks and individual peripheral clocks. Clock
management can be utilized to reduce clock frequencies in order to reduce switching power. For more
details on power management techniques, see Section 4, Device Configurations, Section 7, Peripheraland Electrical Specifications, and see the TMS320DM646x DMSoC ARM Subsystem Reference Guide
(literature number SPRUEP9).
DM6467T gives the programmer full flexibility to use any and all of the previously mentioned capabilities to
customize an optimal power management strategy. Several typical power management scenarios are
described in the following sections.
3.4DSP Subsystem
The DSP Subsystem includes the following features:
•C64x+ DSP CPU
•32KB L1 Program (L1P)/Cache (up to 32KB)
•32KB L1 Data (L1D)/Cache (up to 32KB)
•128KB Unified Mapped RAM/Cache (L2)
•Little endian
SPRS605B–JULY 2009–REVISED JULY 2010
3.4.1C64x+ DSP CPU Description
The C64x+ Central Processing Unit (CPU) consists of eight functional units, two register files, and two
data paths as shown in Figure 3-1. The two general-purpose register files (A and B) each contain
32 32-bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be
data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit
data, 40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are
stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or
32 MSBs in the next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
The C64x+ CPU extends the performance of the C64x core through enhancements and new features.
Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four
16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and
modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The
32 x 32 bit multiply instructions provide the extended precision necessary for audio and other
high-precision algorithms on a variety of signed and unsigned 32-bit data types.
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a
pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Other new features include:
•SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
•Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
•Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
•Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).
•Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.
•Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a
free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
www.ti.com
For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following
documents:
•TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)
•TMS320C64x Technical Overview (literature number SPRU395)
A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
TMS320DM6467T
www.ti.com
SPRS605B–JULY 2009–REVISED JULY 2010
Figure 3-1. TMS320C64x+™ CPU (DSP Core) Data Paths
The DSP memory map is shown in Section 3.5, Memory Map Summary. Configuration of the control
registers for DDR2, EMIFA, and ARM Internal RAM is supported by the ARM. The DSP has access to
memories shown in the following sections.
3.4.2.1ARM Internal Memories
The DSP has access to the 32KB ARM Internal RAM on the ARM D-TCM interface (i.e., data only).
3.4.2.2External Memories
The DSP has access to the following External memories:
•DDR2 Synchronous DRAM
•Asynchronous EMIF / NOR Flash
•ATA
3.4.2.3DSP Internal Memories
The DSP has access to the following DSP memories:
•L2 RAM
•L1P RAM
•L1D RAM
www.ti.com
3.4.2.4C64x+ CPU
The C64x+ core uses a two-level cache-based architecture. The Level 1 Program memory/cache (L1P)
consists of 32 KB memory space that can be configured as mapped memory or direct mapped cache. The
Level 1 Data memory/cache (L1D) consists of 32 KB that can be configured as mapped memory or 2-way
set associated cache. The Level 2 memory/cache (L2) consists of a 128 KB RAM memory space that is
shared between program and data space. L2 memory can be configured as mapped memory, cache, or a
combination of both.
Table 3-2 shows a memory map of the C64x+ CPU cache registers for the device.
Memory Attribute Registers for ARM TCM (corresponds to byte address
0x1000 0000 - 0x10FF FFFF)
Memory Attribute Registers for EMIFA (corresponds to byte address 0x4200
0000 - 0x49FF FFFF)
Memory Attribute Registers for VLYNQ (corresponds to byte address
0x4C00 0000 - 0x4FFF FFFF)
Memory Attribute Registers for DDR2 (corresponds to byte address 0x8000
0000 - 0xBFFF FFFF)
3.4.3Peripherals
The DSP has access/controllability of the following peripherals:
•HDVICP0/1
•EDMA
•McASP0/1
•2 Timers (Timer0 and Timer1) that can each be configured as 1 64-bit or 2 32-bit timers
3.4.4DSP Interrupt Controller
The DSP Interrupt Controller accepts device interrupts and appropriately maps them to the DSP’s
available interrupts. The DSP Interrupt Controller is briefly described in this document in the Interrupts
section. For more detailed on the DSP Interrupt Controller, see the TMS320C64x+ DSP Megamodule
Reference Guide (literature number SPRU871).
Table 3-3 shows the memory map address ranges of the device. Table 3-4 depicts the expanded map of
the Configuration Space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories
associated with its two processors and various subsystems. To help simplify software development a
unified memory map is used where possible to maintain a consistent view of device resources across all
bus masters.
(1) These peripherals have their own DMA engine or master port interface to the DMSoC system bus and do not use the EDMA for data
transfers. The x symbol indicates that the peripheral has a valid connection through the device switch fabric to the memory region
identified in the EDMA access column.
(2) MPPA should be used to disable the hole. For more information on MPPA, see the TMS320C64x+ DSP Megamodule Reference Guide
(SPRU871).
(3) The HPI's, PCI's, and VLYNQ's access to the configuration bus peripherals is limited, see Table 3-4, Configuration Memory Map
0x01C6 60000x01C6 67FF2KATAxxx
0x01C6 68000x01C66FFF2KSPIxxx
0x01C6 70000x01C6 77FF2KGPIOxxx
0x01C6 78000x01C67FFF2KHPIHPIxxx
0x01C6 80000x01C7 FFFF96KReservedReservedxxx
0x01C8 00000x01C80FFF4KEMAC Control Registersxxx
0x01C8 10000x01C81FFF4KEMAC Control Module Registersxxx
0x01C8 20000x01C83FFF8KEMAC Control Module RAMxxx
0x01C8 40000x01C8 47FF2KMDIO Control Registersxxx
0x01C8 48000x01D00FFF498KReservedReservedxxx
0x01D0 10000x01D0 13FF1KMcASP0 RegistersMcASP0 Registersxxx
0x01D0 14000x01D0 17FF1KMcASP0 Data PortMcASP0 Data Portxxx
0x01D0 18000x01D0 1BFF1KMcASP1 RegistersMcASP1 Registersxxx
0x01D0 1C000x01D0 1FFF1KMcASP1 Data PortMcASP1 Data Portxxx
0x01D0 20000x01DF FFFF1016KReservedReserved
0x01E0 00000x01FF FFFF2MReservedReserved
0x0200 00000x021F FFFF2MReservedReserved
0x0220 00000x023F FFFF2MReservedReserved
0x0240 00000x0FFF FFFF220MReservedReserved
ARM/EDMAC64x+
Reserved
MASTER PERIPHERAL
ACCESSIBILITY
HPIPCIVLYNQ
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3.6Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings. For more information on pin
muxing, see Section 4.7, Multiplexed Pin Configurations, of this document.
3.6.1Pin Map (Bottom View)
Figure 3-2 through Figure 3-7 show the bottom view of the package pin assignments in six quadrants (A,
The terminal functions tables (Table 3-5 through Table 3-32) identify the external signal names, the
associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin
has any internal pullup or pulldown resistors, and a functional pin description. For more detailed
information on device configuration, peripheral selection, multiplexed/shared pin, and see the DeviceConfigurations section of this data manual.
ARM Boot Mode configuration bits. These pins are multiplexed between ARM boot mode and the Video Port Interface (VPIF). At reset, the
boot mode inputs BTMODE[3:0] are sampled to determine the ARM boot configuration. See below the boot modes set by these inputs. For
more details on the types of boot modes, see the Section 4.4.1, Boot Modes. After reset, these pins are Video port data outputs 3 through 0
(VP_DOUT[3:0]).
EMIFA CS2 space data bus width. This pin is multiplexed between EMIFA control
and the VPIF. At reset, the input state is sampled to set the EMIFA data bus width
for the CS2 (boot) chip select region.
For an 8-bit-wide EMIFA data bus, CS2BW = 0.
For a 16-bit-wide EMIFA data bus, CS2BW = 1.
After reset, this pin is video port data output 4 (VP_DOUT4).
PCI Enable. This pin is multiplexed between PCI Control and the VPIF. At reset, the
input state is sampled to enable/disable the PCI interface pin multiplexing. Note:
When PCI boot mode is not used, for proper device operation out of reset PCIEN
must be "0".
0 = PCI pin function is disabled; EMIFA or HPI pin function enabled
1 = PCI pin function is enabled
After reset, this pin is video port data output 5 (VP_DOUT5).DSP boot source bit. This pin is multiplexed between DSP boot and the VPIF. At
reset, the input state is sampled to set the DSP boot source DSPBOOT.
VP_DOUT6/IPDThe DSP is booted by the ARM when DSPBOOT = 0.
DSPBOOTDV
AC5I/O/Z
DD33
The DSP boots from EMIFA when DSPBOOT = 1 (and ARM HPI or PCI boot mode
is not selected).
After reset, this pin is video port data output 6 (VP_DOUT6).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
AUX_MXI/McASP1/0). If the internal oscillator is bypassed, this pin is the 1.8-V external
AUX_CLKINoscillator clock input. When the peripheral is not used, AUX_MXI should be left as a
D15S
E14GND
E15S
C15GND
B17IAUX_DV
AUX_MXOA17OAUX_DV
AUX_DV
AUX_DV
AUX_CV
AUX_V
PLL1V
PLL2V
PLL1V
PLL2V
DD18
SS
DD
SS
DD18
DD18
SS
SS
D16S
C16GND
E16S
C17GND
B14
B16
C14
A16
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
(3) For more information, see the Recommended Operating Conditions table
TYPE
S
GND
(1)
OTHER
(2)
DESCRIPTION
OSCILLATOR, PLL
Crystal input DEV_MXI for DEV oscillator (system oscillator, between 27 MHz and
35 MHz, typically 33 MHz or 33.3 MHz). If the internal oscillator is bypassed, this pin
DD18
is the 1.8-V external oscillator clock input.
Crystal output for DEV oscillator. If the internal oscillator is bypassed, DEV_MXO
DD18
should be left as a No Connect.
(3)
(3)
(3)
(3)
1.8-V power supply for DEV oscillator. If the internal oscillator is bypassed,
DEV_DV
should still be connected to the 1.8-V power supply.
DD18
I/O ground for DEV oscillator. If the internal oscillator is bypassed, DEV_DV
should be connected to ground VSS.
1.3-V power supply for DEV oscillator. If the internal oscillator is bypassed,
DEV_CVDDshould be connected to the 1.3-V power supply (CVDD).
Ground for DEV oscillator. Connect to crystal load capacitors. Do not connect to
board ground (VSS). If the internal oscillator is bypassed, DEV_VSSshould still be
connected to ground VSS.
Crystal input for Auxiliary (AUX) oscillator (24/48 MHz for USB, and UART2/1/0 and
DD18
No Connect.
Crystal output for AUX oscillator. If the internal oscillator is bypassed, AUX_MXO
should be left as a No Connect. When the peripheral is not used, AUX_MXO should
DD18
be left as a No Connect.
1.8-V power supply for AUX oscillator. If the internal oscillator is bypassed,
(3)
AUX_DV
peripheral is not used, AUX_DV
supply.
(3)
I/O ground for AUX oscillator. If the internal oscillator is bypassed, AUX_DV
should be connected to ground (VSS). When the peripheral is not used, AUX_DV
should still be connected to the 1.8-V power supply. When the
DD18
should be connected to the 1.8-V power
DD18
should be connected to ground (VSS).
1.3-V power supply for AUX oscillator. If the internal oscillator is bypassed,
(3)
AUX_CVDDshould be connected to the 1.3-V power supply (CVDD). When the
peripheral is not used, AUX_CVDDshould be connected to the 1.3-V power supply
(CVDD).
Ground for AUX oscillator. Connect to crystal load capacitors. Do not connect to
(3)
board ground (VSS). If the internal oscillator is bypassed, AUX_VSSshould still be
connected to ground (VSS). When the peripheral is not used, AUX_VSSshould be
connected to ground (VSS).
GP[3]/IPDThis pin is multiplexed between GPIO and the Audio Clock Selector. For the audio
AUDIO_CLK0DV
GP[2]/IPDThis pin is multiplexed between GPIO and the Audio Clock Selector. For the audio
AUDIO_CLK1DV
GP[4]/IPD
STC_CLKINDV
AB3I/O/Z
AA4I/O/Z
AC3I/O/Zpin is the STC_CLKIN which can be used as an external clock source for the TSIF
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
TYPE
(1)
OTHER
DD33
DD33
DD33
DD33
(2) (3)
DESCRIPTION
CLOCK GENERATOR
Configurable output clock.
clock selector, this pin is the configurable AUDIO_CLK0 output.
clock selector, this pin is the configurable AUDIO_CLK1 output.
This pin is multiplexed between GPIO and the TSIF Clock Selector. For TSIF, this
counters or as TSIF output clock.
Table 3-8. RESET and JTAG Terminal Functions
SIGNAL
NAMENO.
RESETW6IDevice reset.
PORD17IPower-on reset.
TMSD12I
TDOD13O/ZJTAG test-port data output.
TDIE13IJTAG test-port data input.
TCKB12IJTAG test-port clock input.
RTCKC12O/ZJTAG test-port return clock output.
TRSTE12I
EMU1B13I/O/ZEmulation pin 1
EMU0A13I/O/ZEmulation pin 0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
TYPE
(1)
(2) (3)
OTHER
DESCRIPTION
RESET
IPU
DV
DD33
IPU
DV
DD33
JTAG
IPUJTAG test-port mode select input.
DV
DD33
For proper device operation, do not oppose the IPU on this pin.
–
DV
DD33
IPU
DV
DD33
IPU
DV
DD33
–
DV
DD33
IPDJTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1
DV
DD33
JTAG compatibility statement portion of this data manual.
AC5I/O/ZThe DSP is booted by the ARM when DSPBOOT = 0.
PCI_CBE2/
HDS2/C4I/O/Z
EM_CS2
PCI_CBE3/This pin is multiplexed between PCI, HPI, and EMIFA.
HR/WA5I/O/ZIn EMIFA mode, this pin is Chip Select 3 output EM_CS3 (O/Z). Asynchronous
EM_CS3memories (i.e., NOR Flash).
PCI_GNT/
DACK/D10I/O/Z
GP[12]/ EM_CS4
PCI_REQ/This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
DMARQ/B9I/O/ZIn EMIFA mode, this pin is Chip Select 5 output EM_CS5 (O/Z).
GP[11]/ EM_CS5This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_IDSEL/
HDDIR/E8I/O/Z
EM_R/W
PCI_SERR/
HDS1/B2I/O/Z
EM_OE
PCI_STOP/
HCNTL0/D5I/O/Z
EM_WE
PCI_PERR/
HCS/C3I/O/Z
EM_DQM1
PCI_PAR/
HAS/D4I/O/Z
EM_DQM0
PCI_INTA/This pin is multiplexed between PCI and EMIFA.
EM_WAIT2/C11I/O/ZIn EMIFA mode, this pin is wait state extension input 2 EM_WAIT2 (I).
(RDY2/BSY2)When used for EMIFA (NAND), this pin is the ready/busy 2 input (RDY2/BSY2).
PCI_RSV5/IORDY/This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
GP[21]/EM_WAIT3/D11I/O/ZIn EMIFA mode, this pin is wait state extension input 3 EM_WAIT3 (I).
(RDY3/BSY3)When used for EMIFA (NAND), this pin is the ready/busy 3 input (RDY3/BSY3).
PCI_RSV4/DIOW/This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
GP[20]/EM_WAIT4/A11I/O/ZIn EMIFA mode, this pin is wait state extension input 4 EM_WAIT4 (I).
(RDY4/BSY4)When used for EMIFA (NAND), this pin is the ready/busy 4 input (RDY4/BSY4).
TYPE
(1)
(2) (3)
OTHER
DESCRIPTION
EMIFA BOOT CONFIGURATION
EMIFA CS2 space data bus width. This pin is multiplexed between EMIFA control
and the VPIF. At reset, the input state is sampled to set the EMIFA data bus
width for the CS2 (boot) chip select region.
DD33
For an 8-bit-wide EMIFA data bus, CS2BW = 0.
For a 16-bit-wide EMIFA data bus, CS2BW = 1.
After reset, this pin is video port data output 4 (VP_DOUT4).
DSP boot source bit. This pin is multiplexed between DSP boot and the VPIF. At
reset, the input state is sampled to set the DSP boot source DSPBOOT.
DD33
The DSP boots from EMIFA when DSPBOOT=1.
After reset, this pin is video port data output 6 (VP_DOUT6).
EMIFA FUNCTIONAL PINS: ASYNC
This pin is multiplexed between PCI, HPI, and EMIFA.
IPUIn EMIFA mode, this pin is Chip Select 2 output EM_CS2 (O/Z). This is the chip
DV
DD33
select used for EMIFA boot modes. Asynchronous memories (i.e., NOR Flash) or
NAND flash.
IPU
DV
DD33
This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
IPUIn EMIFA mode, this pin is Chip Select 4 output EM_CS4 (O/Z). Asynchronous
DV
DD33
memories (i.e., NOR Flash).
This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
IPU
DV
DD33
IPUThis pin is multiplexed between PCI, ATA, and EMIFA.
DV
DD33
In EMIFA mode, this pin is the read/write output EM_R/W (O/Z).
IPUThis pin is multiplexed between PCI, HPI, and EMIFA.
DV
DD33
In EMIFA mode, this pin is the output enable output EM_OE (O/Z).
IPUThis pin is multiplexed between PCI, HPI, and EMIFA.
DV
DD33
In EMIFA mode, this pin is the write enable output EM_WE (O/Z).
IPU
DV
DV
DD33
IPU
DD33
These pins are multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, these pins are EM_DQM[1:0] and act as byte enables (O/Z).
IPU
DV
DD33
IPU
DV
DD33
IPU
DV
DD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
PCI_AD24/This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
DD8/D8I/O/ZFor EMIFA, this pin is address bit 8 output EM_A[8] (O/Z).
HD24/EM_A[8]This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_AD23/This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
DD7/B5I/O/ZFor EMIFA, this pin is address bit 7 output EM_A[7] (O/Z).
HD23/EM_A[7]This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_AD22/This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
DD6/C7I/O/ZFor EMIFA, this pin is address bit 6 output EM_A[6] (O/Z).
HD22/EM_A[6]This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_AD21/This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
DD5/C5I/O/ZFor EMIFA, this pin is address bit 5 output EM_A[5] (O/Z).
HD21/EM_A[5]This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_AD20/This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
DD4/D7I/O/ZFor EMIFA, this pin is address bit 4 output EM_A[4] (O/Z).
HD20/EM_A[4]This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_AD19/This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
DD3/A4I/O/ZFor EMIFA, this pin is address bit 3 output EM_A[3] (O/Z).
HD19/EM_A[3]This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_AD18/This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
DD2/E7I/O/ZFor EMIFA, this pin is address bit 2 output EM_A[2] (O/Z).
HD18/EM_A[2]This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_AD17/This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
DD1/B4I/O/ZFor EMIFA, this pin is address bit 1 output EM_A[1] (O/Z).
HD17/EM_A[1]This signal is not available when ATA is enabled (i.e., EMIF NAND Flash mode).
PCI_AD16/
DD0/C6I/O/Z
HD16/EM_A[0]
TYPE
(1)
(2) (3)
OTHER
IPD
DV
DD33
IPD
DV
DD33
IPD
DV
DD33
IPD
DV
DD33
IPD
DV
DD33
IPD
DV
DD33
IPD
DV
DD33
IPD
DV
DD33
This pin is multiplexed between PCI, ATA, HPI, and EMIFA.
For EMIFA, this pin is address bit 0 output EM_A[0] (O/Z), which is the least
IPDsignificant bit on a 32-bit word address.
DV
DD33
When connected to a 16-bit asynchronous memory, this pin is the second bit of
the address.
For an 8-bit asynchronous memory, this pin is the third bit of the address.
PCI_IRDY/This pin is multiplexed between PCI, HPI, and EMIFA.
HRDY/A3I/O/ZIn EMIFA mode, this pin is address bit 17 output EM_A[17] (O/Z).
EM_A[17]/(CLE)When used for EMIFA (NAND), this pin is Command Latch Enable output (CLE).
PCI_TRDY/This pin is multiplexed between PCI, HPI, and EMIFA.
HHWIL/E6I/O/ZFor EMIFA, this pin is address bit 16 output EM_A[16] (O/Z).
EM_A[16]/(ALE)When used for EMIFA (NAND), this pin is Address Latch Enable output (ALE).
PCI_INTA/This pin is multiplexed between PCI and EMIFA.
EM_WAIT2/C11I/O/ZIn EMIFA mode, this pin is wait state extension input 2 EM_WAIT2 (I).
(RDY2/BSY2)When used for EMIFA (NAND), this pin is the ready/busy 2 input (RDY2/BSY2).
IORDY/This pin is multiplexed between ATA, GPIO, and EMIFA.
GP[21]/EM_WAIT3/D11I/O/ZIn EMIFA mode, this pin is wait state extension input 3 EM_WAIT3 (I).
(RDY3/BSY3)When used for EMIFA (NAND), this pin is the ready/busy 3 input (RDY3/BSY3).
DIOW/This pin is multiplexed between ATA, GPIO, and EMIFA.
GP[20]/EM_WAIT4/A11I/O/ZIn EMIFA mode, this pin is wait state extension input 4 EM_WAIT4 (I).
(RDY4/BSY4)When used for EMIFA (NAND), this pin is the ready/busy 4 input (RDY4/BSY4).
DIOR/This pin is multiplexed between ATA, GPIO, and EMIFA.
GP[19]/EM_WAIT5/E10I/O/ZFor EMIFA, this pin is wait state extension input 5 EM_WAIT5 (I).
(RDY5/BSY5)When used for EMIFA (NAND), this pin is the ready/busy 5 input (RDY5/BSY5).
PCI_SERR/
HDS1/B2I/O/Z
EM_OE
TYPE
(1)
(2) (3)
OTHER
DD33
DD33
DD33
DD33
DD33
DD33
DD33
DESCRIPTION
These pins are multiplexed between PCI, HPI, and EMIFA.
DD33
For EMIFA mode, these pins are the 16-bit bidirectional data bus (EM_D[15:0])
[I/O/Z].
When EMIFA is configured for an 8-bit asynchronous memory, only EM_D[7:0]
DD33
DD33
DD33
DD33
DD33
DD33
DD33
DD33
pins are used.
EMIFA FUNCTIONAL PINS: NAND
IPU
DV
DD33
IPU
DV
DD33
IPU
DV
DD33
IPU
DV
DD33
IPU
DV
DD33
IPU
DV
DD33
IPUThis pin is multiplexed between PCI, HPI, and EMIFA.
DV
DD33
In EMIFA mode, this pin is the output enable output EM_OE (O/Z).
PCI_CBE3/This pin is multiplexed between PCI, HPI, and EMIFA.
HR/WA5I/O/ZIn EMIFA mode, this pin is Chip Select 3 output EM_CS3 (O/Z). Asynchronous
EM_CS3memories (i.e., NOR Flash).
PCI_AD15/IPD
HD15/EM_D15DV
PCI_AD14/IPD
HD14 /EM_D14DV
PCI_AD13/IPD
HD13/EM_D13DV
PCI_AD12/IPD
HD12/EM_D12DV
PCI_AD11/IPD
HD11/EM_D11DV
PCI_AD10/IPD
HD10/EM_D10DV
PCI_AD9/IPD
HD9/EM_D9DV
PCI_AD8/IPD
HD8/EM_D8DV
PCI_AD7/IPD
HD7/EM_D7DV
PCI_AD6/IPD
HD6/EM_D6DV
PCI_AD5/IPD
HD5/EM_D5DV
PCI_AD4/IPD
HD4/EM_D4DV
PCI_AD3/IPD
HD3/EM_D3DV
PCI_AD2/IPD
HD2/EM_D2DV
PCI_AD1/IPD
HD1/EM_D1DV
PCI_AD0/IPD
HD0/EM_D0DV
E5I/O/Z
C1I/O/Z
E4I/O/Z
D3I/O/Z
E3I/O/Z
D2I/O/Z
F5I/O/Z
D1I/O/Z
E2I/O/Z
F3I/O/Z
E1I/O/Z
G5I/O/Z
F2I/O/Z
G4I/O/Z
F1I/O/Z
G3I/O/Z
TYPE
(1)
(2) (3)
OTHER
DESCRIPTION
IPUThis pin is multiplexed between PCI, HPI, and EMIFA.
DV
DD33
In EMIFA mode, this pin is the write enable output EM_WE (O/Z).
This pin is multiplexed between PCI, HPI, and EMIFA.
IPUIn EMIFA mode, this pin is Chip Select 2 output EM_CS2 (O/Z). This is the chip
DV
DD33
select used for EMIFA boot modes. Asynchronous memories (i.e., NOR Flash) or
NAND flash.
IPU
DV
DD33
DD33
DD33
DD33
DD33
DD33
DD33
DD33
These pins are multiplexed between PCI, HPI, and EMIFA.
DD33
For EMIFA mode, these pins are the 16-bit bidirectional data bus (EM_D[15:0])
[I/O/Z].
When EMIFA is configured for an 8-bit asynchronous memory, only EM_D[7:0]
DDR2 Clock
DDR2 Differential clock
DDR2 Clock Enable
DDR2 Active low chip select
DDR2 Active low Write enable
DDR2 Row Access Signal output
DDR2 Column Access Signal output
DDR2 Data mask outputs
DDR_DQM[3]: For upper byte data bus DDR_D[31:24]
DDR_DQM[2]: For DDR_D[23:16]
DDR_DQM[1]: For DDR_D[15:8]
DDR_DQM[0]: For lower byte DDR_D[7:0]
Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to
the DDR2 memory when writing and inputs when reading. They are used to
synchronize the data transfers.
DDR_DQS[3] : For upper byte DDR_D[31:24]
DDR_DQS[2]: For DDR_D[23:16]
DDR_DQS[1]: For DDR_D[15:8]
DDR_DQS[0]: For bottom byte DDR_D[7:0]
Complimentary data strobe input/outputs for each byte of the 32-bit data bus. They
are outputs to the DDR2 memory when writing and inputs when reading. They are
used to synchronize the data transfers.
DDR_DQS[3] : For upper byte DDR_D[31:24]
DDR_DQS[2]: For DDR_D[23:16]
DDR_DQS[1]: For DDR_D[15:8]
DDR_DQS[0]: For bottom byte DDR_D[7:0]
DDR2 on-die termination control
Bank address outputs (BA[2:0]).
DDR2 address bus
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(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
(3) For more information, see the Recommended Operating Conditions table
(4) For more information, see the Recommended Operating Conditions table
(1)
TYPE
OTHER
I/O/ZDV
DDR2
DDR2
DDR2
DDR2
DDR2
(4)
(4)
(2) (3)
DDR2 data bus can be configured as 32 bits wide or 16 bits wide.
DDR2 strobe gate signal for lower-half data bus
DDR2 strobe gate signal return for lower-half data bus
DDR2 strobe gate signal for upper-half data bus
DDR2 strobe gate signal return for upper-half data bus
(4)
Reference voltage input for the SSTL_18 IO buffers.
Impedance control for DDR2 outputs. This must be connected via a 50-Ω (±5%
tolerance) resistor to VSS.
Impedance control for DDR2 outputs. This must be connected via a 50-Ω (±5%
tolerance) resistor to DV
Notes: When PCI boot mode is not used, for proper device operation out of reset PCIEN must be "0".
The PCI pin functions are enabled when PCIEN = 1 (PCI mode). This can be done via an external PU on the PCIEN pin (AC6) or by setting
the PCIEN bit (bit 2) in the PINMUX0 register to a "1" after device reset. For more details on the PCIEN pin, see Table 3-5, Boot TerminalFunctions.
In PCI mode (PCIEN = 1), the internal pullups/pulldowns (IPUs/IPDs) are disabled on all PCI pins and it is recommended to have external
pullup resistors on the PCI_RSV[5:0] pins. For more detailed information on external pullup/pulldown resistors, see Section 4.8.1,
Pullup/Pulldown Resistors.
Also in PCI mode (PCIEN = 1), the internal pulldowns (IPDs) are disabled on the GP[5:7] pins. It is recommended to have external pullup
resistors on the GP[5] pin when PCIEN = 1 and on GP[6:7] pins when PCIEN = 1 and VADJEN = 0.
PCI_CLK/GP[10]A10I/O/Z
PCI_RST /DA2/[IPD]This pin is multiplexed between the PCI, ATA, GPIO, and EMIFA.
GP[13]/EM_A[22]DV
PCI_IDSEL/[IPU]
HDDIR/EM_R/WDV
PCI_DEVSEL /[IPU]This pin is multiplexed between PCI, HPI, and EMIFA.
HCNTL1/EM_BA[1]DV
PCI_FRAME /[IPU]This pin is multiplexed between PCI, HPI, and EMIFA.
HINT/EM_BA[0]DV
PCI_IRDY /HRDY/[IPU]This pin is multiplexed between PCI, HPI, and EMIFA.
EM_A[17]/(CLE)DV
PCI_ TRDY /HHWIL/[IPU]This pin is multiplexed between PCI, HPI, and EMIFA.
EM_A[16]/(ALE)DV
PCI_STOP /[IPU]This pin is multiplexed between PCI, HPI, and EMIFA.
HCNTL0/EM_WEDV
PCI_SERR /[IPU]This pin is multiplexed between PCI, HPI, and EMIFA.
HDS1/EM_OEDV
PCI_PERR /[IPU]This pin is multiplexed between PCI, HPI, and EMIFA.
HCS/EM_DQM1DV
PCI_PAR/[IPU]This pin is multiplexed between PCI, HPI, and EMIFA.
HAS/EM_DQM0DV
C10I/O/Z
E8I/O/ZIn PCI mode, this pin is the PCI initialization device select, PCI_IDSEL
B3I/O/Z
D6I/O/Z
A3I/O/Z
E6I/O/Z
D5I/O/Z
B2I/O/Z
C3I/O/Z
D4I/O/Z
PCI_INTA /
EM_WAIT2/C11I/O/Z
(RDY2/BSY2)
PCI_REQ /
DMARQ/B9I/O/Z
GP[11]/EM_CS5
PCI_GNT /
DMACK/D10I/O/Z
GP[12]/EM_CS4
PCI_CBE3 /[IPU]
HR/W/EM_CS3DV
PCI_CBE2 /[IPU]
HDS2/EM_CS2DV
A5I/O/ZIn PCI mode, this pin is the PCI command/byte enable 3, PCI_CBE3
C4I/O/ZIn PCI mode, this pin is the PCI command/byte enable 2, PCI_CBE2
PCI_CBE1 /This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
ATA_CS1/C2I/O/ZIn PCI mode, this pin is the PCI command/byte enable 1 PCI_CBE1
GP[32]/EM_A[19](I/O/Z).
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
PCI
[IPU]This pin is multiplexed between PCI and GPIO.
DV
DD33
DD33
In PCI mode, this pin is the PCI clock input PCI_CLK (I).
In PCI mode, this pin is PCI reset PCI_RST (I).
This pin is multiplexed between PCI, ATA, and EMIFA.
DD33
DD33
DD33
DD33
DD33
DD33
DD33
DD33
DD33
(I).
In PCI mode, this pin is the PCI device select, PCI_DEVSEL (I/O/Z).
In PCI mode, this pin is the PCI cycle frame, PCI_FRAME (I/O/Z).
In PCI mode, this pin is the PCI initiator ready, PCI_IRDY (I/O/Z).
In PCI mode, this pin is the PCI target ready, PCI_ TRDY (I/O/Z).
In PCI mode, this pin is the PCI stop, PCI_STOP (I/O/Z).
In PCI mode, this pin is the PCI system error, PCI_SERR (I/O/Z).
In PCI mode, this pin is the PCI parity error, PCI_PERR (I/O/Z).
In PCI mode, this pin is the PCI parity, PCI_PAR (I/O/Z).
[IPU]This pin is multiplexed between the PCI and EMIFA.
DV
DD33
In PCI mode, this pin is the PCI interrupt A, PCI_INTA (O/Z).
[IPU]This pin is multiplexed between the PCI, ATA, GPIO, and EMIFA.
DV
DD33
In PCI mode, this pin is the PCI bus request, PCI_REQ (O/Z).
[IPU]This pin is multiplexed between the PCI, ATA, GPIO, and EMIFA.
DV
DD33
In PCI mode, this pin is PCI bus grant, PCI_GNT (I).
This pin is multiplexed between PCI, HPI, and EMIFA.
DD33
(I/O/Z).
This pin is multiplexed between PCI, HPI, and EMIFA.
DD33
(I/O/Z).
[IPU]
DV
DD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
TYPE
O/Z
(1)
OTHER
(2) (3)
DESCRIPTION
EMAC [G]MII
IPD
DV
DD33
-
DV
DD33
IPD
DV
DD33
-[G]MII transmit data [7:0]. For 1000 GMII operation, MTXD[7:0] are used. For 10/100
DV
DD33
MII operation, only MTXD[3:0] are used.
-
DV
DD33
IPD
DV
DD33
IPD
DV
DD33
IPU
DV
DD33
I
IPU[G]MII receive data [7:0]. For 1000 GMII operation, MRXD[7:0] are used. For 10/100
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
HPI is enabled by the PINMUX0.HPIEN =1 (and PCIEN = 0 and ATAEN dependent for 16-/32-bit modes). For more detailed information on
the HPI pin muxing, see Section 4.7.3.1, PCI, HPI, EMIFA, and ATA Pin Muxing.
PCI_PERR/
HCS /C3I/O/Z
EM_DQM1
PCI_STOP/
HCNTL0/D5I/O/Z
EM_WE
PCI_DEVSEL/
HCNTL1/B3I/O/Z
EM_BA[1]
PCI_PAR/ HAS /IPUIn HPI mode, this pin is the HPI address strobe, HAS (I).
EM_DQM0DV
PCI_SERR/IPUThis pin is multiplexed between PCI, HPI, and EMIFA.
HDS1 /EM_OEDV
PCI_CBE2/IPUThis pin is multiplexed between PCI, HPI, and EMIFA.
HDS2 /EM_CS2DV
PCI_CBE3/IPUThis pin is multiplexed between PCI, HPI, and EMIFA.
HR/W /EM_CS3DV
D4I/O/Z
B2I/O/Z
C4I/O/Z
A5I/O/Z
PCI_TRDY/
HHWIL/E6I/O/Z
EM_A[16]/(ALE)
PCI_AD31/
DD15/A8
HD31/EM_A[15]
PCI_AD30/
DD14/C9
HD30/EM_A[14]
PCI_AD29/
DD13/B8
HD29/EM_A[13]
PCI_AD28/
DD12/D9
HD28/EM_A[12]
PCI_AD27/
DD11/A6
HD27/EM_A[11]
PCI_AD26/
DD10/C8
HD26/ EM_A[10]
PCI_AD25/
DD9/B6
HD25/EM_A[9]
PCI_AD24/
DD8/D8
HD24/EM_A[8]
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
Host-Port Interface (HPI)
IPUThis pin is multiplexed between PCI, HPI, and EMIFA.
DV
DD33
In HPI mode, this pin is the HPI active-low chip select input, HCS (I).
IPUThis pin is multiplexed between PCI, HPI, and EMIFA.
DV
DD33
In HPI mode, this pin is the HPI control input 0, HCNTL0 (I)
IPUThis pin is multiplexed between PCI, HPI, and EMIFA.
DV
DD33
In HPI mode, this pin is the HPI control input 1, HCNTL1 (I).
This pin is multiplexed between PCI, HPI, and EMIFA.
DD33
DD33
DD33
DD33
NOTE: The DM6467T HPI does not support the HAS feature. For proper HPI
operation if the pin is routed out, it must be pulled up via an external resistor.
In HPI mode, this pin is the HPI data strobe input 1, HDS1 (I).
In HPI mode, this pin is the HPI data strobe input 2, HDS2 (I).
In HPI mode, this pin is the HPI host read/write select input, HR/W (I).
IPUThis pin is multiplexed between PCI, HPI, and EMIFA.
DV
DD33
I/O/ZIn HPI-32 mode, these pins are the HPI upper data bus, HD[31:16] (I/O/Z).
DV
IPD
DD33
In HPI mode, this pin is the HPI half-word identification input control, HHWIL (I).
These pins are multiplexed between PCI, ATA, HPI, and EMIFA.
In HPI-16 mode, the HD[31:16] pins are not used by the HPI .
(1) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(2) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(3) Specifies the operating I/O supply voltage for each signal
USB_DPA19A I/OUSB bidirectional Data Differential signal pair [positive/negative].
USB_DNA20A I/O
USB_R1D18A I/O
USB_DRVVBUS/IPDWhen this pin is used as USB_DRVVBUS (PINMUX0.VBUSDIS = 0), and the USB
GP[22]DV
USB_V
SSREF
USB_V
DDA3P3
USB_V
DD1P8
USB_V
DDA1P2LDO
B18I/O/Z
C18GND
F18S
E18S
E17S
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
(4) For more information, see the Recommended Operating Conditions table
OTHER
(4)
(4)
(4)
(4)
(4)
(4)
DD33
(2) (3)
DESCRIPTION
USB 2.0
When the USB peripheral is not used, the USB_DP signal should be pulled up
(high) and the USB_DN signal should be pulled down (low) via a 10-kΩ resistor.
USB current reference output. When the USB peripheral is used, this pin must be
connected via a 10-kΩ ±1% resistor to USB_V
When the USB peripheral is not used, this pin must be connected via a 10-kΩ
resistor to USB_V
SSREF
.
SSREF
.
This pin is multiplexed between USB and GPIO.
Controller is operating as a Host (USBCTL.USBID = 0 and Session is in progress),
this signal is used by the USB Controler to enable the external VBUS charge pump.
Ground for reference current. This pin must be connected via a 10-kΩ ±1% resistor
to USB_R1.
When the USB peripheral is not used, the USB_V
to VSS.
signal should be connected
SSREF
Analog 3.3 V power supply for USB PHY.
When the USB peripheral is not used, the USB_V
connected to DV
DD33
.
DDA3P3
signal should be
1.8-V I/O power supply for USB PHY.
When the USB peripheral is not used, the USB_V
to 1.8-V power supply.
signal should be connected
DD1P8
Core power supply LDO output for USB PHY. This pin must be connected via a
1-mF capacitor to VSS.
When the USB peripheral is not used, the USB_V
connected via a 1-mF capacitor to VSS.
This pin is multiplexed between the VPIF and TSIF0.
DD33
input, VP_DIN15_VSYNC (I).
This pin is multiplexed between the VPIF and TSIF0.
DD33
input, VP_DIN14_HSYNC (I).
This pin is multiplexed between the VPIF and TSIF0.
DD33
DD33
input, VP_DIN13_FIELD (I).
When used for the VPIF, these pins are capture data bits, VP_DIN[12:8] (I).
IPDThese pins are multiplexed between the VPIF, TSIF0, and TSIF1.
DV
DD33
When used for the VPIF, these pins are capture data bits, VP_DIN[7:4] (I).
IPDThese pins are multiplexed between the VPIF and TSIF0.
DV
DD33
When used for the VPIF, these pins are capture data bits, VP_DIN[3:0] (I).
VIDEO-PORT INTERFACE (VPIF) – DISPLAY
IPD
DV
DD33
This pin is multiplexed between the VPIF and TSIF1.
DD33
(I).
-
DV
DD33
DESCRIPTION
www.ti.com
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
Table 3-17. Transport Stream Interface 0 (TSIF0) Terminal Functions
SIGNAL
NAMENO.
TS0_CLKINAC19ITSIF0 receive clock input (I).
UCTS1/USD1/
TS0_EN_WAITO/Y17I/O/Z
GP[26]
URTS1/UIRTX1/IPUWhen TSIF0 input is enabled (PINMUX0.PTSIMUX = 1x), in asynchronous
TS0_WAITO/GP[25]DV
URTS2/UIRTX2/IPU
TS0_PSTIN/GP[41]DV
VP_DIN15_VP_VSYNC/
TS0_DIN7
VP_DIN14_VP_HSYNC/
TS0_DIN6
VP_DIN13_FIELD/
TS0_DIN5
VP_DIN12/
TS0_DIN4
VP_DIN11/
TS0_DIN3
VP_DIN10/
TS0_DIN2
VP_DIN9/
TS0_DIN1
VP_DIN8/
TS0_DIN0
AA18I/O/Z
AC20I/O/ZWhen TSIF0 input is enabled (PINMUX0.PTSIMUX = 1x), this pin is the
AC18
AA17
AB17
AC17
Y16
AA16
AB16
AC16
TS0_CLKINAC19ITSIF0 receive clock input (I).
UCTS1/USD1/
TS0_EN_WAITO/Y17I/O/Z
GP[26]
URTS2/UIRTX2/IPUWhen TSIF0 input is enabled (PINMUX0.PTSIMUX = 1x), in
TS0_PSTIN/GP[41]DV
URXD1/IPDWhen TSIF0 serial input mux mode is enabled (PINMUX0.PTSIMUX = 11), in
TS0_DIN7/GP[23]DV
AC20I/O/Z
Y18I/O/Z
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
TSIF0 PARALLEL INPUT (PINMUX0.PTSIMUX = 10)
IPD
DV
DD33
This pin is multiplexed between UART1, TSIF0, and GPIO.
IPUWhen TSIF0 input is enabled (PINMUX0.PTSIMUX = 1x), in synchronous
DV
DD33
mode, this pin is the data enable indicator (I) or in asynchronous mode, this
pin is the wait output (O/Z), TS0_EN_WAITO.
This pin is multiplexed between UART1, TSIF0, and GPIO.
DD33
mode, this pin is the wait output, TS0_WAITO (O/Z).
This TSIF pin function is not used in synchronous mode.
This pin is multiplexed between UART2, TSIF0, and GPIO.
Table 3-18. Transport Stream Interface 1 (TSIF1) Terminal Functions
SIGNAL
NAMENO.
TS1_CLKINAC11ITSIF1 receive clock input (I).
URXD0/IPD
TS1_DINDV
URTS0/UIRTX0/IPUWhen TSIF1 input on UART0 muxing is enabled (PINMUX0.TSSIMUX = 01), in
TS1_EN_WAITODV
UTXD0/URCTX0/IPD
TS1_PSTINDV
AB13IWhen TSIF1 input on UART0 muxing is enabled (PINMUX0.TSSIMUX = 01), this
AA13I/O/Z
Y13I/O/ZWhen TSIF1 input on UART0 muxing is enabled (PINUMX0.TSSIMUX = 01), this
TS1_CLKINAC11ITSIF1 receive clock input (I).
VP_DOUT15/IPD
TS1_DINDV
VP_DOUT13/IPDWhen TSIF1 input on VPIF DOUT muxing is enabled (PINMUX0.TSSIMUX = 10), in
TS1_EN_WAITODV
VP_DOUT14/IPDWhen TSIF1 input on VPIF DOUT muxing is enabled (PINMUX0.TSSIMUX = 10), in
TS1_PSTINDV
AB8I/O/ZWhen TSIF1 input on VPIF DOUT muxing is enabled (PINMUX0.TSSIMUX = 10),
Y9I/O/Z
AC7I/O/Z
TS1_CLKINAC11ITSIF1 receive clock input (I).
VP_DIN7/This pin is multiplexed between VPIF, TSIF0, and TSIF1.
TS0_DOUT7/Y14I/O/ZWhen TSIF1 input on VPIF DIN muxing is enabled (PINMUX0.TSSIMUX = 11), in
TS1_DINsynchronous/asynchronous modes, this pin is the serial data input, TS1_DIN (I).
VP_DIN5/
TS0_DOUT5/AB14I/O/Z
TS1_EN_WAITO
VP_DIN6/
TS0_DOUT6/AA14I/O/Z
TS1_PSTIN
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
TSIF1 INPUT – UART0 MUXING (PINMUX0.TSSIMUX = 01)
IPD
DV
DD33
This pin is multiplexed between UART0 and TSIF1.
DD33
pin is the serial data input, TS1_DIN (I).
This pin is multiplexed between UART0 and TSIF1.
DD33
synchronous mode, this pin is the data enable indicator (I) or in asynchronous
mode, this pin is the wait output, TS1_EN_WAITO (O/Z).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
TYPE
(1)
OTHER
(2)
DESCRIPTION
I2C
-I2C clock output SCL. For proper device operation, this pin must be pulled up via
DV
DD33
external resistor.
-I2C bidirectional data signal SDA. For proper device operation, this pin must be
DV
DD33
pulled up via external resistor.
Table 3-20. SPI Terminal Functions
SIGNAL
NAMENO.
SPI_CLKV1I/O/ZSPI clock
SPI_ENT5I/O/ZSPI device enable
SPI_CS0T4I/O/ZSPI chip select 0
SPI_CS1U3I/O/ZSPI chip select 1
SPI_SOMIR5I/O/ZSPI slave out, master in data pin
SPI_SIMOP5I/O/ZSPI slave in, master out data pin
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
AB20I/O/ZWhen CRGEN1 is enabled (PINMUX0.CRGMUX = 001), this pin is CRGEN1 input
CRG0_VCXI
UTXD2/ URCTX2/
CRG1_PO/IPD
GP[40]/DV
AA19I/O/ZWhen CRGEN1 is enabled (PINMUX0.CRGMUX = 001), this pin is CRGEN1
CRG0_PO
UCTS2/ USD2/
CRG0_VCXI/IPU
GP[42]/DV
AC21I/O/ZWhen CRGEN0 on UART2/PWM muxing is enabled (PINMUX0.CRGMUX = 10x),
TS1_PSTO
PWM0/This pin is multiplexed between PWM0, CRGEN0, and TSIF1.
CRG0_PO/W17O/ZWhen CRGEN0 on UART2/PWM muxing is enabled (PINMUX0.CRGMUX = 10x),
TS1_ENAOthis pin is CRGEN0 pulse width modulation output, CRG0_PO (O/Z).
URXD2/
CRG1_VCXI/IPD
GP[39]/DV
AB20I/O/ZWhen CRGEN1 is enabled (PINMUX0.CRGMUX = x01), this pin is CRGEN1 input
CRG0_VCXI
UTXD2/ URCTX2/
CRG1_PO/IPD
GP[40]/DV
AA19I/O/ZWhen CRGEN1 is enabled (PINMUX0.CRGMUX = x01), this pin is CRGEN1
CRG0_PO
UCTS2/ USD2/
CRG0_VCXI/IPU
GP[42]/DV
AC21I/O/ZWhen CRGEN0 on UART2/PWM muxing is enabled (PINMUX0.CRGMUX = 10x),
TS1_PSTO
PWM0/This pin is multiplexed between PWM0, CRGEN0, and TSIF1.
CRG0_PO/W17O/ZWhen CRGEN0 on UART2/PWM muxing is enabled (PINMUX0.CRGMUX = 10x),
TS1_ENAOthis pin is CRGEN0 pulse width modulation output, CRG0_PO (O/Z).
URXD2/
CRG1_VCXI/IPD
GP[39]/DV
AB20I/O/ZWhen CRGEN0 on UART2 muxing is enabled (PINMUX0.CRGMUX = 110), this
CRG0_VCXI
UTXD2/ URCTX2/
CRG1_PO/IPD
GP[40]/DV
AA19I/O/ZWhen CRGEN0 on UART2 muxing is enabled (PINMUX0.CRGMUX = 110), this
CRG0_PO
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
TYPE
(1)
OTHER
(2) (3)
DESCRIPTION
CRGEN1 ONLY MODE (PINMUX0.CRGMUX = 001)
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
DD33
clock from external VCXO, CRG1_VCXI (I).
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
DD33
pulse width modulation output, CRG1_PO (O/Z).
CRGEN0 ONLY (UART2/PWM0 MUX) MODE (PINMUX0.CRGMUX = 100)
This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.
DD33
this pin is CRGEN0 input clock from external VCXO, CRG0_VCXI (I).
–
DV
DD33
CRGEN0 AND CRGEN1 MODE (PINMUX0.CRGMUX = 101)
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
DD33
clock from external VCXO, CRG1_VCXI (I).
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
DD33
pulse width modulation output, CRG1_PO (O/Z).
This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.
DD33
this pin is CRGEN0 input clock from external VCXO, CRG0_VCXI (I).
–
DV
DD33
CRGEN0 ONLY (UART2 MUX) MODE (PINMUX0.CRGMUX = 110)
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
DD33
pin is CRGEN0 input clock from external VCXO, CRG0_VCXI (I).
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
DD33
pin is CRGEN0 pulse width modulation output, CRG0_PO (O/Z).
Actual UART0 pin functions are determined by the PINMUX0 and PINMUX1 register bit settings. For more details, see
Section 4.7.3, Pin Multiplexing.
URXD0/IPDWhen UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
TS1_DINDV
AB13I
UTXD0/
URCTX0/Y13I/O/Z
TS1_PSTIN
URTS0 /
UIRTX0/AA13I/O/Z
TS1_EN_WAITO
UCTS0 / USD0AC12I/O/Z
UDTR0 /
TS0_ENAO/Y12I/O/Z
GP[36]
UDSR0 /
TS0_PSTO/AB11I/O/Z
GP[37]
UDCD0 /
TS0_WAITIN/AA11I/O/Z
GP[38]
URIN0 /GP[8]/IPD
TS1_WAITINDV
URXD0/IPDWhen UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
TS1_DINDV
Y11I/O/Z(PINMUX1.UART0CTL = 00) and TSIF1 output on UART/PWM muxing is not
AB13I
UTXD0/
URCTX0/Y13I/O/Z
TS1_PSTIN
URTS0 /
UIRTX0/AA13I/O/Z
TS1_EN_WAITO
UCTS0 /IPU
USD0DV
AC12I/O/Zand TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
(1) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(2) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(3) Specifies the operating I/O supply voltage for each signal
TYPE
(1)
OTHER
(2) (3)
UART0 WITH MODEM CONTROL (PINMUX1.UART0CTL = 00)
This pin is multiplexed between UART0 and TSIF1.
DD33
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 receive data, URXD0 (I).
This pin is multiplexed between UART0 and TSIF1.
IPDWhen UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
DV
DD33
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 transmit data, UTXD0 (O/Z).
This pin is multiplexed between UART0 and TSIF1.
IPUWhen UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
DV
DD33
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is the UART0 request-to-send signal, URTS0 (O/Z).
This pin is multiplexed between UART0 and TSIF1.
IPUWhen UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
DV
DD33
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is the UART0 clear-to-send signal, UCTS0 (I).
This pin is multiplexed between UART0, TSIF0, and GPIO.
IPUWhen UART0 UART with modem functional muxing is selected
DV
DD33
(PINMUX1.UART0CTL = 00) and TSIF0 output muxing is not enabled
(PINMUX0.PTSOMUX ≠ 1x), this pin is UART0 data-terminal-ready, UDTR0 (O/Z).
This pin is multiplexed between UART0, TSIF0, and GPIO.
IPUWhen UART0 UART with modem functional muxing is selected
DV
DD33
(PINMUX1.UART0CTL = 00) and TSIF0 output muxing is not enabled
(PINMUX0.PTSOMUX ≠ 1x), this pin is UART0 data-set-ready, UDSR0 (I).
This pin is multiplexed between UART0, TSIF0, and GPIO.
IPUWhen UART0 UART with modem functional muxing is selected
DV
DD33
(PINMUX1.UART0CTL = 00) and TSIF0 output muxing is not enabled
(PINMUX0.PTSOMUX ≠ 1x), this pin is UART0 data-carrier-detect, UDCD0 (I).
This pin is multiplexed between UART0, GPIO, and TSIF1.
When UART0 UART with modem functional muxing is selected
DD33
enabled (PINMUX0.TSSOMUX ≠ 11), this pin is the UART0 ring indicator,
URIN0 (I).
UART0 WITHOUT MODEM CONTROL (PINMUX1.UART0CTL = 01)
This pin is multiplexed between UART0 and TSIF1.
DD33
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 receive data, URXD0 (I).
This pin is multiplexed between UART0 and TSIF1.
IPDWhen UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
DV
DD33
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 transmit data, UTXD0 (O/Z).
This pin is multiplexed between UART0 and TSIF1.
IPUWhen UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
DV
DD33
and TSIF1 input on UART0 muxing is not enabled (PINMUX0.TSSIMUX ≠ 01), this
pin is UART0 request-to-send signal, URTS0 (O/Z).
When UART0 UART functional muxing is selected (PINMUX1.UART0CTL = 0x)
Actual UART1 pin functions are determined by the PINMUX0 and PINMUX1 register bit settings. For more details, see
Section 4.7.3, Pin Multiplexing.
URXD1/
TS0_DIN7/Y18I/O/Z
GP[23]
UTXD1/This pin is multiplexed between UART1, TSIF0, and GPIO.
URCTX1/IPDWhen UART1 UART functional muxing is selected (PINMUX1.UART1CTL = 0x)
TS0_DOUT7/DV
AB19I/O/Z
GP[24]UART1 transmit data, UTXD1 (O/Z).
URTS1 /UIRTX1/
TS0_WAITO/AA18I/O/Z
GP[25]
UCTS1 /USD1
TS0_EN_WAITO/Y17I/O/Z
GP[26]
URXD1/
TS0_DIN7/Y18I/O/Z
GP[23]
UTXD1/This pin is multiplexed between UART1, TSIF0, and GPIO.
URCTX1/IPDWhen UART1 UART functional muxing is selected (PINMUX1.UART1CTL = 0x)
TS0_DOUT7/DV
AB19I/O/Z
GP[24]UART1 transmit data, UTXD1 (O/Z).
URXD1/
TS0_DIN7/Y18I/O/Z
GP[23]
UTXD1/URCTX1/
TS0_DOUT7/AB19I/O/Z
GP[24]
URTS1/UIRTX1/
TS0_WAITO/AA18I/O/Z
GP[25]
UCTS1/USD1/
TS0_EN_WAITO/Y17I/O/Z
GP[26]
(1) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(2) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(3) Specifies the operating I/O supply voltage for each signal
TYPE
(1)
OTHER
(2) (3)
UART1 WITH FLOW CONTROL (PINMUX1.UART1CTL = 00)
This pin is multiplexed between UART1, TSIF0, and GPIO.
IPDWhen UART1 UART functional muxing is selected (PINMUX1.UART1CTL = 0x)
DV
DD33
DD33
and TSIF0 serial input is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is
UART1 receive data, URXD1 (I).
and TSIF0 serial output is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is
This pin is multiplexed between UART1, TSIF0, and GPIO.
IPUWhen UART1 UART with flow control muxing is selected (PINMUX1.UART1CTL =
DV
DD33
00) and TSIF0 input is not enabled (PINMUX0.PTSIMUX ≠ 0x), this pin is UART1
request-to-send, URTS1 (O/Z).
This pin is multiplexed between UART1, TSIF0, and GPIO.
IPUWhen UART1 UART with flow control muxing is selected (PINMUX1.UART1CTL =
DV
DD33
00) and TSIF0 input is not enabled (PINMUX0.PTSIMUX ≠ 0x), this pin is UART1
clear-to-send, UCTS1 (I).
UART1 WITHOUT FLOW CONTROL (PINMUX1.UART1CTL = 01)
This pin is multiplexed between UART1, TSIF0, and GPIO.
IPDWhen UART1 UART functional muxing is selected (PINMUX1.UART1CTL = 0x)
DV
DD33
DD33
and TSIF0 serial input is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is
UART1 receive data, URXD1 (I).
and TSIF0 serial output is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is
UART1 IrDA/CIR FUNCTION (PINMUX1.UART1CTL = 10)
This pin is multiplexed between UART1, TSIF0, and GPIO.
IPDWhen UART1 IrDA/CIR functional muxing is selected (PINMUX1.UART1CTL = 10)
DV
DD33
and TSIF0 serial input is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is
UART1 receive data, URXD1 (I).
This pin is multiplexed between UART1, TSIF0, and GPIO.
IPDWhen UART1 IrDA/CIR functional muxing is selected (PINMUX1.UART1CTL = 10)
DV
DD33
and TSIF0 serial output is not enabled (PINMUX0.PTSOMUX ≠ 11), this pin is
UART1 CIR transmit data, URCTX1 (O/Z).
This pin is multiplexed between UART1, TSIF0, and GPIO.
IPUWhen UART1 IrDA/CIR functional muxing is selected (PINMUX1.UART1CTL = 10)
DV
DD33
and TSIF0 input is not enabled (PINMUX0.PTSIMUX = 0x), this pin is UART1 IrDA
transmit data, UIRTX1 (O/Z).
This pin is multiplexed between UART1, TSIF0, and GPIO.
IPUWhen UART1 IrDA/CIR functional muxing is selected (PINMUX1.UART1CTL = 10)
DV
DD33
and TSIF0 input is not enabled (PINMUX0.PTSIMUX = 0x), this pin is UART1 IrDA
tranceiver control, USD1 (O/Z).
Actual UART2 pin functions are determined by the PINMUX0 and PINMUX1 register bit settings. For more details, see
Section 4.7.3, Pin Multiplexing.
URXD2/This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
CRG1_VCXI/IPDWhen UART2 UART functional muxing is selected (PINMUX1.UART2CTL = 0x)
GP[39]/DV
AB20I/O/Z
CRG0_VCXIUART2 receive data, URXD2 (I).
UTXD2/
URCTX2/
CRG1_PO/AA19I/O/Z
GP[40]/
CRG0_PO
URTS2 /UIRTX2/
TS0_PSTIN/AC20I/O/Z
GP[41]
UCTS2 /USD2/This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.
CRG0_VCXI/IPUWhen UART2 UART with flow control muxing is selected (PINMUX1.UART2CTL =
GP[42]/DV
AC21I/O/Z
TS1_PSTOUART2 clear-to-send, UCTS2 (I).
URXD2/This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
CRG1_VCXI/IPDWhen UART2 UART functional muxing is selected (PINMUX1.UART2CTL = 0x)
GP[39]/DV
AB20I/O/Z
CRG0_VCXIUART2 receive data, URXD2 (I).
UTXD2/
URCTX2/
CRG1_PO/AA19I/O/Z
GP[40]/
CRG0_PO
URXD2/This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
CRG1_VCXI/IPDWhen UART2 IrDA/CIR functional muxing is selected (PINMUX1.UART2CTL = 10)
GP[39]/DV
AB20I/O/Z
CRG0_VCXIUART2 receive data, URXD2 (I).
UTXD2/URCTX2/This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
CRG1_PO/IPDWhen UART2 IrDA/CIR functional muxing is selected (PINMUX1.UART2CTL = 10)
GP[40]/DV
AA19I/O/Z
CRG0_POUART2 CIR transmit data, URCTX2 (O/Z).
URTS2/UIRTX2/
TS0_PSTIN/AC20I/O/Z
GP[41]
UCTS2/USD2/This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.
CRG0_VCXI/IPUWhen UART2 IrDA/CIR functional muxing is selected (PINMUX1.UART2CTL = 10)
GP[42]/DV
AC21I/O/Z
TS1_PSTOpin is UART2 IrDA tranceiver control, USD2 (O/Z).
(1) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(2) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(3) Specifies the operating I/O supply voltage for each signal
TYPE
(1)
OTHER
(2) (3)
UART2 WITH FLOW CONTROL (PINMUX1.UART2CTL = 00)
DD33
and CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), this pin is
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
IPDWhen UART2 UART functional muxing is selected (PINMUX1.UART2CTL = 0x)
DV
DD33
and CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), this pin is
UART2 transmit data, UTXD2 (O/Z).
This pin is multiplexed between UART2, TSIF0, and GPIO.
IPUWhen UART2 UART with flow control muxing is selected (PINMUX1.UART2CTL =
DV
DD33
DD33
00) and TSIF0 input is not enabled (PINMUX0.PTSIMUX = 0x), this pin is UART2
request-to-send, URTS2 (O/Z).
00) and TSIF1 output is not enabled (PINMUX0.PTSOMUX = 0x), this pin is
UART2 WITHOUT FLOW CONTROL (PINMUX1.UART2CTL = 01)
DD33
and CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), this pin is
This pin is multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
IPDWhen UART2 UART functional muxing is selected (PINMUX1.UART2CTL = 0x)
DV
DD33
and CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), this pin is
UART2 transmit data, UTXD2 (O/Z).
UART2 IrDA/CIR FUNCTION (PINMUX1.UART2CTL = 10)
DD33
DD33
and CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), this pin is
and CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), this pin is the
This pin is multiplexed between UART2, TSIF0, and GPIO.
IPUWhen UART2 IrDA/CIR functional muxing is selected (PINMUX1.UART2CTL = 10)
DV
DD33
DD33
and TSIF0 input is not enabled (PINMUX0.PTSIMUX = 0x), this pin is UART2 IrDA
transmit data, UIRTX2 (O/Z).
and CRGEN0 on TSIF0 output is not enabled (PINMUX0.TSSOMUX = 0x), this
W18O/ZWhen not overridden by TSIF1 output muxing (PINMUX0.TSSOMUX ≠ 11), this pin
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
TYPE
(1)
OTHER
(2)
DESCRIPTION
PWM0
This pin is multiplexed between PWM0, CRGEN0, and TSIF1.
–When not overridden by CRGEN or TSIF1 output muxing (PINMUX0.CRGMUX ≠
DV
DD33
10x and PINMUX0.TSSOMUX ≠ 11), this pin is the pulse width modulation 0 output,
PWM0 (O/Z).
PWM1
This pin is multiplexed between PWM1 and TSIF1.
DD33
is the pulse width modulation 1 output, PWM1 (O/Z).
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
TYPE
(1)
(2) (3)
OTHER
DESCRIPTION
Timer 0
IPDTimer0 lower input. This pin is the Timer0 input for 64-mode operation. For 32-bit
DV
DD33
timer operation, this pin is the input for the Timer0 lower 32-bit counter.
IPDTimer0 upper input. For 32-bit timer operation, this pin is the input for the Timer0
DV
DD33
upper 32-bit counter. Not used for Timer0 64-mode operation.
IPDTimer0 lower output. This pin is the Timer0 output for 64-mode operation. For 32-bit
DV
DD33
timer operation, this pin is the output for the Timer0 lower 32-bit counter.
IPDTimer0 upper output. For 32-bit timer operation, this pin is the output for the Timer0
DV
DD33
upper 32-bit counter. Not used for Timer0 64-mode operation.
Timer 1
IPDTimer1 lower input. This pin is the Timer1 input for 64-mode operation. For 32-bit
DV
DD33
timer operation, this pin is the input for the Timer1 lower 32-bit counter.
IPDTimer1 lower output. This pin is the Timer1 output for 64-mode operation. For 32-bit
DV
DD33
timer operation, this pin is the output for the Timer1 lower 32-bit counter.
IPDTimer1 upper output. For 32-bit timer operation, this pin is the output for the Timer1
DV
DD33
upper 32-bit counter. Not used for Timer1 64-mode operation.
ATA is enabled by the PINMUX0.ATAEN =1 (and PCIEN = 0). For more detailed information on the ATA pin muxing, see Section 4.7.3.1,
PCI, HPI, EMIFA, and ATA Pin Muxing.
PCI_CBE0/
ATA_CS0 /F4I/O/Z
GP[33]/EM_A[18]
PCI_CBE1/
ATA_CS1 /C2I/O/Z
GP[32]/EM_A[19]
PCI_RSV4/ DIOW /IPUThis pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
GP[20]/EM_WAIT4DV
PCI_RSV3/ DIOR /IPUThis pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
GP[19]/EM_WAIT5DV
PCI_RSV5/IORDY/IPUThis pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
GP[21]/EM_WAIT3DV
A11I/O/Z
E10I/O/Z
D11I/O/Z
PCI_RST/
DA2/C10I/O/Z
GP[13]/EM_A[22]
PCI_RSV0/DA1/IPDThis pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
GP[16]/EM_A[21]DV
PCI_RSV1/DA0/IPDThis pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
GP[17]/EM_A[20]DV
PCI_RSV2/INTRQ/IPDThis pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
GP[18]/EM_RSV0DV
A9I/O/Z
E9I/O/Z
B10I/O/Z
PCI_REQ/
DMARQ/B9I/O/Z
GP[11]/EM_CS5
PCI_GNT/This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
DMACK /D10I/O/ZWhen ATA is enabled, this pin is the ATA DMA acknowledge output, DMACK
GP[12]/EM_CS4(O/Z).
PCI_IDSEL/This pin is multiplexed between PCI, ATA, and EMIFA.
HDDIR/E8I/O/ZWhen ATA is enabled, this pin is the data direction indicator for external buffer
EM_R/Wcontrol, HDDIR (O/Z).
TYPE
(1)
(2) (3)
OTHER
DESCRIPTION
ATA
IPUThis pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
DV
DD33
When ATA is enabled, this pin is ATA chip select 0 output, ATA_CS0 (O/Z).
IPUThis pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
DV
DD33
DD33
DD33
DD33
When ATA is enabled, this pin is ATA chip select 1 output, ATA_CS1 (O/Z).
When ATA is enabled, this pin is the ATA write strobe output, DIOW (O/Z).
When ATA is enabled, this pin is the ATA read strobe output, DIOR (O/Z).
When ATA is enabled, this pin is ATA I/O ready, IORDY (I).
IPDThis pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
DV
DD33
DD33
DD33
DD33
When ATA is enabled, this pin is ATA address bit 2, DA2 (O/Z).
When ATA is enabled, this pin is ATA address bit 1, DA1 (O/Z).
When ATA is enabled, this pin is ATA address bit 0, DA0 (O/Z).
When ATA is enabled, this pin is the ATA interrupt request input, INTRQ (I).
IPUThis pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
DV
DD33
When ATA is enabled, this pin is the ATA DMA request input, DMARQ (I).
IPU
DV
DD33
IPU
DV
DD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
Table 3-29. General Purpose Input/Output (GPIO) Terminal Functions
SIGNAL
NAMENO.
The DM6467T device does not support GP[47:43], GP[35:34], GP[31:27], GP[15:14], and GP[9] signals (not pinned out).
GP[7:0] pins have dedicated ARM926 and DSP interrupts.
When PCI is used, GP[19:16] pins are reserved.
GP[0]W5I/O/ZGP[0] (I/O/Z). This pin is general-purpose input/output 0.
GP[1]V5I/O/ZGP[1] (I/O/Z). This pin is general-purpose input/output 1.
GP[2]/IPDThis pin is multiplexed between GPIO and the audio clock selector.
AUDIO_CLK1DV
GP[3]/IPDThis pin is multiplexed between GPIO and the audio clock selector.
AUDIO_CLK0DV
GP[4]/IPD
STC_CLKINDV
AA4I/O/Z
AB3I/O/Z
AC3I/O/ZWhen the STC source clock input is disabled (PINMUX0.STCCK = 0), this pin is
GP[5]B11I/O/ZThis pin is GP[5] (I/O/Z).
GP[6]E11I/O/ZThis pin is GP[6] (I/O/Z).
GP[7]A12I/O/ZThis pin is GP[7] (I/O/Z).
URIN0/GP[8]/IPDWhen UART0 UART with modem functional muxing is not selected
TS1_WAITINDV
Y11I/O/Z
GP[9]n/a––GP[9] is not pinned out on this device.
PCI_CLK/GP[10]A10I/O/Z
PCI_REQ/This pin is multiplexed between PCI, ATA, GPIO, and EMIFA.
GP[13]/EM_A[22]PINMUX0.ATAEN = 0), this pin is GP[13] (I/O/Z).
GP[14:15]n/a––GP[14:15] are not pinned out on this device.
PCI_RSV0/DA1/
GP[16]/A9I/O/Z
EM_A[21]
PCI_RSV1/DA0/IPD
GP[17]/EM_A[20]DV
E9I/O/Z
PCI_RSV2/
INTRQ/IPD
GP[18]/DV
B10I/O/Z
EM_RSV0
PCI_RSV3/DIOR/
GP[19]/E10I/O/Z
EM_WAIT5
TYPE
(1)
(2) (3)
OTHER
DESCRIPTION
GPIO
IPD
DV
DD33
IPD
DV
DD33
DD33
DD33
When audio clock 1 is disabled (PINMUX0.AUDCK1 = 0), this pin is GP[2] (I/O/Z).
When audio clock 0 is disabled (PINMUX0.AUDCK0 = 0), this pin is GP[3] (I/O/Z).
This pin is multiplexed between GPIO and the TSIF clock selector.
DD33
GP[4] (I/O/Z).
IPD
DV
DD33
IPD
DV
DD33
IPD
DV
DD33
This pin is multiplexed between UART0, GPIO, and TSIF1.
DD33
(PINMUX1.UART0CTL = 00) and TSIF1 output on UART/PWM muxing is not
enabled (PINMUX0.TSSOMUX ≠ 11), this pin is GP[8] (I/O/Z).
IPUThis pin is multiplexed between PCI and GPIO.
DV
DD33
When PCI is disabled (PINMUX0.PCIEN = 0), this pin is GP[10] (I/O/Z).
IPU
DV
DD33
IPU
DV
DD33
IPD
DV
DD33
IPD
DV
DD33
DD33
These pins are multiplexed between PCI, ATA, GPIO, and EMIFA.
When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
PINMUX0.ATAEN = 0), these pins are GP[16:19] (I/0/Z). When PCI mode is enabled
DD33
(PINMUX0.PCIEN = 1), these pins are reserved.
IPU
DV
DD33
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
Table 3-29. General Purpose Input/Output (GPIO) Terminal Functions (continued)
SIGNAL
NAMENO.
PCI_RSV4/
DIOW/IPU
GP[20]/DV
A11I/O/Z
EM_WAIT4
PCI_RSV5/
IORDY/IPU
GP[21]/DV
D11I/O/Z
EM_WAIT3
USB_DRVVBUS/IPDThis pin is multiplexed between USB and GPIO.
GP[22]DV
B18I/O/Z
URXD1/This pin is multiplexed between UART1, TSIF0, and GPIO.
TS0_DIN7/Y18I/O/ZWhen UART1 GPIO muxing is selected (PINMUX1.UART1CTL = 11) and TSIF0
GP[23]serial input is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is GP[23] (I/O/Z).
UTXD1/
URCTX1/IPD
TS0_DOUT7/DV
AB19I/O/ZWhen UART1 GPIO muxing is selected (PINMUX1. UART1CTL = 11) and TSIF0
GP[24]
URTS1/
UIRTX1/IPD
TS0_WAITO/DV
AA18I/O/Z
GP[25]
UCTS1/USD1/
TS0_EN_WAITO/Y17I/O/Z
GP[26]
GP[27:31]n/a––GP[27:31] are not pinned out on this device.
PCI_CBE1/
ATA_CS1/IPU
GP[32]/DV
C2I/O/Z
EM_A[19]
PCI_CBE0/
ATA_CS0/IPU
GP[33]/DV
F4I/O/Z
EM_A[18]
GP[34:35]n/a––GP[34:35] are not pinned out on this device.
UDTR0/
TS0_ENAO/Y12I/O/Z
GP[36]
UDSR0/
TS0_PSTO/AB11I/O/Z
GP[37]
UDCD0/
TS0_WAITIN/AA11I/O/Z
GP[38]
URXD2/
CRG1_VCXI/IPD
GP[39]/DV
AB20I/O/Z
CRG0_VCXI
UTXD2/URCTX2/
CRG1_PO/IPD
GP[40]/DV
AA19I/O/Z
CRG0_PO
URTS2/UIRTX2/
TS0_PSTIN/AC20I/O/Z
GP[41]
UCTS2/USD2/
CRG0_VCXI/IPU
GP[42]/DV
AC21I/O/Z(PINMUX1.UART2CTL = x1) and CRGEN0 on UART2/PWM muxing is not enabled
TS1_PSTO
TYPE
(1)
(2) (3)
OTHER
DD33
These pins are multiplexed between PCI, ATA, GPIO, and EMIFA.
DESCRIPTION
When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
PINMUX0.ATAEN = 0), these pins are GP[20:21] (I/0/Z).
DD33
DD33
When not used for USB (PINMUX0.VBUSDIS = 1), this pin is GP[22] (I/O/Z).
IPD
DV
DD33
This pin is multiplexed between UART1, TSIF0, and GPIO.
DD33
DD33
serial input is not enabled (PINMUX0.PTSIMUX ≠ 11), this pin is GP[24] (I/O/Z).
These pins are multiplexed between UART1, TSIF0, and GPIO.
When UART1 GPIO muxing is selected (PINMUX1.UART1CTL = 11) and TSIF0
input is not enabled (PINMUX0.PTSIMUX = 0x), these pins are GP[25:26] (I/O/Z).
These pins are multiplexed between PCI, ATA, GPIO, and EMIFA.
DV
IPU
DD33
DD33
When 32-bit HPI mode is enabled (PINMUX0.PCIEN = 0, PINMUX0.HPIEN = 1,
PINMUX0.ATAEN = 0), these pins are GP[32:33] (I/O/Z).
DD33
IPU
DV
DD33
These pins are multiplexed between UART0, TSIF0, and GPIO.
IPUWhen UART0 UART with modem functional muxing is not selected
DV
DD33
(PINMUX1.UART0CTL ≠ 00) and TSIF0 output muxing is not enabled
(PINMUX0.PTSOMUX ≠ 1x), these pins are GP[36:38] (I/O/Z).
IPU
DV
DD33
DD33
These pins are multiplexed between UART2, CRGEN1, GPIO, and CRGEN0.
When UART2 UART GPIO muxing is selected (PINMUX1.UART2CTL = 11) and
CRGEN0/1 are not enabled (PINMUX0.CRGMUX ≠ x01, 110), these pins are
GP[39:40] (I/O/Z).
DD33
This pin is multiplexed between UART2, TSIF0, and GPIO.
IPUWhen UART2 UART without flow control or GPIO muxing is selected
DV
DD33
(PINMUX1.UART2CTL = x1) and TSIF0 input is not enabled
(PINMUX0.PTSIMUX = 0x), this pin is GP[41] (I/O/Z).
This pin is multiplexed between UART2, CRGEN0, GPIO, and TSIF1.
When UART2 UART without flow control or GPIO muxing is selected
DD33
(PINMUX0.CRGMUX ≠ 10x) and TSIF1 output is not enabled
(PINMUX0.TSSOMUX = 0x), this pin is GP[42] (I/O/Z).
RSV1A1Reserved. For proper device operation, this pin must be tied directly to VSS.
RSV2A2Reserved. For proper device operation, this pin must be tied directly to VSS.
RSV3A22Reserved. For proper device operation, this pin must be tied directly to VSS.
RSV4A23Reserved. (Leave unconnected, do not connect to power or ground.)
RSV5D14Reserved. (Leave unconnected, do not connect to power or ground.)
RSV6F17Reserved. For proper device operation, this pin must be tied directly to CVDD.
RSV7G16Reserved. For proper device operation, this pin must be tied directly to CVDD.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
TI offers an extensive line of development tools for the TMS320DM646x DMSoC platform, including tools
to evaluate the performance of the processors, generate code, develop algorithm implementations, and
fully integrate and debug software and hardware modules. The tool's support documentation is
electronically available within the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of TMS320DM646x SoC-based applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any SoC application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for the TMS320DM646x DMSoC platform, visit the
Texas Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator
(URL). For information on pricing and availability, contact the nearest TI field sales office or authorized
distributor.
SPRS605B–JULY 2009–REVISED JULY 2010
3.8.2Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g.,TMX320DM6467TZUT). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMXExperimental device that is not necessarily representative of the final device's electrical
specifications.
TMPFinal silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
TMSFully-qualified production device.
Support tool development evolutionary flow:
TMDXDevelopment-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDSFully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZUT), the temperature range (for example, "Blank" is the commercial
temperature range), and the device speed range in megahertz or gigahertz (for example, "1" is the default
[1-GHz DSP, 500-MHz ARM9]).
Figure 3-8 provides a legend for reading the complete device name for any TMS320DM6467T DMSoC
The following documents describe the TMS320DM646x Digital Media System-on-Chip (DMSoC). Copies
of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the
search box provided at www.ti.com.
The current documentation that describes the DM646x DMSoC, related peripherals, and other technical
collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.
SPRUEP8TMS320DM646x DMSoC DSP Subsystem Reference Guide. Describes the digital signal
processor (DSP) subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC).
SPRUEP9TMS320DM646x DMSoC ARM Subsystem Reference Guide. Describes the ARM
subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The ARM
subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In
general, the ARM is responsible for configuration and control of the device; including the
DSP subsystem and a majority of the peripherals and external memories.
SPRUEQ0TMS320DM646x DMSoC Peripherals Overview Reference Guide. Provides an overview
and briefly describes the peripherals available on the TMS320DM646x Digital Media
System-on-Chip (DMSoC).
SPRAA84TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the Texas
Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The
objective of this document is to indicate differences between the two cores. Functionality in
the devices that is identical is not included.
SPRS605B–JULY 2009–REVISED JULY 2010
SPRU732TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+
digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP
generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an
enhancement of the C64x DSP with added functionality and an expanded instruction set.
SPRU871TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory
access (IDMA) controller, the interrupt controller, the power-down controller, memory
protection, bandwidth management, and the memory and cache.
Report This application report describes the way the DDR high-speed timing requirements
are now going to be communicated to system designers. The system designer uses this
information to evaluate whether timing specifications are met and can be expected to
operate reliably.
The system module includes status and control registers for configuration of the device.Brief descriptions
of the various registers are shown in Table 4-1. System Module registers required for device
configurations are discussed in the following sections.
Table 4-1. System Module Register Memory Map
HEX ADDRESS RANGEREGISTER ACRONYMDESCRIPTION
0x01C4 0000PINMUX0Pin Multiplexing Control 0 (see Section 4.7.2.1, PINMUX0 Register).
0x01C4 0004PINMUX1Pin Multiplexing Control 1 (see Section 4.7.2.2, PINMUX1 Register).
0x01C4 0008DSPBOOTADDRDSP Boot Address. Decoded by bootloader software for host boots.
0x01C4 000CSUSPSRCEmulator Suspend Source (see Section 4.7.3.12, Emulation Control).
0x01C4 0010BOOTSTATBoot Status (see Section 4.4.2.2, BOOTSTAT Register).
0x01C4 0014BOOTCFGDevice Boot Configuration (see Section 4.4.2.3, BOOTCFG Register).
0x01C4 0018–Reserved
0x01C4 001C - 0x01C4 0020–Reserved
0x01C4 0024ARMBOOTARM926 Boot Control (see Section 4.4.2.4, ARMBOOT Register).
0x01C4 0028JTAGIDDevice ID Number [see Section 7.29.1, JTAG ID (JTAGID) Register
0x01C4 002C–Reserved
0x01C4 0030HPICTLHPI Control (see Section 4.6.2.1, HPICTL Register).
0x01C4 0034USBCTLUSB Control (see Section 4.6.2.2, USBCTL Register).
0x01C4 0038VIDCLKCTLVideo Clock Control (see Section 4.3.2.1, Video Clock Control).
0x01C4 003CMSTPRI0Bus Master Priority Control 0 (see Section 4.6.1, Switch Central
0x01C4 0040MSTPRI1Bus Master Priority Control 1 (see Section 4.6.1, Switch Central
0x01C4 0044MSTPRI2Bus Master Priority Control 2 (see Section 4.6.1, Switch Central
0x01C4 0048VDD3P3V_PWDNVDD3.3-V I/O Powerdown Control (see Section 4.2, Power
0x01C4 004C–Reserved
0x01C4 0050TSIFCTLTSIF Control Register (see Section 4.3.2.2, TSIF Control).
0x01C4 0054PWMCTLPWM Control (see Section 4.6.2.3, PWM (Trigger Source) Control
0x01C4 0058EDMATCCFGEDMA TC Configuration (see Section 4.6.2.4, EDMATCCFG
0x01C4 005CCLKCTLOscillator and Output Clock Control (see Section 4.3.3, Clock and
0x01C4 0060DSPINTARM to DSP Interrupt Status (see Section 4.7.3.11, ARM/DSP
0x01C4 0064DSPINTSETARM to DSP Interrupt Set (see Section 4.7.3.11, ARM/DSP
0x01C4 0068DSPINTCLRARM to DSP Interrupt Clear (see Section 4.7.3.11, ARM/DSP
0x01C4 006CVSCLKDISVideo and TSIF Clock Disable (see Section 4.3.2.3, Video and TSIF
0x01C4 0070ARMINTDSP to ARM Interrupt Status (see Section 4.7.3.11, ARM/DSP
0x01C4 0074ARMINTSETDSP to ARM Interrupt Set (see Section 4.7.3.11, ARM/DSP
The DM6467T provides several means of managing power consumption.
As described in the Section 7.3.4, DM6467T Power and Clock Domains, the DM6467T has one single
power domain—the “Always On” power domain. Within this power domain, the DM6467T utilizes local
clock gating via the Power and Sleep Controller (PSC) to achieve power savings. For more details on the
PSC, see Section 7.3.5, Power and Sleep Controller (PSC) and the TMS320DM646x DMSoC ARMSubsystem Reference Guide (literature number SPRUEP9).
Some of the DM6467T peripherals support additional power saving features. For more details on power
savingfeaturessupported,seethe peripheral-specificreferenceguides[listed/linkedinthe
TMS320DM646x DMSoC Peripherals Overview Reference Guide (literature number SPRUEQ0).
Most DM6467T 3.3-V I/Os can be powered-down to reduce power consumption. The VDD3P3V_PWDN
register in the System Module (see Figure 4-1 ) is used to selectively power down unused 3.3-V I/O pins.
Note: To save power, all other I/O buffers are powered down by default. Before using these pins, the user
must program the VDD3P3V_PWDN register to power up the corresponding I/O buffers.
For a list of multiplexed pins on the device and the pin mux group each pin belongs to, see Section 4.7.3,
Pin Multiplexing Details.
Note: The VDD3P3V_PWDN register only controls the power to the I/O buffers. The Power and Sleep
Controller (PSC) determines the clock/power state of the peripheral.
9UR2FCThis bit controls the URTS2/UIRTX2/TS0_PSTIN/GP[41] and
0 = I/O cells powered up.
1 = I/O cells powered down.
This bit controls the USB_DRVVBUS/GP[22] pin.
CLKOUT0 Powerdown Control.
This bit controls the CLKOUT0 pin.
SPI Powerdown Control.
SPI_SIMO.
VLYNQ Powerdown Control.
VLYNQ_TXD[3:0], and VLYNQ_RXD[3:0].
GMII Powerdown Control.
MRXD[7:4].
MII Powerdown Control.
MTXD[3:0], MTXEN, MCOL, MCRS, MRCLK, MRXD[3:0], MRXDV, MRXER, MDCLK, and MDIO.
McASP1 Powerdown Control.
This bit controls the three McASP1 pins: ACLKX1, AHCLKX1, and AXR1[0].
McASP0 Powerdown Control.
AXR0[3:0], AMUTE0, and AMUTEIN0.
PCI/HPI/EMIFA/ATA Powerdown Control.
This bit controls the 28 pins used by the ATA or PCI`, HPI, or EMIFA. These pins include:
PCI_RST/DA2/GP[13]/EM_A[22], PCI_IDSEL/HDDIR/EM_R/W,
PCI_REQ/DMARQ/GP[11]/EM_CS5, PCI_GNT/DMACK/GP[12]/EM_CS4,
DIOW/GP[20]/EM_WAIT4/(RDY4/BSY4), IORDY/GP[21]/EM_WAIT3/(RDY3/BSY3),
DIOR/GP[19]/EM_WAIT5/(RDY5/BSY5), DA1/GP[16]/EM_A[21], DA0/GP[17]/EM_A[20],
INTRQ/GP[18]/RSV , PCI_AD[31:16]/DD[15:0]/HD[31:16]/EM_A[15:0]
Defaults to powered up for NOR boot.
PCI/HPI/EMIFA Powerdown Control.
This bit controls the 28 pins used by PCI, HPI, or EMIFA but not shared with ATA. These pins
include: PCI_CLK/GP[10], PCI_DEVSEL/HCNTL1/EM_BA[1], PCI_FRAME/HINT/EM_BA[0],
PCI_IRDY/HRDY/EM_A[17]/(CLE), PCI_TRDY/HHWIL/EM_A[16]/(ALE),
PCI_STOP/HCNTL0/EM_WE, PCI_SERR/HDS1/EM_OE, PCI_PERR/HCS/EM_DQM1,
PCI_PAR/HAS/EM_DQM0, PCI_INTA/EM_WAIT2/(RDY2/BSY2), PCI_CBE3/HR/W/EM_CS3,
PCI_CBE2/HDS2/EM_CS2, PCI_AD[15:0]/HD[15:0]/EM_D[15:0]
Defaults to powered up for NOR boot.
GPIO Powerdown Control.
This bit controls the eight GP[7:0] pins. Defaults to powered up.
WD Timer Powerdown Control.
This bit controls the WD Timer pin TOUT2.
Timer1 Powerdown Control.
This bit controls the three Timer1 pins TINP1L, TOUT1L, and TOUT1U.
Timer0 Powerdown Control.
This bit controls the four Timer0 pins TINP0L, TINP0U, TOUT0L, and TOUT0U.
PWM1 Powerdown Control.
This bit controls the PWM1/TS1_DOUT pin.
PWM0 Powerdown Control.
This bit controls the PWM0/CRG0_PO/TS1_ENAO pin.
UART2 Flow Control Powerdown Control.
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PSTO pins.
Global device and local peripheral clocks are controlled by the PLL Controllers (PLLC1 and PLLC2) and
the Power and Sleep Controller (PSC). In addition, the System Module Video Clock Control (VIDCLKCTL),
TSIF Control (TSIFCTL), and Clock and Oscillator Control (CLKCTL) registers configure the clock sources
to the VPIF, TSIF, CRGEN peripherals, and the Auxiliary Oscillator.
The selected Video, TSIF, and CRGEN module input clocks are disabled using the System Module Video
Source Clock Disable (VSCLKDIS) register. Note: To ensure glitch-free operation, the clock should be
disabled before changing the clock source frequency or muxing via the VIDCLKCTL and TSIFCTL.
4.3.1Clock Configurations after Device Reset
After device reset, the user is responsible for programming the PLL Controllers (PLLC1 and PLLC2) and
the Power and Sleep Controller (PSC) to bring the device up to the desired clock frequency and the
desired peripheral clock state (clock gating or not).
For additional power savings, some of the DM6467T peripherals support clock gating within the peripheral
boundary. For more details on clock gating and power saving features supported by a specific peripheral,
see the peripheral-specific reference/user's guides [listed/linked in the TMS320DM646x DMSoCPeripherals Overview Reference Guide (literature number SPRUEQ0)].
4.3.1.1Device Clock Frequency
The DM6467T defaults to PLL bypass mode. If the ROM bootloader is selected (BTMODE[3:0] ≠ 0100),
the bootloader code programs PLLC1 and PLLC2.
SPRS605B–JULY 2009–REVISED JULY 2010
Section 4.4.1, Boot Modes discusses the different boot modes in more detail.
The user must adhere to the various clock requirements when programming the PLLC1 and PLLC2:
•PLL multiplier and frequency ranges. For more details on PLL multiplier and frequency ranges, see
Section 7.5.1, PLL1 and PLL2.
4.3.1.2Module Clock State
The clock and reset state for each of the modules is controlled by the Power and Sleep Controller (PSC).
Table 4-3 shows the default state of each module after a device-level global reset. The DM6467T device
has four different module states—Enable, Disable, SyncReset, or SwRstDisable. For more information on
the definitions of the module states, the PSC, and PSC programming, see Section 7.3.5, Power and SleepController (PSC) and the TMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number
(1) The Video Port Module has a total of five clock inputs that can be controlled by the LPSC. One LPSC can support only a maximum of
four clocks; therefore, two LPSCs are assigned to the Video Port. Both Video Port LPSCs should be controlled together and should be
set to the same state.
(1)
(MDSTATn.LRST = 0).
If DSPBOOT = 1 then, Enable and Module Local Reset is asserted
(MDSTATn.LRST = 1).
SwRstDisable
If BTMODE[3:0] ≠ 0100 and DSPBOOT = 0 then, SwRstDisable
If BTMODE[3:0] = 0100 or DSPBOOT = 1 then, Enable
This section describes the following registers: the VPIF (Video)/TSIF clock control and clock disable
registers and the Clock and Oscillator control register.
4.3.2.1Video Clock Control Register
The Video Clock Control (VIDCLKCTL) register allows the user to select/control the clock muxing for the
video channels' (i.e., channels 1, 2, and 3) output clock source.
3116
RESERVED
R-0000 0000 0000 0000
1514121110875430
RSVVCH3CLKRSVVCH2CLKRESERVEDVCH1CLKRESERVED
R-0R/W-111R-0R/W-110R-000R/W-1R-0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-2. VIDCLKCTL Register [0x01C4 0038]
Table 4-4. VIDCLKCTL Register Bit Descriptions
BITNAMEDESCRIPTION
31:15RESERVEDReserved. Read returns "0".
Video Channel 3 Clock Source.
This field selects the clock source for the Channel 3 output source clock.
000 = CRG0_VCXI (external pin)
001 = CRG1_VCXI (external pin)
Video Channel 2 Clock Source.
This field selects the clock source for the Channel 2 output source clock.
000 = CRG0_VCXI (external pin)
001 = CRG1_VCXI (external pin)
010 = SYSCLK8 (PLLC1)
011 = AUXCLK (PLLC1)
100 = VP_CLKIN0 (external pin)
101 = STC_CLKIN (external pin)
110 = VP_CLKIN2 (external pin)
111 = Reserved
Video Channel 1 Clock Source.
This bit selects the clock source for the Channel 1 input clock.
0 = VP_CLKIN0 (external pin)
1 = VP_CLKIN1 (external pin)
The TSIF Control (TSIFCTL) registers allows the user to select/control the clock muxing for the counter
and serial output of TSIF1 andthe counter and parallel/serial output for TSIF0.
3116
RESERVED
R-0000 0000 0000 0000
151412118764320
RSVTSIF1_CNTCLKTSSO_CLKRSVTSIF0_CNTCLKRSVTSPO_CLK
R-0R/W-000R/W-0000R-0R/W-000R-0R/W-000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-3. TSIFCTL Register [0x01C4 0050]
Table 4-5. TSIFCTL Register Bit Descriptions
BITNAMEDESCRIPTION
31:15RESERVEDReserved. Read returns "0".
TSIF1 Counter Clock Source.
This field selects the clock source for the TSIF1 module's counter.
000 = CRG1_VCXI (external pin)
001 = STC_CLKIN (external pin)
The Video Source Clock Disable (VSCLKDIS) register allows the user to disable the selected Video
(VPIF), TSIF, and CRGEN module input clocks.
Note: To ensure glitch-free operation, the clock should be disabled before changing the clock source
frequency or muxing via the VIDCLKCTL and TSIFCTL.
This bit controls the internal bias resistor conection.
0 = Internal bias resistor connected (normal operation)
1 = Internal bias resistor disconnected (external bias resistor required or clock input used)
This bit disables the oscillator.
0 = Oscillator enabled (normal operation).
1 = Oscillator disabled (clock input used or no Auxiliary clock required).
The boot sequence is a process by which the device's memory is loaded with program and data sections,
and by which some of the device's internal registers are programmed with predetermined values. The boot
sequence is started automatically after each device-level global reset. For more details on device-level
global resets, see Section 7.7, Reset.
There are several methods by which the memory and register initialization can take place. Each of these
methods is referred to as a boot mode. The boot mode to be used is selected at reset. For more
information on the bootmode selections, see Section 4.4.1, Boot Modes.
The device is booted through multiple means—primary bootloaders within internal ROM or EMIFA, and
secondary user bootloaders from peripherals or external memories. Boot modes, pin configurations, and
register configurations required for booting the device, are described in the following subsections.
4.4.1Boot Modes
The DM6467T boot modes are determined by these device boot and configuration pins. For information
on how these pins are sampled at device reset, see Section 7.7.1.2, Latching Boot and ConfigurationPins.
•BTMODE[3:0]
•PCIEN
•CS2BW
•DSPBOOT
www.ti.com
The TMS320DM646x DMSoC ARM can boot either from asynchronous EMIF/NOR Flash or from ARM
ROM, as determined by the device boot and configuration pins at reset (BTMODE[3:0] and PCIEN). The
PCIEN pin configuration is used to select the default configuration of the EMIFA/PCI/HPI pins at reset.
This allows the DM646xT DMSoC to be PCI-compliant at reset. When PCIEN = 1, the PCI module
controls the multiplexed pins with the appropriate pullup/pulldown configuration. For all other bootmodes
(non-PCI bootmodes), the PCIEN must be cleared to "0".
For a more detailed description of the ROM boot modes supported by the DM646xT DMSoC, see Using
the TMS320DM646x Bootloader Application Report (literature number SPRAAS0).
4.4.2Boot Mode Registers
The DSPBOOTADDR, BOOTCMPLT, BOOTCMD, and BOOTCFG registers are used to control boot and
device configurations.
4.4.2.1DSPBOOTADDR Register
The DSPBOOTADDR register contains the upper 22 bits of the DSP reset vector.
311090
BOOTADDR[21:0]RESERVED
R/W-0100 0010 0010 0000 0000 00R-00 0000 0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 4-6. DSPBOOTADDR Register
Table 4-8. DSPBOOTADDR Register Bit Descriptions
BITNAMEDESCRIPTION
31:10BOOTADDR[21:0]Upper 22 bits of the C64x+ DSP boot address.
The Boot Configuration (BOOTCFG) register is a read-only register that indicates the value of the device
bootmode and configuration pins latched at the end of reset. During a hard reset (POR or RESET pin
active [low]), the values of the CFG pins (i.e., BTMODE[3:0], CS2BW, PCIEN, DSPBOOT) are propagated
through the BOOTCFG register to the Boot Controller. When RESET or POR is de-asserted, the value of
the pins is latched. The BOOTCFG value does not change as a result of a soft reset, instead the value
latched at the end of the previous global reset is retained.
31181716
RESERVEDDSP_BTPCIEN
R-0000 0000 0000 00R-LR-L
15987430
RESERVEDCS2_BWRESERVEDBOOTMODE
R-0000000R-LR-0000R-LLLL
LEGEND: R = Read only; L = Latched pin value; -n = value after reset
The ARM Boot Configuration (ARMBOOT) register is used to control the ARM926 boot. The ARMBOOT
value does not change as a result of a soft reset, instead the last value written is retained.
When ROM boot is selected (BTMODE[3:0] ≠ 0100), a jump to the internal TCM ROM (0x0000 8000) is
forced into the first fetched instruction word. The embedded ROM boot loader (RBL) code can then
perform certain configuration steps, read the BOOTCFG register to determine the desired boot method,
and branch to an appropriate secondary loader utility.
If EMIFA boot is selected (BTMODE[3:0] = 0100), a jump to the highest branch address (0x0200 0000) is
forced into the first fetched instruction word. This must be modified to address 0x4200 0000 in order to
map to the EMIFA. The ARM will then continue executing from external memory using the default EMIFA
timings until modified by software. Note: that either NOR Flash or ROM must be connected to the first
EMIFA chip select space (EM_CS2). The EMIFA does not support direct execution from NAND Flash.
LEGEND: R/W = Read/Write; R = Read only; C = Clear; -n = value after reset
Figure 4-9. ARMBOOT Register
Table 4-11. ARMBOOT Register Bit Descriptions
BITNAMEDESCRIPTION
31:5RESERVEDReserved. Read returns "0".
IAHB Address Modification.
0 = No address modification.
1 = Address bit 30 is tied high to modify IAHB fetch address to point to EMIFA.
The default value for this bit is determined by the BOOTMODE configuration bits (BTMODE[3:0]). If
BTMODE[3:0] = 0100 [EMIFA direct boot (ROM/NOR)] , then ADDRMOD defaults to "1" so that
4ADDRMODinstruction fetches from the ARM will point to EMIFA CS2 memory space. For all other
BTMODE[3:0] values, ADDRMOD defaults to "0" because ARM will boot from its TCM (ROM or
RAM).
The ADDRMOD value is ignored when TRAMBOOT is set (1) [address modification is disabled].
After branching into the EMIFA CS2 space, software should clear this bit as part of the reset routine
so that subsequent IAHB access addresses are not modified.
3:1RESERVEDReserved. Read returns "0".
ARM TCM RAM Boot.
0 = Use BTMODE[3:0] selected boot mode
1 = Boot from ITCM RAM
0TRAMBOOTThis is a "sticky" bit that can be used to force the ARM926 to boot from ITCM RAM. On POR reset,
this bit will be initialized to "0" because TCM RAM is not initialized; otherwise, the bit retains the
value. After initializing ITCM RAM, software can set this bit so that subsequent Warm Reset
(RESET) or Soft Reset will boot from the ITCM.
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4.4.2.5ARMWAIT Register
The ARM Wait State Control (ARMWAIT) register is used to control ARM926 accesses to its TCM RAM.
At normal ARM operating frequency, a wait state must be inserted when accessing TCM RAM. When the
device is operated at low speeds, performance may be increased by removing the wait state. Note: TCM
ROM will always operate with a wait state enabled.
3110
RESERVEDRAMWAIT
R-0000 0000 0000 0000 0000 0000 0000 000R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Some device configurations are determined at reset. The following subsections give more details.
4.5.1Device and Peripheral Configurations at Device Reset
Table 3-5, BOOT Terminal Functions lists the device boot and configuration pins that are latched at device
reset for configuring basic device settings for proper device operation. Table 4-13, summarizes the device
boot and configuration pins, and the device functions that they affect.
Table 4-13. Default Functions Affected by Device Boot and Configuration Pins
Based onBOOTMODE[3:0], theBOOTMODE[3:0], the
BOOTMODE[3:0], thebootloader code programs bootloader code programs
bootloader code programs VDD3P3V_PWDN register the PSC to put
PINMUX0 and PINMUX1to power up the I/O pinsboot-related peripheral(s)
registers to select therequired for boot.in the Enable State, and
appropriate pin functionsprograms the peripheral(s)
required for boot.for boot operation.
Host Boot:PINMUX0.PCIEN:–PSC/Peripheral
PCIEN selects the type of sets this field to control(Applicable to Host Boot
Host Bootthe PCI pin muxing in .only):
(HPI Boot or PCI Boot)
(1) (2)
determined by the
CS2BW value. If CS2BW
= 0, the space defaults to
8-bits wide. If CS2BW = 1,
it defaults to 16-bits wide.
This allows the ARM to
make full use of the width
of the attached memory
device when booting from
EMIFA.
Based on the Host Boot
type (PCI or HPI), the
bootloader code programs
the PSC to put the
corresponding peripheral
in the Enable State, and
programs the peripheral
for boot operation.
(1) Software can modify all PINMUX0 and PINMUX1 bit fields from their defaults.
(2) In addition to pin mux control, PCIEN also affects the internal pullup/down resistors of the PCI capable pins. When PCIEN = 0, internal
pullup/down resistors on the PCI capable pins are enabled. When PCIEN = 1, internal pullup/down resistors on the PCI capable pins are
disabled to be compliant to the PCI Local Bus Specification Revision 2.3.