Texas instruments TMS320DM641 Data Manual
TMS320DM641/TMS320DM640
Video/Imaging Fixed-Point Digital
Signal Processors
Data Manual
Literature Number: SPRS222F
June 2003 − Revised October 2010
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
This page intentionally left blank
Revision History
Revision History
This data sheet revision history highlights the technical changes made to the SPRS222E device-specific data
sheet to make it an SPRS222F revision.
PAGE(s)
NO.
82 Added note for VOH and VOL.
ADDS/CHANGES/DELETES
June 2003 − Revised October 2010 SPRS222F
3
Contents
Contents
Section Page
1 Device Overview 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Description 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Device Characteristics 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Device Compatibility 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Functional Block Diagram 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 CPU (DSP Core) Description 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6.1 CPU Core Registers 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Memory Map Summary 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7.1 L2 Architecture Expanded 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 Bootmode 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9 Pin Assignments 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.1 Pin Map 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.2 Signal Groups Description 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9.3 Terminal Functions 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10 Development 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10.1 Development Support 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10.2 Device Support 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10.2.1 Device and Development-Support Tool Nomenclature 65. . . . . . . . .
1.10.2.2 Documentation Support 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10.2.3 Device Silicon Revision 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Device Configurations 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Configurations at Reset 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 Peripheral Selection at Device Reset 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 Device Configuration at Device Reset 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Configurations After Reset 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 Peripheral Selection After Device Reset 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Peripheral Configuration Lock 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Device Status Register Description 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Multiplexed Pin Configurations 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Debugging Considerations 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Configuration Examples 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Device Operating Conditions 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Absolute Maximum Ratings Over Operating Case Temperature Range 82. . . . . . . . . . . . . . . . . .
3.2 Recommended Operating Conditions 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and
4 DM641/DM640 Peripheral Information and Electrical Specifications 84. . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Parameter Information 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Case Temperature 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 Parameter Information Device-Specific Information 84. . . . . . . . . . . . . . . . . . . . . . .
4.1.1.1 Signal Transition Levels 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1.2 Signal Transition Rates 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
June 2003 − Revised October 2010SPRS222F
Contents
Section Page
4.1.1.3 AC Transient Rise/Fall Time Specifications 85. . . . . . . . . . . . . . . . . .
4.1.1.4 Timing Parameters and Board Routing Analysis 85. . . . . . . . . . . . . .
4.2 Recommended Clock and Control Signal Transition Behavior 86. . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Power Supplies 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1 Power-Supply Sequencing 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.2 Power-Supply Design Considerations 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.3 Power-Supply Decoupling 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.4 Peripheral Power-Down Operation 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.5 Power-Down Modes Logic 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.6 Triggering, Wake-up, and Effects 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.7 C64x Power-Down Mode with an Emulator 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Enhanced Direct Memory Access (EDMA) Controller 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1 EDMA Device-Specific Information 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1.1 EDMA Channel Synchronization Events 90. . . . . . . . . . . . . . . . . . . . .
4.4.2 EDMA Peripheral Register Description(s) 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Interrupts 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.1 Interrupt Sources and Interrupt Selector 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2 Interrupts Peripheral Register Description(s) 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.3 External Interrupts Electrical Data/Timing 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Reset 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6.1 Reset Electrical Data/Timing 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Clock PLL 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1 Clock PLL Device-Specific Information 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.2 Clock PLL Electrical Data/Timing (Input and Output Clocks) 101. . . . . . . . . . . . . . .
4.8 External Memory Interface (EMIIF) 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.1 EMIF Device-Specific Information 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.2 EMIF Peripheral Register Description(s) 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.3 EMIF Electrical Data/Timing 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.3.1 Asynchronous Memory Timing 106. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.3.2 Programmable Synchronous Interface Timing 109. . . . . . . . . . . . . . .
4.8.3.3 Synchronous DRAM Timing 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.3.4 HOLD
/HOLDA Timing 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.3.5 BUSREQ Timing 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Multichannel Audio Serial Port (McASP0) Peripheral 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.1 McASP0 Device-Specific Information 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.1.1 McASP Block Diagram 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.2 McASP0 Peripheral Register Description(s) 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.3 McASP0 Electrical Data/Timing 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9.3.1 Multichannel Audio Serial Port (McASP) Timing 125. . . . . . . . . . . . .
4.10 Inter-Integrated Circuit (I2C) 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10.1 I2C Device-Specific Information 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10.2 I2C Peripheral Register Description(s) 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10.3 I2C Electrical Data/Timing 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10.3.1 Inter-Integrated Circuits (I2C) Timing 131. . . . . . . . . . . . . . . . . . . . . . .
4.11 Host-Port Interface (HPI) [DM641 Only] 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11.1 HPI Peripheral Register Description(s) [DM641 Only] 133. . . . . . . . . . . . . . . . . . . .
4.11.2 Host-Port Interface (HPI) Electrical Data/Timing [DM641 Only] 133. . . . . . . . . . . .
June 2003 − Revised October 2010 SPRS222F
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4.12 Multichannel Buffered Serial Port (McBSP) 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12.1 McBSP Peripheral Register Description(s) 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12.2 McBSP Electrical Data/Timing 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12.2.1 Multichannel Buffered Serial Port (McBSP) Timing 139. . . . . . . . . . .
4.13 Video Port 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.1 Video Port Device-Specific Information 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.2 Video Port Peripheral Register Description(s) 146. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.3 Video Port (VP0 [DM641/DM640], VP1 [DM641 Only]) Electrical
Data/Timing 149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.3.1 VCLKIN Timing (Video Capture Mode) 149. . . . . . . . . . . . . . . . . . . . .
4.13.3.2 Video Data and Control Timing (Video Capture Mode) 150. . . . . . . .
4.13.3.3 VCLKIN Timing (Video Display Mode) 151. . . . . . . . . . . . . . . . . . . . . .
4.13.3.4 Video Control Input/Output and Video Display Data Output
Timing With Respect to VPxCLKINx and VPxCLKOUTx
(Video Display Mode) 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13.3.5 Video Dual-Display Sync Mode Timing (With Respect to
VPxCLKINx) 153. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 VCXO Interpolated Control (VIC) 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14.1 VIC Device-Specific Information 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14.2 VIC Peripheral Register Description(s) 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14.3 VIC Electrical Data/Timing 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14.3.1 STCLK Timing 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 Ethernet Media Access Controller (EMAC) 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15.1 EMAC Device-Specific Information 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15.2 EMAC Peripheral Register Description(s) 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15.3 EMAC Electrical Data/Timing 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 Management Data Input/Output (MDIO) 162. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16.1 Device-Specific Information 162. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16.2 Peripheral Register Description(s) 162. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16.3 Management Data Input/Output (MDIO) Electrical Data/Timing 163. . . . . . . . . . . .
4.17 Timer 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17.1 Timer Device-Specific Information 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17.2 Timer Peripheral Register Description(s) 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17.3 Timer Electrical Data/Timing 165. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 General-Purpose Input/Output (GPIO) 166. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18.1 GPIO Device-Specific Information 166. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18.2 GPIO Peripheral Register Description(s) 167. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18.3 General-Purpose Input/Output (GPIO) Electrical Data/Timing 167. . . . . . . . . . . . .
4.19 JTAG 168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19.1 JTAG Device-Specific Information 168. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19.1.1 IEEE 1149.1 JTAG Compatibility Statement 168. . . . . . . . . . . . . . . . .
4.19.1.2 JTAG ID Register Description 168. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19.2 JTAG Peripheral Register Description(s) 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19.3 JTAG Test-Port Electrical Data/Timing 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Mechanical Data 170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Thermal Data 170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
June 2003 − Revised October 2010SPRS222F
Figures
List of Figures
Figure Page
1−1 Functional Block Diagram 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2 TMS320C64x CPU (DSP Core) Data Paths 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−3 TMS320DM641/DM640 L2 Architecture Memory Configuration 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−4 DM641/DM640 Pin Map [Quadrant A] 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−5 CPU and Peripheral Signals 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−6 Peripheral Signals 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−7 TMS320DM64x DSP Device Nomenclature (Including the DM641 and DM640 Devices) 66. . . . . . . . . .
2−1 Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000 − 0x01B3F003] 70. . . .
2−2 VP1, VP0, McBSP1, and McBSP0 Pin Muxing 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 Peripheral Enable/Disable Flow Diagram 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] − Read/Write Accesses 73. . . . . . . .
2−5 Device Status Register (DEVSTAT) Description − 0x01B3 F004 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Configuration Example A for DM641 (2 8-Bit Video Ports + 1 McASP0 + VIC + I2C0 + EMIF) 78. . . . .
2−7 Configuration Example B for DM641 (1 McASP0 + 2 McBSPs + VIC + I2C0 + EMIF) 79. . . . . . . . . . . . .
2−8 Configuration Example A for DM640 (1 8-Bit Video Port + 1 McASP0 + VIC + I2C0 + EMIF) 80. . . . . .
2−9 Configuration Example B for DM640 (1 McASP0 + 2 McBSPs + VIC + I2C0 + EMIF) 81. . . . . . . . . . . . .
4−1 Test Load Circuit for AC Timing Measurements 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Input and Output Voltage Reference Levels for AC Timing Measurements 84. . . . . . . . . . . . . . . . . . . . . .
4−3 Rise and Fall Transition Time Voltage Reference Levels 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 AC Transient Specification Rise Time 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 AC Transient Specification Fall Time 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 Board-Level Input/Output Timings 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 Schottky Diode Diagram 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 Power-Down Mode Logic 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−9 PWRD Field of the CSR Register 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10 External/NMI Interrupt Timing 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−11 Reset Timing 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−12 External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode 100. . . . . . . . . . . . . . . . . . . . .
4−13 CLKIN Timing 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−14 CLKOUT4 Timing 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−15 CLKOUT6 Timing 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−16 AECLKIN Timing for EMIFA 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−17 AECLKOUT1 Timing for the EMIFA Module 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−18 AECLKOUT2 Timing for the EMIFA Module 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−19 Asynchronous Memory Read Timing for EMIFA 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−20 Asynchronous Memory Write Timing for EMIFA 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−21 Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2) 110. . . . . . . . .
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7
Figures
Figure Page
4−22 Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0) 111. . . . . . . . .
4−23 Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1) 112. . . . . . . . .
4−24 SDRAM Read Command (CAS Latency 3) for EMIFA 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−25 SDRAM Write Command for EMIFA 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−26 SDRAM ACTV Command for EMIFA 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−27 SDRAM DCAB Command for EMIFA 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−28 SDRAM DEAC Command for EMIFA 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−29 SDRAM REFR Command for EMIFA 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−30 SDRAM MRS Command for EMIFA 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−31 SDRAM Self-Refresh Timing for EMIFA 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−32 HOLD
/HOLDA Timing for EMIFA 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−33 BUSREQ Timing for EMIFA 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−34 McASP0 Configuration 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−35 McASP Input Timings 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−36 McASP Output Timings 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−37 I2C0 Module Block Diagram 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−38 I2C Receive Timings 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−39 I2C Transmit Timings 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−40 HPI16 Read Timing (HAS Not Used, Tied High) [DM641 Only] 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−41 HPI16 Read Timing (HAS Used) [DM641 Only] 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−42 HPI16 Write Timing (HAS Not Used, Tied High) [DM641 Only] 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−43 HPI16 Write Timing (HAS Used) [DM641 Only] 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−44 McBSP Timing 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−45 FSR Timing When GSYNC = 1 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−46 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 142. . . . . . . . . . . . . . . . . . . . . . . . . .
4−47 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 143. . . . . . . . . . . . . . . . . . . . . . . . . .
4−48 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 144. . . . . . . . . . . . . . . . . . . . . . . . . .
4−49 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 145. . . . . . . . . . . . . . . . . . . . . . . . . .
4−50 Video Port Capture VPxCLKINx TIming 149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−51 Video Port Capture Data and Control Input Timing 150. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−52 Video Port Display VPxCLKINx Timing 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−53 Video Port Display Data Output Timing and Control Input/Output Timing With Respect to
VPxCLKINx and VPxCLKOUTx 152. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−54 Video Port Dual-Display Sync Timing 153. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−55 STCLK Timing 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−56 MRCLK Timing (EMAC − Receive) 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−57 MTCLK Timing (EMAC − Transmit) 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−58 EMAC Receive Interface Timing 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−59 EMAC Transmit Interface Timing 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−60 MDIO Input Timing 163. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−61 MDIO Output Timing 163. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−62 Timer Timing 165. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
June 2003 − Revised October 2010SPRS222F
Figures
Figure Page
4−63 GPIO Enable Register (GPEN) [Hex Address: 01B0 0000] 166. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−64 GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004] 166. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−65 GPIO Port Timing 167. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−66 JTAG ID Register Description − TMS320DM641/DM640 Register Value − 0x0007 902F 168. . . . . . . . .
4−67 JTAG Test-Port Timing 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
June 2003 − Revised October 2010 SPRS222F
9
Tables
List of Tables
Table Page
1−1 Characteristics of the DM641 Processor 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−2 Characteristics of the DM640 Processor 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−3 Peripherals Available on the DM641 and DM640 Devices 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−4 L2 Cache Registers (C64x) 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−5 TMS320DM641/DM640 Memory Map Summary 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1−6 Terminal Functions 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−1 MAC_EN Peripheral Selection (EMAC and MDIO) 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 DM641/DM640 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], and
TOUT0/MAC_EN) 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 Peripheral Configuration (PERCFG) Register Selection Bit Descriptions 70. . . . . . . . . . . . . . . . . . . . . . . .
2−4 PCFGLOCK Register Selection Bit Descriptions − Read Accesses 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 PCFGLOCK Register Selection Bit Descriptions − Write Accesses 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Device Status (DEVSTAT) Register Selection Bit Descriptions 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 DM641/DM640 Device Multiplexed Pin Configurations 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 Board-Level Timing Example 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Characteristics of the Power-Down Modes 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 TMS320DM641/DM640 EDMA Channel Synchronization Events 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 EDMA Registers (C64x) 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Quick DMA (QDMA) and Pseudo Registers 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 EDMA Parameter RAM (C64x) 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 DM641/DM640 DSP Interrupts 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 Interrupt Selector Registers (C64x) 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−9 Timing Requirements for External Interrupts 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10 Timing Requirements for Reset 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−11 Switching Characteristics Over Recommended Operating Conditions During Reset 97. . . . . . . . . . . . . .
4−12 TMS320DM641/DM640 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical
Lock Time 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−13 Timing Requirements for CLKIN for −400 Devices 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−14 Timing Requirements for CLKIN for −500 Devices 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−15 Timing Requirements for CLKIN for −600 Devices 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−16 Switching Characteristics Over Recommended Operating Conditions for CLKOUT4 102. . . . . . . . . . . . .
4−17 Switching Characteristics Over Recommended Operating Conditions for CLKOUT6 103. . . . . . . . . . . . .
4−18 Timing Requirements for AECLKIN for EMIFA 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−19 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the
EMIFA Module 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−20 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the
EMIFA Module 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−21 EMIFA Registers 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−22 Timing Requirements for Asynchronous Memory Cycles for EMIFA Module 106. . . . . . . . . . . . . . . . . . . .
4−23 Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory
Cycles for EMIFA Module 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−24 Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module 109. . . . . . .
4−25 Switching Characteristics Over Recommended Operating Conditions for Programmable
Synchronous Interface Cycles for EMIFA Module 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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June 2003 − Revised October 2010SPRS222F
Tables
Table Page
4−26 Timing Requirements for Synchronous DRAM Cycles for EMIFA Module 113. . . . . . . . . . . . . . . . . . . . . .
4−27 Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM
Cycles for EMIFA Module 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−28 Timing Requirements for the HOLD
/HOLDA Cycles for EMIFA Module 119. . . . . . . . . . . . . . . . . . . . . . . .
4−29 Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
Cycles for EMIFA Module 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−30 Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles
for EMIFA Module 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−31 McASP0 Control Registers 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−32 McASP0 Data Registers 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−33 Timing Requirements for McASP 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−34 Switching Characteristics Over Recommended Operating Conditions for McASP 126. . . . . . . . . . . . . . .
4−35 I2C0 Registers 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−36 Timing Requirements for I2C Timings 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−37 Switching Characteristics for I2C Timings 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−38 HPI Registers [DM641 Only] 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−39 Timing Requirements for Host-Port Interface Cycles [DM641 Only] 133. . . . . . . . . . . . . . . . . . . . . . . . . . .
4−40 Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface
Cycles [DM641 Only] 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−41 McBSP 0 Registers 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−42 McBSP 1 Registers 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−43 Timing Requirements for McBSP 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−44 Switching Characteristics Over Recommended Operating Conditions for McBSP 140. . . . . . . . . . . . . . .
4−45 Timing Requirements for FSR When GSYNC = 1 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−46 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 142. . . . . . . . . .
4−47 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 0 142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−48 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 143. . . . . . . . . .
4−49 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 0 143. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−50 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 144. . . . . . . . . .
4−51 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 1 144. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−52 Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 145. . . . . . . . . .
4−53 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 1 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−54 Video Port 0 and 1 (VP0 and VP1) Control Registers 146. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−55 Timing Requirements for Video Capture Mode for VPxCLKINx 149. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−56 Timing Requirements in Video Capture Mode for Video Data and Control Inputs 150. . . . . . . . . . . . . . . .
4−57 Timing Requirements for Video Display Mode for VPxCLKINx 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−58 Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to
VPxCLKINx and VPxCLKOUTx 151. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−59 Switching Characteristics Over Recommended Operating Conditions in Video Display Mode
for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx 152. . . . . .
4−60 Timing Requirements for Dual-Display Sync Mode for VPxCLKINx 153. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−61 VCXO Interpolated Control (VIC) Port Registers 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−62 Timing Requirments for STCLK 155. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−63 Ethernet MAC (EMAC) Control Registers 156. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−64 EMAC Statistics Registers 159. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−65 EMAC Wrapper 159. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
June 2003 − Revised October 2010 SPRS222F
11
Tables
Table Page
4−66 EWRAP Registers 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−67 Timing Requirements for MRCLK 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−68 Timing Requirements for MTCLK 160. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−69 Timing Requirements for EMAC MII Receive 10/100 Mbit/s 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−70 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit
10/100 Mbit/s 161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−71 MDIO Registers 162. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−72 Timing Requirements for MDIO Input 163. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−73 Switching Characteristics Over Recommended Operating Conditions for MDIO Output 163. . . . . . . . . .
4−74 Timer 0 Registers 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−75 Timer 1 Registers 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−76 Timer 2 Registers 164. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−77 Timing Requirements for Timer Inputs 165. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−78 Switching Characteristics Over Recommended Operating Conditions for Timer Outputs 165. . . . . . . . .
4−79 GP0 Registers 167. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−80 Timing Requirements for GPIO Inputs 167. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−81 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs 167. . . . . . . . .
4−82 JTAG ID Register Selection Bit Descriptions 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−83 JTAG ID Register 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−84 Timing Requirements for JTAG Test Port 169. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−85 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port 169. . . . . . . .
5−1 Thermal Resistance Characteristics (S-PBGA Package) [GDK] 170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 Thermal Resistance Characteristics (S-PBGA Package) [GNZ] 170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
June 2003 − Revised October 2010SPRS222F
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Tables
June 2003 − Revised October 2010 SPRS222F
13
Device Overview
1 Device Overview
1.1 Features
D High-Performance Digital Media Processor
(TMS320DM641/TMS320DM640)
− 2.5-, 2-, 1.67-ns Instruction Cycle Time
− 400-, 500-, 600-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− 3200, 4000, 4800 MIPS
− Fully Software-Compatible With C64x™
D VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x™ DSP Core
− Eight Highly Independent Functional
Units With VelociTI.2™ Extensions:
− Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
− Load-Store Architecture With
Non-Aligned Support
− 64 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
D Instruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− VelociTI.2™ Increased Orthogonality
D L1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 1M-Bit (128K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible RAM/Cache Allocation)
D Endianess: Little Endian, Big Endian
D 32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
− 1024M-Byte Total Addressable External
Memory Space
D Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
D 10/100 Mb/s Ethernet MAC (EMAC)
− IEEE 802.3 Compliant
− Media Independent Interface (MII)
− 8 Independent Transmit (TX) Channels
and 1 Receive (RX) Channel
D Management Data Input/Output (MDIO)
D Two Configurable Video Ports (DM641)
D One Configurable Video Port (DM640)
− Providing a Glueless I/F to Common
Video Decoder and Encoder Devices
− Supports Multiple Resolutions and Video
Standards
D VCXO Interpolated Control Port (VIC)
− Supports Audio/Video Synchronization
D Host-Port Interface (HPI) [16-Bit] (DM641)
D Multichannel Audio Serial Port (McASP)
− Four Serial Data Pins
− Wide Variety of I2S and Similar Bit
Stream Format
− Integrated Digital Audio I/F Transmitter
Supports S/PDIF, IEC60958-1, AES-3,
CP-430 Formats
D Inter-Integrated Circuit (I
2
C) Bus
D Two Multichannel Buffered Serial Ports
D Three 32-Bit General-Purpose Timers
D Eight General-Purpose I/O (GPIO) Pins
D Flexible PLL Clock Generator
D IEEE-1149.1 (JTAG
Boundary-Scan-Compatible
†
)
D 548-Pin Ball Grid Array (BGA) Package
(GDK and ZDK Suffixes), 0.8-mm Ball Pitch
D 548-Pin Ball Grid Array (BGA) Package
(GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
D 0.13-μm/6-Level Cu Metal Process (CMOS)
D 3.3-V I/O, 1.2-V Internal (-400, -500)
D 3.3-V I/O, 1.4-V Internal (-600)
C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
14
June 2003 − Revised October 2010SPRS222F
1.2 Description
The TMS320C64x™ DSPs (including the TMS320DM641 and TMS320DM640 devices) are the
highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM641
(DM641) and TMS320DM640 (DM640) devices are based on the second-generation high-performance,
advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas
Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a
code-compatible member of the C6000™ DSP platform.
With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM641
device offers cost-effective solutions to high-performance DSP programming challenges.
With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the DM640
device offers cost-effective solutions to high-performance DSP programming challenges.
The DM641/DM640 DSP possesses the operational flexibility of high-speed controllers and the numerical
capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit
word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic
logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units
include new instructions to accelerate the performance in video and imaging applications and extend the
parallelism of the VelociTI™ architecture. The DM641 can produce four 16-bit multiply-accumulates (MACs)
per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of
4800 MMACS. The DM640 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of
1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The
DM641/DM640 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000™ DSP platform devices.
Description
The DM641/DM640 uses a two-level cache-based architecture and has a powerful and diverse set of
peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache
(L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1-Mbit memory
space that is shared between program and data space. L2 memory can be configured as mapped memory,
cache, or combinations of the two. The peripheral set includes: two configurable video ports (DM641); one
configurable video port (DM640); a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output
(MDIO) module; a VCXO interpolated control port (VIC); one 4-bit multichannel buffered audio serial port
(McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs);
three 32-bit general-purpose timers; a 16-bit host-port interface (HPI16) [DM641]; an 8-pin general-purpose
input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external
memory interface (EMIF A), which is capable of interfacing to synchronous and asynchronous memories and
peripherals.
The DM641 device has two single-channel 8-bit configurable video port peripherals (VP0 and VP1). The
DM640 device has one single-channel 8-bit configurable video port peripheral (VP0). These video port
peripherals provide a glueless interface to common video decoder and encoder devices. The DM641/DM640
video port peripherals support multiple resolutions and video standards (e. g., CCIR601 and ITU−BT.656).
These video port peripherals are configurable and can support either video capture and/or video display
modes.
For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated
Control (VIC) Port Reference Guide (literature number SPRU629).
The McASP0 port supports one transmit and one receive clock zone, with four serial data pins which can be
individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin
from 2 to 32 time slots. The DM641/DM640 has sufficient bandwidth to support all 4 serial data pins
transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple
serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S)
format.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
June 2003 − Revised October 2010 SPRS222F
15
Description
In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3,
CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user
data and channel status fields.
McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit
for each high-frequency master clock which verifies that the master clock is within a programmed frequency
range.
The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits to
up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port,
see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature
number SPRU629).
The ethernet media access controller (EMAC) provides an efficient interface between the DM641/DM640 DSP
core processor and the network. The DM641/DM640 EMAC support both 10Base-T and 100Base-TX, or 10
Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of
service (QOS) support. The DM641/DM640 EMAC makes use of a custom interface to the DSP core that
allows ef ficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP
Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference
Guide (literature number SPRU628).
The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO
module transparently monitors its link state by reading the PHY status register. Link change events are stored
in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device
without continuously performing costly MDIO accesses. For more details on the MDIO, see the
TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO)
Module Reference Guide (literature number SPRU628).
The I2C0 port on the TMS320DM641/DM640 allows the DSP to easily control peripheral devices and
communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may
be used to communicate with serial peripheral interface (SPI) mode peripheral devices.
The DM641/DM640 has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into
source code execution.
Windows is a registered trademark of the Microsoft Corporation.
16
June 2003 − Revised October 2010SPRS222F
Device Characteristics
available at the same time
available at the same time
(For more detail, see the
section).
Voltage
Voltage
BGA Package
1.3 Device Characteristics
Table 1−1 provides an overview of the DM641 DSP. The table shows significant features of the DM641 device,
including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin
count.
Table 1−1. Characteristics of the DM641 Processor
HARDWARE FEATURES DM641
EMIFA (32-bit bus width)
(clock source = AECLKIN)
EDMA (64 independent channels) 1
McASP0 (uses Peripheral Clock [AUXCLK]) 1
Peripherals
Not all peripherals pins are
(For more detail, see the
Device Configuration
On-Chip Memory
CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x0C01
JTAG BSDL_ID JTAGID register (address location: 0x01B3F008) 0x0007902F
Frequency MHz 500, 600
Cycle Time ns
PLL Options CLKIN frequency multiplier Bypass (x1), x6, x12
Process Technology μm 0.13 μm
Product Status
†
On this DM64x™ device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device
speed portion of this data sheet.
‡
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
‡
I2C0 (uses Peripheral Clock) 1
HPI (16-bit) 1 (HPI16)
McBSPs
(internal clock source = CPU/4 clock frequency)
Configurable Video Ports (VP0 and VP1) 2
10/100 Ethernet MAC (EMAC) 1
Management Data Input/Output (MDIO) 1
VCXO Interpolated Control Port (VIC) 1
32-Bit Timers
(internal clock source = CPU/8 clock frequency)
General-Purpose Input/Output Port (GP0) 8
Size (Bytes) 160K
16K-Byte (16KB) L1 Program (L1P) Cache
Organization
Core (V)
I/O (V) 3.3 V
23 x 23 mm 548-Pin BGA (GDK and ZDK)
27 x 27 mm 548-Pin BGA (GNZ and ZNZ)
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
16KB L1 Data (L1D) Cache
128KB Unified Mapped RAM/Cache (L2)
2 ns (DM641-500)
[500-MHz CPU, 100 MHz EMIF†]
1.67 ns (DM641-600)
[600-MHz CPU, 133 MHz EMIF†]
1
2
3
1.2 V (-500)
1.4 V (-600)
PD
June 2003 − Revised October 2010 SPRS222F
17
Device Characteristics
Peripherals
Peripherals
Not all peripherals pins are
(For more detail, see the
Device Configuration
Voltage
BGA Package
Table 1−2 provides an overview of the DM640 DSP. The table shows significant features of the DM640 device,
including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin
count.
Table 1−2. Characteristics of the DM640 Processor
HARDWARE FEATURES DM640
EMIFA (32-bit bus width)
(clock source = AECLKIN)
EDMA (64 independent channels) 1
McASP0 (uses Peripheral Clock [AUXCLK]) 1
I2C0 (uses Peripheral Clock) 1
Not all peripherals pins are
available at the same time
Device Configuration
section).
On-Chip Memory
CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x0C01
JTAG BSDL_ID JTAGID register (address location: 0x01B3F008) 0x0007902F
Frequency MHz 400
Cycle Time ns
PLL Options CLKIN frequency multiplier Bypass (x1), x6, x12
Process Technology μm 0.13 μm
Product Status
†
On this DM64x™ device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device
speed portion of this data sheet.
‡
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
‡
McBSPs
(internal clock source = CPU/4 clock frequency)
Configurable Video Port (VP0) 1
10/100 Ethernet MAC (EMAC) 1
Management Data Input/Output (MDIO) 1
VCXO Interpolated Control Port (VIC) 1
32-Bit Timers
(internal clock source = CPU/8 clock frequency)
General-Purpose Input/Output Port (GP0) 8
Size (Bytes) 160K
16K-Byte (16KB) L1 Program (L1P) Cache
Organization
Core (V) 1.2 V (-400)
I/O (V) 3.3 V
23 x 23 mm 548-Pin BGA (GDK and ZDK)
27 x 27 mm 548-Pin BGA (GNZ and ZNZ)
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
16KB L1 Data (L1D) Cache
128KB Unified Mapped RAM/Cache (L2)
2.5 ns (DM640-400)
[400-MHz CPU, 100 MHz EMIF†]
1
2
3
PD
18
June 2003 − Revised October 2010SPRS222F
1.4 Device Compatibility
The DM641/DM640 device is a code-compatible member of the C6000™ DSP platform.
The C64x™ DSP generation of devices has a diverse and powerful set of peripherals. The common peripheral
set and pin-compatibility that the DM641 and DM640 devices offer lead to easier system designs and faster
time to market.
The DM640 device is a sub-set of the DM641 device and does not support an HPI peripheral or a second Video
Port (VP1) peripheral. Table 1−3 identifies the peripherals that are available on the DM641 and DM640
devices.
Table 1−3. Peripherals Available on the DM641 and DM640 Devices
EMIFA (32-bit bus width) √ √
EDMA (64 independent channels) √ √
10/100 EMAC √ √
MDIO √ √
HPI (16-bit) √ —
McBSPs (McBSP0, McBSP1) √ √
McASP (4-bit) √ √
8-bit Video Port (VP0) √ √
8-bit Video Port (VP1) √ —
VIC √ √
I2C √ √
Timers (32-bit) [TIMER0, TIMER1, TIMER2] √ √
GPIOs (GP[7:0]) √ √
†
— denotes peripheral/coprocessor is not available on this device.
‡
Not all peripherals pins are available at the same time. (For more details, see the Device
Configuration section.)
Device Compatibility
†‡
PERIPHERALS/COPROCESSORS DM641 DM640
1.5 Functional Block Diagram
Figure 1−1 shows the functional block diagram of the DM641/DM640 devices.
June 2003 − Revised October 2010 SPRS222F
19
Functional Block Diagram
SDRAM
SBSRAM
ZBT SRAM
FIFO
SRAM
ROM/FLASH
I/O Devices
See Note A
32
EMIF A
Timer 2
Timer 1
Timer 0
VCXO
Interpolated
Control Port
(VIC)
8-Bit
VP0
OR
McBSP0
AND
McASP0
Control
8-Bit
†
VP1
OR
McBSP1
‡
A Register File
Enhanced
DMA
Controller
(EDMA)
‡
L2
Cache
Memory
128KBytes
.L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2
TMS320DM641/TMS320DM640
L1P Cache
Direct-Mapped
16K Bytes Total
C64x DSP Core
Instruction Fetch
Instruction Dispatch
Advanced Instruction Packet
Instruction Decode
Data Path A
A31−A16
A15−A0
Data Path B
B Register File
B31−B16
B15−B0
Control
Registers
Control
Logic
Test
Advanced
In-Circuit
Emulation
Interrupt
Control
AND
McASP0
Data
†
HPI
L1D Cache 2-Way Set-Associative
16K Bytes Total
PLL
(x1, x6, x12)
Power-Down
Logic
EMAC
MDIO
8
16
†
HPI and VP1 are not supported on the DM640 device.
‡
McBSPs: Framing Chips − H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs
GP0
I2C0
Boot Configuration
NOTE A: The Video Port 0 (VP0) peripheral is muxed with the McBSP0 peripheral and the McASP0 control pins (DM641/DM640). The Video
Port 1 (VP1) peripheral is muxed with the McBSP1 peripheral and the McASP0 data pins (DM641 only). For more details on the
multiplexed pins of these peripherals, see the Device Configurations section of this data sheet.
Figure 1−1. Functional Block Diagram
20
June 2003 − Revised October 2010SPRS222F
1.6 CPU (DSP Core) Description
The CPU fetches VelociTI™ advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to
eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI™ VLIW architecture
features controls by which all eight units do not have to be supplied with instructions if they are not ready to
execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute
packet as the previous instruction, or whether it should be executed in the following clock as a part of the next
execute packet. Fetch packets are always 256 bits wide; however , the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other
VLIW architectures. The C64x™ VelociTI.2™ extensions add enhancements to the TMS320C62x™ DSP
VelociTI™ architecture. These enhancements include:
• Register file enhancements
• Data path extensions
• Quad 8-bit and dual 16-bit extensions with data flow enhancements
• Additional functional unit hardware
• Increased orthogonality of the instruction set
• Additional instructions that reduce code size and increase register flexibility
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register
files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the
packed 16-bit and 32-/40-bit fixed-point data types found in the C62x™ VelociTI™ VLIW architecture, the
C64x™ register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional
units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP
core) diagram, and Figure 1−2]. The four functional units on each side of the CPU can freely share the 32
registers belonging to that side. Additionally, each side features a “data cross path”—a single data bus
connected to all the registers on the other side, by which the two sets of functional units can access data from
the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock
cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in
the same execute packet. All functional units in the C64x CPU can access operands via the data cross path.
Register access by functional units on the same side of the CPU as the register file can service all the units
in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read
a register via a data cross path if that register was updated in the previous clock cycle.
CPU (DSP Core) Description
In addition to the C62x™ DSP fixed-point instructions, the C64x™ DSP includes a comprehensive collection
of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2™ extensions allow the C64x CPU
to operate directly on packed data to streamline data flow and increase instruction set efficiency. This is a key
factor for video and imaging applications.
Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file.
The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single
instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits)
with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access
words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes
using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most
can access any one of the 64 registers. Some registers, however, are singled out to support specific
addressing modes or to hold the condition for conditional instructions (if the condition is not automatically
“true”).
TMS320C62x and C62x are trademarks of Texas Instruments.
June 2003 − Revised October 2010 SPRS222F
21
CPU (DSP Core) Description
The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two
16 × 16-bit multiplies or four 8 ×8-bit multiplies per clock cycle. The .M unit can also perform 16 ×32-bit multiply
operations, dual 16 × 16-bit multiplies with add/subtract operations, and quad 8 × 8-bit multiplies with add
operations. In a ddition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies,
and bidirectional variable shift hardware.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual
16-bit, and quad 8-bit operations.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. A C64x™ DSP device enhancement
now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x™/TMS320C67x™ DSP
devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in
the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the
C64x™ DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the
NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute
packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective
functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the
execute packets from the current fetch packet have been dispatched. After decoding, the instructions
simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock
cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes,
half-words, or doublewords. All load and store instructions are byte-, half-word-, word-, or
doubleword-addressable.
For more details on the C64x CPU functional units enhancements, see the following documents:
• TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189)
• TMS320C64x Technical Overview (literature number SPRU395)
TMS320C67x is a trademark of Texas Instruments.
22
June 2003 − Revised October 2010SPRS222F
Data Path A
ST1b (Store Data)
ST1a (Store Data)
LD1b (Load Data)
LD1a (Load Data)
DA1 (Address)
32 MSBs
32 LSBs
32 MSBs
32 LSBs
src1
.L1
src2
long dst
long src
long src
long dst
src1
.S1
src2
long dst
long dst
src1
.M1
src2
src2
src1
.D1
src2
dst
dst
dst
dst
dst
CPU (DSP Core) Description
8
8
8
8
Register
File A
(A0−A31)
See Note A
See Note A
2X
Data Path B
DA2 (Address)
LD2a (Load Data)
LD2b (Load Data)
ST2a (Store Data)
ST2b (Store Data)
32 LSBs
32 MSBs
32 MSBs
32 LSBs
src2
.D2
src1
src2
src1
.M2
long dst
src2
.S2
src1
long dst
long src
long src
long dst
src2
.L2
src1
dst
dst
dst
dst
1X
See Note A
See Note A
Register
File B
(B0− B31)
8
8
8
8
Control Register
File
NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs.
Figure 1−2. TMS320C64x™ CPU (DSP Core) Data Paths
June 2003 − Revised October 2010 SPRS222F
23
CPU (DSP Core) Description
1.6.1 CPU Core Registers
T able 1−4. L2 Cache Registers (C64x)
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0184 0000 CCFG Cache configuration register
0184 0004 − 0184 0FFC − Reserved
0184 1000 EDMAWEIGHT L2 EDMA access control register
0184 1004 − 0184 1FFC − Reserved
0184 2000 L2ALLOC0 L2 allocation register 0
0184 2004 L2ALLOC1 L2 allocation register 1
0184 2008 L2ALLOC2 L2 allocation register 2
0184 200C L2ALLOC3 L2 allocation register 3
0184 2010 − 0184 3FFC − Reserved
0184 4000 L2WBAR L2 writeback base address register
0184 4004 L2WWC L2 writeback word count register
0184 4010 L2WIBAR L2 writeback invalidate base address register
0184 4014 L2WIWC L2 writeback invalidate word count register
0184 4018 L2IBAR L2 invalidate base address register
0184 401C L2IWC L2 invalidate word count register
0184 4020 L1PIBAR L1P invalidate base address register
0184 4024 L1PIWC L1P invalidate word count register
0184 4030 L1DWIBAR L1D writeback invalidate base address register
0184 4034 L1DWIWC L1D writeback invalidate word count register
0184 4038 − 0184 4044 − Reserved
0184 4048 L1DIBAR L1D invalidate base address register
0184 404C L1DIWC L1D invalidate word count register
0184 4050 − 0184 4FFC − Reserved
0184 5000 L2WB L2 writeback all register
0184 5004 L2WBINV L2 writeback invalidate all register
0184 5008 − 0184 7FFC − Reserved
0184 8000 −0184 81FC
0184 8200 MAR128 Controls EMIFA CE0 range 8000 0000 − 80FF FFFF
0184 8204 MAR129 Controls EMIFA CE0 range 8100 0000 − 81FF FFFF
0184 8208 MAR130 Controls EMIFA CE0 range 8200 0000 − 82FF FFFF
0184 820C MAR131 Controls EMIFA CE0 range 8300 0000 − 83FF FFFF
0184 8210 MAR132 Controls EMIFA CE0 range 8400 0000 − 84FF FFFF
0184 8214 MAR133 Controls EMIFA CE0 range 8500 0000 − 85FF FFFF
0184 8218 MAR134 Controls EMIFA CE0 range 8600 0000 − 86FF FFFF
0184 821C MAR135 Controls EMIFA CE0 range 8700 0000 − 87FF FFFF
0184 8220 MAR136 Controls EMIFA CE0 range 8800 0000 − 88FF FFFF
0184 8224 MAR137 Controls EMIFA CE0 range 8900 0000 − 89FF FFFF
0184 8228 MAR138 Controls EMIFA CE0 range 8A00 0000 − 8AFF FFFF
0184 822C MAR139 Controls EMIFA CE0 range 8B00 0000 − 8BFF FFFF
0184 8230 MAR140 Controls EMIFA CE0 range 8C00 0000 − 8CFF FFFF
0184 8234 MAR141 Controls EMIFA CE0 range 8D00 0000 − 8DFF FFFF
MAR0 to
MAR127
Reserved
24
June 2003 − Revised October 2010SPRS222F
Table 1−4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE COMMENTSREGISTER NAMEACRONYM
0184 8238 MAR142 Controls EMIFA CE0 range 8E00 0000 − 8EFF FFFF
0184 823C MAR143 Controls EMIFA CE0 range 8F00 0000 − 8FFF FFFF
0184 8240 MAR144 Controls EMIFA CE1 range 9000 0000 − 90FF FFFF
0184 8244 MAR145 Controls EMIFA CE1 range 9100 0000 − 91FF FFFF
0184 8248 MAR146 Controls EMIFA CE1 range 9200 0000 − 92FF FFFF
0184 824C MAR147 Controls EMIFA CE1 range 9300 0000 − 93FF FFFF
0184 8250 MAR148 Controls EMIFA CE1 range 9400 0000 − 94FF FFFF
0184 8254 MAR149 Controls EMIFA CE1 range 9500 0000 − 95FF FFFF
0184 8258 MAR150 Controls EMIFA CE1 range 9600 0000 − 96FF FFFF
0184 825C MAR151 Controls EMIFA CE1 range 9700 0000 − 97FF FFFF
0184 8260 MAR152 Controls EMIFA CE1 range 9800 0000 − 98FF FFFF
0184 8264 MAR153 Controls EMIFA CE1 range 9900 0000 − 99FF FFFF
0184 8268 MAR154 Controls EMIFA CE1 range 9A00 0000 − 9AFF FFFF
0184 826C MAR155 Controls EMIFA CE1 range 9B00 0000 − 9BFF FFFF
0184 8270 MAR156 Controls EMIFA CE1 range 9C00 0000 − 9CFF FFFF
0184 8274 MAR157 Controls EMIFA CE1 range 9D00 0000 − 9DFF FFFF
0184 8278 MAR158 Controls EMIFA CE1 range 9E00 0000 − 9EFF FFFF
0184 827C MAR159 Controls EMIFA CE1 range 9F00 0000 − 9FFF FFFF
0184 8280 MAR160 Controls EMIFA CE2 range A000 0000 − A0FF FFFF
0184 8284 MAR161 Controls EMIFA CE2 range A100 0000 − A1FF FFFF
0184 8288 MAR162 Controls EMIFA CE2 range A200 0000 − A2FF FFFF
0184 828C MAR163 Controls EMIFA CE2 range A300 0000 − A3FF FFFF
0184 8290 MAR164 Controls EMIFA CE2 range A400 0000 − A4FF FFFF
0184 8294 MAR165 Controls EMIFA CE2 range A500 0000 − A5FF FFFF
0184 8298 MAR166 Controls EMIFA CE2 range A600 0000 − A6FF FFFF
0184 829C MAR167 Controls EMIFA CE2 range A700 0000 − A7FF FFFF
0184 82A0 MAR168 Controls EMIFA CE2 range A800 0000 − A8FF FFFF
0184 82A4 MAR169 Controls EMIFA CE2 range A900 0000 − A9FF FFFF
0184 82A8 MAR170 Controls EMIFA CE2 range AA00 0000 − AAFF FFFF
0184 82AC MAR171 Controls EMIFA CE2 range AB00 0000 − ABFF FFFF
0184 82B0 MAR172 Controls EMIFA CE2 range AC00 0000 − ACFF FFFF
0184 82B4 MAR173 Controls EMIFA CE2 range AD00 0000 − ADFF FFFF
0184 82B8 MAR174 Controls EMIFA CE2 range AE00 0000 − AEFF FFFF
0184 82BC MAR175 Controls EMIFA CE2 range AF00 0000 − AFFF FFFF
0184 82C0 MAR176 Controls EMIFA CE3 range B000 0000 − B0FF FFFF
0184 82C4 MAR177 Controls EMIFA CE3 range B100 0000 − B1FF FFFF
0184 82C8 MAR178 Controls EMIFA CE3 range B200 0000 − B2FF FFFF
0184 82CC MAR179 Controls EMIFA CE3 range B300 0000 − B3FF FFFF
0184 82D0 MAR180 Controls EMIFA CE3 range B400 0000 − B4FF FFFF
0184 82D4 MAR181 Controls EMIFA CE3 range B500 0000 − B5FF FFFF
0184 82D8 MAR182 Controls EMIFA CE3 range B600 0000 − B6FF FFFF
0184 82DC MAR183 Controls EMIFA CE3 range B700 0000 − B7FF FFFF
0184 82E0 MAR184 Controls EMIFA CE3 range B800 0000 − B8FF FFFF
CPU (DSP Core) Description
June 2003 − Revised October 2010 SPRS222F
25
CPU (DSP Core) Description
Table 1−4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE COMMENTSREGISTER NAMEACRONYM
0184 82E4 MAR185 Controls EMIFA CE3 range B900 0000 − B9FF FFFF
0184 82E8 MAR186 Controls EMIFA CE3 range BA00 0000 − BAFF FFFF
0184 82EC MAR187 Controls EMIFA CE3 range BB00 0000 − BBFF FFFF
0184 82F0 MAR188 Controls EMIFA CE3 range BC00 0000 − BCFF FFFF
0184 82F4 MAR189 Controls EMIFA CE3 range BD00 0000 − BDFF FFFF
0184 82F8 MAR190 Controls EMIFA CE3 range BE00 0000 − BEFF FFFF
0184 82FC MAR191 Controls EMIFA CE3 range BF00 0000 − BFFF FFFF
0184 8300 −0184 83FC
0184 8400 −0187 FFFF − Reserved
MAR192 to
MAR255
Reserved
26
June 2003 − Revised October 2010SPRS222F
1.7 Memory Map Summary
Table 1−5 shows the memory map address ranges of the DM641/DM640 device. Internal memory is always
located at address 0 and can be used as both program and data memory. The external memory address
ranges in the DM641/DM640 device begin at the hex address location 0x8000 0000 for EMIF A.
T able 1−5. TMS320DM641/DM640 Memory Map Summary
Memory Map Summary
MEMORY BLOCK DESCRIPTION
Internal RAM (L2) 128K
Reserved 768K
Reserved 23M
External Memory Interface A (EMIFA) Registers 256K
L2 Registers 256K
HPI Registers (DM641 only)
McBSP 0 Registers 256K
McBSP 1 Registers 256K
Timer 0 Registers 256K
Timer 1 Registers 256K
Interrupt Selector Registers 256K
EDMA RAM and EDMA Registers 256K
Reserved 512K
Timer 2 Registers 256K
GP0 Registers 256K − 4K
Device Configuration Registers 4K
I2C0 Data and Control Registers 16K
Reserved 32K
McASP0 Control Registers 16K
Reserved 192K
Reserved 256K
Emulation 256K
Reserved 256K
VP0 Control 16K
VP1 Control (DM641 only)
Reserved 32K
Reserved 192K
EMAC Control 4K
EMAC Wrapper 8K
EWRAP Registers 2K
MDIO Control Registers 2K
Reserved 3.5M
QDMA Registers 52
Reserved 928M – 52
McBSP 0 Data 64M
†
For the DM640 device, these memory address locations are reserved.The DM640 device does not support the HPI and VP1 peripherals.
†
†
BLOCK SIZE
(BYTES)
256K
16K
HEX ADDRESS RANGE
0000 0000 – 0001 FFFF
0004 0000 – 000F FFFF
0010 0000 – 017F FFFF
0180 0000 – 0183 FFFF
0184 0000 – 0187 FFFF
0188 0000 – 018B FFFF
018C 0000 – 018F FFFF
0190 0000 – 0193 FFFF
0194 0000 – 0197 FFFF
0198 0000 – 019B FFFF
019C 0000 – 019F FFFF
01A0 0000 – 01A3 FFFF
01A4 0000 – 01AB FFFF
01AC 0000 – 01AF FFFF
01B0 0000 – 01B3 EFFF
01B3 F000 – 01B3 FFFF
01B4 0000 – 01B4 3FFF
01B4 4000 – 01B4 BFFF
01B4 C000 – 01B4 FFFF
01B5 0000 – 01B7 FFFF
01B8 0000 – 01BB FFFF
01BC 0000 – 01BF FFFF
01C0 0000 – 01C3 FFFF
01C4 0000 – 01C4 3FFF
01C4 4000 – 01C4 7FFF
01C4 8000 – 01C4 FFFF
01C5 0000 – 01C7 FFFF
01C8 0000 – 01C8 0FFF
01C8 1000 – 01C8 2FFF
01C8 3000 – 01C8 37FF
01C8 3800 – 01C8 3FFF
01C8 4000 – 01FF FFFF
0200 0000 – 0200 0033
0200 0034 – 2FFF FFFF
3000 0000 – 33FF FFFF
June 2003 − Revised October 2010 SPRS222F
27
Memory Map Summary
Table 1−5. TMS320DM641/DM640 Memory Map Summary (Continued)
MEMORY BLOCK DESCRIPTION HEX ADDRESS RANGE
McBSP 1 Data 64M
Reserved 64M
McASP0 Data 1M
Reserved 64M − 1M
Reserved 832M
VP0 Channel A Data 32M
Reserved 32M
VP1 Channel A Data (DM641 only)
Reserved 32M
Reserved 64M
EMIFA CE0 256M
EMIFA CE1 256M
EMIFA CE2 256M
EMIFA CE3 256M
Reserved 1G
†
For the DM640 device, these memory address locations are reserved.The DM640 device does not support the HPI and VP1 peripherals.
†
BLOCK SIZE
(BYTES)
32M
3400 0000 – 37FF FFFF
3800 0000 – 3BFF FFFF
3C00 0000 – 3C0F FFFF
3C10 0000 – 3FFF FFFF
4000 0000 – 73FF FFFF
7400 0000 – 75FF FFFF
7600 0000 – 77FF FFFF
7800 0000 – 79FF FFFF
7A00 0000 – 7BFF FFFF
7C00 0000 – 7FFF FFFF
8000 0000 – 8FFF FFFF
9000 0000 – 9FFF FFFF
A000 0000 – AFFF FFFF
B000 0000 – BFFF FFFF
C000 0000 – FFFF FFFF
28
June 2003 − Revised October 2010SPRS222F
1.7.1 L2 Architecture Expanded
Figure 1−3 shows the detail of the L2 architecture on the TMS320DM641/DM640 devices. For more
information on the L2MODE bits, see the cache configuration (CCFG) register bit field descriptions in the
TMS320C64x Two-Level Internal Memory Reference Guide (literature number SPRU610).
Memory Map Summary
L2MODE
000
†
L2 Memory Block Base Address
011010001
64K-Byte RAM
64K SRAM
96K SRAM
128K SRAM (All)
(4 Way)
32K Cache
†
The L2MODE = 111b is not supported on the DM641/DM640 devices.
64K Cache (4 Way)
128K Cache (4 Way)
32K-Byte RAM
32K-Byte RAM
Figure 1−3. TMS320DM641/DM640 L2 Architecture Memory Configuration
0x0000 0000
0x0001 0000
0x0001 8000
0x0001 FFFF
0x0002 0000
June 2003 − Revised October 2010 SPRS222F
29
Bootmode
1.8 Bootmode
The DM641/DM640 device resets using the active-low signal RESET. While RESET is low, the device is held
in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and
states of device pins during reset. The release of RESET starts the processor running with the prescribed
device configuration and boot mode.
The DM641 has three types of boot modes while the DM640 has only two types of boot modes:
• Host boot [DM641 only]
If host boot is selected, upon release of RESET, the CPU is internally “stalled” while the remainder of the
device is released. During this period, an external host can initialize the CPU’s memory space as
necessary through the host interface, including internal configuration registers, such as those that control
the EMIF or other peripherals. For the DM641 device, the HPI peripheral is used for host boot. Once the
host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete
the boot process. This transition causes the boot configuration logic to bring the CPU out of the “stalled”
state. The CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU,
because it o c c u r s w h i l e t h e C P U i s still internally “stalled”. Also, DSPINT brings the CPU out of the “stalled”
state only if the host boot process is selected. All memory may be written to and read by the host. This
allows for the host to verify what it sends to the DSP if required. After the CPU is out of the “stalled” state,
the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
• EMIF boot (using default ROM timings)
Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0
by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be
stored in the endian format that the system is using. In this case, the EMIF automatically assembles
consecutive 8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done
by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block
transfer, the CPU is released from the “stalled” state and starts running from address 0.
• No boot
With no boot, the CPU begins direct execution from the memory located at address 0. Note: operation is
undefined if invalid code is located at address 0.
30
June 2003 − Revised October 2010SPRS222F
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