Texas Instruments TMS320C6670 Data Manual

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

Data Manual

PRODUCT ION DATA infor mation is current as of p ublication dat e.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Literature Number: SPRS689D

March 2012

TMS320C6670

Data Manual

SPRS689D—March 2012

Release History

Revision Date Description/Comments

D March 2012

C October 2011

B August 2011

A April 2011

SPRS689 February 2011 Initial Release

Updated PASS PLL section (block diagram, PASS PLL Control Register, and initialization sequence)

Updated Switch Fabric Matrix tables with bridge numbers and added Switch Fabric block diagrams

Updated the JTAGID register table

Restricted Output_Divide of SECCTL to max value of divide by 2

Changed TPTCn to EDMA3TCn and TPCCn to EDMA3CCn throughout the data manual

Replaced all INTC with CIC and CPT with Tracer throughout the document

Updated main PLL lock time

Added DDR3PLL and PASS PLL Reset bits in DDR3PLLCTL1 and PASSPLLCTL1 registers

Added the DDR3PLL and PASSPLL Initialization Sequence

Added po_vcon_smpserr_intr SmartReflex event

Corrected the SPI and DDR3/Hyperbridge Config Memory Map end address

Added DEVSPEED Register section

Removed Parameter Information section from chapter 7 as the content was not relevant

Added more description to Boot Sequence section

Changed all footnote references from CORECLK to SYSCLK1

Corrected the typo in the address of MACID2

Re-arranged the wording for description of SYSCLK1

Removed example from footnote

Updated footnote on AIF jitter value to 4 ps RMS

Revised the INTC1 Events Input table, description for BWADJ field, and power sequencing timing tables and diagrams

Removed all mentions of HHV and the Max parameters for PHY Sync and Radio Sync Pulses

Updated the GMacs and GFlops for 1.2 GHz and changed output skew time for the trace from 500 ps to 1ns

Added thermal values to the thermal resistance characteristics table, and Power Supply to Peripheral I/O Mapping table

Added register and field description table for DDR3PLLCTL1, PASSPLLCTL1, and SerDes status and config registers

Corrected RESET electrical timing parameters

Updated all PLL block Diagrams – Main PLL, DDR PLL, and PASS PLL

Completed all tables in Device Operating Conditions chapter

Updated/Added Master and Priv ID tables, added MasterID Settings table

Added MMR space

Updated the power-up sequencing section. RESETFULL

Updated the description of VARIANT bit field in JTAGID register

Added Setup and Hold times for RP1CLK and RP1CLK signals, and BWADJ field to DDR3PLLCTL and PASSPLLCTL

Corrected the size of TETBs for the 4 cores from 16k to 4k

Added RSV0A and RSV0B pins to the terminal list table

Revised power rail terminology and changed reference parameter in t2c description from t7 to t6

Added a note on Level Interrupts and EOI values for various modules

Corrected the address range for I

must always de-assert after POR

2

C MMRs and corrected extended temp max to 100C from 105C

www.ti.com

For detailed revision information, see ‘‘Revision History’’ on page A-219.

2 Release History Copyright 2012 Texas Instruments Incorporated

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

www.ti.com

SPRS689D—March 2012

Contents

1 TMS320C6670 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

1.1 KeyStone Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

1.2 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

1.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

2 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.1 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.2 Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.3 Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

2.4 Boot Modes Supported and PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

2.4.1 Boot Device Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

2.4.2 Device Configuration Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

2.4.3 PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

2.5 Second-Level Bootloaders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

2.6 Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

2.6.1 Package Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

2.6.2 Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

2.7 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

2.8 Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

2.8.1 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

2.8.2 Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

2.9 Related Documentation from Texas Instruments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

3 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

3.1 Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

3.2 Peripheral Selection After Device Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

3.3 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

3.3.1 Device Status (DEVSTAT) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

3.3.2 Device Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

3.3.3 JTAG ID (JTAGID) Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

3.3.4 Kicker Mechanism (KICK0 and KICK1) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

3.3.7 Reset Status (RESET_STAT) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

3.3.8 Reset Status Clear (RESET_STAT_CLR) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

3.3.9 Boot Complete (BOOTCOMPLETE) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

3.3.10 Power State Control (PWRSTATECTL) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

3.3.11 NMI Event Generation to CorePac (NMIGRx) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

3.3.12 IPC Generation (IPCGRx) Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

3.3.13 IPC Acknowledgement (IPCARx) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

3.3.14 IPC Generation Host (IPCGRH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

3.3.15 IPC Acknowledgement Host (IPCARH) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

3.3.16 Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

3.3.17 Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

3.3.18 Reset Mux (RSTMUXx) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

3.3.19 Device Speed (DEVSPEED) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

3.4 Pullup/Pulldown Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

4 System Interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

4.1 Internal Buses and Switch Fabrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

4.2 Switch Fabric Connections Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

4.3 TeraNet Switch Fabric Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

4.4 Bus Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

5 C66x CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

5.1 Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

5.1.1 L1P Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

5.1.2 L1D Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.1.3 L2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Copyright 2012 Texas Instruments Incorporated Contents 3

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

5.1.4 MSM SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.1.5 L3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.2 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.3 Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.4 Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

5.5 CorePac Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

5.6 C66x CorePac Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6 Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

6.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

6.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

6.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

6.4 Power Supply to Peripheral I/O Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7 TMS320C6670 Peripheral Information and Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

7.1 Recommended Clock and Control Signal Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

7.2 Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

7.2.1 Power-Up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

7.2.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

7.2.3 Power Supply Decoupling and Bulk Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

7.2.4 SmartReflex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

7.3 Power Sleep Controller (PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

7.3.1 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

7.3.2 Clock Domains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

7.3.3 PSC Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

7.4 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

7.4.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

7.4.2 Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.4.3 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7.4.4 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

7.4.5 Reset Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.4.6 Reset Controller Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.4.7 Reset Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

7.5 Main PLL and the PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7.5.1 Main PLL Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

7.5.2 PLL Controller Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

7.5.3 Main PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

7.5.4 Main PLL and PLL Controller Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

7.5.5 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

7.6 DDR3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

7.6.1 DDR3 PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

7.6.2 DDR3 PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

7.6.3 DDR3 PLL Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

7.6.4 DDR3 PLL Input Clock Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

7.7 PASS PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

7.7.1 PASS PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

7.7.2 PASS PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

7.7.3 PASS PLL Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

7.7.4 PASS PLL Input Clock Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

7.8 Enhanced Direct Memory Access (EDMA3) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

7.8.1 EDMA3 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

7.8.2 EDMA3 Channel Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

7.8.3 EDMA3 Transfer Controller Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

7.8.4 EDMA3 Channel Synchronization Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

7.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

7.9.1 Interrupt Sources and Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

7.9.2 CIC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

7.9.3 Inter-Processor Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

7.9.4 NMI

7.9.5 External Interrupts Electrical Data/Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

and LRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

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4 Contents Copyright 2012 Texas Instruments Incorporated

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

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7.10 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

7.10.1 MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

7.10.2 MPU Programmable Range Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

7.11 DDR3 Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

7.11.1 DDR3 Memory Controller Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

7.11.2 DDR3 Memory Controller Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

2

7.12 I

7.13 SPI Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

7.14 HyperLink Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

7.15 UART Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

7.16 PCIe Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

7.17 Packet Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

7.18 Security Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

7.19 Gigabit Ethernet (GbE) Switch Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

7.20 Management Data Input/Output (MDIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

7.21 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

7.22 Rake Search Accelerator (RSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

7.23 Enhanced Viterbi-Decoder Coprocessor (VCP2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

7.24 Turbo Decoder Coprocessor (TCP3d). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

7.25 Turbo Encoder Coprocessor (TCP3e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

7.26 Bit Rate Coprocessor (BCP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

7.27 Serial RapidIO (SRIO) Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

7.28 General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

7.29 Semaphore2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

7.30 Antenna Interface Subsystem 2 (AIF2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

7.31 Receive Accelerator Coprocessor (RAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

7.32 Transmit Accelerator Coprocessor (TAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

7.33 Fast Fourier Transform Coprocessor (FFTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

7.34 Emulation Features and Capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

7.12.1 I2C Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

7.12.2 I

7.12.3 I2C Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

7.13.1 SPI Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

7.21.1 Timers Device-Specific Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

7.21.2 Timers Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

7.28.1 GPIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

7.28.2 GPIO Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

7.34.1 Advanced Event Triggering (AET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

7.34.2 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

7.34.3 IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

2

C Peripheral Register Description(s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

A Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

B Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

B.1 Thermal Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

B.2 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

SPRS689D—March 2012

Copyright 2012 Texas Instruments Incorporated Contents 5

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

www.ti.com

List of Figures

Figure 1-1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Figure 2-1 CPU (DSP Core) Data Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 2-2 Boot Mode Pin Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 2-3 No Boot Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 2-4 Serial Rapid I/O Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 2-5 Ethernet (SGMII) Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 2-6 PCI Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 2-7 I
Figure 2-8 I

Figure 2-9 SPI Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 2-10 HyperLink Boot Device Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 2-11 CYP 841-PIN BGA Package (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 2-12 Pin Map Quadrants (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 2-13 Upper Left Quadrant—A (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 2-14 Upper Right Quadrant—B (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 2-15 Lower Right Quadrant—C (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 2-16 Lower Left Quadrant—D (Bottom View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 2-17 C66x™ DSP Device Nomenclature (including the TMS320C6670 DSP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 3-1 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 3-2 Device Configuration Register (DEVCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Figure 3-3 JTAG ID (JTAGID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 3-4 LRESETNMI PIN Status Register (LRSTNMIPINSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Figure 3-5 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 3-6 Reset Status Register (RESET_STAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Figure 3-7 Reset Status Clear Register (RESET_STAT_CLR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Figure 3-8 Boot Complete Register (BOOTCOMPLETE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Figure 3-9 Power State Control Register (PWRSTATECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Figure 3-10 NMI Generation Register (NMIGRx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Figure 3-11 IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Figure 3-12 IPC Acknowledgement Registers (IPCARx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Figure 3-13 IPC Generation Registers (IPCGRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Figure 3-14 IPC Acknowledgement Register (IPCARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Figure 3-15 Timer Input Selection Register (TINPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Figure 3-16 Timer Output Selection Register (TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Figure 3-17 Reset Mux Register (RSTMUX0 through RSTMUX3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Figure 3-18 Device Speed Register (DEVSPEED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Figure 4-1 TeraNet 3A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Figure 4-2 TeraNet 2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Figure 4-3 TeraNet 3P and 3M and 2M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Figure 4-4 TeraNet 3P_A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Figure 4-5 TeraNet 3P_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Figure 4-6 TeraNet 6P_B and 3P_Tracer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Figure 4-7 Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Figure 5-1 C66x CorePac Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Figure 5-2 L1P Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Figure 5-3 L1D Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Figure 5-4 L2 Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

Figure 5-5 CorePac Revision ID Register (MM_REVID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Figure 7-1 Core Before IO Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

Figure 7-2 IO Before Core Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

Figure 7-3 SmartReflex 4-Pin VID Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

Figure 7-4 RESETFULL

2

C Master Mode Device Configuration Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

2

C Passive Mode Device Configuration Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

6 List of Figures Copyright 2012 Texas Instruments Incorporated

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

www.ti.com

Figure 7-5 Soft/Hard Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Figure 7-6 Boot Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Figure 7-7 Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Figure 7-8 PLL Secondary Control Register (SECCTL)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Figure 7-9 PLL Controller Divider Register (PLLDIVn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Figure 7-10 PLL Controller Clock Align Control Register (ALNCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Figure 7-11 PLLDIV Divider Ratio Change Status Register (DCHANGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Figure 7-12 SYSCLK Status Register (SYSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Figure 7-13 Reset Type Status Register (RSTYPE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Figure 7-14 Reset Control Register (RSTCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Figure 7-15 Reset Configuration Register (RSTCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Figure 7-16 Reset Isolation Register (RSISO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Figure 7-17 Main PLL Control Register (MAINPLLCTL0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Figure 7-18 Main PLL Control Register (MAINPLLCTL1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Figure 7-19 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Figure 7-20 Main PLL Transition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Figure 7-21 DDR3 PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Figure 7-22 DDR3 PLL Control Register (DDR3PLLCTL0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Figure 7-23 DDR3 PLL Control Register 1 (DDR3PLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Figure 7-24 DDR3 PLL DDRCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

Figure 7-25 PASS PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Figure 7-26 PASS PLL Control Register (PASSPLLCTL0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

Figure 7-27 PASS PLL Control Register 1 (PASSPLLCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

Figure 7-28 PASS PLL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Figure 7-29 Interrupt Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

Figure 7-30 NMI

and LRESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

Figure 7-31 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

Figure 7-32 Programmable Range n Start Address Register (PROGn_MPSAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Figure 7-33 Programmable Range n End Address Register (PROGn_MPEAR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Figure 7-34 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Figure 7-35 I
Figure 7-36 I
Figure 7-37 I

2

C Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

2

C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

2

C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

Figure 7-38 SPI Master Mode Timing Diagrams — Base Timings for 3-Pin Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

Figure 7-39 SPI Additional Timings for 4-Pin Master Mode with Chip Select Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

Figure 7-40 HyperLink Station Management Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

Figure 7-41 HyperLink Station Management Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

Figure 7-42 HyperLink Station Management Receive Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

Figure 7-43 UART Receive Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Figure 7-44 UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Figure 7-45 UART Transmit Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Figure 7-46 UART RTS (Request-to-Send Output) – Autoflow Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Figure 7-47 MACID1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Figure 7-48 MACID2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Figure 7-49 RFTCLK Select Register (CPTS_RFTCLK_SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

Figure 7-50 MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Figure 7-51 MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Figure 7-52 Timer Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Figure 7-53 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

Figure 7-54 AIF2 RP1 Frame Synchronization Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

Figure 7-55 AIF2 RP1 Frame Synchronization Burst Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214

Figure 7-56 AIF2 Physical Layer Synchronization Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

Figure 7-57 AIF2 Radio Synchronization Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

Figure 7-58 AIF2 Timer External Frame Event Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

SPRS689D—March 2012

Copyright 2012 Texas Instruments Incorporated List of Figures 7

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

Figure 7-59 Trace Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

Figure 7-60 JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

www.ti.com

8 List of Figures Copyright 2012 Texas Instruments Incorporated

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

www.ti.com

SPRS689D—March 2012

List of Tables

Table 2-1 Characteristics of the C6670 SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 2-2 Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 2-3 Boot Mode Pins: Boot Device Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 2-4 No Boot Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 2-5 Serial Rapid I/O Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 2-6 Ethernet (SGMII) Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 2-7 PCI Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 2-8 BAR Config / PCIe Window Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 2-9 I
Table 2-10 I

Table 2-11 SPI Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 2-12 HyperLink Boot Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 2-13 C66x CorePac System PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 2-14 I/O Functional Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 2-15 Terminal Functions — Signals and Control by Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 2-16 Terminal Functions — Power and Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Table 2-17 Terminal Functions — By Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 2-18 Terminal Functions — By Ball Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Table 3-1 Device Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 3-2 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 3-3 Device Status Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 3-4 Device Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 3-5 JTAG ID Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 3-6 LRESETNMI PIN Status Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 3-7 LRESETNMI PIN Status Clear Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 3-8 Reset Status Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 3-9 Reset Status Clear Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Table 3-10 Boot Complete Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Table 3-11 Power State Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Table 3-12 NMI Generation Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 3-13 IPC Generation Registers Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 3-14 IPC Acknowledgement Registers Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 3-15 IPC Generation Registers Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 3-16 IPC Acknowledgement Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 3-17 Timer Input Selection Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Table 3-18 Timer Output Selection Field Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 3-19 Reset Mux Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 3-20 Device Speed Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Table 4-1 Switch Fabric Connection Matrix Section 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 4-2 Switch Fabric Connection Matrix Section 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Table 4-3 Switch Fabric Connection Matrix Section 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Table 4-4 Packed DMA Priority Allocation Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Table 5-1 Available Memory Page Protection Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Table 5-2 CorePac Revision ID Register (MM_REVID) Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Table 6-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105

Table 6-2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Table 6-3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Table 6-4 Power Supply to Peripheral I/O Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108

Table 7-1 Power Supply Rails on the TMS320C6670. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Table 7-2 Core Before IO Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Table 7-3 IO Before Core Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Table 7-4 Clock Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

2

C Master Mode Device Configuration Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

2

C Passive Mode Device Configuration Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Copyright 2012 Texas Instruments Incorporated List of Tables 9

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

Table 7-5 SmartReflex 4-Pin VID Interface Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

Table 7-6 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Table 7-7 Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

Table 7-8 PSC Register Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Table 7-9 Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

Table 7-10 Reset Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Table 7-11 Reset Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Table 7-12 Boot Configuration Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

Table 7-13 Main PLL Stabilization, Lock, and Reset Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

Table 7-14 PLL Controller Registers (Including Reset Controller). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131

Table 7-15 PLL Secondary Control Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132

Table 7-16 PLL Controller Divider Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Table 7-17 PLL Controller Clock Align Control Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133

Table 7-18 PLLDIV Divider Ratio Change Status Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Table 7-19 SYSCLK Status Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Table 7-20 Reset Type Status Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

Table 7-21 Reset Control Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Table 7-22 Reset Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136

Table 7-23 Reset Isolation Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

Table 7-24 Main PLL Control Register (MAINPLLCTL0) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Table 7-25 Main PLL Control Register (MAINPLLCTL1) Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138

Table 7-26 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Table 7-27 DDR3 PLL Control Register 0 Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Table 7-28 DDR3 PLL Control Register 1 Field Descriptions (DDR3PLLCTL1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143

Table 7-29 DDR3 PLL DDRCLK(N|P) Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144

Table 7-30 PASS PLL Control Register 0 Field Descriptions (PASSPLLCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

Table 7-31 PASS PLL Control Register 1 Field Descriptions (PASSPLLCTL1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

Table 7-32 PASS PLL Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Table 7-33 EDMA3 Channel Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Table 7-34 EDMA3 Transfer Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Table 7-35 EDMA3CC0 Events for C6670 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Table 7-36 EDMA3CC1 Events for C6670 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151

Table 7-37 EDMA3CC2 Events for C6670 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152

Table 7-38 System Event Mapping — C66x CorePac Primary Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156

Table 7-39 CIC0 Event Inputs — C66x CorePac Secondary Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160

Table 7-40 CIC1 Event Inputs (Secondary Events for EDMA3CC1 and EDMA3CC2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165

Table 7-41 CIC2 Event Inputs (Secondary Events for EDMA3CC0 and HyperLink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Table 7-42 CIC0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

Table 7-43 CIC1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

Table 7-44 CIC2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

Table 7-45 IPC Generation Registers (IPCGRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

Table 7-46 LRESET
Table 7-47 NMI

Table 7-48 MPU Default Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

Table 7-49 MPU Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

Table 7-50 Master ID Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

Table 7-51 Privilege ID Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

Table 7-52 MPU0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

Table 7-53 MPU1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

Table 7-54 MPU2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

Table 7-55 MPU3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

Table 7-56 MPU4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186

Table 7-57 MPU5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187

Table 7-58 Configuration Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

and NMI Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

and LRESET Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

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Table 7-59 Programmable Range n Start Address Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Table 7-60 Programmable Range n Start Address Register (PROGn_MPSAR) Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Table 7-61 Programmable Range n End Address Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Table 7-62 Programmable Range n End Address Register (PROGn_MPEAR) Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

Table 7-63 Programmable Range n Memory Protection Page Attribute Register Field Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . .191

Table 7-64 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Reset Values . . . . . . . . . . . . . . . . .193

Table 7-65 I
Table 7-66 I
Table 7-67 I

2

C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196

2

C Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198

2

C Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

Table 7-68 SPI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

Table 7-69 SPI Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

Table 7-70 HyperLink Peripheral Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

Table 7-71 HyperLink Peripheral Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

Table 7-72 UART Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Table 7-73 UART Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Table 7-74 MACID1 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Table 7-75 MACID2 Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

Table 7-76 RFTCLK Select Register Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208

Table 7-77 MDIO Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Table 7-78 MDIO Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Table 7-79 Timer Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Table 7-80 Timer Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Table 7-81 GPIO Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

Table 7-82 GPIO Output Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

Table 7-83 AIF2 Timer Module Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

Table 7-84 AIF2 Timer Module Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215

Table 7-85 Trace Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

Table 7-86 JTAG Test Port Timing Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

Table 7-87 JTAG Test Port Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

Table B-1 Thermal Resistance Characteristics (PBGA Package) [CYP]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

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1 TMS320C6670 Features

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

• Four TMS320C66x™ DSP Core Subsystems, Each With
– 1.0-GHz or 1.2-GHz C66x Fixed/Floating-Point

DSP Core
› 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
› 19.2 GFlops/Core for Floating Point @ 1.2 GHz

–Memory

› 32K Byte L1P Per Core
› 32K Byte L1D Per Core
› 1024K Byte Local L2 Per Core

• Multicore Shared Memory Controller (MSMC)
– 2048KB MSM SRAM Memory Shared by Four DSP

Cores

– Memory Protection Unit for Both MSM SRAM and

DDR3_EMIF

• Hardware Coprocessors
– Three Enhanced Coprocessors for Turbo Decoding

› Supports WCDMA/HSPA/HSPA+/TD-SCDMA,

LTE, and WiMAX

› Supports up to 548 Mbps for LTE and up to

353 Mbps for WCDMA

› Low DSP Overhead – HW Interleaver Table

Generation and CRC Check

– One Enhanced Coprocessor for Turbo Encoding

› Supports up to 500 Mbps for LTE and WCDMA

– Four Viterbi Decoders

› Supports More Than 38 Mbps @ 40-bit Block

Size

– Two WCDMA Receive Acceleration Coprocessors

› Up to 256 Users @ 8 Fingers w/o Measurement

– WCDMA Transmit Acceleration Coprocessor

› Up to 256 Users with two Radio Links and

Diversity

– Three Fast Fourier Transform Coprocessors

› 2048 pt FFT in 4.8 μs

– Bit Rate Coprocessor

› WCDMA/HSPA+, TD-SCDMA, LTE, and WiMAX

Uplink and Downlink Bit Processing

› Includes Encoding, Rate Matching/Dematching,

Segmentation, Multiplexing, and More

› Supports Up To 914 Mbps for LTE and 405 Mbps

for WCDMA/TD-SCDMA

• Multicore Navigator
– 8192 Multipurpose Hardware Queues with Queue

Manager

– Packet-Based DMA for Zero-Overhead Transfers

• Network Coprocessor
– Packet Accelerator Enables Support for

› Transport Plane IPsec, GTP-U, SCTP, PDCP
› L2 User Plane PDCP (RoHC, Air Ciphering)
› 1 Gbps Wire-Speed Throughput at 1.5 M Packets

Per Second

– Security Accelerator Engine Enables Support for

› IPSec, SRTP, 3GPP and WiMAX Air Interface, and

SSL/TLS Security

› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC,

CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW
3G, SHA-1, SHA-2 (256-bit Hash), MD5

› Up to 2.8 Gbps Encryption Speed

• Four Rake/Search Accelerators (RSA) for
– Chip-Rate Processing for WCDMA Rel'99, HSDPA,

and HSDPA+

– Reed-Muller Decoding

• Peripherals
– Six-Lane SerDes-Based Antenna Interface (AIF2)

› Operating at up to 6.144 Gbps
› Compliant with OBSAI RP3 and CPRI Standards

for 3G / 4G (WCDMA, LTE TDD, LTE FDD,
TD-SCDMA, and WiMAX)

– Four Lanes of SRIO 2.1

› 5 GBaud Operation Per Lane
› Supports Direct I/O, Message Passing

– Two Lanes PCIe Gen2

› Supports Up To 5 GBaud Per Lane

– Hyperlink

› Supports Connections to Other KeyStone

Architecture Devices Providing Resource
Scalability

› Supports up to 50 Gbaud

– Gigabit Ethernet (GbE) Switch Subsystem

›Two SGMII Ports

› IEEE1588 Support
– 64-Bit DDR3 Interface with Speeds up to 1600 MHz
–UART Interface

2

–I

C Interface
– Sixteen GPIO pins
–SPI Interface
– Semaphore Module
–Eight 64-Bit Timers
– Three On-Chip PLLs

• Commercial Temperature:
– 0°C to 100°C

• Extended Temperature:
– - 40°C to 100°C

PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.

Copyright 2012 Texas Instruments Incorporated

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

www.ti.com

1.1 KeyStone Architecture

TI’s KeyStone Multicore Architecture provides a high-performance structure for integrating RISC and DSP cores
with application-specific coprocessors and I/O. KeyStone is the first of its kind in that it provides adequate internal
bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with
four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and
HyperLink.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to
the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate
available hardware. The packet-based system on a chip (SoC) uses the 2-Tbps capacity of the TeraNet switched
central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access
shared memory directly without drawing from the TeraNet’s capacity, so packet movement cannot be blocked by
memory access.

HyperLink provides a 50-GBaud chip-level interconnect that allows SoCs to work in tandem. Its low-protocol
overhead and high throughput make Hyperlink an ideal interface for chip-to-chip interconnections. Working with
Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are
running on local resources.

1.2 Device Description

The TMS320C6670 Communications Infrastructure KeyStone SoC is a member of the C66xx SoC family based on
TI's new KeyStone Multicore SoC Architecture designed specifically for high performance wireless infrastructure
applications. The C6670 provides a very high performance macro basestation platform for developing all wireless
standards including WCDMA/HSPA/HSPA+, TD-SCDMA, GSM, TDD-LTE, FDD-LTE, and WiMAX. Even with
aggregate data rates for 20-MHz LTE systems above 400 Mbps per sector, the C6670 can support two sectors running
at full rate. The C6670 also sets a new standard for clock speed with operating frequencies up to 1.2 GHz.

TI's SoC architecture provides a programmable platform integrating various subsystems (C66x CorePacs, IP
network, radio layers 1 and 2, and transport processing) and uses a queue-based communication system that allows
the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet Switch
that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high speed
IO, to each operate at maximum efficiency with no blocking or stalling.

TI's new C66x core launches a new era of DSP technology by combining fixed-point and floating-point
computational capability in the processor without sacrificing speed, size, or power consumption. The
raw computational performance is an industry-leading 32 GMACS/core and 16 Gflops/core (@ 1.2 GHz operating
frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core
incorporates 90 new instructions targeted for floating-point (FPi) and vector-math-oriented (VPi) processing.
These enhancements yield tremendous performance improvements in multi-antenna 4.8G signal processing for
algorithms like MIMO and beamforming.

The C6670 contains many wireless basestation coprocessors to offload the bulk of the processing demands of layer 1
and layer 2 base station processing. This keeps the cores free for receiver algorithms and other differentiating
functions. The SoC contains multiple copies of key coprocessors such as the FFTC and TCP3d. A key coprocessor
for enabling high data rates is the bit rate coprocessor (BCP), which handles the entire downlink bit processing chain
and much of the receive bit processing.The architectural elements of the SoC (Multicore Navigator) ensure that all
the bits are processed without any CPU intervention or overhead, allowing the system to make optimal use of its
resources.

14 TMS320C6670 Features Copyright 2012 Texas Instruments Incorporated

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TI's scalable multicore SoC architecture solutions provide developers with a range of software- and
hardware-compatible devices to minimize development time and maximize reuse across all base station platforms
from Femto to Macro.

The C6670 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to
simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

SPRS689D—March 2012

Copyright 2012 Texas Instruments Incorporated TMS320C6670 Features 15

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1.3 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the TMS320C6670 device.

Figure 1-1 Functional Block Diagram

www.ti.com

Memory Subsystem

64-Bit

DDR3 EMIF

Debug & Trace

Boot ROM

Semaphore

Power

Management

PLL

EDMA

HyperLink

´3

´3

2MB

MSM

SRAM

MSMC

RSA RSA

C66x™

CorePac

32KB L1
P-Cache

1024KB L2 Cache

4 Cores @ 1.0 GHz / 1.2 GHz

TeraNet

32KB L1
D-Cache

´2

Coprocessors

RAC

TAC

VCP2

TCP3d

TCP3e

FFTC

BCP

Multicore Navigator

´2

´4

´3

´3

C6670

2

IC

Others

Queue

Manager

6

´

SPI

UART

PCIe 2

´

AIF2

´

Switch

SRIO 4

Ethernet

2

´

SGMII

Network Coprocessor

Switch

Packet

DMA

Security

Accelerator

Packet

Accelerator

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2 Device Overview

2.1 Device Characteristics

Table 2-1 provides an overview of the TMS320C6670 SoC. The table shows the significant features of the device,

including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count.

Table 2-1 Characteristics of the C6670 SoC (Part 1 of 2)

Hardware Features TMS320C6670

DDR3 memory controller (64-bit bus width) [1.5-V I/O]
(clock source = DDRREFCLKN|P)

EDMA3 (16 independent channels) [CPU/2 clock rate] 1

EDMA3 (64 independent channels) [CPU/3 clock rate] 2

High-speed 1×/2×/4× Serial RapidIO port (4 lanes) 1

Second-generation Antenna Interface (AIF2) 1

2

C 1

I

Peripherals

Encoder/Decoder
Coprocessors

Accelerators

On-Chip Memory

C66x CorePac
Revision ID

JTAG BSDL_ID JTAGID register (address location: 0x02620018)

Frequency MHz 1200 (1.2 GHz) [-1200]

Cycle Time ns 0.83 ns [-1200]

Voltage

SPI 1

PCIe (2 lanes) 1

UART 1

10/100/1000 Ethernet 2

Management Data Input/Output (MDIO) 1

64-Bit Timers (configurable)
(internal clock source = CPU/6 clock frequency)

General-Purpose Input/Output Port (GPIO) 16

VCP2 (clock source = CPU/3 clock frequency) 4

TCP3d (clock source = CPU/2 clock frequency) 3

TCP3e (clock source = CPU/3 clock frequency) 1

FFTC (clock source = CPU/3 clock frequency) 3

BCP (clock source = CPU/3 clock frequency) 1

Receive Accelerator (RAC) 2

Transmit Accelerator (TAC) 1

Rake/Search Accelerator (RSA) 4

Packet Accelerator (PA) 1

(1)

Security Accelerator

Size (Bytes) 6528K

Organization

CorePac Revision ID Register (address location: 0181 2000h) See Section 5.5 ‘‘CorePac Revision’’ on page 104.

Core (V) SmartReflex variable supply

I/O (V) 1.0 V, 1.5 V, and 1.8 V

(SA) 1

1

Eight 64-bit or Sixteen 32-bit

128KB L1 Program Memory Controller
[SRAM/Cache] 128KB L1 Data Memory Controller
[SRAM/Cache] 4096KB L2 Unified Memory/Cache
2048KB MSM SRAM
128KB L3 ROM

See Section 3.3.3 ‘‘JTAG ID (JTAGID) Register

Description’’ on page 73

1000 (1.0 GHz) [-1000]

1 ns [-1000]

Copyright 2012 Texas Instruments Incorporated Device Overview 17

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Table 2-1 Characteristics of the C6670 SoC (Part 2 of 2)

Hardware Features TMS320C6670

BGA Package 24 mm × 24 mm 841-Pin Flip-Chip Plastic BGA (CYP)

Process Technology μm 0.040 μm

Product Status

End of Table 2-1

1 The Security Accelerator function is subject to export control and will be enabled only for approved device shipments.
2 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

(2)

Product Preview (PP), Advance Information (AI),
or Production Data (PD)

PD

The C66x Central Processing Unit (CPU) extends the performance of the C64x+ and C674x CPUs through
enhancements and new features. Many of the new features target increased performance for vector processing. The
C64x+ and C674x CPUs support 2-way SIMD operations for 16-bit data and 4-way SIMD operations for 8-bit data.
On the C66x CPU, the vector processing capability is improved by extending the width of the SIMD instructions.
C66x CPUs can execute instructions that operate on 128-bit vectors. For example the QMPY32 instruction is able
to perform the element-to-element multiplication between two vectors of four 32-bit data each. The C66x CPU also
supports SIMD for floating-point operations. Improved vector processing capability (each instruction can process
multiple data in parallel) combined with the natural instruction-level parallelism of C6000 architecture (e.g
execution of up to 8 instructions per cycle) results in a very high level of parallelism that can be exploited by DSP
programmers through the use of TI's optimized C/C++ compiler.

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The C66x CPU consists of eight functional units, two register files, and two data paths as shown in Figure 2-1. The
two general-purpose register files (A and B) each contain thirty-two 32-bit registers for a total of 64 registers. The
general-purpose registers can be used for data or can be data address pointers. The data types supported include
packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Multiplies also support 128-bit data.
40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and
the remaining 8 or 32 MSBs in the next upper register (which is always an odd-numbered register). 128-bit data
values are stored in register quadruplets, with the 32 LSBs of data placed in a register that is a multiple of 4 and the
remaining 96 MSBs in the next 3 upper registers.

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction
every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set
of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and
store results from the register file into memory.

Each C66x .M unit can perform one of the following fixed-point operations each clock cycle: four 32 × 32 bit
multiplies, sixteen 16 × 16 bit multiplies, four 16 × 32 bit multiplies, four 8 × 8 bit multiplies, four 8 × 8 bit multiplies
with add operations, and four 16 × 16 multiplies with add/subtract capabilities. There is also support for Galois field
multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and modems require
complex multiplication. Each C66x .M unit can perform one 16 × 16 bit complex multiply with or without rounding
capabilities, two 16 × 16 bit complex multiplies with rounding capability, and a 32 × 32 bit complex multiply with
rounding capability. The C66x can also perform two 16 × 16 bit and one 32 × 32 bit complex multiply instructions
that multiply a complex number with a complex conjugate of another number with rounding capability.
Communication signal processing also requires an extensive use of matrix operations. Each C66x .M unit is capable
of multiplying a [1 × 2] complex vector by a [2 × 2] complex matrix per cycle with or without rounding capability.
A version also exists allowing multiplication of the conjugate of a [1 × 2] vector with a [2 × 2] complex matrix.

Each C66x .M unit also includes IEEE floating-point multiplication operations from the C674x CPU. This includes
one single-precision multiply each cycle and one double precision multiply every 4 cycles. There is also a
mixed-precision multiply that allows multiplication of a single-precision value by a double-precision value and an
operation allowing multiplication of two single-precision numbers resulting in a double-precision number. The

18 Device Overview Copyright 2012 Texas Instruments Incorporated

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C66x CPU improves the performance over the C674x double-precision multiplies by adding a instruction allowing
one double-precision multiply per cycle and also reduces the number of delay slots from ten to four. Each C66x .M
unit can also perform one the following floating-point operations each clock cycle: one, two, or four single-precision
multiplies or a complex single-precision multiply.

The .L and .S units can now support up to 64-bit operands. This allows for new versions of many of the arithmetic,
logical, and data packing instructions to allow for more parallel operations per cycle. Additional instructions were
added yielding performance enhancements of the floating point addition and subtraction instructions, including the
ability to perform one double-precision addition or subtraction per cycle. Conversion to/from integer and
single-precision values can now be done on both .L and .S units on the C66x. Also, by taking advantage of the larger
operands, instructions were also added to double the number of these conversions that can be done. The .L unit also
has additional instructions for logical AND and OR instructions, as well as 90 degree or 270 degree rotation of
complex numbers (up to two per cycle). Instructions have also been added that allow for computing the conjugate
of a complex number.

The MFENCE instruction is a new instruction introduced with the C66x DSP. This instruction creates a CPU stall
until the completion of all the CPU-triggered memory transactions, including:

• Cache line fills

• Writes from L1D to L2 or from the CorePac to MSMC and/or other system endpoints

• Victim write backs

• Block or global coherence operations

•Cache mode changes

• Outstanding XMC prefetch requests

SPRS689D—March 2012

This is useful as a simple mechanism for programs to wait for these requests to reach their endpoint. It also provides
ordering guarantees for writes arriving at a single endpoint via multiple paths, multiprocessor algorithms that
depend on ordering, and manual coherence operations.

For more details on the C66x CPU and its enhancements over the C64x+ and C674x architectures, see the following
documents (2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66):

• C66x CPU and Instruction Set Reference Guide

• C66x DSP Cache User Guide

• C66x CorePac User Guide

Copyright 2012 Texas Instruments Incorporated Device Overview 19

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Figure 2-1 shows the DSP core functional units and data paths.

Figure 2-1 CPU (DSP Core) Data Paths

www.ti.com

Note:
Default bus width
is 64 bits
(i.e. a register pair)

Data Path A

ST1

LD1

DA1

DA2

LD2

src1

.L1

src2

dst

Register

File A

(A0, A1, A2,

...A31)

src1

.S1

.M1

32

32

.D1

.D2

.M2

src2

dst

src1

src1_hi

src2

src2_hi

dst2

dst1

src1

dst

src2

src2

src1

dst1

dst2

src2_hi

src2

src1_hi

src1

dst

32

32

32

32

32

32

32

2

´

1

´

32

32

Register

File B

(B0, B1, B2,

...B31)

Data Path B

dst

.S2

ST2

.L2

66xx

20 Device Overview Copyright 2012 Texas Instruments Incorporated

src2

src1

dst

src2

src1

32

Control

Register

32

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2.2 Memory Map Summary

Table 2-2 shows the memory map address ranges of the TMS320C6670 device.

Table 2-2 Memory Map Summary (Part 1 of 9)

Logical 32 bit Address Physical 36 bit Address

Bytes DescriptionStart End Start End

0000 0000 007F FFFF 0 0000 0000 0 007F FFFF 8M Reserved

0080 0000 008F FFFF 0 0080 0000 0 008F FFFF 1M L2 SRAM

0090 0000 00DF FFFF 0 0090 0000 0 00DF FFFF 5M Reserved

00E00000 00E0 7FFF 0 00E00000 0 00E0 7FFF 32K L1P SRAM

00E08000 00EF FFFF 0 00E08000 0 00EF FFFF 1M-32K Reserved

00F00000 00F0 7FFF 0 00F00000 0 00F0 7FFF 32K L1D SRAM

00F08000 00FF FFFF 0 00F08000 0 00FF FFFF 1M-32K Reserved

0100 0000 01BF FFFF 0 0100 0000 0 01BF FFFF 12 M C66x CorePac registers

01C0 0000 01CF FFFF 0 01C0 0000 0 01CF FFFF 1M Reserved

01D0 0000 01D0 007F 0 01D0 0000 0 01D0 007F 128 Tracer 0

01D0 0080 01D0 7FFF 0 01D0 0080 0 01D0 7FFF 32K-128 Reserved

01D0 8000 01D0 807F 0 01D0 8000 0 01D0 807F 128 Tracer 1

01D0 8080 01D0 FFFF 0 01D0 8080 0 01D0 FFFF 32K-128 Reserved

01D1 0000 01D1 007F 0 01D1 0000 0 01D1 007F 128 Tracer 2

01D1 0080 01D1 7FFF 0 01D1 0080 0 01D1 7FFF 32K-128 Reserved

01D1 8000 01D1 807F 0 01D1 8000 0 01D1 807F 128 Tracer 3

01D1 8080 01D1 FFFF 0 01D1 8080 0 01D1 FFFF 32K-128 Reserved

01D2 0000 01D2 007F 0 01D2 0000 0 01D2 007F 128 Tracer 4

01D2 0080 01D2 7FFF 0 01D2 0080 0 01D2 7FFF 32K-128 Reserved

01D2 8000 01D2 807F 0 01D2 8000 0 01D2 807F 128 Tracer 5

01D2 8080 01D2 FFFF 0 01D2 8080 0 01D2 FFFF 32K-128 Reserved

01D3 0000 01D3 007F 0 01D3 0000 0 01D3 007F 128 Tracer 6

01D3 0080 01D3 7FFF 0 01D3 0080 0 01D3 7FFF 32K-128 Reserved

01D3 8000 01D3 807F 0 01D3 8000 0 01D3 807F 128 Tracer 7

01D3 8080 01D3 FFFF 0 01D3 8080 0 01D3 FFFF 32K-128 Reserved

01D4 0000 01D4 007F 0 01D4 0000 0 01D4 007F 128 Tracer 8

01D4 0080 01D4 7FFF 0 01D4 0080 0 01D4 7FFF 32K-128 Reserved

01D4 8000 01D4 807F 0 01D4 8000 0 01D4 807F 128 Tracer 9

01D4 8080 01D4 FFFF 0 01D4 8080 0 01D4 FFFF 32K-128 Reserved

01D5 0000 01D5 007F 0 01D5 0000 0 01D5 007F 128 Tracer 10

01D5 0080 01D5 7FFF 0 01D5 0080 0 01D5 7FFF 32K-128 Reserved

01D5 8000 01D5 807F 0 01D5 8000 0 01D5 807F 128 Tracer 11

01D5 8080 01D5 FFFF 0 01D5 8080 0 01D5 FFFF 32K-128 Reserved

01D6 0000 01D6 007F 0 01D6 0000 0 01D6 007F 128 Tracer 12

01D6 0080 01D6 7FFF 0 01D6 0080 0 01D6 7FFF 32K-128 Reserved

01D6 8000 01D6 807F 0 01D6 8000 0 01D6 807F 128 Tracer 13

01D6 8080 01D6 FFFF 0 01D6 8080 0 01D6 FFFF 32K-128 Reserved

01D7 0000 01D7 007F 0 01D7 0000 0 01D7 007F 128 Tracer 14

01D7 0080 01D7 7FFF 0 01D7 0080 0 01D7 7FFF 32K-128 Reserved

01D7 8000 01D7 807F 0 01D7 8000 0 01D7 807F 128 Tracer 15

TMS320C6670

SPRS689D—March 2012

Copyright 2012 Texas Instruments Incorporated Device Overview 21

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Table 2-2 Memory Map Summary (Part 2 of 9)

Logical 32 bit Address Physical 36 bit Address

Bytes DescriptionStart End Start End

01D7 8080 01D7 FFFF 0 01D7 8080 0 01D7 FFFF 32K-128 Reserved

01D8 0000 01D8 007F 0 01D8 0000 0 01D8 007F 128 Reserved

01D8 0080 01D8 7FFF 0 01D8 0080 0 01D8 7FFF 32K-128 Reserved

01D8 8000 01DF FFFF 0 01D8 8000 0 01DF FFFF 480K Reserved

01E0 0000 01E3 FFFF 0 01E0 0000 0 01E3 FFFF 256K Reserved

01E4 0000 01E7 FFFF 0 01E4 0000 0 01E7 FFFF 256K Reserved

01E8 0000 01EB FFFF 0 01E8 0000 0 01EB FFFF 256K Reserved

01EC 0000 01EF FFFF 0 01EC 0000 0 01EF FFFF 256K Reserved

01F0 0000 01F7 FFFF 0 01F0 0000 0 01F7 FFFF 512K AIF2 control

01F8 0000 01F8 FFFF 0 01F8 0000 0 01F8 FFFF 64K RAC_B - FEI control

01F9 0000 01F9 FFFF 0 01F9 0000 0 01F9 FFFF 64K RAC_B - BEI control

01FA 0000 01FB FFFF 0 01FA 0000 0 01FB FFFF 128K RAC_B - GCCP 0 control

01FC 0000 01FD FFFF 0 01FC 0000 0 01FD FFFF 128K RAC_B - GCCP 1 control

01FE 0000 01FF FFFF 0 01FE 0000 0 01FF FFFF 128K Reserved

0200 0000 020F FFFF 0 0200 0000 0 020F FFFF 1M Network Coprocessor (Packet Accelerator, Gigabit Ethernet

Switch subsystem, and Security Accelerator)

0210 0000 0210 FFFF 0 0210 0000 0 0210 FFFF 64K RAC_A - FEI control

0211 0000 0211 FFFF 0 0211 0000 0 0211 FFFF 64K RAC_A - BEI control

0212 0000 0213 FFFF 0 0212 0000 0 0213 FFFF 128K RAC_A - GCCP 0 control

0214 0000 0215 FFFF 0 0214 0000 0 0215 FFFF 128K RAC_A - GCCP 1 control

0216 0000 0217 FFFF 0 0216 0000 0 0217 FFFF 128K Reserved

0218 0000 0218 7FFF 0 0218 0000 0 0218 7FFF 32K TAC - FEI control

0218 8000 0218 FFFF 0 0218 8000 0 0218 FFFF 32K TAC- BEI control

0219 0000 0219 FFFF 0 0219 0000 0 0219 FFFF 64K TAC - SGCCP 0 control

021A 0000 021A FFFF 0 021A 0000 0 021A FFFF 64K TAC - SGCCP 1 control

021B 0000 021B FFFF 0 021B 0000 0 021B FFFF 64K Reserved

021C 0000 021C 03FF 0 021C 0000 0 021C 03FF 1K TCP3d-A

021C 0400 021C 7FFF 0 021C 0400 0 021C 7FFF 31K Reserved

021C 8000 021C 83FF 0 021C 8000 0 021C 83FF 1K TCP3d-B

021C 8400 021C FFFF 0 021C 8400 0 021C FFFF 31K Reserved

021D 0000 021D 00FF 0 021D 0000 0 021D 00FF 256 VCP2_A

021D 0100 021D 3FFF 0 021D 0100 0 021D 3FFF 16K Reserved

021D 4000 021D 40FF 0 021D 4000 0 021D 40FF 256 VCP2_B

021D 4100 021D 7FFF 0 021D 4100 0 021D 7FFF 16K Reserved

021D 8000 021D 80FF 0 021D 8000 0 021D 80FF 256 VCP2_C

021D 8100 021D BFFF 0 021D 8100 0 021D BFFF 16K Reserved

021D C000 021D C0FF 0 021D C000 0 021D C0FF 256 VCP2_D

021D C100 021D FFFF 0 021D C100 0 021D FFFF 16K Reserved

021E 0000 021E 0FFF 0 021E 0000 0 021E 0FFF 4K TCP3e

021E 1000 021E FFFF 0 021E 1000 0 021E FFFF 60K Reserved

021F 0000 021F 07FF 0 021F 0000 0 021F 07FF 2K FFTC-A configuration

021F 0800 021F 3FFF 0 021F 0800 0 021F 3FFF 14K Reserved

021F 4000 021F 47FF 0 021F 4000 0 021F 47FF 2K FFTC-B configuration

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Table 2-2 Memory Map Summary (Part 3 of 9)

Logical 32 bit Address Physical 36 bit Address

Bytes DescriptionStart End Start End

021F 4800 021F FFFF 0 021F 4800 0 021F FFFF 46K Reserved

0220 0000 0220 007F 0 0220 0000 0 0220 007F 128 Timer0

0220 0080 0220 FFFF 0 0220 0080 0 0220 FFFF 64K-128 Reserved

0221 0000 0221 007F 0 0221 0000 0 0221 007F 128 Timer1

0221 0080 0221 FFFF 0 0221 0080 0 0221 FFFF 64K-128 Reserved

0222 0000 0222 007F 0 0222 0000 0 0222 007F 128 Timer2

0222 0080 0222 FFFF 0 0222 0080 0 0222 FFFF 64K-128 Reserved

0223 0000 0223 007F 0 0223 0000 0 0223 007F 128 Timer3

0223 0080 0223 FFFF 0 0223 0080 0 0223 FFFF 64K-128 Reserved

0224 0000 0224 007F 0 0224 0000 0 0224 007F 128 Timer4

0224 0080 0224 FFFF 0 0224 0080 0 0224 FFFF 64K-128 Reserved

0225 0000 0225 007F 0 0225 0000 0 0225 007F 128 Timer5

0225 0080 0225 FFFF 0 0225 0080 0 0225 FFFF 64K-128 Reserved

0226 0000 0226 007F 0 0226 0000 0 0226 007F 128 Timer6

0226 0080 0226 FFFF 0 0226 0080 0 0226 FFFF 64K-128 Reserved

0227 0000 0227 007F 0 0227 0000 0 0227 007F 128 Timer7

0227 0080 0227 FFFF 0 0227 0080 0 0227 FFFF 64K-128 Reserved

0228 0000 0228 007F 0 0228 0000 0 0228 007F 128 Reserved

0228 0080 0228 FFFF 0 0228 0080 0 0228 FFFF 64K-128 Reserved

0229 0000 0229 007F 0 0229 0000 0 0229 007F 128 Reserved

0229 0080 0229 FFFF 0 0229 0080 0 0229 FFFF 64K-128 Reserved

022A 0000 022A 007F 0 022A 0000 0 022A 007F 128 Reserved

022A 0080 022A FFFF 0 022A 0080 0 022A FFFF 64K-128 Reserved

022B 0000 022B 007F 0 022B 0000 0 022B 007F 128 Reserved

022B 0080 022B FFFF 0 022B 0080 0 022B FFFF 64K-128 Reserved

022C 0000 022C 007F 0 022C 0000 0 022C 007F 128 Reserved

022C 0080 022C FFFF 0 022C 0080 0 022C FFFF 64K-128 Reserved

022D 0000 022D 007F 0 022D 0000 0 022D 007F 128 Reserved

022D 0080 022D FFFF 0 022D 0080 0 022D FFFF 64K-128 Reserved

022E 0000 022E 007F 0 022E 0000 0 022E 007F 128 Reserved

022E 0080 022E FFFF 0 022E 0080 0 022E FFFF 64K-128 Reserved

022F 0000 022F 007F 0 022F 0000 0 022F 007F 128 Reserved

022F 0080 022F FFFF 0 022F 0080 0 022F FFFF 64K-128 Reserved

0230 0000 0230 FFFF 0 0230 0000 0 0230 FFFF 64K Reserved

0231 0000 0231 01FF 0 0231 0000 0 0231 01FF 512 PLL controller

0231 0200 0231 FFFF 0 0231 0200 0 0231 FFFF 64K-512 Reserved

0232 0000 0232 00FF 0 0232 0000 0 0232 00FF 256 GPIO

0232 0100 0232 FFFF 0 0232 0100 0 0232 FFFF 64K-256 Reserved

0233 0000 0233 03FF 0 0233 0000 0 0233 03FF 1K SmartReflex

0233 0400 0233 FFFF 0 0233 0400 0 0233 FFFF 63K Reserved

0234 0000 0234 FFFF 0 0234 0000 0 0234 FFFF 64K Reserved

0235 0000 0235 0FFF 0 0235 0000 0 0235 0FFF 4K Power Sleep Controller (PSC)

0235 1000 0235 FFFF 0 0235 1000 0 0235 FFFF 64K-4K Reserved

TMS320C6670

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Table 2-2 Memory Map Summary (Part 4 of 9)

Logical 32 bit Address Physical 36 bit Address

Bytes DescriptionStart End Start End

0236 0000 0236 03FF 0 0236 0000 0 0236 03FF 1K Memory Protection Unit (MPU) 0

0236 0400 0236 7FFF 0 0236 0400 0 0236 7FFF 31K Reserved

0236 8000 0236 83FF 0 0236 8000 0 0236 83FF 1K Memory Protection Unit (MPU) 1

0236 8400 0236 FFFF 0 0236 8400 0 0236 FFFF 31K Reserved

0237 0000 0237 03FF 0 0237 0000 0 0237 03FF 1K Memory Protection Unit (MPU) 2

0237 0400 0237 7FFF 0 0237 0400 0 0237 7FFF 31K Reserved

0237 8000 0237 83FF 0 0237 8000 0 0237 83FF 1K Memory Protection Unit (MPU) 3

0237 8400 0237 FFFF 0 0237 8400 0 0237 FFFF 31K Reserved

0238 0000 0238 03FF 0 0238 0000 0 0238 03FF 1K Memory Protection Unit (MPU) 4

0238 0400 023F FFFF 0 0238 0400 0 023F FFFF 511K Reserved

0240 0000 0243 FFFF 0 0240 0000 0 0243 FFFF 256K Reserved

0244 0000 0244 3FFF 0 0244 0000 0 0244 3FFF 16K DSP trace formatter 0

0244 4000 0244 FFFF 0 0244 4000 0 0244 FFFF 48K Reserved

0245 0000 0245 3FFF 0 0245 0000 0 0245 3FFF 16K DSP trace formatter 1

0245 4000 0245 FFFF 0 0245 4000 0 0245 FFFF 48K Reserved

0246 0000 0246 3FFF 0 0246 0000 0 0246 3FFF 16K DSP trace formatter 2

0246 4000 0246 FFFF 0 0246 4000 0 0246 FFFF 48K Reserved

0247 0000 0247 3FFF 0 0247 0000 0 0247 3FFF 16K DSP trace formatter 3

0247 4000 0247 FFFF 0 0247 4000 0 0247 FFFF 48K Reserved

0248 0000 0248 3FFF 0 0248 0000 0 0248 3FFF 16K Reserved

0248 4000 0248 FFFF 0 0248 4000 0 0248 FFFF 48K Reserved

0249 0000 0249 3FFF 0 0249 0000 0 0249 3FFF 16K Reserved

0249 4000 0249 FFFF 0 0249 4000 0 0249 FFFF 48K Reserved

024A 0000 024A 3FFF 0 024A 0000 0 024A 3FFF 16K Reserved

024A 4000 024A FFFF 0 024A 4000 0 024A FFFF 48K Reserved

024B 0000 024B 3FFF 0 024B 0000 0 024B 3FFF 16K Reserved

024B 4000 024B FFFF 0 024B 4000 0 024B FFFF 48K Reserved

024C 0000 024C 01FF 0 024C 0000 0 024C 01FF 512 Reserved

024C 0200 024C 03FF 0 024C 0200 0 024C 03FF 1K-512 Reserved

024C 0400 024C 07FF 0 024C 0400 0 024C 07FF 1K Reserved

024C 0800 024C FFFF 0 024C 0800 0 024C FFFF 62K Reserved

024D 0000 024F FFFF 0 024D 0000 0 024F FFFF 192K Reserved

0250 0000 0250 007F 0 0250 0000 0 0250 007F 128 Reserved

0250 0080 0250 7FFF 0 0250 0080 0 0250 7FFF 32K-128 Reserved

0250 8000 0250 FFFF 0 0250 8000 0 0250 FFFF 32K Reserved

0251 0000 0251 FFFF 0 0251 0000 0 0251 FFFF 64K Reserved

0252 0000 0252 03FF 0 0252 0000 0 0252 03FF 1K Reserved

0252 0400 0252 FFFF 0 0252 0400 0 0252 FFFF 64K-1K Reserved

0253 0000 0253 007F 0 0253 0000 0 0253 007F 128 I

0253 0080 0253 FFFF 0 0253 0080 0 0253 FFFF 64K-128 Reserved

0254 0000 0254 003F 0 0254 0000 0 0254 003F 64 UART

0254 0400 0254 FFFF 0 0254 0400 0 0254 FFFF 64K-64 Reserved

0255 0000 0257 FFFF 0 0255 0000 0 0257 FFFF 192K Reserved

2

C data & control

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Table 2-2 Memory Map Summary (Part 5 of 9)

Logical 32 bit Address Physical 36 bit Address

Bytes DescriptionStart End Start End

0258 0000 025B FFFF 0 0258 0000 0 025B FFFF 256K Reserved

025C 0000 025F FFFF 0 025C 0000 0 025F FFFF 256K Reserved

0260 0000 0260 1FFF 0 0260 0000 0 0260 1FFF 8K Secondary Chip Interrupt Contoller CIC 0

0260 2000 0260 3FFF 0 0260 2000 0 0260 3FFF 8K Reserved

0260 4000 0260 5FFF 0 0260 4000 0 0260 5FFF 8K Secondary Chip Interrupt Contoller CIC 1

0260 6000 0260 7FFF 0 0260 6000 0 0260 7FFF 8K Reserved

0260 8000 0260 9FFF 0 0260 8000 0 0260 9FFF 8K Secondary Chip Interrupt Contoller CIC 2

0260 A000 0260 BFFF 0 0260 A000 0 0260 BFFF 8K Reserved

0260 C000 0260 DFFF 0 0260 C000 0 0260 DFFF 8K Reserved

0260 E000 0260 FFFF 0 0260 E000 0 0260 FFFF 8K Reserved

0261 0000 0261 FFFF 0 0261 0000 0 0261 FFFF 64K Reserved

0262 0000 0262 03FF 0 0262 0000 0 0262 03FF 1K Chip-level registers

0262 0400 0262 FFFF 0 0262 0400 0 0262 FFFF 63K Reserved

0263 0000 0263 FFFF 0 0263 0000 0 0263 FFFF 64K Reserved

0264 0000 0264 07FF 0 0264 0000 0 0264 07FF 2K Semaphore

0264 0800 0264 FFFF 0 0264 0800 0 0264 FFFF 64K-2K Reserved

0265 0000 026F FFFF 0 0265 0000 0 026F FFFF 704K Reserved

0270 0000 0270 7FFF 0 0270 0000 0 0270 7FFF 32K EDMA3 channel controller EDMA3CC0

0270 8000 0271 FFFF 0 0270 8000 0 0271 FFFF 96K Reserved

0272 0000 0272 7FFF 0 0272 0000 0 0272 7FFF 32K EDMA3 channel controller EDMA3CC1

0272 8000 0273 FFFF 0 0272 8000 0 0273 FFFF 96K Reserved

02740000 0274 7FFF 0 02740000 0 0274 7FFF 32K EDMA3 channel controller EDMA3CC2

0274 8000 0275 FFFF 0 0274 8000 0 0275 FFFF 96K Reserved

0276 0000 0276 03FF 0 0276 0000 0 0276 03FF 1K EDMA3CC0 transfer controller EDMA3TC0

0276 0400 0276 7FFF 0 0276 0400 0 0276 7FFF 31K Reserved

0276 8000 0276 83FF 0 0276 8000 0 0276 83FF 1K EDMA3CC0 transfer controller EDMA3TC1

0276 8400 0276 FFFF 0 0276 8400 0 0276 FFFF 31K Reserved

0277 0000 0277 03FF 0 0277 0000 0 0277 03FF 1K EDMA3CC1 transfer controller EDMA3TC0

0277 0400 0277 7FFF 0 0277 0400 0 0277 7FFF 31K Reserved

0277 8000 0277 83FF 0 0277 8000 0 0277 83FF 1K EDMA3CC1 transfer controller EDMA3TC1

0278 0400 0277 FFFF 0 0278 0400 0 0277 FFFF 31K Reserved

0278 0000 0278 03FF 0 0278 0000 0 0278 03FF 1K EDMA3CC1 transfer controller EDMA3TC2

0278 0400 0278 7FFF 0 0278 0400 0 0278 7FFF 31K Reserved

0278 8000 0278 83FF 0 0278 8000 0 0278 83FF 1K EDMA3CC1 transfer controller EDMA3TC3

0278 8400 0278 FFFF 0 0278 8400 0 0278 FFFF 31K Reserved

0279 0000 0279 03FF 0 0279 0000 0 0279 03FF 1K EDMA3CC2 transfer controllerEDMA3TC0

0279 0400 0279 7FFF 0 0279 0400 0 0279 7FFF 31K Reserved

0279 8000 0279 83FF 0 0279 8000 0 0279 83FF 1K EDMA3CC2 transfer controller EDMA3TC1

0279 8400 0279 FFFF 0 0279 8400 0 0279 FFFF 31K Reserved

027A 0000 027A 03FF 0 027A 0000 0 027A 03FF 1K EDMA3CC2 transfer controllerEDMA3TC2

027A 0400 027A 7FFF 0 027A 0400 0 027A 7FFF 31K Reserved

027A 8000 027A 83FF 0 027A 8000 0 027A 83FF 1K EDMA3CC2 transfer controller EDMA3TC3

027A 8400 027A FFFF 0 027A 8400 0 027A FFFF 31K Reserved

TMS320C6670

SPRS689D—March 2012

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Multicore Fixed and Floating-Point System-on-Chip

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Table 2-2 Memory Map Summary (Part 6 of 9)

Logical 32 bit Address Physical 36 bit Address

Bytes DescriptionStart End Start End

027B 0000 027B FFFF 0 027B 0000 0 027B FFFF 64K Reserved

027C 0000 027C FFFF 0 027C 0000 0 027C FFFF 64K Reserved

027D 0000 027D 3FFF 0 027D 0000 0 027D 3FFF 16K TI embedded trace buffer (TETB) - CorePac0

027D 4000 027D FFFF 0 027D 4000 0 027D FFFF 48K Reserved

027E 0000 027E 3FFF 0 027E 0000 0 027E 3FFF 16K TI embedded trace buffer (TETB) - CorePac1

027E 4000 027E FFFF 0 027E 4000 0 027E FFFF 48K Reserved

027F 0000 027F 3FFF 0 027F 0000 0 027F 3FFF 16K TI embedded trace buffer (TETB) - CorePac2

027F 4000 027F FFFF 0 027F 4000 0 027F FFFF 48K Reserved

0280 0000 0280 3FFF 0 0280 0000 0 0280 3FFF 16 TI embedded trace buffer (TETB) - CorePac3

0280 4000 0280 FFFF 0 0280 4000 0 0280 FFFF 48K Reserved

0281 0000 0281 3FFF 0 0281 0000 0 0281 3FFF 16K Reserved

0281 4000 0281 FFFF 0 0281 4000 0 0281 FFFF 48K Reserved

0282 0000 0282 3FFF 0 0282 0000 0 0282 3FFF 16K Reserved

0282 4000 0282 FFFF 0 0282 4000 0 0282 FFFF 48K Reserved

0283 0000 0283 3FFF 0 0283 0000 0 0283 3FFF 16K Reserved

0283 4000 0283 FFFF 0 0283 4000 0 0283 FFFF 48K Reserved

0284 0000 0284 3FFF 0 0284 0000 0 0284 3FFF 16K Reserved

0284 4000 0284 FFFF 0 0284 4000 0 0284 FFFF 48K Reserved

0285 0000 0285 7FFF 0 0285 0000 0 0285 7FFF 32K TI embedded trace buffer (TETB) - system

0285 8000 0285 FFFF 0 0285 8000 0 0285 FFFF 32K Reserved

0286 0000 028F FFFF 0 0286 0000 0 028F FFFF 640K Reserved

0290 0000 0290 0FFF 0 0290 0000 0 0290 0FFF 4K Serial RapidIO (SRIO) configuration

0290 8000 029F FFFF 0 0290 8000 0 029F FFFF 1M-32K Reserved

02A0 0000 02AF FFFF 0 02A0 0000 0 02AF FFFF 1M Queue Manager subsystem configuration

02B0 0000 02BF FFFF 0 02B0 0000 0 02BF FFFF 1M Reserved

02C0 0000 02FF FFFF 0 02C0 0000 0 02FF FFFF 4M Reserved

03000 000 07FF FFFF 0 03000 000 0 07FF FFFF 80M Reserved

0800 0000 0800 FFFF 0 0800 0000 0 0800 FFFF 64K Extended Memory Controller (XMC) configuration

0801 0000 0BBF FFFF 0 0801 0000 0 0BBF FFFF 60M-64K Reserved

0BC0 0000 0BCF FFFF 0 0BC0 0000 0 0BCF FFFF 1M Multicore Shared Memory Controller (MSMC) config

0BD0 0000 0BFF FFFF 0 0BD0 0000 0 0BFF FFFF 3M Reserved

0C00 0000 0C1F FFFF 0 0C00 0000 0 0C1F FFFF 2M Multicore Shared Memory (MSM)

0C20 0000 0C3F FFFF 0 0C20 0000 0 0C3F FFFF 2M Reserved

0C40 0000 0FFF FFFF 0 0C40 0000 0 0FFF FFFF 60M Reserved

1000 0000 107F FFFF 0 1000 0000 0 107F FFFF 8M Reserved

1080 0000 108F FFFF 0 1080 0000 0 108F FFFF 1M CorePac0 L2 SRAM

1090 0000 10DF FFFF 0 1090 0000 0 10DF FFFF 5M Reserved

10E0 0000 10E0 7FFF 0 10E0 0000 0 10E0 7FFF 32K CorePac0 L1P SRAM

10E0 8000 10EF FFFF 0 10E0 8000 0 10EF FFFF 1M-32K Reserved

10F0 0000 10F0 7FFF 0 10F0 0000 0 10F0 7FFF 32K CorePac0 L1D SRAM

10F0 8000 117F FFFF 0 10F0 8000 0 117F FFFF 9M-32K Reserved

1180 0000 118F FFFF 0 1180 0000 0 118F FFFF 1M CorePac1 L2 SRAM

1190 0000 11DF FFFF 0 1190 0000 0 11DF FFFF 5M Reserved

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Table 2-2 Memory Map Summary (Part 7 of 9)

Logical 32 bit Address Physical 36 bit Address

Bytes DescriptionStart End Start End

11E0 0000 11E0 7FFF 0 11E0 0000 0 11E0 7FFF 32K CorePac1 L1P SRAM

11E0 8000 11EF FFFF 0 11E0 8000 0 11EF FFFF 1M-32K Reserved

11F0 0000 11F0 7FFF 0 11F0 0000 0 11F0 7FFF 32K CorePac1 L1D SRAM

11F0 8000 127F FFFF 0 11F0 8000 0 127F FFFF 9M-32K Reserved

1280 0000 128F FFFF 0 1280 0000 0 128F FFFF 1M CorePac2 L2 SRAM

1290 0000 12DF FFFF 0 1290 0000 0 12DF FFFF 5M Reserved

12E0 0000 12E0 7FFF 0 12E0 0000 0 12E0 7FFF 32K CorePac2 L1P SRAM

12E0 8000 12EF FFFF 0 12E0 8000 0 12EF FFFF 1M-32K Reserved

12F0 0000 12F0 7FFF 0 12F0 0000 0 12F0 7FFF 32K CorePac2 L1D SRAM

12F0 8000 137F FFFF 0 12F0 8000 0 137F FFFF 9M-32K Reserved

1380 0000 1388 FFFF 0 1380 0000 0 1388 FFFF 1M CorePac3 L2 SRAM

1390 0000 13DF FFFF 0 1390 0000 0 13DF FFFF 5M Reserved

13E0 0000 13E0 7FFF 0 13E0 0000 0 13E0 7FFF 32K CorePac3 L1P SRAM

13E0 8000 13EF FFFF 0 13E0 8000 0 13EF FFFF 1M-32K Reserved

13F0 0000 13F0 7FFF 0 13F0 0000 0 13F0 7FFF 32K CorePac3 L1D SRAM

13F0 8000 147F FFFF 0 13F0 8000 0 147F FFFF 9M-32K Reserved

1480 0000 1487 FFFF 0 1480 0000 0 1487 FFFF 512K Reserved

1488 0000 148F FFFF 0 1488 0000 0 148F FFFF 512K Reserved

1490 0000 14DF FFFF 0 1490 0000 0 14DF FFFF 5M Reserved

14E0 0000 14E0 7FFF 0 14E0 0000 0 14E0 7FFF 32K Reserved

14E0 8000 14EF FFFF 0 14E0 8000 0 14EF FFFF 1M-32K Reserved

14F0 0000 14F0 7FFF 0 14F0 0000 0 14F0 7FFF 32K Reserved

14F0 8000 157F FFFF 0 14F0 8000 0 157F FFFF 9M-32K Reserved

1580 0000 1587 FFFF 0 1580 0000 0 1587 FFFF 512K Reserved

1588 0000 158F FFFF 0 1588 0000 0 158F FFFF 512K Reserved

1590 0000 15DF FFFF 0 1590 0000 0 15DF FFFF 5M Reserved

15E0 0000 15E0 7FFF 0 15E0 0000 0 15E0 7FFF 32K Reserved

15E0 8000 15EF FFFF 0 15E0 8000 0 15EF FFFF 1M-32K Reserved

15F0 0000 15F0 7FFF 0 15F0 0000 0 15F0 7FFF 32K Reserved

15F0 8000 167F FFFF 0 15F0 8000 0 167F FFFF 9M-32K Reserved

1680 0000 1687 FFFF 0 1680 0000 0 1687 FFFF 512K Reserved

1688 0000 168F FFFF 0 1688 0000 0 168F FFFF 512K Reserved

1690 0000 16DF FFFF 0 1690 0000 0 16DF FFFF 5M Reserved

16E0 0000 16E0 7FFF 0 16E0 0000 0 16E0 7FFF 32K Reserved

16E0 8000 16EF FFFF 0 16E0 8000 0 16EF FFFF 1M-32K Reserved

16F0 0000 16F0 7FFF 0 16F0 0000 0 16F0 7FFF 32K Reserved

16F0 8000 177F FFFF 0 16F0 8000 0 177F FFFF 9M-32K Reserved

1780 0000 1787 FFFF 0 1780 0000 0 1787 FFFF 512K Reserved

1788 0000 178F FFFF 0 1788 0000 0 178F FFFF 512K Reserved

1790 0000 17DF FFFF 0 1790 0000 0 17DF FFFF 5M Reserved

17E0 0000 17E0 7FFF 0 17E0 0000 0 17E0 7FFF 32K Reserved

17E0 8000 17EF FFFF 0 17E0 8000 0 17EF FFFF 1M-32K Reserved

17F0 0000 17F0 7FFF 0 17F0 0000 0 17F0 7FFF 32K Reserved

TMS320C6670

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Table 2-2 Memory Map Summary (Part 8 of 9)

Logical 32 bit Address Physical 36 bit Address

Bytes DescriptionStart End Start End

17F0 8000 1FFF FFFF 0 17F0 8000 0 1FFF FFFF 129M-32K Reserved

2000 0000 200F FFFF 0 2000 0000 0 200F FFFF 1M System trace manager (STM) configuration

2010 0000 201F FFFF 0 2010 0000 0 201F FFFF 1M Reserved

2020 0000 205F FFFF 0 2020 0000 0 205F FFFF 4M RAC_B data

2060 0000 206F FFFF 0 2060 0000 0 206F FFFF 1M TCP3d-B data

2070 0000 207F FFFF 0 2070 0000 0 207F FFFF 1M Reserved

2080 0000 208F FFFF 0 2080 0000 0 208F FFFF 1M TCP3d-A data

2090 0000 2090 1FFF 0 2090 0000 0 2090 1FFF 8K TCP3e data write port

2090 2000 2090 3FFF 0 2090 2000 0 2090 3FFF 8K TCP3e data read port

2090 4000 209F FFFF 0 2090 4000 0 209F FFFF 1M-16K Reserved

20A0 0000 20A3 FFFF 0 20A0 0000 0 20A3 FFFF 256K Reserved

20A4 0000 20A4 FFFF 0 20A4 0000 0 20A4 FFFF 64K Reserved

20A5 0000 20AF FFFF 0 20A5 0000 0 20AF FFFF 704K Reserved

20B0 0000 20B1 FFFF 0 20B0 0000 0 20B1 FFFF 128K Boot ROM

20B2 0000 20BE FFFF 0 20B2 0000 0 20BE FFFF 832K Reserved

20BF 0000 20BF 01FF 0 20BF 0000 0 20BF 01FF 512 SPI

20BF 0400 20BF FFFF 0 20BF 0400 0 20BF FFFF 63K Reserved

20C0 0000 20C0 00FF 0 20C0 0000 0 20C0 00FF 256 Reserved

20C0 0100 20FF FFFF 0 20C0 0100 0 20FF FFFF 4M-256 Reserved

2100 0000 2100 01FF 1 0000 0000 1 0000 01FF 512 DDR3 EMIF configuration

2100 0200 213F FFFF 0 2100 0200 0 213F FFFF 4M-256 Reserved

2140 0000 2140 00FF 0 2140 0000 0 2140 00FF 256 HyperLink config

2140 0400 217F FFFF 0 2140 0400 0 217F FFFF 4M-1K Reserved

2180 0000 2180 7FFF 0 2180 0000 0 2180 7FFF 32K PCIe config

2180 8000 21BF FFFF 0 2180 8000 0 21BF FFFF 4M-32K Reserved

21C0 0000 21FF FFFF 0 21C0 0000 0 21FF FFFF 4M Reserved

2200 0000 229F FFFF 0 2200 0000 0 229F FFFF 10M Reserved

22A0 0000 22A0 FFFF 0 22A0 0000 0 22A0 FFFF 64K VCP2_A

22A1 0000 22AF FFFF 0 22A1 0000 0 22AF FFFF 1M-64K Reserved

22B0 0000 22B0 FFFF 0 22B0 0000 0 22B0 FFFF 64K VCP2_B

22B1 0000 22BF FFFF 0 22B1 0000 0 22BF FFFF 1M-64K Reserved

22C0 0000 22C0 FFFF 0 22C0 0000 0 22C0 FFFF 64K VCP2_C

22C1 0000 22CF FFFF 0 22C1 0000 0 22CF FFFF 1M-64K Reserved

22D0 0000 22D0 FFFF 0 22D0 0000 0 22D0 FFFF 64K VCP2_D

22D1 0000 22DF FFFF 0 22D1 0000 0 22DF FFFF 1M-64K Reserved

22E0 0000 23FF FFFF 0 22E0 0000 0 23FF FFFF 18M Reserved

2400 0000 2FFF FFFF 0 2400 0000 0 2FFF FFFF 192M Reserved

3000 0000 331F FFFF 0 3000 0000 0 331F FFFF 50M Reserved

3320 0000 335F FFFF 0 3320 0000 0 335F FFFF 4M RAC_A data

3360 0000 33FF FFFF 0 3360 0000 0 33FF FFFF 10M Reserved

3400 0000 341F FFFF 0 3400 0000 0 341F FFFF 2M Queue Manager subsystem data

3420 0000 342F FFFF 0 3420 0000 0 342F FFFF 1M Reserved

3430 0000 3439 FFFF 0 3430 0000 0 3439 FFFF 640K Reserved

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Table 2-2 Memory Map Summary (Part 9 of 9)

Logical 32 bit Address Physical 36 bit Address

Bytes DescriptionStart End Start End

343A 0000 343F FFFF 0 343A 0000 0 343F FFFF 384K Reserved

3440 0000 347F FFFF 0 3440 0000 0 347F FFFF 4M Reserved

3480 0000 34BF FFFF 0 3480 0000 0 34BF FFFF 4M Reserved

34C0 0000 34C2 FFFF 0 34C0 0000 0 34C2 FFFF 192K TAC data

34C3 0000 34FF FFFF 0 34C3 0000 0 34FF FFFF 4M-192K Reserved

3500 0000 3500 03FF 0 3500 0000 0 3500 03FF 1K Memory protection unit (MPU) 5

3500 0400 3500 7FFF 0 3500 0400 0 3500 7FFF 31K Reserved

3500 8000 3500 81FF 0 3500 8000 0 3500 81FF 512 Reserved

3500 8200 3501 FFFF 0 3500 8200 0 3501 FFFF 95K Reserved

3502 0000 3502 03FF 0 3502 0000 0 3502 03FF 1K TCP3d_C config

3502 0400 3503 FFFF 0 3502 0400 0 3503 FFFF 127K Reserved

3504 0000 3504 07FF 0 3504 0000 0 3504 07FF 2K FFTC_C config

3504 0800 350F FFFF 0 3504 0800 0 350F FFFF 766K Reserved

3510 0000 351F FFFF 0 3510 0000 0 351F FFFF 1M Reserved

3520 0000 3521 FFFF 0 3520 0000 0 3521 FFFF 128K BCP config

3522 0000 355F FFFF 0 3522 0000 0 355F FFFF 3968K Reserved

3560 0000 356F FFFF 0 3560 0000 0 356F FFFF 1M TCP3d_C data

3570 0000 37FF FFFF 0 3570 0000 0 37FF FFFF 41M Reserved

3800 0000 3FFF FFFF 0 3800 0000 0 3FFF FFFF 128M Reserved

4000 0000 4FFF FFFF 0 4000 0000 0 4FFF FFFF 256M HyperLink data

5000 0000 5FFF FFFF 0 5000 0000 0 5FFF FFFF 256M Reserved

6000 0000 6FFF FFFF 0 6000 0000 0 6FFF FFFF 256M PCIe data

7000 0000 73FF FFFF 0 7000 0000 0 73FF FFFF 64M Reserved

7400 0000 77FF FFFF 0 7400 0000 0 77FF FFFF 64M Reserved

7800 0000 7BFF FFFF 0 7800 0000 0 7BFF FFFF 64M Reserved

7C00 0000 7FFF FFFF 0 7C00 0000 0 7FFF FFFF 64M Reserved

8000 0000 FFFF FFFF 8 0000 0000 8 7FFF FFFF 2G DDR3 EMIF data

End of Table 2-2

TMS320C6670

SPRS689D—March 2012

2.3 Boot Sequence

The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections. The
DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically
after each power-on reset. A hard reset, soft reset or local reset to an individual C66x CorePac should not affect the
state of the hardware boot controller on the device. For more details on the initiators of the resets, see section

7.4 ‘‘Reset Controller’’ on page 122. The bootloader uses a section of the L2 SRAM (start address 0x008F 2DC0 and
end address 0x008F FFFF) during initial booting of the device. For more details on the type of configurations stored
in this reserved L2 section see the Bootloader for the C66x DSP User Guide in ‘‘Related Documentation from Texas

Instruments’’ on page 66.

The C6670 supports several boot processes that begins execution at the ROM base address, which contains the
bootloader code necessary to support various device boot modes. The boot processes are software-driven and use
the BOOTMODE[12:0] device configuration inputs to determine the software configuration that must be
completed. For more details on boot sequence see the Bootloader for the C66x DSP User Guide in ‘‘Related

Documentation from Texas Instruments’’ on page 66.

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2.4 Boot Modes Supported and PLL Settings

The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software
driven, using the BOOTMODE[3:0] device configuration inputs to determine the software configuration that must
be completed. From a hardware perspective, there are two possible boot modes:

• Public ROM Boot - C66x CorePac is released from reset and begins executing from the L3 ROM base address.
After performing the boot process (e.g., from I
execution from the L2 RAM base address.

• Secure ROM Boot - On secure devices, the C66x CorePac is released from reset and begins executing from
secure ROM. Software in the secure ROM will free up internal RAM pages, after which the C66x CorePac
initiates the boot process. The C66x CorePac performs any authentication and decryption required on the
bootloaded image prior to beginning execution.

The boot process performed by the C66x CorePac in public ROM boot and secure ROM boot is determined by the
BOOTMODE[12:0] value in the DEVSTAT register. The C66x CorePac reads this value, and then executes the
associated boot process in software. Figure 2-2 shows the bits associated with BOOTMODE[12:0]. PLL settings are
shown at the end of this section, and the PLL setup details can be found in Section 7.5 ‘‘Main PLL and the PLL

Controller’’ on page 128

Figure 2-2 Boot Mode Pin Decoding

12 11 10 9 8 7 6 5 4 3 2 1 0

PLL Mult I

1 BOOTMODE[4:3] are reserved in all modes except No-Boot, Ethernet (SGMII), I2C and SPI boot mode

2

C /SPI Ext Dev Cfg Device Configuration Reserved

2

C ROM, Ethernet, or RapidIO), the C66x CorePac then begins

Boot Mode Pins

(1)

Boot Device

2.4.1 Boot Device Field

The Boot Device field BOOTMODE[2:0] defines the boot device that is chosen. Table 2-3 shows the supported boot
modes.

Table 2-3 Boot Mode Pins: Boot Device Values

Bit Field Description

2-0 Boot Device Device boot mode

End of Table 2-3

0 = No boot
1 = Serial Rapid I/O
2 = Ethernet (SGMII) (PA driven from core clk)
3 = Ethernet (SGMII) (PA driver from PA clk)
4 = PCI

2

5 = I

C
6 = SPI
7 = HyperLink

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2.4.2 Device Configuration Field

The device configuration fields BOOTMODE[9:3] are used to configure the boot peripheral and, therefore, the bit
definitions depend on the boot mode.

2.4.2.1 No Boot Device Configuration

Figure 2-3 No Boot Configuration Fields

9 8 7 6 5 4 3

Sub-Mode

Table 2-4 No Boot Configuration Field Descriptions

Bit Field Description

9-8 Sub-Mode Sub mode select

0 = No boot
1 - 3 = Reserved

7-3 Reserved Reserved

End of Table 2-4

Reserved

SPRS689D—March 2012

2.4.2.2 Serial Rapid I/O Boot Device Configuration

The device ID is always set to 0xff (8-bit node IDs) or 0xffff (16 bit node IDs) at power-on reset.

Figure 2-4 Serial Rapid I/O Device Configuration Fields

9 8 7 6 5 4 3

Lane Setup Data Rate Ref Clock Reserved

Table 2-5 Serial Rapid I/O Configuration Field Descriptions

Bit Field Description

9 Lane Setup SRIO port and lane configuration

0 = Port configured as 4 ports each 1 lane wide (4 -1× ports)
1 = Port configured as 2 ports 2 lanes wide (2 – 2× ports)

8-7 Data Rate SRIO data rate configuration

0 = 1.25 GBs
1 = 2.5 GBs
2 = 3.125 GBs
3 = 5.0 GBs

6-5 Ref Clock SRIO reference clock configuration

0 = Reference clock = 156.25 MHz
1 = Reference clock = 250 MHz
2 = Reference clock = 312.5 MHz
3 = Reserved

4-3 Reserved Reserved

End of Table 2-5

In SRIO boot mode, both the message mode and DirectIO mode will be enabled by default. If use of the memory
reserved for received messages is required and reception of messages cannot be prevented, the master can disable
the message mode by writing to the boot table and generating a boot restart.

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2.4.2.3 Ethernet (SGMII) Boot Device Configuration

Figure 2-5 Ethernet (SGMII) Device Configuration Fields

9 8 7 6 5 4 3

SerDes Clock Mult Ext connection Dev ID

Table 2-6 Ethernet (SGMII) Configuration Field Descriptions

Bit Field Description

9-8 SerDes clock mult SGMII SerDes input clock. The output frequency of the PLL must be 1.25 GBs.

0 = ×8 for input clock of 156.25 MHz
1 = ×5 for input clock of 250 MHz
2 = ×4 for input clock of 312.5 MHz
3 = Reserved

7-6 Ext connection External connection mode

0 = MAC to MAC connection, master with auto negotiation
1 = MAC to MAC connection, slave, and MAC to PHY
2 = MAC to MAC, forced link
3 = MAC to fiber connection

5-3 Device ID This value can range from 0 to 7 and is used in the device ID field of the Ethernet-ready frame.

End of Table 2-6

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2.4.2.4 PCI Boot Device Configuration

Additional device configuration is provided in the PCI bits in the DEVSTAT register.

Figure 2-6 PCI Device Configuration Fields

9 8 7 6 5 4 3

Reserved BAR Config Reserved

Table 2-7 PCI Device Configuration Field Descriptions

Bit Field Description

9 Reserved Reserved

8-5 Bar Config PCIe BAR registers configuration

This value can range from 0 to 0xf. See Table 2-8.

4-3 Reserved Reserved

End of Table 2-7

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Table 2-8 BAR Config / PCIe Window Sizes

32-Bit Address Translation 64-Bit Address Translation

BAR cfg BAR0

0b0000PCIe MMRs32323232Clone of BAR4

0b0001 16163264

0b0010 16323264

0b0011 32323264

0b0100 16166464

0b0101 16326464

0b0110 32326464

0b0111 32 32 64 128

0b1000 64 64 128 256

0b1001 4 128 128 128

0b1010 4 128 128 256

0b1011 4 128 256 256

0b1100

0b1101 512 512

0b1110 1024 1024

0b1111 2048 2048

BAR1 BAR2 BAR3 BAR4 BAR5 BAR2/3 BAR4/5

SPRS689D—March 2012

256 256

2.4.2.5 I2C Boot Device Configuration

2.4.2.5.1 I2C Master Mode

In master mode, the I2C device configuration uses ten bits of device configuration instead of seven as used in other
boot modes. In this mode, the device will make the initial read of the I

2

C EEPROM while the PLL is in bypass mode.

The initial read will contain the desired clock multiplier, which will be set up prior to any subsequent reads.

Figure 2-7 I2C Master Mode Device Configuration Fields

12 11 10 9 8 7 6 5 4 3

Reserved Speed Address Reserved Mode Parameter Index

Table 2-9 I2C Master Mode Device Configuration Field Descriptions

Bit Field Description

12 Reserved Reserved

2

11 Speed I

10 Address I

9 Reserved Reserved

8 Mode I

7-3 Parameter Index Identifies the index of the configuration table initially read from the I

End of Table 2-9

C data rate configuration

2

0 = I

C data rate set to approximately 20 kHz

2

C fast mode. Data rate set to approximately 400 kHz (will not exceed)

1 = I

2

C bus address configuration
0 = Boot from I
1 = Boot from I

2

C operation mode
0 = Master mode

1 = Passive mode (see 2.4.2.5.2 ‘‘I2C Passive Mode’’)

This value can range from 0 to 32.

2

C EEPROM at I2C bus address 0x50

2

C EEPROM at I2C bus address 0x51

2

C EEPROM.

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2

2.4.2.5.2 I

In passive mode, the device does not drive the clock, but simply acks data received on the specified address.

Figure 2-8 I2C Passive Mode Device Configuration Fields

Table 2-10 I2C Passive Mode Device Configuration Field Descriptions

Bit Field Description

9 Reserved Reserved

8Mode I

8-5 Receive I

4-3 Reserved Reserved

End of Table 2-10

C Passive Mode

9 8 7 6 5 4 3

Reserved Mode

2

C Address I2C bus address configuration

2

C operation mode
0 = Master mode (see ‘‘I2C Master Mode’’ on page 33)
1 = Passive mode

0 - 7 = The I

The actual value on the bus is 0x19 plus the value in bits [8:5]. For Ex. if bits[8:5] = 0 then the device will listen to I
bus address 0x19.

2

C bus address the device will listen to for data

Receive I

2

C Address

Reserved

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2

C

2.4.2.6 SPI Boot Device Configuration

In SPI boot mode, the SPI device configuration uses ten bits of device configuration instead of seven as used in other
boot modes.

Figure 2-9 SPI Device Configuration Fields

12 11 10 9 8 7 6 5 4 3

Mode 4, 5 Pin Addr Width Chip Select Parameter Table Index

Table 2-11 SPI Device Configuration Field Descriptions

Bit Field Description

12-11 Mode Clk Pol / Phase

0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.
1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges. Input

data is latched on the rising edge of SPICLK.
2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge.
3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges. Input

data is latched on the falling edge of SPICLK.

10 4, 5 Pin SPI operation mode configuration

0 = 4-pin mode used
1 = 5-pin mode used

9 Addr Width SPI address width configuration

0 = 16-bit address values are used
1 = 24-bit address values are used

8-7 Chip Select The chip select field value

6-3 Parameter Table Index Specifies which parameter table is loaded

End of Table 2-11

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2.4.2.7 HyperLink Boot Device Configuration

Figure 2-10 HyperLink Boot Device Configuration Fields

9 8 7 6 5 4 3

Reserved Data Rate Ref Clock Reserved

Table 2-12 HyperLink Boot Device Configuration Field Descriptions

Bit Field Description

9 Reserved Reserved

8-7 Data Rate HyperLink data rate configuration

0 = 1.25 GBs
1 = 3.125 GBs
2 = 6.25 GBs
3 = Reserved

6-5 Ref Clocks HyperLink reference clock configuration

0 = 156.25 MHz
1 = 250 MHz
2 = 312.5 MHz
3 = Reserved

4-3 Reserved Reserved

End of Table 2-12

TMS320C6670

SPRS689D—March 2012

2.4.3 PLL Settings

The PLL default settings are determined by the BOOTMODE[12:10] bits. Table 2-13 shows settings for various
input clock frequencies. This will set the PLL to the maximum clock setting for the device.

CLK = CLKIN × (PLLM+1) ÷ (2 × (PLLD+1))

The configuration for the PASS PLL is also shown. The PASS PLL is configured with these values only if the Ethernet
boot mode is selected with the input clock set to match the main PLL clock (not the SGMII SerDes clock). See

Table 2-3 for details on configuring Ethernet boot mode. The output from the PASS PLL goes through an on-chip

divider to reduce the operating frequency before reaching the NETCP. The PASS PLL generates 1050 MHz, and after
the chip divider (/3), applies 350 MHz to the NETCP.

The Main PLL is controlled using a PLL controller and a chip-level MMR. The DDR3 PLL and PASS PLL are
controlled by chip level MMRs. For details on how to set up the PLL see Section 7.5 ‘‘Main PLL and the PLL

Controller’’ on page 128. For details on the operation of the PLL controller module, see the Phase Locked Loop (PLL)

Controller for KeyStone Devices User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66.

Table 2-13 C66x CorePac System PLL Configuration

BOOTMODE
[12:10]

0b000 50.00 0 31 800 0 39 1000 0 47 1200 0 41 1050

0b001 66.67 0 23 800.04 0 29 1000.05 0 35 1200.06 1 62 1050.053

0b010 80.00 0 19 800 0 24 1000 0 29 1200 3 104 1050

0b011 100.00 0 15 800 0 19 1000 0 23 1200 0 20 1050

0b100 156.25 24 255 800 4 63 1000 24 383 1200 24 335 1050

0b101 250.00 4 31 800 0 7 1000 4 47 1200 4 41 1050

0b110 312.50 24 127 800 4 31 1000 24 191 1200 24 167 1050

0b111 122.88 47 624 800 28 471 999.989 31 624 1200 11 204 1049.6

1 The PASS PLL generates 1050 MHz and is internally divided by 3 to feed 350 MHz to the packet accelerator.
2 ƒ represents frequency in MHz.

Input Clock
Freq (MHz)

800 MHz Device 1000 MHz Device 1200 MHz Device PA = 350 MHz

PLLD PLLM DSP ƒ PLLD PLLM DSP ƒ PLLD PLLM DSP ƒ PLLD PLLM DSP ƒ

(1)

(2)

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2.5 Second-Level Bootloaders

Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for any
level of customization to current boot methods as well as the definition of a completely customized boot.

2.6 Terminals

2.6.1 Package Terminals

Figure 2-11 shows the TMS320C6670 CYP ball grid array package (bottom view).

Figure 2-11 CYP 841-PIN BGA Package (Bottom View)

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

24

3

5

9

7

6810

11

12 14

13

151719

16 18 20

21

22 24

23

252729

26 28

2.6.2 Pin Map

Figure 2-13 through Figure 2-16 show the TMS320C6670 pin assignments in four quadrants (A, B, C, and D).

Figure 2-12 Pin Map Quadrants (Bottom View)

A

D

B

C

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Figure 2-13 Upper Left Quadrant—A (Bottom View)

123456789101112131415

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Multicore Fixed and Floating-Point System-on-Chip

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VSS CVDD1 VSS

AJ

CVDD1 VSS

AH

VSS CVDD1 VSS

AG

CVDD1 VSS

AF

VSS CVDD1 VSS VDDT2 RSV17 VDDR3 VSS RSV15 VSS VDDT2 VDDR4 VDDT2 VSS RSV16 VDDR2

AE

CVDD1 VSS CVDD1 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS CORESEL2

AD

VSS DVDD18 VSS DVDD18 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS

AC

VCNTL3 VSS VCNTL1 VCNTL0 DVDD18 VSS VSS VSS VSS VSS VSS VSS VSS VSS AVDDA3

AB

AA

MCMTX
PMDAT

MCMTX

Y

FLCLK

MCMTX

PMCLK

MCMTX

FLDAT

SGMII0

SGMII0

MCMRX

PMCLK

MCMRX
PMDAT

SGMII1

SGMII1RXP VSS RIORXN2 RIORXP2 VSS RIORXP0 RIORXN0 VSS PCIERXP0 PCIERXN0 VSS

RXN

SGMII0

RXN

TXN

RXP

SGMII1

TXN

SGMII0

TXP

VCNTL2 VSS VSS VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS

RSV28 DVDD18 VSS VDDT1 VSS CVDD VSS CVDD1 VSS CVDD1 VSS CVDD1

VSS RIORXN3 RIORXP3 VSS RIORXP1 RIORXN1 VSS PCIERXN1 PCIERXP1 VSS CORESEL0

SGMII1TXP VSS RIOTXN2 RIOTXP2 VSS RIOTXP0 RIOTXN0 VSS PCIETXP0 PCIETXN0 VSS

VSS RIOTXN3 RIOTXP3 VSS RIOTXN1 RIOTXP1 VSS PCIETXN1 PCIETXP1 VSS VSS

MCMCLKP MCMCLKN

W

V

U

T

MCMREF

CLKOUTN

MCMREF

CLKOUTP

VSS VSS VSS VSS VSS VSS VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS

VSS MCMRXN0 VSS VSS MCMTXN0 VSS VDDT1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD

MCMRX

FLDAT

MCMRX

FLCLK

RSV29 VSS VDDT1 VSS CVDD VSS CVDD VSS CVDD1 VSS CVDD1 VSS

RSV14 DVDD18 VSS VDDT1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD

A

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Figure 2-14 Upper Right Quadrant—B (Bottom View)

16 17 18 19 20 21 22 23 24 25 26 27 28 29

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SRIOSGMII

SRIOSGMII

MDIO RSV24 GPIO01 GPIO10 GPIO06 SPICLK VSS TIMI1 UARTRTS EMU13 VSS EMU12 EMU11 EMU09

MDCLK RSV25 GPIO04 D VDD18 VSS GPIO13 DVDD18 TIMO1 UARTRXD EMU06 EMU10 EMU08 EMU03 EMU01

RSV22

RSV23 SDA RESETSTAT GPIO0 2 GPIO11 GPIO15 RSV12 PACLKSEL VSS EMU05 TRST VSS TDI TCK

CORESEL1 SCL HOUT POR

CVDD VSS CVDD VSS CVDD VSS CVDD VSS RSV18 VSS SYSCLKOUT RADSYNC RP1CLKN RP1FBN

PCIECLKN PASSCLKP GP IO08 GPIO00 SPIDOUT SPISCS1 TIMI0 UARTTXD RSV01 EMU17 EMU15 DVDD18 VSS

CLKP

PCIECLKP PASSCLKN GPIO07 GPIO14 SPISCS0 SPIDIN TIMO0 UARTCTS EMU18 DVDD18 EMU16 EMU14 DVDD18

CLKN

EXTFRAME

EVENT

VSS DVDD18 VSS DVDD18 VSS DVDD18 VSS CVDD VSS

VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD VSS DVDD18 VSS RSV04 RP1CLKP RP1FBP

GPIO05 GPIO03 GPIO12 GPIO09 LRESET RESETFULL DVDD18 EMU07 EMU04 DVDD18 EMU02 EMU00

LRESET
NMIEN

BOOT

COMPLETE

RSV13 RSV03 RESET NMI TMS TDO SYSCLKN SYSCLKP

CORE

CLKSEL

RSV20 PHYSYNC

ALTCORE

CLKN

ALTCORE

CLKP

AJ

AH

AG

AF

AE

AD

AC

AB

AA

Y

CVDD1 VSS CVDD VSS CVDD VSS CVDD VSS AVDD A1 VSS VSS RSV05 VSS VSS

VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS VDDT3 AIFTXP5 VSS AIFRXP5 VSS

CVDD VSS CVDD VSS CVDD VSS CVDD VSS VDDT3 RSV26 AIFTXN5 AIFTXN4 AIFRXN5 AIFRXP4

VSS CVDD VSS CVDD VSS CVDD VSS VDDT3 VSS VDDT3 VSS AIFTXP4 VSS AIFRXN4

W

V

U

T

B

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Figure 2-15 Lower Right Quadrant—C (Bottom View)

C

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CVDD VS S CVDD VSS CVDD VSS CVDD VSS VDDT3 VDDR5 AIFTXN2 VSS AIFRXN2 VSS

VSS CVDD VSS CVDD VSS CVDD VSS VDDT3 VSS VDDT3 AIFTXP2 AIFTXN3 AIFRXP2 AIFRXN3

CVDD VS S CVDD VSS CVDD VSS CVDD VSS VDDT3 VDDR6 VSS AIFTXP3 VSS AIFRXP3

VSS CVDD VSS CVDD VSS CVDD1 VSS VDDT3 VSS VDDT3 AIFTXP0 VSS AIFRXP0 VSS

CVDD1 VSS CVDD VSS CVDD1 VS S CVDD1 VSS VDDT3 RSV27 AIFTXN0 AIFTXN1 AIFRXN0 AIFRXP1

VSS CVDD1 VSS CVDD VSS CVDD1 VSS RSV0B RSV0A VDDT3 VSS AIFTXP1 VSS AIFRXN1

CVDD1 VSS CVDD VSS CVDD1 VS S CVDD1 RSV11 RSV08 RSV09 AVDDA2 VSS RSV06 VSS

VSS CVDD VSS CVDD VSS CVDD VSS RSV10 PTV15 DVDD18

DVDD15 VSS DVDD15 VSS DVDD15 VS S DVDD15 VSS DVD D15 VSS RSV21 RSV1 9 DVDD18 DDRCLKP

VSS DVDD15 VSS DVDD15 DDRD25 DDRD27 DDRD17 DDRD16 DDRD08 DDRD07 VSS DVDD15 VSS VSS

DDRSL

RATE1

DDRSL
RATE0

RSV07 DDRCLKN

R

P

N

M

L

K

J

H

G

F

DDRA10 DDRA 12 DDRCKE1 DDRCB 00 VSS DDRD26 DDRD23 DDRD19 DDRD09 DDRD10 DDRD06 DDRD02 DDRD00 DDRDQM0

DDRA11 DDRA14 VSS DDRCB02 DVDD15 DDRD24 DDRD28 DVDD15 DDRD18 DDRD11 DDRD12 DDRD04 DDRD03 DDRD01

DDRA13 DDRA 15 DDRCB05 DDRCB04 DDR CB01 DDRD29 DDRD31 VSS DDRD22 DV DD15 DDRD13 DDRDQM1 DDRDQS0P DDRDQS0N

DDRCLK

OUTN1

DDRCLK

OUTP1

VSS DDRCB06 DDRDQS8N DDRCB03 DDRDQS3N DDRD30 DDRD21 DDRDQS2N VSS DDRD14 DDRDQS1N DDRD05 DVDD15

DVDD15 DDRCB07 DDRDQS8P DDRDQM8 DDRDQS3P DDRDQM3 DDRD20 DDRDQS2P DDRDQM2 DDRD15 DDRDQS1P DVDD15 VSS

16 17 18 19 20 21 22 23 24 25 26 27 28 29

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E

D

C

B

A

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Figure 2-16 Lower Left Quadrant—D (Bottom View)

D

MCMRXP1 MCMRXP0 VSS MCMTXN1 MCMTXP0 VDDT1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS

R

MCMRXN1 VSS VSS MCMTXP1 VSS VSS VDDT1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD

P

VSS MCMRXN3 VSS VSS MCMTXP3 VDDT1 VSS CVDD VSS CVDD VSS CVDD VSS CVDD VSS

N

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MCMRXP2 MCMRXP3 VSS MCMTXP2 MCMTXN3 VSS VDDT1 VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD

M

MCMRXN2 VSS VSS MCMTXN2 VSS VSS VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD1 VSS

L

VSS VSS VSS VSS VSS VDDR1 CVDD1 VSS CVDD1 VSS CVDD VSS CVDD1 VSS CVDD1

K

VSS CVDD1 VSS CVDD1 VSS CVDD1 VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD1 VSS

J

CVDD1 VSS CVDD1 VSS CVDD1 VSS CVDD1 VSS CVDD1 VSS CVDD VSS CVDD VSS CVDD

H

VSS DVDD15 VSS DVDD15 VSS CVDD1 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS

G

DDRD63 DDRD60 DDRD61 DDRD56 DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DDRA03 DDRA02 DDRA08

F

DDRD62 DDRD58 DVDD15 DDRD53 VSS DDRD45 DD RD42 DDRD39 DDRD36 DDRD32 DDRRESET DDRWE DDRODT1 VREFSSTL DDRA09

E

DDRDQS7P DDRD57 VSS DDRD52 DVDD15 DDRD46 DDRD41 DVDD15 DDRD35 DDRD33 DDRCKE0 DDRCAS DDRODT0 VSS DDRA07

D

DDRDQS7N DDRD59 DDRD55 DDRD54 DDRD48 DDRD47 DDRD43 VSS DDRD37 DDRRAS DDRCE0 DDRCE1 DDRBA2 DVDD15 DDRA05

C

DVDD15 DDRDQM7 DDRDQS6P DDRD50 DDRDQM6 DDRDQS5P DDRD44 DDRD38 DDRDQS4N DDRD34 VSS

B

VSS DVDD15 DDRDQS6N DDRD51 DDRD49 DDRDQS5N DDRD40 DDRDQM5 DDRDQS4P DDRDQM4 DVDD15

A

DDRCLK

OUTN0

DDRCLK

OUTP0

DDRBA1 DDRA01 DDRA06

DDRBA0 DDRA00 DDRA04

123456789101112131415

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2.7 Terminal Functions

The terminal functions table (Table 2-15) identifies the external signal names, the associated pin (ball) numbers, the
pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and gives functional pin
descriptions. This table is arranged by function. The power terminal functions table (Table 2-16) lists the various
power supply pins and ground pins and gives functional pin descriptions. Table 2-17 shows all pins arranged by
signal name. Table 2-18 shows all pins arranged by ball number.

There are 17 pins that have a secondary function as well as a primary function. The secondary function is indicated
with a dagger (†).

For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and
pullup/pulldown resistors, see chapter 3 ‘‘Device Configuration’’ on page 67.

Use the symbol definitions in Table 2-14 when reading Table 2-15.

Table 2-14 I/O Functional Symbol Definitions

Functional

Symbol

Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can

IPD or IPU

AAnalog signal Type

GND Ground Type

IInput terminal Type

OOutput terminal Type

S Supply voltage Type

Z Three-state terminal or high impedance Type

End of Table 2-14

be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and
situations in which external pulldown/pullup resistors are required, see the Hardware Design Guide for
KeyStone Devices in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66.

Definition

Table 2-15

Column Heading

IPD/IPU

Table 2-15 Terminal Functions — Signals and Control by Function (Part 1 of 12)

Signal Name Ball No. Type IPD/IPU Description

AIF

AIFRXN0 L28 I

AIFRXP0 M28 I

AIFRXN1 K29 I

AIFRXP1 L29 I

AIFRXN2 R28 I

AIFRXP2 P28 I

AIFRXN3 P29 I

AIFRXP3 N29 I

AIFRXN4 T29 I

AIFRXP4 U29 I

AIFRXN5 U28 I

AIFRXP5 V28 I

Antenna interface receive data (6 links)

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Table 2-15 Terminal Functions — Signals and Control by Function (Part 2 of 12)

Signal Name Ball No. Type IPD/IPU Description

AIFTXN0 L26 O

AIFTXP0 M26 O

AIFTXN1 L27 O

AIFTXP1 K27 O

AIFTXN2 R26 O

AIFTXP2 P26 O

AIFTXN3 P27 O

AIFTXP3 N27 O

AIFTXN4 U27 O

AIFTXP4 T27 O

AIFTXN5 U26 O

AIFTXP5 V26 O

RP1CLKP Y28 I

RP1CLKN AA28 I

EXTFRAMEEVENT AE17 OZ Down

RP1FBP Y29 I

RP1FBN AA29 I

PHYSYNC AB27 I Down

RADSYNC AA27 I Down

LENDIAN † AJ20 IOZ Up Endian configuration pin (pin shared with GPIO[0])

BOOTMODE00 † AG18 IOZ Down

BOOTMODE01† AD19 IOZ Down

BOOTMODE02 † AE19 IOZ Down

BOOTMODE03 † AF18 IOZ Down

BOOTMODE04 † AE18 IOZ Down

BOOTMODE05 † AG20 IOZ Down

BOOTMODE06 † AH19 IOZ Down

BOOTMODE07 † AJ19 IOZ Down

BOOTMODE08 † AE21 IOZ Down

BOOTMODE09 † AG19 IOZ Down

BOOTMODE10 † AD20 IOZ Down

BOOTMODE11 † AE20 IOZ Down

BOOTMODE12 † AF21 IOZ Down

PCIESSMODE0 † AH20 IOZ Down

PCIESSMODE1 † AD21 IOZ Down

PCIESSEN † AJ23 I PCIe module enable (pin shared with TIMI0)

SYSCLKP AC29 I

SYSCLKN AC28 I

PASSCLKP AJ18 I

PASSCLKN AH18 I

Antenna interface transmit data (6 links)

AIF2 Timer (AT) Module

Frame sync interface clock used to drive the frame synchronization interface (OBSAI RP1 clock)

Frame sync clock output

Frame burst to drive frame indicators to the frame synchronization module (OBSAI RP1)

Frame sync input for PHY timer

Frame sync input for radio timer

Boot Configuration Pins

See Section 2.4 ‘‘Boot Modes Supported and PLL Settings’’ on page 30 for more details

(Pins shared with GPIO[1:13])

PCIe mode selection pins (pins shared with GPIO[14:15])

Clock / Reset

System clock input to antenna interface and/or main PLL

Network coprocessor reference clock to PASS PLL

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Table 2-15 Terminal Functions — Signals and Control by Function (Part 3 of 12)

Signal Name Ball No. Type IPD/IPU Description

ALTCORECLKP AB29 I

ALTCORECLKN AB28 I

SRIOSGMIICLKP AJ16 I

SRIOSGMIICLKN AH16 I

DDRCLKP G29 I

DDRCLKN H29 I

PCIECLKP AH17 I

PCIECLKN AJ17 I

MCMCLKP W1 I

MCMCLKN W2 I

SYSCLKOUT AA26 OZ Down

CORECLKSEL AB25 I Down

PACLKSEL AD23 IOZ Down PA clock select to choose between PASSCLK and the output of main PLL MUX (dependent on

HOUT AC18 OZ Up

NMI

LRESET AE22 I Up

LRESETNMIEN AC20 I Up

CORESEL0 AH15 I Down

CORESEL1 AC16 I Down

CORESEL2 AD15 I Down

RESETFULL

RESET AC24 I Up

POR AC19 I

RESETSTAT AD18 O Up

BOOTCOMPLETE AC21 OZ Down

PTV15 H24 A PTV Compensation NMOS Reference Input. A precision resistor placed between the PTV15

DDRDQM0 E29 OZ

DDRDQM1 C27 OZ

DDRDQM2 A25 OZ

DDRDQM3 A22 OZ

DDRDQM4 A10 OZ

DDRDQM5 A8 OZ

DDRDQM6 B5 OZ

DDRDQM7 B2 OZ

DDRDQM8 A20 OZ

AC25 I Up

AE23 I Up

Alternate System clock input to main PLL

RapidIO/SGMII reference clock to drive the RapidIO and SGMII SerDes

DDR reference clock input to DDR PLL

PCIe reference clock input to drive PCIe SerDes

HyperLink reference clock input to drive the HyperLink SerDes

System clock output to be used as a general purpose output clock for debug purposes

Core clock select to select between SYSCLK and ALTCORECCLK to the main PLL

CORECLKSEL pin) to the PA sub-system PLL

Interrupt output pulse created by IPCGRH

Non-maskable Interrupt

Local Reset

Enable for core selects

Select for the target core for LRESET and NMI. For more details see Table 7-47 ‘‘NMI and LRESET

Timing Requirements’’ on page 178

Full reset power-on reset

Reset of non isolated portion on the device

POR (power-on reset)

Reset status output

Boot progress indication output

pin and ground is used to closely tune the output impedance of the DDR interface drivers
to 50 Ohms. Presently, the recommended value for this 1% resistor is 45.3 Ohms.

DDR

DDR EMIF data masks

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Table 2-15 Terminal Functions — Signals and Control by Function (Part 4 of 12)

Signal Name Ball No. Type IPD/IPU Description

DDRDQS0P C28 IOZ

DDRDQS0N C29 IOZ

DDRDQS1P A27 IOZ

DDRDQS1N B27 IOZ

DDRDQS2P A24 IOZ

DDRDQS2N B24 IOZ

DDRDQS3P A21 IOZ

DDRDQS3N B21 IOZ

DDRDQS4P A9 IOZ

DDRDQS4N B9 IOZ

DDRDQS5P B6 IOZ

DDRDQS5N A6 IOZ

DDRDQS6P B3 IOZ

DDRDQS6N A3 IOZ

DDRDQS7P D1 IOZ

DDRDQS7N C1 IOZ

DDRDQS8P A19 IOZ

DDRDQS8N B19 IOZ

DDRCB00 E19 IOZ

DDRCB01 C20 IOZ

DDRCB02 D19 IOZ

DDRCB03 B20 IOZ

DDRCB04 C19 IOZ

DDRCB05 C18 IOZ

DDRCB06 B18 IOZ

DDRCB07 A18 IOZ

DDR EMIF data strobe

DDR EMIF check bits

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Table 2-15 Terminal Functions — Signals and Control by Function (Part 5 of 12)

Signal Name Ball No. Type IPD/IPU Description

DDRD00 E28 IOZ

DDRD01 D29 IOZ

DDRD02 E27 IOZ

DDRD03 D28 IOZ

DDRD04 D27 IOZ

DDRD05 B28 IOZ

DDRD06 E26 IOZ

DDRD07 F25 IOZ

DDRD08 F24 IOZ

DDRD09 E24 IOZ

DDRD10 E25 IOZ

DDRD11 D25 IOZ

DDRD12 D26 IOZ

DDRD13 C26 IOZ

DDRD14 B26 IOZ

DDRD15 A26 IOZ

DDRD16 F23 IOZ

DDRD17 F22 IOZ

DDRD18 D24 IOZ

DDRD19 E23 IOZ

DDRD20 A23 IOZ

DDRD21 B23 IOZ

DDRD22 C24 IOZ

DDRD23 E22 IOZ

DDRD24 D21 IOZ

DDRD25 F20 IOZ

DDRD26 E21 IOZ

DDRD27 F21 IOZ

DDRD28 D22 IOZ

DDRD29 C21 IOZ

DDR EMIF data bus

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Table 2-15 Terminal Functions — Signals and Control by Function (Part 6 of 12)

Signal Name Ball No. Type IPD/IPU Description

DDRD30 B22 IOZ

DDRD31 C22 IOZ

DDRD32 E10 IOZ

DDRD33 D10 IOZ

DDRD34 B10 IOZ

DDRD35 D9 IOZ

DDRD36 E9 IOZ

DDRD37 C9 IOZ

DDRD38 B8 IOZ

DDRD39 E8 IOZ

DDRD40 A7 IOZ

DDRD41 D7 IOZ

DDRD42 E7 IOZ

DDRD43 C7 IOZ

DDRD44 B7 IOZ

DDRD45 E6 IOZ

DDRD46 D6 IOZ

DDRD47 C6 IOZ

DDRD48 C5 IOZ

DDRD49 A5 IOZ

DDRD50 B4 IOZ

DDRD51 A4 IOZ

DDRD52 D4 IOZ

DDRD53 E4 IOZ

DDRD54 C4 IOZ

DDRD55 C3 IOZ

DDRD56 F4 IOZ

DDRD57 D2 IOZ

DDRD58 E2 IOZ

DDRD59 C2 IOZ

DDRD60 F2 IOZ

DDRD61 F3 IOZ

DDRD62 E1 IOZ

DDRD63 F1 IOZ

DDRCE0

DDRCE1

DDRBA0 A13 OZ

DDRBA2 C13 OZ

C11 OZ

C12 OZ

DDR EMIF data bus

DDR EMIF chip enables

DDR EMIF bank addressDDRBA1 B13 OZ

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Table 2-15 Terminal Functions — Signals and Control by Function (Part 7 of 12)

Signal Name Ball No. Type IPD/IPU Description

DDRA00 A14 OZ

DDRA01 B14 OZ

DDRA02 F14 OZ

DDRA03 F13 OZ

DDRA04 A15 OZ

DDRA05 C15 OZ

DDRA06 B15 OZ

DDRA07 D15 OZ

DDRA08 F15 OZ

DDRA09 E15 OZ

DDRA10 E16 OZ

DDRA11 D16 OZ

DDRA12 E17 OZ

DDRA13 C16 OZ

DDRA14 D17 OZ

DDRA15 C17 OZ

DDRCAS

DDRRAS C10 OZ

DDRWE E12 OZ

DDRCKE0 D11 OZ

DDRCKE1 E18 OZ

DDRCLKOUTP0 A12 OZ

DDRCLKOUTN0 B12 OZ

DDRCLKOUTP1 A16 OZ

DDRCLKOUTN1 B16 OZ

DDRODT0 D13 OZ

DDRODT1 E13 OZ

DDRRESET

DDRSLRATE0 H27 I Down

DDRSLRATE1 H26 I Down

VREFSSTL E14 P

D12 OZ

E11 OZ

DDR EMIF address bus

DDR EMIF column address strobe

DDR EMIF row address strobe

DDR EMIF write enable

DDR EMIF clock enables

DDR EMIF output clocks to drive SDRAMs (one clock pair per SDRAM)

DDR EMIF on-die termination outputs used to set termination on the SDRAMs

DDR reset signal

DDR slew rate control

Reference voltage input for SSTL15 buffers used by DDR EMIF (VDDS15 ÷ 2)

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Table 2-15 Terminal Functions — Signals and Control by Function (Part 8 of 12)

Signal Name Ball No. Type IPD/IPU Description

EMU

EMU00 AE29 IOZ Up

EMU01 AF29 IOZ Up

EMU02 AE28 IOZ Up

EMU03 AF28 IOZ Up

EMU04 AE26 IOZ Up

EMU05 AD25 IOZ Up

EMU06 AF25 IOZ Up

EMU07 AE25 IOZ Up

EMU08 AF27 IOZ Up

EMU09 AG29 IOZ Up

EMU10 AF26 IOZ Up

EMU11 AG28 IOZ Up

EMU12 AG27 IOZ Up

EMU13 AG25 IOZ Up

EMU14 AH28 IOZ Up

EMU15 AJ27 IOZ Up

EMU16 AH27 IOZ Up

EMU17 AJ26 IOZ Up

EMU18 AH25 IOZ Up

GPIO00 AJ20 IOZ Up

GPIO01 AG18 IOZ Down

GPIO02 AD19 IOZ Down

GPIO03 AE19 IOZ Down

GPIO04 AF18 IOZ Down

GPIO05 AE18 IOZ Down

GPIO06 AG20 IOZ Down

GPIO07 AH19 IOZ Down

GPIO08 AJ19 IOZ Down

GPIO09 AE21 IOZ Down

GPIO10 AG19 IOZ Down

GPIO11 AD20 IOZ Down

GPIO12 AE20 IOZ Down

GPIO13 AF21 IOZ Down

GPIO14 AH20 IOZ Down

GPIO15 AD21 IOZ Down

Emulation and trace ports

General Purpose Input/Output (GPIO)

General purpose input/output

These GPIO pins have secondary functions assigned to them as mentioned in the Boot
Configuration Pins section above.

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Table 2-15 Terminal Functions — Signals and Control by Function (Part 9 of 12)

Signal Name Ball No. Type IPD/IPU Description

HyperLink

MCMRXN0 T2 I

MCMRXP0 R2 I

MCMRXN1 P1 I

MCMRXP1 R1 I

MCMRXN2 L1 I

MCMRXP2 M1 I

MCMRXN3 N2 I

MCMRXP3 M2 I

MCMTXN0 T5 O

MCMTXP0 R5 O

MCMTXN1 R4 O

MCMTXP1 P4 O

MCMTXN2 L4 O

MCMTXP2 M4 O

MCMTXN3 M5 O

MCMTXP3 N5 O

MCMRXFLCLK V3 O Down

MCMRXFLDAT W3 O Down

MCMTXFLCLK Y1 I Down

MCMTXFLDAT Y2 I Down

MCMRXPMCLK AA3 I Down

MCMRXPMDAT Y3 I Down

MCMTXPMCLK AA2 O Down

MCMTXPMDAT AA1 O Down

MCMREFCLKOUTP V2 O

MCMREFCLKOUTN V1 O

SCL AC17 IOZ

SDA AD17 IOZ

TCK AD29 I Up

TDI AD28 I Up

TDO AC27 OZ Up

TMS AC26 I Up

TRST

MDIO AG16 IOZ Up

MDCLK AF16 O Down

AD26 I Down

Serial HyperLink receive data (4 links)

Serial HyperLink transmit data (4 links)

Serial HyperLink sideband signals

HyperLink reference clock output for daisy chain connection

2

C

2

C clock

I

2

C data

I

JTAG clock input

JTAG data input

JTAG data output

JTAG test mode input

JTAG reset

MDIO data

MDIO clock

I

JTAG

MDIO

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Table 2-15 Terminal Functions — Signals and Control by Function (Part 10 of 12)

Signal Name Ball No. Type IPD/IPU Description

PCIe

PCIERXN0 AJ14 I

PCIERXP0 AJ13 I

PCIERXN1 AH12 I

PCIERXP1 AH13 I

PCIETXN0 AG14 O

PCIETXP0 AG13 O

PCIETXN1 AF12 O

PCIETXP1 AF13 O

RIORXN0 AJ11 I

RIORXP0 AJ10 I

RIORXN1 AH10 I

RIORXP1 AH9 I

RIORXN2 AJ7 I

RIORXP2 AJ8 I

RIORXN3 AH6 I

RIORXP3 AH7 I

RIOTXN0 AG11 O

RIOTXP0 AG10 O

RIOTXN1 AF9 O

RIOTXP1 AF10 O

RIOTXN2 AG7 O

RIOTXP2 AG8 O

RIOTXN3 AF6 O

RIOTXP3 AF7 O

SGMII0RXN AH3 I

SGMII0RXP AH4 I

SGMII1RXN AJ4 I

SGMII1RXP AJ5 I

SGMII0TXN AF3 O

SGMII0TXP AF4 O

SGMII1TXN AG4 O

SGMII1TXP AG5 O

VCNTL0 AB4 OZ

VCNTL1 AB3 OZ

VCNTL2 AA4 OZ

VCNTL3 AB1 OZ

PCIexpress receive data (2 links)

PCIexpress transmit data (2 links)

Serial RapidIO

Serial RapidIO receive data (4 links)

Serial RapidIO transmit data (4 links)

SGMII

Ethernet MAC SGMII receive data (2 links)

Ethernet MAC SGMII transmit data (2 links)

SmartReflex

Voltage control outputs to variable core power supply

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Table 2-15 Terminal Functions — Signals and Control by Function (Part 11 of 12)

Signal Name Ball No. Type IPD/IPU Description

SPI

SPISCS0 AH21 OZ Up SPI interface enable 0

SPISCS1 AJ22 OZ Up SPI interface enable 1

SPICLK AG21 OZ Down SPI clock

SPIDIN AH22 I Down SPI data in

SPIDOUT AJ21 OZ Down SPI data out

Timer

TIMI0 AJ23 I Down

TIMI1 AG23 I Down

TIMO0 AH23 OZ Down

TIMO1 AF23 OZ Down

UARTRXD AF24 I Down UART serial data in

UARTTXD AJ24 OZ Down UART serial data out

UARTCTS AH24 I Down UART clear to send

UARTRTS AG24 OZ Down UART request to send

RSV0A K24 Reserved - leave unconnected

RSV0B K23 Reserved - leave unconnected

RSV01 AJ25 IOZ Down Reserved - pullup to DVDD18

RSV03 AC23 OZ Down Reserved - leave unconnected

RSV04 Y27 O Reserved - leave unconnected

RSV05 W27 O Reserved - leave unconnected

RSV06 J28 O Reserved - leave unconnected

RSV07 H28 O Reserved - leave unconnected

RSV08 J24 A Reserved - connect to GND

RSV09 J25 A Reserved - leave unconnected

RSV10 H23 A Reserved - leave unconnected

RSV11 J23 A Reserved - leave unconnected

RSV12 AD22 A Reserved - leave unconnected

RSV13 AC22 A Reserved - leave unconnected

RSV14 V4 A Reserved - leave unconnected

RSV15 AE8 A Reserved - leave unconnected

RSV16 AE14 A Reserved - leave unconnected

RSV17 AE5 A Reserved - leave unconnected

RSV18 AA24 A Reserved - leave unconnected

RSV19 G27 A Reserved - leave unconnected

RSV20 AB26 OZ Down Reserved - leave unconnected

RSV21 G26 OZ Down Reserved - leave unconnected

RSV22 AE16 OZ Down Reserved - leave unconnected

RSV23 AD16 A Reserved - leave unconnected

RSV24 AG17 O Reserved - leave unconnected

RSV25 AF17 O Reserved - leave unconnected

RSV26 U25 A Reserved - leave unconnected

Timer inputs

Timer outputs

UART

Reserved

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Table 2-15 Terminal Functions — Signals and Control by Function (Part 12 of 12)

Signal Name Ball No. Type IPD/IPU Description

RSV27 L25 A Reserved - leave unconnected

RSV28 Y4 IOZ Reserved - leave unconnected

RSV29 W4 IOZ Reserved - leave unconnected

End of Table 2-15

Table 2-16 Terminal Functions — Power and Ground

Supply Ball No. Volts Description

AVDDA1 W24 1.8 PLL supply: Main PLL

AVDDA2 J26 1.8 PLL supply: DDR3 PLL

AVDDA3 AB15 1.8 PLL supply: PASS PLL

0.9

CVDD H11, H13, H15, H17, H19, H21, J12, J18, K11, K19, L12, L18, M11, M13, M15 M17,

M19, N8, N10, N12, N14, N16, N18, N20, N22, P9, P11, P13, P15, P17, P19, P21, R8,
R10, R12, R14, R16, R18, R20, R22, T9, T11, T13, T15, T17, T19, T21, U8, U10, U12, U14,
U16, U18, U20, U22, V9, V11, V13, V15, V17, V19, V21, V23, W8, W10, W18, W20, W22,
Y9, Y19, Y21, Y23, AA8, AA10, AA12, AA14, AA16, AA18, AA20, AA22, AB23

CVDD1 G6, H1, H3, H5, H7, H9, J2, J4, J6, J8, J10, J14, J16, J20, J22, K7, K9, K13, K15, K17, K21,

L8, L10, L14, L16, L20, L22, M9, M21, W12, W14, W16, Y11, Y13, Y15, Y17, AD1, AD3,
AE2, AF1, AG2, AH1, AJ2

DVDD15 A2, A11, A17, A28, B1, B29, C14, C25, D5, D8, D20, D23, E3, F5, F7, F9, F11, F17, F19,

F27, G2, G4, G8, G10, G12, G14, G16 G18, G20, G22, G24

DVDD18 G28, H25, V5, Y5, Y25, AB5, AB17, AB19, AB21, AC2, AC4, AE24, AE27, AF19, AF22,

AH26, AH29, AJ28

VDDR1 K6 1.5 HyperLink SerDes regulator supply

VDDR2 AE15 1.5 PCIe SerDes regulator supply

VDDR3 AE6 1.5 SGMII SerDes regulator supply

VDDR4 AE11 1.5 SRIO SerDes regulator supply

VDDR5 R25

VDDR6 N25

VDDT1 M7, N6, P7, R6, T7, V7, W6, Y7 1.0 HyperLink SerDes termination supply

VDDT2 AC6, AC8, AC10, AC12, AC14, AD5, AD7, AD9, AD11, AD13, AE4, AE10, AE12 1.0 SGMII/SRIO/PCIe SerDes termination supply

VDDT3 K25, L24, M23, M25, N24, P23, P25, R24, T23, T25, U24, V25 1.0 AIF SerDes termination supply

VREFSSTL E14 0.75 DDR3 reference voltage

VSS A1, A29, B11, B17, B25, C8, C23, D3, D14, D18, E5, E20, F6, F8, F10, F12, F16, F18, F26,

F28, F29, G1, G3, G5, G7, G9, G11, G13, G15, G17, G19, G21, G23, G25, H2, H4, H6, H8,
H10, H12, H14, H16, H18, H20, H22, J1, J3, J5, J7, J9, J11, J13, J15, J17, J19, J21, J27,
J29, K1, K2, K3, K4, K5, K8, K10, K12, K14, K16, K18, K20, K22, K26, K28, L2, L3,L5, L6,
L7, L9, L11, L13, L15, L17, L19, L21, L23, M3, M6, M8, M10, M12, M14, M16, M18, M20,
M22, M24, M27, M29, N1, N3, N4, N7, N9, N11, N13, N15, N17, N19, N21, N23, N26,
N28, P2, P3, P5, P6, P8, P10, P12, P14, P16, P18, P20, P22, P24, R3, R7, R9, R11, R13,
R15, R17, R19, R21, R23, R27, R29, T1, T3, T4, T6, T8, T10, T12, T14, T16, T18, T20, T22,
T24, T26, T28, U1, U2, U3, U4, U5, U6, U7, U9, U11, U13, U15, U17, U19, U21, U23, V6,
V8, V10, V12, V14, V16, V18, V20, V22, V24, V27, V29, W5, W7, W9, W11, W13, W15,
W17, W19, W21, W23, W25, W26, W28, W29, Y6, Y8, Y10, Y12, Y14, Y16, Y18, Y20,
Y22, Y24, Y26, AA5, AA6, AA7, AA9, AA11, AA13, AA15, AA17, AA19, AA21, AA23,
AA25, AB2, AB6, AB7, AB8, AB9, AB10, AB11, AB12, AB13, AB14, AB16, AB18, AB20,
AB22, AB24, AC1, AC3, AC5, AC7, AC9, AC11, AC13, AC15, AD2, AD4, AD6, AD8,
AD10, AD12, AD14, AD24, AD27, AE1, AE3, AE7, AE9, AE13, AF2, AF5, AF8, AF11,
AF14, AF15, AF20, AG1, AG3, AG6, AG9, AG12, AG15, AG22, AG26, AH2, AH5, AH8,
AH11, AH14, AJ1, AJ3, AJ6, AJ9, AJ12, AJ15, AJ29

End of Table 2-16

SmartReflex core supply voltage

to

1.1

1.0 Fixed core supply voltage

1.5 DDR IO supply

1.8 IO supply

1.5 AIF SerDes regulator supply

Gnd Ground

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Table 2-17 Terminal Functions

— By Signal Name
(Part 1 of 11)

Signal Name Ball Number

AIFRXN0 L28

AIFRXN1 K29

AIFRXN2 R28

AIFRXN3 P29

AIFRXN4 T29

AIFRXN5 U28

AIFRXP0 M28

AIFRXP1 L29

AIFRXP2 P28

AIFRXP3 N29

AIFRXP4 U29

AIFRXP5 V28

AIFTXN0 L26

AIFTXN1 L27

AIFTXN2 R26

AIFTXN3 P27

AIFTXN4 U27

AIFTXN5 U26

AIFTXP0 M26

AIFTXP1 K27

AIFTXP2 P26

AIFTXP3 N27

AIFTXP4 T27

AIFTXP5 V26

ALTCORECLKN AB28

ALTCORECLKP AB29

AVDDA1 W24

AVDDA2 J26

AVDDA3 AB15

BOOTCOMPLETE AC21

BOOTMODE00 † AG18

BOOTMODE01 † AD19

BOOTMODE02 † AE19

BOOTMODE03 † AF18

BOOTMODE04 † AE18

BOOTMODE05 † AG20

BOOTMODE06 † AH19

BOOTMODE07 † AJ19

BOOTMODE08 † AE21

BOOTMODE09 † AG19

BOOTMODE10 † AD20

BOOTMODE11 † AE20

Table 2-17 Terminal Functions

— By Signal Name
(Part 2 of 11)

Signal Name Ball Number

BOOTMODE12 † AF21

CORECLKSEL AB25

CORESEL0 AH15

CORESEL1 AC16

CORESEL2 AD15

CVDD H11, H13, H15, H17,

H19, H21, J12, J18,
K11, K19, L12, L18,
M11, M13, M15
M17, M19, N8, N10,
N12, N14, N16, N18,
N20, N22, P9, P11,
P13, P15, P17, P19

CVDD P21, R8, R10, R12,

R14, R16, R18, R20,
R22, T9, T11, T13,
T15, T17, T19, T21,
U8, U10, U12, U14,
U16, U18, U20, U22,
V9, V11, V13, V15,
V17, V19, V21, V23

CVDD W8, W10, W18, W20,

W22, Y9, Y19, Y21,
Y23, AA8, AA10,
AA12, AA14, AA16,
AA18, AA20, AA22,
AB23

CVDD1 G6, H1, H3, H5, H7,

H9, J2, J4, J6, J8, J10,
J14, J16, J20, J22, K7,
K9, K13, K15, K17,
K21, L8, L10, L14,
L16, L20, L22, M9,
M21, W12, W14,
W16, Y11, Y13, Y15,
Y17, AD1, AD3, AE2,
AF1, AG2, AH1, AJ2

DDRA00 A14

DDRA01 B14

DDRA02 F14

DDRA03 F13

DDRA04 A15

DDRA05 C15

DDRA06 B15

DDRA07 D15

DDRA08 F15

DDRA09 E15

DDRA10 E16

DDRA11 D16

DDRA12 E17

DDRA13 C16

DDRA14 D17

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Table 2-17 Terminal Functions

—BySignalName
(Part 3 of 11)

Signal Name Ball Number

DDRA15 C17

DDRBA0 A13

DDRBA1 B13

DDRBA2 C13

DDRCAS

DDRCB00 E19

DDRCB01 C20

DDRCB02 D19

DDRCB03 B20

DDRCB04 C19

DDRCB05 C18

DDRCB06 B18

DDRCB07 A18

DDRCE0

DDRCE1

DDRCKE0 D11

DDRCKE1 E18

DDRCLKN H29

DDRCLKOUTN0 B12

DDRCLKOUTN1 B16

DDRCLKOUTP0 A12

DDRCLKOUTP1 A16

DDRCLKP G29

DDRD00 E28

DDRD01 D29

DDRD02 E27

DDRD03 D28

DDRD04 D27

DDRD05 B28

DDRD06 E26

DDRD07 F25

DDRD08 F24

DDRD09 E24

DDRD10 E25

DDRD11 D25

DDRD12 D26

DDRD13 C26

DDRD14 B26

DDRD15 A26

DDRD16 F23

DDRD17 F22

DDRD18 D24

D12

C11

C12

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Table 2-17 Terminal Functions

— By Signal Name
(Part 4 of 11)

Signal Name Ball Number

DDRD19 E23

DDRD20 A23

DDRD21 B23

DDRD22 C24

DDRD23 E22

DDRD24 D21

DDRD25 F20

DDRD26 E21

DDRD27 F21

DDRD28 D22

DDRD29 C21

DDRD30 B22

DDRD31 C22

DDRD32 E10

DDRD33 D10

DDRD34 B10

DDRD35 D9

DDRD36 E9

DDRD37 C9

DDRD38 B8

DDRD39 E8

DDRD40 A7

DDRD41 D7

DDRD42 E7

DDRD43 C7

DDRD44 B7

DDRD45 E6

DDRD46 D6

DDRD47 C6

DDRD48 C5

DDRD49 A5

DDRD50 B4

DDRD51 A4

DDRD52 D4

DDRD53 E4

DDRD54 C4

DDRD55 C3

DDRD56 F4

DDRD57 D2

DDRD58 E2

DDRD59 C2

DDRD60 F2

Multicore Fixed and Floating-Point System-on-Chip

Table 2-17 Terminal Functions

— By Signal Name
(Part 5 of 11)

Signal Name Ball Number

DDRD61 F3

DDRD62 E1

DDRD63 F1

DDRDQM0 E29

DDRDQM1 C27

DDRDQM2 A25

DDRDQM3 A22

DDRDQM4 A10

DDRDQM5 A8

DDRDQM6 B5

DDRDQM7 B2

DDRDQM8 A20

DDRDQS0N C29

DDRDQS0P C28

DDRDQS1N B27

DDRDQS1P A27

DDRDQS2N B24

DDRDQS2P A24

DDRDQS3N B21

DDRDQS3P A21

DDRDQS4N B9

DDRDQS4P A9

DDRDQS5N A6

DDRDQS5P B6

DDRDQS6N A3

DDRDQS6P B3

DDRDQS7N C1

DDRDQS7P D1

DDRDQS8N B19

DDRDQS8P A19

DDRODT0 D13

DDRODT1 E13

DDRRAS

DDRRESET

DDRSLRATE0 H27

DDRSLRATE1 H26

DDRWE

DVDD15 A2, A11, A17, A28,

C10

E11

E12

B1, B29, C14, C25,
D5, D8, D20, D23,
E3, F5, F7, F9, F11,
F17, F19, F27, G2,
G4, G8, G10, G12,
G14, G16 G18, G20,
G22, G24

TMS320C6670

SPRS689D—March 2012

Table 2-17 Terminal Functions

—BySignalName
(Part 6 of 11)

Signal Name Ball Number

DVDD18 G28, H25, V5, Y5,

Y25, AB5, AB17,
AB19, AB21, AC2,
AC4, AE24, AE27,
AF19, AF22, AH26,
AH29, AJ28

EMU00 AE29

EMU01 AF29

EMU02 AE28

EMU03 AF28

EMU04 AE26

EMU05 AD25

EMU06 AF25

EMU07 AE25

EMU08 AF27

EMU09 AG29

EMU10 AF26

EMU11 AG28

EMU12 AG27

EMU13 AG25

EMU14 AH28

EMU15 AJ27

EMU16 AH27

EMU17 AJ26

EMU18 AH25

EXTFRAMEEVENT AE17

GPIO00 AJ20

GPIO01 AG18

GPIO02 AD19

GPIO03 AE19

GPIO04 AF18

GPIO05 AE18

GPIO06 AG20

GPIO07 AH19

GPIO08 AJ19

GPIO09 AE21

GPIO10 AG19

GPIO11 AD20

GPIO12 AE20

GPIO13 AF21

GPIO14 AH20

GPIO15 AD21

HOUT AC18

LENDIAN AJ20 †

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TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

Table 2-17 Terminal Functions

— By Signal Name
(Part 7 of 11)

Signal Name Ball Number

LRESETNMIEN AC20

LRESET

MCMCLKN W2

MCMCLKP W1

MCMREFCLKOUTN V1

MCMREFCLKOUTP V2

MCMRXFLCLK V3

MCMRXFLDAT W3

MCMRXN0 T2

MCMRXN1 P1

MCMRXN2 L1

MCMRXN3 N2

MCMRXP0 R2

MCMRXP1 R1

MCMRXP2 M1

MCMRXP3 M2

MCMRXPMCLK AA3

MCMRXPMDAT Y3

MCMTXFLCLK Y1

MCMTXFLDAT Y2

MCMTXN0 T5

MCMTXN1 R4

MCMTXN2 L4

MCMTXN3 M5

MCMTXP0 R5

MCMTXP1 P4

MCMTXP2 M4

MCMTXP3 N5

MCMTXPMCLK AA2

MCMTXPMDAT AA1

MDCLK AF16

MDIO AG16

NMI

PACLKSEL AD23

PASSCLKN AH18

PASSCLKP AJ18

PCIECLKN AJ17

PCIECLKP AH17

PCIERXN0 AJ14

PCIERXN1 AH12

PCIERXP0 AJ13

PCIERXP1 AH13

AE22

AC25

Table 2-17 Terminal Functions

— By Signal Name
(Part 8 of 11)

Signal Name Ball Number

PCIESSMODE0 † AH20

PCIESSMODE1 † AD21

PCIESSEN † AJ23

PCIETXN0 AG14

PCIETXN1 AF12

PCIETXP0 AG13

PCIETXP1 AF13

PHYSYNC AB27

POR

PTV15 H24

RADSYNC AA27

RESETFULL

RESETSTAT

RESET

RIORXN0 AJ11

RIORXN1 AH10

RIORXN2 AJ7

RIORXN3 AH6

RIORXP0 AJ10

RIORXP1 AH9

RIORXP2 AJ8

RIORXP3 AH7

RIOTXN0 AG11

RIOTXN1 AF9

RIOTXN2 AG7

RIOTXN3 AF6

RIOTXP0 AG10

RIOTXP1 AF10

RIOTXP2 AG8

RIOTXP3 AF7

RP1CLKN AA28

RP1CLKP Y28

RP1FBN AA29

RP1FBP Y29

RSV01 AJ25

RSV03 AC23

RSV04 Y27

RSV05 W27

RSV06 J28

RSV07 H28

RSV08 J24

RSV09 J25

AC19

AE23

AD18

AC24

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Table 2-17 Terminal Functions

—BySignalName
(Part 9 of 11)

Signal Name Ball Number

RSV0A K24

RSV0B K23

RSV10 H23

RSV11 J23

RSV12 AD22

RSV13 AC22

RSV14 V4

RSV15 AE8

RSV16 AE14

RSV17 AE5

RSV18 AA24

RSV19 G27

RSV20 AB26

RSV21 G26

RSV22 AE16

RSV23 AD16

RSV24 AG17

RSV25 AF17

RSV26 U25

RSV27 L25

RSV28 Y4

RSV29 W4

SCL AC17

SDA AD17

SGMII0RXN AH3

SGMII0RXP AH4

SGMII0TXN AF3

SGMII0TXP AF4

SGMII1RXN AJ4

SGMII1RXP AJ5

SGMII1TXN AG4

SGMII1TXP AG5

SPICLK AG21

SPIDIN AH22

SPIDOUT AJ21

SPISCS0 AH21

SPISCS1 AJ22

SRIOSGMIICLKN AH16

SRIOSGMIICLKP AJ16

SYSCLKN AC28

SYSCLKOUT AA26

SYSCLKP AC29

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Table 2-17 Terminal Functions

— By Signal Name
(Part 10 of 11)

Signal Name Ball Number

TCK AD29

TDI AD28

TDO AC27

TIMI0 AJ23

TIMI1 AG23

TIMO0 AH23

TIMO1 AF23

TMS AC26

TRST

UARTCTS AH24

UARTRTS AG24

UARTRXD AF24

UARTTXD AJ24

VCNTL0 AB4

VCNTL1 AB3

VCNTL2 AA4

VCNTL3 AB1

VDDR1 K6

VDDR2 AE15

VDDR3 AE6

VDDR4 AE11

VDDR5 R25

VDDR6 N25

VDDT1 M7, N6, P7, R6, T7,

VDDT2 AC6, AC8, AC10,

VDDT3 K25, L24, M23, M25,

VREFSSTL E14

VSS A1, A29, B11, B17,

VSS H2, H4, H6, H8, H10,

AD26

V7, W6, Y7

AC12, AC14, AD5,
AD7, AD9, AD11,
AD13, AE4, AE10,
AE12

N24, P23, P25, R24,
T23, T25, U24, V25

B25, C8, C23, D3,
D14, D18, E5, E20,
F6, F8, F10, F12, F16,
F18, F26, F28, F29,
G1, G3, G5, G7, G9,
G11, G13, G15, G17,
G19, G21, G23, G25

H12, H14, H16, H18,
H20, H22, J1, J3, J5,
J7, J9, J11, J13, J15,
J17, J19, J21, J27,
J29, K1, K2, K3, K4,
K5, K8, K10, K12,
K14, K16, K18, K20

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

Table 2-17 Terminal Functions

— By Signal Name
(Part 11 of 11)

Signal Name Ball Number

VSS K22, K26, K28, L2,

L3,L5, L6, L7, L9, L11,
L13, L15, L17, L19,
L21, L23, M3, M6,
M8, M10, M12, M14,
M16, M18, M20,
M22, M24, M27,
M29, N1, N3, N4, N7

VSS N9, N11, N13, N15,

N17, N19, N21, N23,
N26, N28, P2, P3, P5,
P6, P8, P10, P12,
P14, P16, P18, P20,
P22, P24, R3, R7, R9,
R11, R13, R15, R17,
R19, R21, R23, R27

VSS R29, T1, T3, T4, T6,

T8, T10, T12, T14,
T16, T18, T20, T22,
T24, T26, T28, U1,
U2, U3, U4, U5, U6,
U7, U9, U11, U13,
U15, U17, U19, U21,
U23, V6, V8, V10

VSS V12, V14, V16, V18,

V20, V22, V24, V27,
V29, W5, W7, W9,
W11, W13, W15,
W17, W19, W21,
W23, W25, W26,
W28, W29, Y6, Y8,
Y10, Y12, Y14, Y16

VSS Y18, Y20, Y22, Y24,

Y26, AA5, AA6, AA7,
AA9, AA11, AA13,
AA15, AA17, AA19,
AA21, AA23, AA25,
AB2, AB6, AB7, AB8,
AB9, AB10, AB11,
AB12, AB13, AB14

VSS AB16, AB18, AB20,

AB22, AB24, AC1,
AC3, AC5, AC7, AC9,
AC11, AC13, AC15,
AD2, AD4, AD6,
AD8, AD10, AD12,
AD14, AD24, AD27,
AE1, AE3, AE7, AE9

VSS AE13, AF2, AF5, AF8,

AF11, AF14, AF15,
AF20, AG1, AG3,
AG6, AG9, AG12,
AG15, AG22, AG26,
AH2, AH5, AH8,
AH11, AH14, AJ1,
AJ3, AJ6, AJ9, AJ12

VSS AJ15, AJ29

End of Table 2-17

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TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

Table 2-18 Terminal Functions

— By Ball Number
(Part 1 of 21)

Ball Number Signal Name

A1 VSS

A2 DVDD15

A3 DDRDQS6N

A4 DDRD51

A5 DDRD49

A6 DDRDQS5N

A7 DDRD40

A8 DDRDQM5

A9 DDRDQS4P

A10 DDRDQM4

A11 DVDD15

A12 DDRCLKOUTP0

A13 DDRBA0

A14 DDRA00

A15 DDRA04

A16 DDRCLKOUTP1

A17 DVDD15

A18 DDRCB07

A19 DDRDQS8P

A20 DDRDQM8

A21 DDRDQS3P

A22 DDRDQM3

A23 DDRD20

A24 DDRDQS2P

A25 DDRDQM2

A26 DDRD15

A27 DDRDQS1P

A28 DVDD15

A29 VSS

B1 DVDD15

B2 DDRDQM7

B3 DDRDQS6P

B4 DDRD50

B5 DDRDQM6

B6 DDRDQS5P

B7 DDRD44

B8 DDRD38

B9 DDRDQS4N

B10 DDRD34

B11 VSS

B12 DDRCLKOUTN0

B13 DDRBA1

Table 2-18 Terminal Functions

— By Ball Number
(Part 2 of 21)

Ball Number Signal Name

B14 DDRA01

B15 DDRA06

B16 DDRCLKOUTN1

B17 VSS

B18 DDRCB06

B19 DDRDQS8N

B20 DDRCB03

B21 DDRDQS3N

B22 DDRD30

B23 DDRD21

B24 DDRDQS2N

B25 VSS

B26 DDRD14

B27 DDRDQS1N

B28 DDRD05

B29 DVDD15

C1 DDRDQS7N

C2 DDRD59

C3 DDRD55

C4 DDRD54

C5 DDRD48

C6 DDRD47

C7 DDRD43

C8 VSS

C9 DDRD37

C10 DDRRAS

C11 DDRCE0

C12 DDRCE1

C13 DDRBA2

C14 DVDD15

C15 DDRA05

C16 DDRA13

C17 DDRA15

C18 DDRCB05

C19 DDRCB04

C20 DDRCB01

C21 DDRD29

C22 DDRD31

C23 VSS

C24 DDRD22

C25 DVDD15

C26 DDRD13

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Table 2-18 Terminal Functions

— By Ball Number
(Part 3 of 21)

Ball Number Signal Name

C27 DDRDQM1

C28 DDRDQS0P

C29 DDRDQS0N

D1 DDRDQS7P

D2 DDRD57

D3 VSS

D4 DDRD52

D5 DVDD15

D6 DDRD46

D7 DDRD41

D8 DVDD15

D9 DDRD35

D10 DDRD33

D11 DDRCKE0

D12 DDRCAS

D13 DDRODT0

D14 VSS

D15 DDRA07

D16 DDRA11

D17 DDRA14

D18 VSS

D19 DDRCB02

D20 DVDD15

D21 DDRD24

D22 DDRD28

D23 DVDD15

D24 DDRD18

D25 DDRD11

D26 DDRD12

D27 DDRD04

D28 DDRD03

D29 DDRD01

E1 DDRD62

E2 DDRD58

E3 DVDD15

E4 DDRD53

E5 VSS

E6 DDRD45

E7 DDRD42

E8 DDRD39

E9 DDRD36

E10 DDRD32

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Table 2-18 Terminal Functions

— By Ball Number
(Part 4 of 21)

Ball Number Signal Name

E11 DDRRESET

E12 DDRWE

E13 DDRODT1

E14 VREFSSTL

E15 DDRA09

E16 DDRA10

E17 DDRA12

E18 DDRCKE1

E19 DDRCB00

E20 VSS

E21 DDRD26

E22 DDRD23

E23 DDRD19

E24 DDRD09

E25 DDRD10

E26 DDRD06

E27 DDRD02

E28 DDRD00

E29 DDRDQM0

F1 DDRD63

F2 DDRD60

F3 DDRD61

F4 DDRD56

F5 DVDD15

F6 VSS

F7 DVDD15

F8 VSS

F9 DVDD15

F10 VSS

F11 DVDD15

F12 VSS

F13 DDRA03

F14 DDRA02

F15 DDRA08

F16 VSS

F17 DVDD15

F18 VSS

F19 DVDD15

F20 DDRD25

F21 DDRD27

F22 DDRD17

F23 DDRD16

Multicore Fixed and Floating-Point System-on-Chip

Table 2-18 Terminal Functions

— By Ball Number
(Part 5 of 21)

Ball Number Signal Name

F24 DDRD08

F25 DDRD07

F26 VSS

F27 DVDD15

F28 VSS

F29 VSS

G1 VSS

G2 DVDD15

G3 VSS

G4 DVDD15

G5 VSS

G6 CVDD1

G7 VSS

G8 DVDD15

G9 VSS

G10 DVDD15

G11 VSS

G12 DVDD15

G13 VSS

G14 DVDD15

G15 VSS

G16 DVDD15

G17 VSS

G18 DVDD15

G19 VSS

G20 DVDD15

G21 VSS

G22 DVDD15

G23 VSS

G24 DVDD15

G25 VSS

G26 RSV21

G27 RSV19

G28 DVDD18

G29 DDRCLKP

H1 CVDD1

H2 VSS

H3 CVDD1

H4 VSS

H5 CVDD1

H6 VSS

H7 CVDD1

TMS320C6670

SPRS689D—March 2012

Table 2-18 Terminal Functions

— By Ball Number
(Part 6 of 21)

Ball Number Signal Name

H8 VSS

H9 CVDD1

H10 VSS

H11 CVDD

H12 VSS

H13 CVDD

H14 VSS

H15 CVDD

H16 VSS

H17 CVDD

H18 VSS

H19 CVDD

H20 VSS

H21 CVDD

H22 VSS

H23 RSV10

H24 PTV15

H25 DVDD18

H26 DDRSLRATE1

H27 DDRSLRATE0

H28 RSV07

H29 DDRCLKN

J1 VSS

J2 CVDD1

J3 VSS

J4 CVDD1

J5 VSS

J6 CVDD1

J7 VSS

J8 CVDD1

J9 VSS

J10 CVDD1

J11 VSS

J12 CVDD

J13 VSS

J14 CVDD1

J15 VSS

J16 CVDD1

J17 VSS

J18 CVDD

J19 VSS

J20 CVDD1

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TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

Table 2-18 Terminal Functions

— By Ball Number
(Part 7 of 21)

Ball Number Signal Name

J21 VSS

J22 CVDD1

J23 RSV11

J24 RSV08

J25 RSV09

J26 AVDDA2

J27 VSS

J28 RSV06

J29 VSS

K1 VSS

K2 VSS

K3 VSS

K4 VSS

K5 VSS

K6 VDDR1

K7 CVDD1

K8 VSS

K9 CVDD1

K10 VSS

K11 CVDD

K12 VSS

K13 CVDD1

K14 VSS

K15 CVDD1

K16 VSS

K17 CVDD1

K18 VSS

K19 CVDD

K20 VSS

K21 CVDD1

K22 VSS

K23 RSV0B

K24 RSV0A

K25 VDDT3

K26 VSS

K27 AIFTXP1

K28 VSS

K29 AIFRXN1

L1 MCMRXN2

L2 VSS

L3 VSS

L4 MCMTXN2

Table 2-18 Terminal Functions

— By Ball Number
(Part 8 of 21)

Ball Number Signal Name

L5 VSS

L6 VSS

L7 VSS

L8 CVDD1

L9 VSS

L10 CVDD1

L11 VSS

L12 CVDD

L13 VSS

L14 CVDD1

L15 VSS

L16 CVDD1

L17 VSS

L18 CVDD

L19 VSS

L20 CVDD1

L21 VSS

L22 CVDD1

L23 VSS

L24 VDDT3

L25 RSV27

L26 AIFTXN0

L27 AIFTXN1

L28 AIFRXN0

L29 AIFRXP1

M1 MCMRXP2

M2 MCMRXP3

M3 VSS

M4 MCMTXP2

M5 MCMTXN3

M6 VSS

M7 VDDT1

M8 VSS

M9 CVDD1

M10 VSS

M11 CVDD

M12 VSS

M13 CVDD

M14 VSS

M15 CVDD

M16 VSS

M17 CVDD

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Table 2-18 Terminal Functions

— By Ball Number
(Part 9 of 21)

Ball Number Signal Name

M18 VSS

M19 CVDD

M20 VSS

M21 CVDD1

M22 VSS

M23 VDDT3

M24 VSS

M25 VDDT3

M26 AIFTXP0

M27 VSS

M28 AIFRXP0

M29 VSS

N1 VSS

N2 MCMRXN3

N3 VSS

N4 VSS

N5 MCMTXP3

N6 VDDT1

N7 VSS

N8 CVDD

N9 VSS

N10 CVDD

N11 VSS

N12 CVDD

N13 VSS

N14 CVDD

N15 VSS

N16 CVDD

N17 VSS

N18 CVDD

N19 VSS

N20 CVDD

N21 VSS

N22 CVDD

N23 VSS

N24 VDDT3

N25 VDDR6

N26 VSS

N27 AIFTXP3

N28 VSS

N29 AIFRXP3

P1 MCMRXN1

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Table 2-18 Terminal Functions

— By Ball Number
(Part 10 of 21)

Ball Number Signal Name

P2 VSS

P3 VSS

P4 MCMTXP1

P5 VSS

P6 VSS

P7 VDDT1

P8 VSS

P9 CVDD

P10 VSS

P11 CVDD

P12 VSS

P13 CVDD

P14 VSS

P15 CVDD

P16 VSS

P17 CVDD

P18 VSS

P19 CVDD

P20 VSS

P21 CVDD

P22 VSS

P23 VDDT3

P24 VSS

P25 VDDT3

P26 AIFTXP2

P27 AIFTXN3

P28 AIFRXP2

P29 AIFRXN3

R1 MCMRXP1

R2 MCMRXP0

R3 VSS

R4 MCMTXN1

R5 MCMTXP0

R6 VDDT1

R7 VSS

R8 CVDD

R9 VSS

R10 CVDD

R11 VSS

R12 CVDD

R13 VSS

R14 CVDD

Multicore Fixed and Floating-Point System-on-Chip

Table 2-18 Terminal Functions

— By Ball Number
(Part 11 of 21)

Ball Number Signal Name

R15 VSS

R16 CVDD

R17 VSS

R18 CVDD

R19 VSS

R20 CVDD

R21 VSS

R22 CVDD

R23 VSS

R24 VDDT3

R25 VDDR5

R26 AIFTXN2

R27 VSS

R28 AIFRXN2

R29 VSS

T1 VSS

T2 MCMRXN0

T3 VSS

T4 VSS

T5 MCMTXN0

T6 VSS

T7 VDDT1

T8 VSS

T9 CVDD

T10 VSS

T11 CVDD

T12 VSS

T13 CVDD

T14 VSS

T15 CVDD

T16 VSS

T17 CVDD

T18 VSS

T19 CVDD

T20 VSS

T21 CVDD

T22 VSS

T23 VDDT3

T24 VSS

T25 VDDT3

T26 VSS

T27 AIFTXP4

TMS320C6670

SPRS689D—March 2012

Table 2-18 Terminal Functions

— By Ball Number
(Part 12 of 21)

Ball Number Signal Name

T28 VSS

T29 AIFRXN4

U1 VSS

U2 VSS

U3 VSS

U4 VSS

U5 VSS

U6 VSS

U7 VSS

U8 CVDD

U9 VSS

U10 CVDD

U11 VSS

U12 CVDD

U13 VSS

U14 CVDD

U15 VSS

U16 CVDD

U17 VSS

U18 CVDD

U19 VSS

U20 CVDD

U21 VSS

U22 CVDD

U23 VSS

U24 VDDT3

U25 RSV26

U26 AIFTXN5

U27 AIFTXN4

U28 AIFRXN5

U29 AIFRXP4

V1 MCMREFCLKOUTN

V2 MCMREFCLKOUTP

V3 MCMRXFLCLK

V4 RSV14

V5 DVDD18

V6 VSS

V7 VDDT1

V8 VSS

V9 CVDD

V10 VSS

V11 CVDD

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TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

Table 2-18 Terminal Functions

— By Ball Number
(Part 13 of 21)

Ball Number Signal Name

V12 VSS

V13 CVDD

V14 VSS

V15 CVDD

V16 VSS

V17 CVDD

V18 VSS

V19 CVDD

V20 VSS

V21 CVDD

V22 VSS

V23 CVDD

V24 VSS

V25 VDDT3

V26 AIFTXP5

V27 VSS

V28 AIFRXP5

V29 VSS

W1 MCMCLKP

W2 MCMCLKN

W3 MCMRXFLDAT

W4 RSV29

W5 VSS

W6 VDDT1

W7 VSS

W8 CVDD

W9 VSS

W10 CVDD

W11 VSS

W12 CVDD1

W13 VSS

W14 CVDD1

W15 VSS

W16 CVDD1

W17 VSS

W18 CVDD

W19 VSS

W20 CVDD

W21 VSS

W22 CVDD

W23 VSS

W24 AVDDA1

Table 2-18 Terminal Functions

— By Ball Number
(Part 14 of 21)

Ball Number Signal Name

W25 VSS

W26 VSS

W27 RSV05

W28 VSS

W29 VSS

Y1 MCMTXFLCLK

Y2 MCMTXFLDAT

Y3 MCMRXPMDAT

Y4 RSV28

Y5 DVDD18

Y6 VSS

Y7 VDDT1

Y8 VSS

Y9 CVDD

Y10 VSS

Y11 CVDD1

Y12 VSS

Y13 CVDD1

Y14 VSS

Y15 CVDD1

Y16 VSS

Y17 CVDD1

Y18 VSS

Y19 CVDD

Y20 VSS

Y21 CVDD

Y22 VSS

Y23 CVDD

Y24 VSS

Y25 DVDD18

Y26 VSS

Y27 RSV04

Y28 RP1CLKP

Y29 RP1FBP

AA1 MCMTXPMDAT

AA2 MCMTXPMCLK

AA3 MCMRXPMCLK

AA4 VCNTL2

AA5 VSS

AA6 VSS

AA7 VSS

AA8 CVDD

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Table 2-18 Terminal Functions

— By Ball Number
(Part 15 of 21)

Ball Number Signal Name

AA9 VSS

AA10 CVDD

AA11 VSS

AA12 CVDD

AA13 VSS

AA14 CVDD

AA15 VSS

AA16 CVDD

AA17 VSS

AA18 CVDD

AA19 VSS

AA20 CVDD

AA21 VSS

AA22 CVDD

AA23 VSS

AA24 RSV18

AA25 VSS

AA26 SYSCLKOUT

AA27 RADSYNC

AA28 RP1CLKN

AA29 RP1FBN

AB1 VCNTL3

AB2 VSS

AB3 VCNTL1

AB4 VCNTL0

AB5 DVDD18

AB6 VSS

AB7 VSS

AB8 VSS

AB9 VSS

AB10 VSS

AB11 VSS

AB12 VSS

AB13 VSS

AB14 VSS

AB15 AVDDA3

AB16 VSS

AB17 DVDD18

AB18 VSS

AB19 DVDD18

AB20 VSS

AB21 DVDD18

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Table 2-18 Terminal Functions

— By Ball Number
(Part 16 of 21)

Ball Number Signal Name

AB22 VSS

AB23 CVDD

AB24 VSS

AB25 CORECLKSEL

AB26 RSV20

AB27 PHYSYNC

AB28 ALTCORECLKN

AB29 ALTCORECLKP

AC1 VSS

AC2 DVDD18

AC3 VSS

AC4 DVDD18

AC5 VSS

AC6 VDDT2

AC7 VSS

AC8 VDDT2

AC9 VSS

AC10 VDDT2

AC11 VSS

AC12 VDDT2

AC13 VSS

AC14 VDDT2

AC15 VSS

AC16 CORESEL1

AC17 SCL

AC18 HOUT

AC19 POR

AC20 LRESETNMIEN

AC21 BOOTCOMPLETE

AC22 RSV13

AC23 RSV03

AC24 RESET

AC25 NMI

AC26 TMS

AC27 TDO

AC28 SYSCLKN

AC29 SYSCLKP

AD1 CVDD1

AD2 VSS

AD3 CVDD1

AD4 VSS

AD5 VDDT2

Multicore Fixed and Floating-Point System-on-Chip

Table 2-18 Terminal Functions

— By Ball Number
(Part 17 of 21)

Ball Number Signal Name

AD6 VSS

AD7 VDDT2

AD8 VSS

AD9 VDDT2

AD10 VSS

AD11 VDDT2

AD12 VSS

AD13 VDDT2

AD14 VSS

AD15 CORESEL2

AD16 RSV23

AD17 SDA

AD18 RESETSTAT

AD19 GPIO02

AD19 † BOOTMODE01

AD20 GPIO11

AD20 † BOOTMODE10

AD21 GPIO15

AD21 † PCIESSMODE1

AD22 RSV12

AD23 PACLKSEL

AD24 VSS

AD25 EMU05

AD26 TRST

AD27 VSS

AD28 TDI

AD29 TCK

AE1 VSS

AE2 CVDD1

AE3 VSS

AE4 VDDT2

AE5 RSV17

AE6 VDDR3

AE7 VSS

AE8 RSV15

AE9 VSS

AE10 VDDT2

AE11 VDDR4

AE12 VDDT2

AE13 VSS

AE14 RSV16

AE15 VDDR2

TMS320C6670

SPRS689D—March 2012

Table 2-18 Terminal Functions

— By Ball Number
(Part 18 of 21)

Ball Number Signal Name

AE16 RSV22

AE17 EXTFRAMEEVENT

AE18 GPIO05

AE18 † BOOTMODE04

AE19 GPIO03

AE19 † BOOTMODE02

AE20 GPIO12

AE20 † BOOTMODE11

AE21 GPIO09

AE22 LRESET

AE23 RESETFULL

AE24 DVDD18

AE25 EMU07

AE26 EMU04

AE27 DVDD18

AE28 EMU02

AE29 EMU00

AF1 CVDD1

AF2 VSS

AF3 SGMII0TXN

AF4 SGMII0TXP

AF5 VSS

AF6 RIOTXN3

AF7 RIOTXP3

AF8 VSS

AF9 RIOTXN1

AF10 RIOTXP1

AF11 VSS

AF12 PCIETXN1

AF13 PCIETXP1

AF14 VSS

AF15 VSS

AF16 MDCLK

AF17 RSV25

AF18 GPIO04

AF18 † BOOTMODE03

AF19 DVDD18

AF20 VSS

AF21 GPIO13

AF21 † BOOTMODE12

AF22 DVDD18

AF23 TIMO1

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Multicore Fixed and Floating-Point System-on-Chip

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Table 2-18 Terminal Functions

— By Ball Number
(Part 19 of 21)

Ball Number Signal Name

AF24 UARTRXD

AF25 EMU06

AF26 EMU10

AF27 EMU08

AF28 EMU03

AF29 EMU01

AG1 VSS

AG2 CVDD1

AG3 VSS

AG4 SGMII1TXN

AG5 SGMII1TXP

AG6 VSS

AG7 RIOTXN2

AG8 RIOTXP2

AG9 VSS

AG10 RIOTXP0

AG11 RIOTXN0

AG12 VSS

AG13 PCIETXP0

AG14 PCIETXN0

AG15 VSS

AG16 MDIO

AG17 RSV24

AG18 GPIO01

AG18 † BOOTMODE00

AG19 GPIO10

AG20 GPIO06

AG20 † BOOTMODE05

AG21 SPICLK

AG22 VSS

AG23 TIMI1

AG24 UARTRTS

AG25 EMU13

AG26 VSS

AG27 EMU12

AG28 EMU11

AG29 EMU09

AH1 CVDD1

AH2 VSS

AH3 SGMII0RXN

AH4 SGMII0RXP

AH5 VSS

Table 2-18 Terminal Functions

— By Ball Number
(Part 20 of 21)

Ball Number Signal Name

AH6 RIORXN3

AH7 RIORXP3

AH8 VSS

AH9 RIORXP1

AH10 RIORXN1

AH11 VSS

AH12 PCIERXN1

AH13 PCIERXP1

AH14 VSS

AH15 CORESEL0

AH16 SRIOSGMIICLKN

AH17 PCIECLKP

AH18 PASSCLKN

AH19 GPIO07

AH19 † BOOTMODE06

AH20 GPIO14

AH20 † PCIESSMODE0

AH21 SPISCS0

AH22 SPIDIN

AH23 TIMO0

AH24 UARTCTS

AH25 EMU18

AH26 DVDD18

AH27 EMU16

AH28 EMU14

AH29 DVDD18

AJ1 VSS

AJ2 CVDD1

AJ3 VSS

AJ4 SGMII1RXN

AJ5 SGMII1RXP

AJ6 VSS

AJ7 RIORXN2

AJ8 RIORXP2

AJ9 VSS

AJ10 RIORXP0

AJ11 RIORXN0

AJ12 VSS

AJ13 PCIERXP0

AJ14 PCIERXN0

AJ15 VSS

AJ16 SRIOSGMIICLKP

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Table 2-18 Terminal Functions

— By Ball Number
(Part 21 of 21)

Ball Number Signal Name

AJ17 PCIECLKN

AJ18 PASSCLKP

AJ19 GPIO08

AJ19 † BOOTMODE07

AJ20 GPIO00

AJ20 † LENDIAN

AJ21 SPIDOUT

AJ22 SPISCS1

AJ23 TIMI0

AJ23 † PCIESSEN

AJ24 UARTTXD

AJ25 RSV01

AJ26 EMU17

AJ27 EMU15

AJ28 DVDD18

AJ29 VSS

End of Table 2-18

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Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

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2.8 Development

2.8.1 Development Support

In case the customer would like to develop their own features and software on the C6670 device, TI offers an
extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the
performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug
software and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).

The following products support development of C6000™ DSP-based applications:

• Software Development Tools:
– Code Composer Studio™ Integrated Development Environment (IDE), including Editor C/C++/Assembly

Code Generation, and Debug plus additional development tools

– Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software

needed to support any DSP application.

• Hardware Development Tools:

– Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)
– EVM (Evaluation Module)

2.8.2 Device Support

2.8.2.1 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP devices
and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS
(e.g., TMX320CMH). Texas Instruments recommends two of three possible prefix designators for its support tools:
TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

• TMX: Experimental device that is not necessarily representative of the final device's electrical specifications

• TMP: Final silicon die that conforms to the device's electrical specifications but has not completed quality and
reliability verification

• TMS: Fully qualified production device

Support tool development evolutionary flow:

• TMDX: Development-support product that has not yet completed Texas Instruments internal qualification
testing.

• TMDS: Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer:

Developmental product is intended for internal evaluation purposes.

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of
the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.

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Multicore Fixed and Floating-Point System-on-Chip

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TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for
example, CYP), the temperature range (for example, blank is the default case temperature range), and the device
speed range, in Megahertz (for example, blank is 1000 MHz [1 GHz]).

For device part numbers and further ordering information for TMS320C6670 in the CYP package type, see the TI
website www.ti.com or contact your TI sales representative.

Figure 2-17 provides a legend for reading the complete device name for any C66x+™ DSP generation member.

Figure 2-17 C66x™ DSP Device Nomenclature (including the TMS320C6670 DSP)

PREFIX

TMX=Experimental device
TMS =Qualified device

TMX 320

C6670

()

()

CYP

()

()

DEVICE SPEED RANGE

Blank=1GHz

2 = 1.2GHz

SPRS689D—March 2012

DEVICE FAMILY

320 = TMS320 DSP family

DEVICE

C66x DSP: C6670

SILICON REVISION

Blank=Initial Silicon 1.0
A = Silicon Revision 2.0

TEMPERATURE RANGE

Blank=0°Cto+100°C (default case temperature)

A =Extended temperature range

(-40°Cto+100°C)

PACKAGE TYPE

CYP = 841-pinplasticball grid array,

with Pb-free solder balls

ENCRYPTION

Blank=Encryption NOT enabled

X=Encryption enabled

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Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

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2.9 Related Documentation from Texas Instruments

These documents describe the TMS320C6670 Multicore Fixed and Floating-Point System-on-Chip. Copies of these
documents are available on the Internet at www.ti.com

64-bit Timer (Timer 64) for KeyStone Devices User Guide SPRUGV5

Antenna Interface 2 (AIF2) for KeyStone Devices User Guide SPRUGV7

Bit Coprocessor (BCP) for KeyStone Devices User Guide SPRUGZ1

Bootloader for the C66x DSP User Guide SPRUGY5

C66x CorePac User Guide SPRUGW0

C66x CPU and Instruction Set Reference Guide SPRUGH7

C66x DSP Cache User Guide SPRUGY8

DDR3 Design Guide for KeyStone Devices SPRABI1

DSP Power Consumption Summary for KeyStone Devices SPRABL4

Emulation and Trace Headers Technical Reference SPRU655

Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User Guide SPRUGS5

Fast Fourier Transform Coprocessor (FFTC) for KeyStone Devices User Guide SPRUGS2

General Purpose Input/Output (GPIO) for KeyStone Devices User Guide SPRUGV1

Gigabit Ethernet (GbE) Switch Subsystem for KeyStone Devices User Guide SPRUGV9

Hardware Design Guide for KeyStone Devices SPRABI2

HyperLink for KeyStone Devices User Guide SPRUGW8

2

Inter Integrated Circuit (I

Chip Interrupt Controller (CIC) for KeyStone Devices User Guide SPRUGW4

Memory Protection Unit (MPU) for KeyStone Devices User Guide SPRUGW5

Multicore Navigator for KeyStone Devices User Guide SPRUGR9

Multicore Shared Memory Controller (MSMC) for KeyStone Devices User Guide SPRUGW7

Network Coprocessor (NETCP) for KeyStone Devices User Guide SPRUGZ6

Packet Accelerator (PA) for KeyStone Devices User Guide SPRUGS4

Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User Guide SPRUGS6

Phase Locked Loop (PLL) Controller for KeyStone Devices User Guide SPRUGV2

Power Sleep Controller (PSC) for KeyStone Devices User Guide SPRUGV4

Serial Peripheral Interface (SPI) for KeyStone Devices User Guide SPRUGP2

Serial RapidIO (SRIO) for KeyStone Devices User Guide SPRUGW1

Turbo Decoder Coprocessor 3 (TCP3d) for KeyStone Devices User Guide SPRUGS0

Turbo Encoder Coprocessor 3 (TCP3e) for KeyStone Devices User Guide SPRUGS1

Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User Guide SPRUGP1

Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor Systems SPRA387

Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs SPRA753

Using IBIS Models for Timing Analysis SPRA839

Viterbi Coprocessor (VCP2) for KeyStone Devices User Guide SPRUGV6

C) for KeyStone Devices User Guide SPRUGV3

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3 Device Configuration

On the TMS320C6670 device, certain device configurations like boot mode and endianess, are selected at device
power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset. By
default, the peripherals on the device are disabled and need to be enabled by software before being used.

3.1 Device Configuration at Device Reset

Table 3-1 describes the device configuration pins. The logic level is latched at power-on reset to determine the device

configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors
or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device,
care should be taken to ensure there is no contention on the lines when the device is out of reset. The device
configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid
contention, the control device must stop driving the device configuration pins of the DSP.

Note—If a configuration pin must be routed out from the device and it is not driven (Hi-Z state),

the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an
external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and
situations in which external pullup/pulldown resistors are required, see Section 3.4 ‘‘Pullup/Pulldown

Resistors’’ on page 85.

Table 3-1 Device Configuration Pins

Configuration Pin Pin No. IPD/IPU

LENDIAN

BOOTMODE[12:0]

PCIESSMODE[1:0]

PCIESSEN

CORECLKSEL

PACLKSEL

End of Table 3-1

1 Internal 100-μA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU. For more detailed information on

2 These signal names are the secondary functions of these pins.

(1) (2)

(1) (2)

(1)

(1)

pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Section 3.4 ‘‘Pullup/Pulldown Resistors’’ on page 85.

AJ20 IPU Device endian mode (LENDIAN)

(1) (2)

AF21, AE20, AD20,
AG19, AE21, AJ19,
AH19, AG20,
AE18, AF18, AE19,
AD19, AG18

(1) (2)

AD21, AH20 IPD PCIe subsystem mode selection

AJ23 IPD PCIe subsystem enable/disable

AB25 IPD Core clock select

AD23 IPD Network coprocessor clock select

(1)

Functional Description

0 = Device operates in big endian mode
1 = Device operates in little endian mode

IPD Method of boot

See ‘‘Boot Modes Supported and PLL Settings’’ on page 30 for more details. See the

Bootloader for the C66x DSP User Guide in ‘‘Related Documentation from Texas

Instruments’’ on page 66 for detailed information on boot configuration

00 = PCIe in end point mode
01 = PCIe legacy end point (support for legacy INTx)
10 = PCIe in root complex mode
11 = Reserved

0 = PCIE subsystem is disabled
1 = PCIE subsystem is enabled

0 = SYSCLK is used as the input to Main PLL
1 = ALTCORECLK is used as the input to Main PLL

0 = SYSCLK / ALTCORECLK (controlled by CORECLKSEL pin) is used as the input to PA_SS PLL
1 = PASSCLK is used as the input to PASS PLL

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3.2 Peripheral Selection After Device Reset

Several of the peripherals on the TMS320C6670 are controlled by the Power Sleep Controller (PSC). By default, the
PCIe, SRIO, HyperLink, RAC, TAC, FFTC, AIF2, TCP3d, TCP3e, and VCP are held in reset and clock-gated. The
memories in these modules are also in a low-leakage sleep mode. Software is required to turn these memories on.
Then, the software enables the modules (turns on clocks and de-asserts reset) before these modules can be used.

If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically enable the
module.

All other modules come up enabled by default and there is no special software sequence to enable. For more detailed
information on the PSC usage, see the Power Sleep Controller (PSC) for KeyStone Devices User Guide in 2.9 ‘‘Related

Documentation from Texas Instruments’’ on page 66.

3.3 Device State Control Registers

The TMS320C6670 device has a set of registers that are used to control the status of its peripherals. These registers
are shown in Table 3-2.

Table 3-2 Device State Control Registers (Part 1 of 4)

Address Start Address End Size Acronym Description

0x02620000 0x02620007 8B Reserved

0x02620008 0x02620017 16B Reserved

0x02620018 0x0262001B 4B JTAGID See section 3.3.3

0x0262001C 0x0262001F 4B Reserved

0x02620020 0x02620023 4B DEVSTAT See section 3.3.1

0x02620024 0x02620037 20B Reserved

0x02620038 0x0262003B 4B KICK0

0x0262003C 0x0262003F 4B KICK1

0x02620040 0x02620043 4B DSP_BOOT_ADDR0 The boot address for C66x DSP CorePac0

0x02620044 0x02620047 4B DSP_BOOT_ADDR1 The boot address for C66x DSP CorePac1

0x02620048 0x0262004B 4B DSP_BOOT_ADDR2 The boot address for C66x DSP CorePac2

0x0262004C 0x0262004F 4B DSP_BOOT_ADDR3 The boot address for C66x DSP CorePac3

0x02620050 0x02620053 4B Reserved

0x02620054 0x02620057 4B Reserved

0x02620058 0x0262005B 4B Reserved

0x0262005C 0x0262005F 4B Reserved

0x02620060 0x026200DF 128B Reserved

0x026200E0 0x0262010F 48B Reserved

0x02620110 0x02620117 8B MACID See section 7.19 ‘‘Gigabit Ethernet (GbE) Switch Subsystem’’ on

0x02620118 0x0262012F 24B Reserved

0x02620130 0x02620133 4B LRSTNMIPINSTAT_CLR See section 3.3.6

0x02620134 0x02620137 4B RESET_STAT_CLR See section 3.3.8

0x02620138 0x0262013B 4B Reserved

0x0262013C 0x0262013F 4B BOOTCOMPLETE See section 3.3.9

0x02620140 0x02620143 4B Reserved

0x02620144 0x02620147 4B RESET_STAT See section 3.3.7

0x02620148 0x0262014B 4B LRSTNMIPINSTAT See section 3.3.5

0x0262014C 0x0262014F 4B DEVCFG See section 3.3.2

See section 3.3.4

page 207

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Table 3-2 Device State Control Registers (Part 2 of 4)

Address Start Address End Size Acronym Description

0x02620150 0x02620153 4B PWRSTATECTL See section 3.3.10

0x02620154 0x02620157 4B SRIO_SERDES_STS See ‘‘Related Documentation from Texas Instruments’’ on page 66

0x02620158 0x0262015B 4B SGMII_SERDES_STS

0x0262015C 0x0262015F 4B PCIE_SERDES_STS

0x02620160 0x02620160 4B HYPERLINK_SERDES_STS

0x02620164 0x02620167 4B AIF2_A_SERDES_STS

0x02620168 0x0262016B 4B AIF2_B_SERDES_STS

0x0262016C 0x0262017F 20B Reserved

0x02620180 0x02620183 4B SmartReflex Class0

0x02620184 0x0262018F 12B Reserved

0x02620190 0x02620193 4B Reserved

0x02620194 0x02620197 4B Reserved

0x02620198 0x0262019B 4B Reserved

0x0262019C 0x0262019F 4B Reserved

0x026201A0 0x026201A3 4B Reserved

0x026201A4 0x026201A7 4B Reserved

0x026201A8 0x026201AB 4B Reserved

0x026201AC 0x026201AF 4B Reserved

0x026201B0 0x026201B3 4B Reserved

0x026201B4 0x026201B7 4B Reserved

0x026201B8 0x026201BB 4B Reserved

0x026201BC 0x026201BF 4B Reserved

0x026201C0 0x026201C3 4B Reserved

0x026201C4 0x026201C7 4B Reserved

0x026201C8 0x026201CB 4B Reserved

0x026201CC 0x026201CF 4B Reserved

0x026201D0 0x026201FF 48B Reserved

0x02620200 0x02620203 4B NMIGR0 See section 3.3.11

0x02620204 0x02620207 4B NMIGR1

0x02620208 0x0262020B 4B NMIGR2

0x0262020C 0x0262020F 4B NMIGR3

0x02620210 0x02620213 4B Reserved

0x02620214 0x02620217 4B Reserved

0x02620218 0x0262021B 4B Reserved

0x0262021C 0x0262021F 4B Reserved

0x02620220 0x0262023F 32B Reserved

0x02620240 0x02620243 4B IPCGR0 See section 3.3.12

0x02620244 0x02620247 4B IPCGR1

0x02620248 0x0262024B 4B IPCGR2

0x0262024C 0x0262024F 4B IPCGR3

0x02620250 0x02620253 4B Reserved

0x02620254 0x02620257 4B Reserved

0x02620258 0x0262025B 4B Reserved

SPRS689D—March 2012

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Table 3-2 Device State Control Registers (Part 3 of 4)

Address Start Address End Size Acronym Description

0x0262025C 0x0262025F 4B Reserved

0x02620260 0x0262027B 28B Reserved

0x0262027C 0x0262027F 4B IPCGRH See section 3.3.14

0x02620280 0x02620283 4B IPCAR0 See section 3.3.13

0x02620284 0x02620287 4B IPCAR1

0x02620288 0x0262028B 4B IPCAR2

0x0262028C 0x0262028F 4B IPCAR3

0x02620290 0x02620293 4B Reserved

0x02620294 0x02620297 4B Reserved

0x02620298 0x0262029B 4B Reserved

0x0262029C 0x0262029F 4B Reserved

0x026202A0 0x026202BB 28B Reserved

0x026202BC 0x026202BF 4B IPCARH See section 3.3.15

0x026202C0 0x026202FF 64B Reserved

0x02620300 0x02620303 4B TINPSEL See section 3.3.16

0x02620304 0x02620307 4B TOUTPSEL

0x02620308 0x0262030B 4B RSTMUX0 See section 3.3.18

0x0262030C 0x0262030F 4B RSTMUX1

0x02620310 0x02620313 4B RSTMUX2

0x02620314 0x02620317 4B RSTMUX3

0x02620318 0x0262031B 4B Reserved

0x0262031C 0x0262031F 4B Reserved

0x02620320 0x02620323 4B Reserved

0x02620324 0x02620327 4B Reserved

0x02620328 0x0262032B 4B MAINPLLCTL0 See section 7.5 ‘‘Main PLL and the PLL Controller’’ on page 128

0x0262032C 0x0262032F 4B MAINPLLCTL1

0x02620330 0x02620333 4B DDR3PLLCTL0 See section 7.6 ‘‘DDR3 PLL’’ on page 142

0x02620334 0x02620337 4B DDR3PLLCTL1

0x02620338 0x0262033B 4B PASSPLLCTL0 See section 7.7 ‘‘PASS PLL’’ on page 144

0x0262033C 0x0262033F 4B PASSPLLCTL1

0x02620340 0x02620343 4B SGMII_SERDES_CFGPLL See ‘‘Related Documentation from Texas Instruments’’ on page 66

0x02620344 0x02620347 4B SGMII_SERDES_CFGRX0

0x02620348 0x0262034B 4B SGMII_SERDES_CFGTX0

0x0262034C 0x0262034F 4B SGMII_SERDES_CFGRX1

0x02620350 0x02620353 4B SGMII_SERDES_CFGTX1

0x02620354 0x02620357 4B Reserved

0x02620358 0x0262035B 4B PCIE_SERDES_CFGPLL

0x0262035C 0x0262035F 4B Reserved

0x02620360 0x02620363 4B SRIO_SERDES_CFGPLL

0x02620364 0x02620367 4B SRIO_SERDES_CFGRX0

0x02620368 0x0262036B 4B SRIO_SERDES_CFGTX0

0x0262036C 0x0262036F 4B SRIO_SERDES_CFGRX1

0x02620370 0x02620373 4B SRIO_SERDES_CFGTX1

See section 3.3.17

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Table 3-2 Device State Control Registers (Part 4 of 4)

Address Start Address End Size Acronym Description

0x02620374 0x02620377 4B SRIO_SERDES_CFGRX2 See ‘‘Related Documentation from Texas Instruments’’ on page 66

0x02620378 0x0262037B 4B SRIO_SERDES_CFGTX2

0x0262037C 0x0262037F 4B SRIO_SERDES_CFGRX3

0x02620380 0x02620383 4B SRIO_SERDES_CFGTX3

0x02620384 0x02620387 4B Reserved

0x02620388 0x026203AF 28B Reserved

0x026203B0 0x026203B3 4B Reserved

0x026203B4 0x026203B7 4B HYPERLINK_SERDES_CFGPLL See ‘‘Related Documentation from Texas Instruments’’ on page 66

0x026203B8 0x026203BB 4B HYPERLINK_SERDES_CFGRX0

0x026203BC 0x026203BF 4B HYPERLINK_SERDES_CFGTX0

0x026203C0 0x026203C3 4B HYPERLINK_SERDES_CFGRX1

0x026203C4 0x026203C7 4B HYPERLINK_SERDES_CFGTX1

0x026203C8 0x026203CB 4B HYPERLINK_SERDES_CFGRX2

0x026203CC 0x026203CF 4B HYPERLINK_SERDES_CFGTX2

0x026203D0 0x026203D3 4B HYPERLINK_SERDES_CFGRX3

0x026203D4 0x026203D7 4B HYPERLINK_SERDES_CFGTX3

0x026203D8 0x026203DB 4B Reserved

0x026203DC 0x026203F7 28B Reserved

0x026203F8 0x026203FB 4B DEVSPEED See section 3.3.19

0x026203FC 0x026203FF 4B Reserved

0x02620400 0x02620403 4B PKTDMA_PRI_ALLOC See section 4.4 ‘‘Bus Priorities’’ on page 97

0x02620404 0x02620467 100B Reserved

End of Table 3-2

SPRS689D—March 2012

3.3.1 Device Status (DEVSTAT) Register

The Device Status Register depicts the device configuration selected upon a power-on reset by either the POR
RESETFULL

pin. Once set, these bits will remain set until a power-on reset. The Device Status Register is shown in

or

Figure 3-1 and described in Table 3-3.

Figure 3-1 Device Status Register

31 18 17 16 15 14 13 1 0

Reserved PACLKSEL PCIESSEN PCIESSMODE[1:0 BOOTMODE[12:0] LENDIAN

R-0 R-x R/W-xx R/W-xxxxxxxxxxxx R-x

Legend: R = Read only; RW = Read/Write; -n = value after reset

1 x indicates the bootstrap value latched via the external pin

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Table 3-3 Device Status Register Field Descriptions

Bit Field Description

31-18 Reserved Reserved. Read only, writes have no effect.

17 PACLKSEL PA Clock select to select the reference clock for PA subsystem PLL

0 = Selects output of Main PLL MUX (SYSCLK vs. ALTCORECLK - depending on CORECLKSEL pin)
1 = Selects PASSCLKP/N

16 PCIESSEN PCIe module enable

0 = PCIe module disabled
1 = PCIe module enabled

15-14 PCIESSMODE[1:0] PCIe mode selection pins

00b = PCIe in end-point mode
01b = PCIe in legacy end-point mode (support for legacy INTx)
10b = PCIe in root complex mode
11b = Reserved

13-1 BOOTMODE[12:0] Determines the bootmode configured for the device. For more information on bootmode, see Section 2.4 ‘‘Boot Modes

Supported and PLL Settings’’ on page 30 and see the Bootloader for the C66x DSP User Guide in2.9 ‘‘Related
Documentation from Texas Instruments’’ on page 66.

0 LENDIAN Device endian mode (LENDIAN) — shows the status of whether the system is operating in big endian mode or little

endian mode (default).

0 = System is operating in big endian mode
1 = System is operating in little endian mode (default)

End of Table 3-3

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3.3.2 Device Configuration Register

The Device Configuration Register is one-time writeable through software. The register is reset on all hard resets
and is locked after the first write. The Device Configuration Register is shown in Figure 3-2 and described in

Table 3-4.

Figure 3-2 Device Configuration Register (DEVCFG)

31 10

Reserved SYSCLKOUTEN

R-0 R/W-1

Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 3-4 Device Configuration Register Field Descriptions

Bit Field Description

31-1 Reserved Reserved. Read only, writes have no effect.

0 SYSCLKOUTEN SYSCLKOUT enable

End of Table 3-4

0 = No clock output
1 = Clock output enabled (default)

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3.3.3 JTAG ID (JTAGID) Register Description

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the
JTAG ID register resides at address location 0x02620018. The JTAG ID Register is shown in the tables below.

Figure 3-3 JTAG ID (JTAGID) Register

31 28 27 12 11 1 0

VARIANT PART NUMBER MANUFACTURER LSB

R-xxxx R-1011 1001 0100 0001 0000 0010 111b R-1

Legend: RW = Read/Write; R = Read only; -n = value after reset

Table 3-5 JTAG ID Register Field Descriptions

Bit Field Value Description

31-28 VARIANT xxxxb Variant value

27-12 PART NUMBER 1011 1001 0100 0001b Part Number for boundary scan

11-1 MANUFACTURER 0000 0010 111b Manufacturer

0 LSB 1b This bit is read as a 1 for TMS320C6670

End of Table 3-5

SPRS689D—March 2012

Note—The value of the VARIANT and PART NUMBER fields depend on the silicon revision being used.

See the Silicon Errata for details.

3.3.4 Kicker Mechanism (KICK0 and KICK1) Register

The Bootcfg module contains a kicker mechanism to prevent any spurious writes from changing any of the Bootcfg
MMR values. When the kicker is locked (which it is initially after power on reset) none of the Bootcfg MMRs are
writable (they are only readable). This mechanism requires two MMR writes to the KICK0 and KICK1 registers with
exact data values before the kicker lock mechanism is un-locked. See Table 3-2 ‘‘Device State Control Registers’’ on
page 68 for the address location. Once released then all the Bootcfg MMRs having write permissions are writable
(the read only MMRs are still read only). The first KICK0 data is 0x83e70b13. The second KICK1 data is 0x95a4f1e0.
Writing any other data value to either of these kick MMRs will lock the kicker mechanism and block any writes to
Bootcfg MMRs. In order to ensure protection to all Bootcfg MMRs, software must always re-lock the kicker
mechanism after completing the MMR writes.

3.3.5 LRESETNMI PIN Status (LRSTNMIPINSTAT) Register

The LRSTNMIPINSTAT Register is used to latch the status of LRESET

and NMI based on the setting of

CORESEL[2:0]. The LRESETNMI PIN Status Register is shown in Figure 3-4 and described in Table 3-6.

Figure 3-4 LRESETNMI PIN Status Register (LRSTNMIPINSTAT)

31 201918171615 43210

Reserved NMI3 NMI2 NMI1 NMI0 Reserved LR3 LR2 LR1 LR0

R, +000000000000 R-0 R-0 R-0 R-0 R, +000000000000 R-0 R-0 R-0 R-0

Legend: R = Read only; -n = value after reset

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Table 3-6 LRESETNMI PIN Status Register Field Descriptions

Bit Field Description

31-20 Reserved Reserved

19 NMI3 CorePac3 in NMI

18 NMI2 CorePac2 in NMI

17 NMI1 CorePac1 in NMI

16 NMI0 CorePac0 in NMI

15-4 Reserved Reserved

3 LR4 CorePac3 in Local Reset

2 LR3 CorePac2 in Local Reset

1LR31 CorePac1 in Local Reset

0 LR0 CorePac0 in Local Reset

End of Table 3-6

3.3.6 LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register

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The LRSTNMIPINSTAT_CLR Register is used to clear the status of LRESET

and NMI based on CORESEL[2:0]. The

LRESETNMI PIN Status Clear Register is shown in Figure 3-5 and described in Table 3-7.

Figure 3-5 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)

31 201918171615 43210

Reserved NMI3 NMI2 NMI1 NMI0 Reserved LR3 LR2 LR1 LR0

R,+000000000000 WC,+0 WC,+0 WC,+0 WC,+0 R,+000000000000 WC,+0 WC,+0 WC,+0 WC,+0

Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear

Table 3-7 LRESETNMI PIN Status Clear Register Field Descriptions

Bit Field Description

31-20 Reserved Reserved

19 NMI3 CorePac3 in NMI Clear

18 NMI2 CorePac2 in NMI Clear

17 NMI1 CorePac1 in NMI Clear

16 NMI0 CorePac0 in NMI Clear

15-4 Reserved Reserved

3 LR3 CorePac3 in Local Reset Clear

2 LR2 CorePac2 in Local Reset Clear

1 LR1 CorePac1 in Local Reset Clear

0 LR0 CorePac0 in Local Reset Clear

End of Table 3-7

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3.3.7 Reset Status (RESET_STAT) Register

The reset status register (RESET_STAT) captures the status of Local reset (LRx) for each of the cores and also the
global device reset (GR). Software can use this information to take different device initialization steps, if desired.

• In case of local reset: The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives
an local reset without receiving a global reset.

• In case of global reset: The LRx bits are written as 0 and GR bit is written as 1 only when a global reset is
asserted.

The Reset Status Register is shown in Figure 3-6 and described in Table 3-8.

Figure 3-6 Reset Status Register (RESET_STAT)

31 30 43210

GR Reserved LR3 LR2 LR1 LR0

R, +1 R, + 000 0000 0000 0000 0000 0000 0000 R,+0 R,+0 R,+0 R,+0

Legend: R = Read only; -n = value after reset

Table 3-8 Reset Status Register Field Descriptions

Bit Field Description

31 GR Global reset status

0 = Device has not received a global reset.
1 = Device received a global reset.

30-4 Reserved Reserved.

3 LR3 CorePac3 reset status

0 = CorePac3 has not received a local reset.
1 = CorePac3 received a local reset.

2 LR2 CorePac2 reset status

0 = CorePac2 has not received a local reset.
1 = CorePac2 received a local reset.

1 LR1 CorePac1 reset status

0 = CorePac1 has not received a local reset.
1 = CorePac1 received a local reset.

0 LR0 CorePac0 reset status

0 = CorePac0 has not received a local reset.
1 = CorePac0 received a local reset.

End of Table 3-8

SPRS689D—March 2012

3.3.8 Reset Status Clear (RESET_STAT_CLR) Register

The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The
Reset Status Clear Register is shown in Figure 3-7 and described in Table 3-9.

Figure 3-7 Reset Status Clear Register (RESET_STAT_CLR)

31 30 43210

GR Reserved LR3 LR2 LR1 LR0

RW, +0 R, + 000 0000 0000 0000 0000 0000 0000 RW,+0 RW,+0 RW,+0 RW,+0

Legend: R = Read only; RW = Read/Write; -n = value after reset

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Table 3-9 Reset Status Clear Register Field Descriptions

Bit Field Description

31 GR Global reset clear bit

0 = Writing a 0 has no effect.
1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.

30-4 Reserved Reserved.

3 LR3 CorePac3 reset clear bit

0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR3 bit clears the corresponding bit in the RESET_STAT register.

2 LR2 CorePac2 reset clear bit

0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR2 bit clears the corresponding bit in the RESET_STAT register.

1 LR1 CorePac1 reset clear bit

0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR1 bit clears the corresponding bit in the RESET_STAT register.

0 LR0 CorePac0 reset clear bit

0 = Writing a 0 has no effect.
1 = Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.

End of Table 3-9

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3.3.9 Boot Complete (BOOTCOMPLETE) Register

The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status. The purpose is to indicate the
completion of the ROM booting process. The Boot Complete Register is shown in Figure 3-8 and described in

Table 3-10.

Figure 3-8 Boot Complete Register (BOOTCOMPLETE)

31 43210

Reserved BC3 BC BC1 BC0

R, + 0000 0000 0000 0000 0000 0000 0000 RW,+0 RW,+0 RW,+0 RW,+0

Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 3-10 Boot Complete Register Field Descriptions

Bit Field Description

31-4 Reserved Reserved.

3 BC3 CorePac 4 boot status

0 = CorePac 4 boot NOT complete
1 = CorePac 4 boot complete

2 BC2 CorePac3 boot status

1 BC1 CorePac2 boot status

0 BC0 CorePac1 boot status

End of Table 3-10

0 = CorePac3 boot NOT complete
1 = CorePac3 boot complete

0 = CorePac2 boot NOT complete
1 = CorePac2 boot complete

0 = CorePac1 boot NOT complete
1 = CorePac1 boot complete

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The BCx bit indicates the boot complete status of the corresponding CorePac. All BCx bits are sticky bits — that is
they can be set only once by the software after device reset and they will be cleared to 0 on all device resets.

Boot ROM code will be implemented such that each CorePac will set its corresponding BCx bit immediately before
branching to the predefined location in memory.

3.3.10 Power State Control (PWRSTATECTL) Register

The PWRSTATECTL register is controlled by the software to indicate the power-saving mode. ROM code reads this
register to differentiate between the various power saving modes. This register is cleared only by POR and will
survive all other device resets. See the Hardware Design Guide for KeyStone Devices in‘‘Related Documentation from

Texas Instruments’’ on page 66 for more information. The Power State Control Register is shown in Figure 3-9 and

described in Table 3-11.

Figure 3-9 Power State Control Register (PWRSTATECTL)

31 3 2 1 0

GENERAL_PURPOSE HIBERNATION_MODE HIBERNATION STANDBY

RW, +0000 0000 0000 0000 0000 0000 0000 0 RW,+0 RW,+0 RW,+0

Legend: RW = Read/Write; -n = value after reset

SPRS689D—March 2012

Table 3-11 Power State Control Register Field Descriptions

Bit Field Description

31-3 GENERAL_PURPOSE Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the C66x DSP User

2 HIBERNATION_MODE Indicates whether the device is in hibernation mode 1 or mode 2.

1 HIBERNATION Indicates whether the device is in hibernation mode or not.

0 STANDBY Indicates whether the device is in standby mode or not.

End of Table 3-11

Guide in2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66.

0 = Hibernation mode 1
1 = Hibernation mode 2

0 = Not in hibernation mode
1 = Hibernation mode

0 = Not in standby mode
1 = Standby mode

3.3.11 NMI Event Generation to CorePac (NMIGRx) Register

NMIGRx registers are used for generating NMI events to the corresponding CorePac. The C6670 has
four NMIGRx registers (NMIGR0 through NMIGR3). The NMIGR0 register generates an NMI event to CorePac0,
the NMIGR1 register generates an NMI event to CorePac1, and so on. Writing a 1 to the NMIG field generates a
NMI pulse. Writing a 0 has no effect and Reads return 0 and have no other effect. The NMI Event Generation to
CorePac Register is shown in Figure 3-10 and described in Table 3-12.

Figure 3-10 NMI Generation Register (NMIGRx)

31 10

Reserved NMIG

R, +0000 0000 0000 0000 0000 0000 0000 000 RW,+0

Legend: RW = Read/Write; -n = value after reset

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Table 3-12 NMI Generation Register Field Descriptions

Bit Field Description

31-1 Reserved Reserved

0NMIG Reads return 0

Writes:

0 = No effect
1 = Creates NMI pulse to the corresponding CorePac — CorePac0 for NMIGR0, etc.

End of Table 3-12

3.3.12 IPC Generation (IPCGRx) Registers

IPCGRx are the IPC interrupt generation registers to facilitate inter CorePac interrupts.

The C6670 has four IPCGRx registers (IPCGR0 through IPCGR3) registers. This can be used by external hosts or
CorePacs to generate interrupts to other CorePacs. A write of 1 to IPCG field of IPCGRx register will generate an
interrupt pulse to CorePacx (0 <= x <= 3).

These registers also provide a Source ID facility by which up to 28 different sources of interrupts can be identified.
Al location of source bits to source processor and meaning is entirely based on software convention. The register field
descriptions are given in the following tables. Virtually anything can be a source for these registers as this is
completely controlled by software. Any master that has access to BOOTCFG module space can write to these
registers. The IPC Generation Register is shown in Figure 3-11 and described in Table 3-13.

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Figure 3-11 IPC Generation Registers (IPCGRx)

31 30 29 28 27 8 7 6 5 4 3 1 0

SRCS27 SRCS26 SRCS25 SRCS24 SRCS23 – SRCS4 SRCS3 SRCS2 SRCS1 SRCS0 Reserved IPCG

RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field) RW +0 RW +0 RW +0 RW +0 R, +000 RW +0

Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 3-13 IPC Generation Registers Field Descriptions

Bit Field Description

31-4 SRCSx Reads return current value of internal register bit.

Writes:

0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.

3-1 Reserved Reserved

0IPCG Reads return 0.

Writes:

0 = No effect
1 = Creates an inter-DSP interrupt.

End of Table 3-13

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3.3.13 IPC Acknowledgement (IPCARx) Registers

IPCARx are the IPC interrupt-acknowledgement registers to facilitate inter-CorePac core interrupts.

The C6670 has four IPCARx (IPCAR0 through IPCAR3) registers. These registers also provide a Source ID facility
by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and
meaning is entirely based on software convention. The register field descriptions are given in the following tables.
Virtually anything can be a source for these registers as this is completely controlled by software. Any master that
has access to BOOTCFG module space can write to these registers. The IPC Acknowledgement Register is shown in

Figure 3-12 and described in Table 3-14.

Figure 3-12 IPC Acknowledgement Registers (IPCARx)

31 30 29 28 27 8 7 6 5 4 3 0

SRCC27 SRCC26 SRCC25 SRCC24 SRCC23 – SRCC4 SRCC3 SRCC2 SRCC1 SRCC0 Reserved

RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field) RW +0 RW +0 RW +0 RW +0 R, +0000

Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 3-14 IPC Acknowledgement Registers Field Descriptions

Bit Field Description

31-4 SRCCx Reads return current value of internal register bit.

Writes:

0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx

3-0 Reserved Reserved

End of Table 3-14

SPRS689D—March 2012

3.3.14 IPC Generation Host (IPCGRH) Register

IPCGRH register is provided to facilitate host CPU interrupt. Operation and use of IPCGRH is the same as other
IPCGR registers. Interrupt output pulse created by IPCGRH is driven on a device pin, host interrupt/event output
(HOUT).

The host interrupt output pulse should be stretched. It should be asserted for 4 bootcfg clock cycles (CPU/6)
followed by a deassertion of 4 bootcfg clock cycles. Generating the pulse will result in 8 CPU/6 cycle pulse blocking
window. Write to IPCGRH with IPCG bit (bit 0) set will only generate a pulse if they are beyond 8 CPU/6 cycle
period. The IPC Generation Host Register is shown in Figure 3-13 and described in Table 3-15.

Figure 3-13 IPC Generation Registers (IPCGRH)

31 30 29 28 27 8 7 6 5 4 3 1 0

SRCS27 SRCS26 SRCS25 SRCS24 SRCS23 – SRCS4 SRCS3 SRCS2 SRCS1 SRCS0 Reserved IPCG

RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field) RW +0 RW +0 RW +0 RW +0 R, +000 RW +0

Legend: R = Read only; RW = Read/Write; -n = value after reset

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Table 3-15 IPC Generation Registers Field Descriptions

Bit Field Description

31-4 SRCSx Reads return current value of internal register bit.

Writes:

0 = No effect
1 = Sets both SRCSx and the corresponding SRCCx.

3-1 Reserved Reserved

0IPCG Reads return 0.

Writes:

0 = No effect
1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)

End of Table 3-15

3.3.15 IPC Acknowledgement Host (IPCARH) Register

IPCARH registers are provided to facilitate host CPU interrupt. Operation and use of IPCARH is the same as
other IPCAR registers. The IPC Acknowledgement Host Register is shown in Figure 3-14 and described in

Table 3-16.

Figure 3-14 IPC Acknowledgement Register (IPCARH)

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31 30 29 28 27 8 7 6 5 4 3 0

SRCC27 SRCC26 SRCC25 SRCC24 SRCC23 – SRCC4 SRCC3 SRCC2 SRCC1 SRCC0 Reserved

RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field) RW +0 RW +0 RW +0 RW +0 R, +0000

Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 3-16 IPC Acknowledgement Register Field Descriptions

Bit Field Description

31-4 SRCCx Reads return current value of internal register bit.

Writes:

0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx

3-0 Reserved Reserved

End of Table 3-16

3.3.16 Timer Input Selection Register (TINPSEL)

Timer input selection is handled within the control register TINPSEL. The Timer Input Selection Register is shown
in Figure 3-15 and described in Table 3-17.

Figure 3-15 Timer Input Selection Register (TINPSEL)

31 16 15 14 13 12 11 10 9

Reserved TINPHSEL7 TINPLSEL7 TINPHSEL6 TINPLSEL6 TINPHSEL5 TINPLSEL5 TINPHSEL4

0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1

spacer

876543210

TINPLSEL4 TINPHSEL3 TINPLSEL3 TINPHSEL2 TINPLSEL2 TINPHSEL1 TINPLSEL1 TINPHSEL0 TINPLSEL0

RW, +0 RW, +1 RW, +0 RW, +1 RW, +0 RW, +1 RW, +1 RW, +1 RW, +0

Legend: R = Read only; RW = Read/Write; -n = value after reset

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Table 3-17 Timer Input Selection Field Description

Bit Field Description

31-16 Reserved Reserved

15 TINPHSEL7 Input select for TIMER7 high.

0 = TIMI0
1 = TIMI1

14 TINPLSEL7 Input select for TIMER7 low.

0 = TIMI0
1 = TIMI1

13 TINPHSEL6 Input select for TIMER6 high.

0 = TIMI0
1 = TIMI1

12 TINPLSEL6 Input select for TIMER6 low.

0 = TIMI0
1 = TIMI1

11 TINPHSEL5 Input select for TIMER5 high.

0 = TIMI0
1 = TIMI1

10 TINPLSEL5 Input select for TIMER5 low.

0 = TIMI0
1 = TIMI1

9 TINPHSEL4 Input select for TIMER4 high.

0 = TIMI0
1 = TIMI1

8 TINPLSEL4 Input select for TIMER4 low.

0 = TIMI0
1 = TIMI1

7 TINPHSEL3 Input select for TIMER3 high.

0 = TIMI0
1 = TIMI1

6 TINPLSEL3 Input select for TIMER3 low.

0 = TIMI0
1 = TIMI1

5 TINPHSEL2 Input select for TIMER2 high.

0 = TIMI0
1 = TIMI1

4 TINPLSEL2 Input select for TIMER2 low.

0 = TIMI0
1 = TIMI1

3 TINPHSEL1 Input select for TIMER1 high.

0 = TIMI0
1 = TIMI1

2 TINPLSEL1 Input select for TIMER1 low.

0 = TIMI0
1 = TIMI1

1 TINPHSEL0 Input select for TIMER0 high.

0 = TIMI0
1 = TIMI1

0 TINPLSEL0 Input select for TIMER0 low.

0 = TIMI0
1 = TIMI1

End of Table 3-17

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

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3.3.17 Timer Output Selection Register (TOUTPSEL)

The timer output selection is handled within the control register TOUTSEL. The Timer Output Selection Register
is shown in Figure 3-16 and described in Table 3-18.

Figure 3-16 Timer Output Selection Register (TOUTPSEL)

31 98 543 0

Reserved TOUTPSEL1 Reserved TOUTPSEL0

R,+0000000000000000000000000 RW,+0001 0 RW,+0000

Legend: R = Read only; RW = Read/Write; -n = value after reset

Table 3-18 Timer Output Selection Field Description

Bit Field Description

31-9 Reserved Reserved

8-5 TOUTPSEL1 Output select for TIMO1

0000: TOUTL0
0001: TOUTH0
0010: TOUTL1
0011: TOUTH1
0100: TOUTL2
0101: TOUTH2
0110: TOUTL3
0111: TOUTH3

1000: TOUTL4
1001: TOUTH4
1010: TOUTL5
1011: TOUTH5
1100: TOUTL6
1101: TOUTH6
1110: TOUTL7
1111: TOUTH7

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4 Reserved Reserved

3-0 TOUTPSEL0 Output select for TIMO0

0000: TOUTL0
0001: TOUTH0
0010: TOUTL1
0011: TOUTH1
0100: TOUTL2
0101: TOUTH2
0110: TOUTL3
0111: TOUTH3

End of Table 3-18

1000: TOUTL4
1001: TOUTH4
1010: TOUTL5
1011: TOUTH5
1100: TOUTL6
1101: TOUTH6
1110: TOUTL7
1111: TOUTH7

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3.3.18 Reset Mux (RSTMUXx) Register

The software controls the Reset Mux block through the reset multiplex registers using RSTMUX0 through
RSTMUX3 for each of the four CorePacs on the C6670. These registers are located in Bootcfg memory space. The
Timer Output Selection Register is shown in Figure 3-17 and described in Table 3-19.

Figure 3-17 Reset Mux Register (RSTMUX0 through RSTMUX3)

31 109 8754310

Reserved EVTSTATCLR Reserved DELAY EVTSTAT OMODE LOCK

R, +0000 0000 0000 0000 0000 00 RC, +0 R, +0 RW, +100 R, +0 RW, +000 RW, +0

Legend: R = Read only; RW = Read/Write; -n = value after reset; RC

Table 3-19 Reset Mux Register Field Descriptions

Bit Field Description

31-10 Reserved Reserved

9EVTSTATCLRClear event status

0 = Writing 0 has no effect
1 = Writing 1 to this bit clears the EVTSTAT bit

8 Reserved Reserved

7-5 DELAY Delay cycles between NMI & local reset

000b = 256 CPU/6 cycles delay between NMI & local reset, when OMODE = 100b
001b = 512 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
010b = 1024 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
011b = 2048 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
100b = 4096 CPU/6 cycles delay between NMI & local reset, when OMODE=100b (default)
101b = 8192 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
110b = 16384 CPU/6 cycles delay between NMI & local reset, when OMODE=100b
111b = 32768 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

4EVTSTAT Event status

0 = No event received (Default)
1 = WD timer event received by Reset Mux block

3-1 OMODE Timer event operation mode

000b = WD timer event input to the Reset Mux block does not cause any output event (default)
001b = Reserved
010b = WD Timer Event input to the Reset Mux block causes local reset input to CorePac
011b = WD Timer Event input to the Reset Mux block causes NMI input to CorePac
100b = WD Timer Event input to the Reset Mux block causes NMI input followed by local reset input to CorePac. Delay

between NMI and local reset is set in DELAY bit field.
101b = WD timer event input to the Reset Mux block causes device reset to C6670
110b = Reserved
111b = Reserved

0 LOCK Lock register fields

0 = Register fields are not locked (default)
1 = Register fields are locked until the next timer reset

End of Table 3-19

= Read only and write 1 to clear

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3.3.19 Device Speed (DEVSPEED) Register

The Device Speed Register shows the device speed grade. The Device Speed Register is shown below.

Figure 3-18 Device Speed Register (DEVSPEED)

31 23 22 0

DEVSPEED Reserved

R-n R-n

Legend: R = Read only; -n = value after reset

Table 3-20 Device Speed Register Field Descriptions

Bit Field Description

31-23 DEVSPEED Indicates the speed of the device (read only)

0b0000 0000 0 = 800 MHz
0b0000 0000 1 = 1000 MHz
0b0000 0001 x = 1200 MHz
0b001x xxxx x = 1200 MHz
0b01xx xxxx x = 1000 MHz
0b1xxx xxxx x = 800 MHz

22-0 Reserved Reserved. Read only

End of Table 3-20

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3.4 Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This
may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown
(IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.

An external pullup/pulldown resistor needs to be used in the following situations:

• Device Configuration Pins: If the pin is both routed out and are not driven (in Hi-Z state), an external
pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.

• Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown
resistor to pull the signal to the opposite rail.

For the device configuration pins (listed in Table 3-1), if they are both routed out and are not driven (in Hi-Z state),
it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal
pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing
external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In
addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user
in debugging and flexibility in switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to
include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown
resistors.

• Decide a target value for the net. For a pulldown resistor, this should be below the lowest V
connected to the net. For a pullup resistor, this should be above the highest V
A reasonable choice would be to target the V
by definition, have margin to the V

and VIH levels.

IL

or VOH levels for the logic family of the limiting device; which,

OL

level of all inputs on the net.

IH

• Select a pullup/pulldown resistor with the largest possible value that can still ensure that the net will reach the
target pulled value when maximum current from all devices on the net is flowing through the resistor. The
current to be considered includes leakage current plus, any other internal and external pullup/pulldown
resistors on the net.

• For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value of the
external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to
the opposite logic level (including margin).

• Remember to include tolerances when selecting the resistor value.

• For pullup resistors, also remember to include tolerances on the DVDD rail.

level of all inputs

IL

For most systems:

•A 1-kΩ resistor can be used to op pose t he I PU/I PD whi le meeting the above criteria. Users should confirm this
resistor value is correct for their specific application.

• A 20-kΩ resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the
above criteria. Users should confirm this resistor value is correct for their specific application.

For more detailed information on input current (I

), and the low-level/high-level input voltages (VIL and VIH) for

I

the TMS320C6670 device, see Section 6.3 ‘‘Electrical Characteristics’’ on page 107.

To determine which pins on the device include internal pullup/pulldown resistors, see Table 2-16 ‘‘Terminal

Functions — Power and Ground’’ on page 52.

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4 System Interconnect

On the TMS320C6670 device, the C66x CorePacs, the EDMA3 transfer controllers, and the system peripherals are
interconnected through the TeraNet, which is a non-blocking switch fabric enabling fast and contention-free
internal data movement. The TeraNet provides low-latency, concurrent data transfers between master peripherals
and slave peripherals. The TeraNet also allows for seamless arbitration between the system masters when accessing
system slaves.

4.1 Internal Buses and Switch Fabrics

Two types of buses exist in the device; data buses and configuration buses. Some peripherals have both a data bus
and a configuration bus interface, while others only have one type of interface. Furthermore, the bus interface width
and speed varies from peripheral to peripheral. Configuration buses are mainly used to access the register space of
a peripheral and the data buses are used mainly for data transfers.

The C66x CorePacs, the EDMA3 traffic controllers, and the various system peripherals can be classified into two
categories: masters and slaves. Masters are capable of initiating read and write transfers in the system and do not rely
on the EDMA3 for their data transfers. Slaves on the other hand rely on the masters to perform transfers to and from
them. Examples of masters include the EDMA3 traffic controllers, SRIO, and network coprocessor packet DMA.
Examples of slaves include the SPI, UART, and I

2

C.

The masters and slaves in the device are communicating through the TeraNet (switch fabric). The device contains
two switch fabrics. The data switch fabric (data TeraNet) and the configuration switch fabric (configuration
TeraNet). The data TeraNet, is a high-throughput interconnect mainly used to move data across the system. The
data TeraNet connects masters to slaves via data buses. The configuration TeraNet, is mainly used to access
peripheral registers. The configuration TeraNet connects masters to slaves via configuration buses. Note that the
data TeraNet also connects to the configuration TeraNet. For more details see 4.2 ‘‘Switch Fabric Connections

Matrix’’ on page 87.

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4.2 Switch Fabric Connections Matrix

The tables below list the master and slave end point connections.

Intersecting cells may contain one of the following:

• Y — There is a connection between this master and that slave.

• - — There is NO connection between this master and that slave.

• n — A numeric value indicates that the path between this master and that slave goes through bridge n.

Table 4-1 Switch Fabric Connection Matrix Section 1 (Part 1 of 2)

Slave

CorePac0_SDMA

CorePac1_SDMA

CorePac2_SDMA

CorePac3_SDMA

Boot_ROM

SPI

PCIe_Slave

QM_Slave

HyperLink_Slave

MSMC_SES

MSMC_SMS

STM

TETB_System

TETB0

TETB1

TETB2

TETB3

VCP2(0-4)

TCP3d

TCP_3e_w

TCP3e_r

TAC_BE

Masters

HyperLink_Master 11111111 - YY- - - - - -YYYY- - -

BCP_FFTCC_TCP3dC
Master

EDMA3CC0_TC0_RD 22222222YYY- Y- - - - ------Y

EDMA3CC0_TC0_WR 2222-222YYY------------Y

EDMA3CC0_TC1_RD 3333333- YYY-Y- - - - ------Y

EDMA3CC0_TC1_WR 3333-33-YYY------------Y

EDMA3CC1_TC0_RD YYYYYYY-555-Y---------Y-

EDMA3CC1_TC0_WR YYYY-YY-555Y----------Y-

EDMA3CC1_TC1_RD YYYYYYYY666--YY-------Y-

EDMA3CC1_TC1_WR YYYY-YYY666-----------Y-

EDMA3CC1_TC2_RD YYYYYYY-777----YY----Y--

EDMA3CC1_TC2_WR YYYY-YY-777----------Y--

EDMA3CC1_TC3_RD YYYYYYY-888-Y--------Y--

EDMA3CC1_TC3_WR YYYY-YY-888Y---------Y--

EDMA3CC2_TC0_RD YYYYYYY - 999 - Y - - - - YYYY - - Y

EDMA3CC2_TC0_WR YYYY- YY - 999Y - - - - - YYYY - - Y

EDMA3CC2_TC1_RD YYYYYYYY101010- - YY- -YYYY - - Y

EDMA3CC2_TC1_WR YYYY-YYY101010------YYYY--Y

EDMA3CC2_TC2_RD YYYYYYY - 555 - Y - - - - YY - - - - Y

EDMA3CC2_TC2_WR YYYY-YY-555Y-----YY----Y

EDMA3CC2_TC3_RD YYYYYYY - 666 - - - - YYY - YY - - Y

EDMA3CC2_TC3_WR YYYY-YY-666------Y-YY--Y

SRIO Packet DMA YYYY---Y-99-------------

SRIO_Master YYYY- Y - Y777YYYYYYYYYYYYY

PCIe_Master YYYY - Y - Y777YYYYYYYYYYYYY

Network Coprocessor
Packet DMA

MSMC_Data_Master 44444444Y- - Y - - - - -YYYYYYY

QM_SS_Master YYYY---Y888-------------

QM_SS_Second YYYY----888-------------

YYYY---Y-YY-------------

YYYY---Y-1010-------------

RAC_Slave

BCP_FFTCC_TCP3dC_S

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Table 4-1 Switch Fabric Connection Matrix Section 1 (Part 2 of 2)

Slave

CorePac0_SDMA

CorePac1_SDMA

CorePac2_SDMA

CorePac3_SDMA

Boot_ROM

SPI

PCIe_Slave

QM_Slave

HyperLink_Slave

MSMC_SES

MSMC_SMS

STM

TETB_System

TETB0

TETB1

TETB2

TETB3

VCP2(0-4)

TCP3d

Masters

DebugSS_Master YYYYYYYY101010YYYYYYYYYYYYY

FFTC YYYY---Y666-------------

RAC_BE0 YYYY----777-------------

RAC_BE1 YYYY----888-------------

AIF_Master YYYY---Y777----------YY-

TAC_FE YYYY----999-------------

CorePac0_CFG ------------YYYYY-------

CorePac1_CFG ------------YYYYY-------

CorePac2_CFG ------------YYYYY-------

CorePac3_CFG ------------YYYYY-------

Tracer_Master -----------Y------------

End of Table 4-1

TCP_3e_w

TCP3e_r

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TAC_BE

RAC_Slave

BCP_FFTCC_TCP3dC_S

Table 4-2 Switch Fabric Connection Matrix Section 2 (Part 1 of 2)

Slave

C

EDMA3CC0

EDMA3CC1

EDMA3CC2

EDMA3CC0_TC(0-1)

EDMA3CC1_TC(0-3)

EDMA3CC2_TC(0-3)

Semaphore

QM_SS_CFG

CP Tracer(0~15/16)

NETCP_CFG

SRIO_CFG

Masters

HyperLink_Master 1, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121, 121,

BCP_FFTCC_TCP3dC
Master

EDMA3CC0_TC0_RD 2, 122, 122, 122, 122, 122, 12-----------------

EDMA3CC0_TC0_WR 2, 122, 122, 122, 122, 122, 12-----------------

EDMA3CC0_TC1_RD 3, 123, 123, 123, 123, 123, 12-----------------

EDMA3CC0_TC1_WR 3, 123, 123, 123, 123, 123, 12-----------------

EDMA3CC1_TC0_RD 1212121212121212121212121212121212121212121212

EDMA3CC1_TC0_WR 1212121212121212121212121212121212121212121212

EDMA3CC1_TC1_RD 131313131313-----------------

EDMA3CC1_TC1_WR 131313131313-----------------

EDMA3CC1_TC2_RD 141414141414-----------------

EDMA3CC1_TC2_WR 141414141414-----------------

EDMA3CC1_TC3_RD 1212121212121212121212121212121212121212121212

YYYYYYYY - YYYYY - - - - - YYY -

Timer

GPIO

2

I

SEC_CTL

SEC_Key_MGR

Boot_CFG

GPSC

PLL_CTL

CP_CIC

MPU

Debug_SS_CFG

12

SR_MMR

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Table 4-2 Switch Fabric Connection Matrix Section 2 (Part 2 of 2)

Slave

C

EDMA3CC0

EDMA3CC1

EDMA3CC2

EDMA3CC0_TC(0-1)

EDMA3CC1_TC(0-3)

EDMA3CC2_TC(0-3)

Semaphore

QM_SS_CFG

CP Tracer(0~15/16)

NETCP_CFG

SRIO_CFG

Masters

EDMA3CC1_TC3_WR 1212121212121212121212121212121212121212121212

EDMA3CC2_TC0_RD 1212121212121212121212121212121212121212121212

EDMA3CC2_TC0_WR 1212121212121212121212121212121212121212121212

EDMA3CC2_TC1_RD 131313131313-----------------

EDMA3CC2_TC1_WR 131313131313-----------------

EDMA3CC2_TC2_RD 1212121212121212121212121212121212121212121212

EDMA3CC2_TC2_WR 1212121212121212121212121212121212121212121212

EDMA3CC2_TC3_RD 141414141414-----------------

EDMA3CC2_TC3_WR 141414141414-----------------

SRIO Packet DMA -----------------------

SRIO_M 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

PCIe_Master 1212121212121212121212121212121212121212121212

Network Coprocessor
Packet DMA

MSMC_Data_Master -----------------------

QM_SS Packet DMA -----------------------

QM_SS Second -----------------------

DebugSS_Master 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12

FFTC -----------------------

RAC_BE0 -----------------------

RAC_BE1 -----------------------

AIF_Master -----------------------

TAC_FE -----------------------

EDMA3CC0 ---Y-------------------

EDMA3CC1 ----Y------------------

EDMA3CC2 -----Y-----------------

CorePac0_CFG YYYYYYYYYYYYYYYYYYYYYYY

CorePac1_CFG YYYYYYYYYYYYYYYYYYYYYYY

CorePac2_CFG YYYYYYYYYYYYYYYYYYYYYYY

CorePac3_CFG YYYYYYYYYYYYYYYYYYYYYYY

End of Table 4-2

-----------------------

Timer

GPIO

2

I

SEC_CTL

SEC_Key_MGR

SPRS689D—March 2012

Boot_CFG

GPSC

PLL_CTL

CP_CIC

MPU

Debug_SS_CFG

SR_MMR

Table 4-3 Switch Fabric Connection Matrix Section 3 (Part 1 of 2)

Slave

Masters

HyperLink_Master 1, 12 Y 1, 12 1, 12 1, 12 1, 12 Y Y

BCP_FFTCC_TCP3dC
Master

EDMA3CC0_TC0_RD - - - - - - - -

RAC_CFG FFTC_CFG TAC_CFG TCP3e_CFG TCP3d_CFG VCP2_CFG AIF2_CFG UART_CFG

YYY Y Y Y Y Y

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Table 4-3 Switch Fabric Connection Matrix Section 3 (Part 2 of 2)

Slave

Masters

EDMA3CC0_TC0_WR - - - - - - - -

EDMA3CC0_TC1_RD - - - - - - - -

EDMA3CC0_TC1_WR - - - - - - - -

EDMA3CC1_TC0_RD 12 Y 12 12 12 12 Y Y

EDMA3CC1_TC0_WR 12 Y 12 12 12 12 Y Y

EDMA3CC1_TC1_RD - - - - - - - -

EDMA3CC1_TC1_WR - - - - - - - -

EDMA3CC1_TC2_RD - - - - - - - -

EDMA3CC1_TC2_WR - - - - - - - -

EDMA3CC1_TC3_RD 12 Y 12 12 12 12 Y Y

EDMA3CC1_TC3_WR 12 Y 12 12 12 12 Y Y

EDMA3CC2_TC0_RD 12 Y 12 12 12 12 Y Y

EDMA3CC2_TC0_WR 12 Y 12 12 12 12 Y Y

EDMA3CC2_TC1_RD - - - - - - - -

EDMA3CC2_TC1_WR - - - - - - - -

EDMA3CC2_TC2_RD 12 Y 12 12 12 12 Y Y

EDMA3CC2_TC2_WR 12 Y 12 12 12 12 Y Y

EDMA3CC2_TC3_RD - - - - - - - -

EDMA3CC2_TC3_WR - - - - - - - -

SRIO Packet DMA - - - - - - - -

SRIO_M 12 Y 12 12 12 12 Y Y

PCIe_Master 12 Y 12 12 12 12 Y Y

Network Coprocessor
Packet DMA

MSMC_Data_Master - - - - - - - -

QM_SS Packet DMA - - - - - - - -

QM_SS Second - - - - - - - -

DebugSS_Master 12 Y 12 12 12 12 Y Y

FFTC - - - - - - - -

RAC_BE0 - - - - - - - -

RAC_BE1 - - - - - - - -

AIF_Master ---- - ---

TAC_FE ---- - ---

EDMA3CC0 ---- - ---

EDMA3CC1 ---- - ---

EDMA3CC2 ---- - ---

CorePac0_CFG Y Y Y Y Y Y Y Y

CorePac1_CFG Y Y Y Y Y Y Y Y

CorePac2_CFG Y Y Y Y Y Y Y Y

CorePac3_CFG Y Y Y Y Y Y Y Y

End of Table 4-3

RAC_CFG FFTC_CFG TAC_CFG TCP3e_CFG TCP3d_CFG VCP2_CFG AIF2_CFG UART_CFG

---- - ---

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4.3 TeraNet Switch Fabric Connections

The figures below show the connections between masters and slaves through various sections of the TeraNet.

Figure 4-1 TeraNet 3A

CorePac_0

S

S

S

S

S

S

S

S

S

S

CorePac_1

CorePac_2

CorePac_3

TAC_BE

QM_SS

TCP3e_r

TCP3e_w

PCIe

VCP2

Bridge_1

Bridge_2

Bridge_3

Bridge_4

Packet DMA

From TeraNet_2_A

PCIe

SRIO_M

SRIO

M

M

M

Tracer_L2_0

Tracer_L2_1

Tracer_L2_2

Tracer_L2_3

Tracer_TAC

MPU_1

Tracer_QM_M

TNet_3_F

CPU/3

Packet DMA

Packet DMA

Packet DMA

RAC_A_BE1

RAC_A_BE0

RAC_B_BE1

RAC_B_BE0

EDMA

CC1

EDMA

CC2

NETCP

QM_SS

QM_SS

Second

Debug_SS

FFTC_B

FFTC_A

TAC_FE

AIF/DMA

TC_0

TC_1

TC_2

TC_3

TC_0

TC_1

TC_2

TC_3

M

M

M

M

M

M

M

M

M

M

M

M

M
M
M
M

M
M
M
M

TNet_3_H

CPU/3

TNet_3_D

CPU/3

Tracer
_RAC

TeraNet 3_A CPU/3

TNet_3_B

CPU/3

TNet_3_G

CPU/3

TNet_3_E

CPU/3

TNet_6P_A

CPU/3

To TeraNet_2_A

To TeraNet_3P_A

S

S

S

S

S

S

S

S

S

S

VCP2

VCP2

VCP2

SRIO

RAC_A_FE

RAC_B_FE

TCP3d_A

TCP3d_B

SPI

Boot_ROM

Bridge_5

Bridge_6

Bridge_7

Bridge_8

Bridge_9

Bridge_10

Bridge_12

Bridge_13

Bridge_14

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Figure 4-2 TeraNet 2A

XMC 4

´

www.ti.com

From TeraNet 2M

Bridge_5

Bridge_6

Bridge_7

Bridge_8

Bridge_9

Bridge_10

EDMA

CC0

From TeraNet_3_A

HyperLink

TC_0

TC_1

M

M

M
M

S

S

TeraNet 2_A CPU/2

SES

SMS

M S

MSMC

Tracer_MSMC0

Tracer_MSMC1

Tracer_MSMC2

Tracer_MSMC3

To TeraNet_3_A

M

Tracer_DDR

S

S

DDR3

HyperLink

To TeraNet 2A

Bridge_1

Bridge_2

Bridge_3

Bridge_4

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Figure 4-3 TeraNet 3P and 3M and 2M

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

FFTC_

Packet DMA

BCP_

Packet DMA

BCP_DIO0

BCP_DIO1

From TeraNet 2A

M

M

M

M

M

CPU/3

TeraNet 2M

CPU/3

TeraNet 3M

To Te r a Net 2A

S

TCP3d_DMA

S

MPU_CFG

S

TCP3D_CFG

S

MPU

S

S

FFTC_CFG

BCP_CFG

CPU/3

TeraNet 3P

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Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

Figure 4-4 TeraNet 3P_A

Bridge_12

Bridge_13

Bridge_14

From TeraNet_3_A

CorePac_0

CorePac_1

CorePac_2

CorePac_3

M

M

M

M

Tracer_QM_CFG

Tracer_SM

TNet_2P

CPU/2

TNet_3P_C

CPU/3

TNet_3P_D

CPU/3

MPU_2

MPU_3

www.ti.com

MPU *n

S

TC ( 2)×

S

S

S

S

S

S

S

S

TETB (Debug_SS)

TETB (core) ( 4)×

CC0

TC ( 4)×

CC1

TC ( 4)×

CC2

QM_SS

Semaphore

*

n indicates the number of MPUs present in the specific device.

MPU_4

Tracer_RAC_CFG

TeraNet 3P_A CPU/3

Tracer_CFG

RAC_A_CFG

TNet_3P_H

CPU/3

MPU_0 To TeraNet_3P_B

S

RAC_B_CFG

S

To TeraNet_3P_Tracer

94 System Interconnect Copyright 2012 Texas Instruments Incorporated

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Figure 4-5 TeraNet 3P_B

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

From TeraNet_3P_A

TeraNet 3P_B CPU/3

TNet_3P_E

CPU/3

TNet_3P_F

CPU/3

TNet_3P_G

CPU/3

To TeraNet_6P_B

S

S

S

S

S

S

S

S

S

S

S

S

S

S

Tracer

( 11 / 12)××

SRIO

NETCP

VCP2

VCP2

VCP2

VCP2

AIF2

TCP3d_A

TCP3d_B

TCP3e

TAC

FFTC_A

FFTC_B

Bridge_20

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Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

Figure 4-6 TeraNet 6P_B and 3P_Tracer

From TeraNet_3P_A

www.ti.com

Tracer_

MSMC_0

Tracer_

MSMC_1

Tracer_

MSMC_2

Tracer_

MSMC_3

Tracer_CFG

Tracer_DDR

Tracer_SM

Tracer_

QM_M

Tracer_

QM_P

Tracer_L2_

0to3

Tracer_RAC

Tracer_TAC

Tracer_

RAC_CFG

M

M

M

M

M

M

M

M

M

M

M

M

M

TeraNet 3P_Tracer CPU/3

S

S

Debug_SS

STM

Debug_SS

TETB

SmartReflex

Bridge_20

From TeraNet_3P_B

CPU/6

TeraNet 6P_B

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S

S

S

S

BOOTCFG

S

S

PLL_CTL

S

Debug_SS

S

CIC ( 3 / 4)××

S

Timer ( 8)×

S

GPIO

2

IC

UART

PSC

TMS320C6670

Multicore Fixed and Floating-Point System-on-Chip

www.ti.com

SPRS689D—March 2012

4.4 Bus Priorities

The priority level of all master peripheral traffic is defined at the TeraNet boundary. User programmable priority
registers will be present to allow software configuration of the data traffic through the TeraNet. Note that a lower
number means higher priority - PRI = 000b = urgent, PRI = 111b = low.

All other masters provide their priority directly and do not need a default priority setting. Examples include the
CorePacs, whose priorities are set through software in the UMC control registers. All the Packet DMA based
peripherals also have internal registers to define the priority level of their initiated transactions.

The Packet DMA secondary port is one master port that does not have priority allocation register inside the IP. The
priority level for transaction from this master port is described by PKTDMA_PRI_ALLOC register in Figure 4-7 and

Table 4-4.

Figure 4-7 Packed DMA Priority Allocation Register (PKTDMA_PRI_ALLOC)

31 320

Reserved PKTDMA_PRI

R/W-00000000000000000000001000011 RW-000

Legend: R = Read only; R/W = Read/Write; -n = value after reset

Table 4-4 Packed DMA Priority Allocation Register Field Descriptions

Bit Field Description

31-3 Reserved Reserved.

2-0 PKDTDMA_PRI Control the priority level for the transactions from packet DMA master port, which access the external linking RAM.

End of Table 4-4

For all other modules, see the respective User Guides in 2.9 ‘‘Related Documentation from Texas Instruments’’ on

page 66 for programmable priority registers.

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Multicore Fixed and Floating-Point System-on-Chip

SPRS689D—March 2012

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5 C66x CorePac

The C66x CorePac consists of several components:

• The C66x DSP core

• Level-one and level-two memories (L1P, L1D, L2)

• RSA accelerator (on cores 1 and 2 only)

• Data Trace Formatter (DTF)

• Embedded Trace Buffer (ETB)

• Interrupt controller

• Power-down controller

• External memory controller

• Extended memory controller

• A dedicated power/sleep controller (LPSC)

The C66x CorePac also provides support for memory protection and bandwidth management (for resources local
to the CorePac). Figure 5-1 shows a block diagram of the C66x CorePac.

Figure 5-1 C66x CorePac Block Diagram

32KB L1P

Boot

Controller

LPSCPLLC

GPSC

Memory Controller (PMC) With

Memory Protect/Bandwidth Mgmt

C66x DSP Core

Instruction Fetch

16-/32-bit Instruction Dispatch

Control Registers

In-Circuit Emulation

Instruction Decode

Data Path A

A Register File

A31-A16

A15-A0

.M1

.L1 .S1

xxxx.D1 .D2

Data Memory Controller (DMC) With

Memory Protect/Bandwidth Mgmt

B Register File

Data Path B

B31-B16

B15-B0

.M2

xxxx.S2 .L2

Interrupt and Exception Controller

(UMC)

Unified Memory

Controller

(XMC)

Extended Memory

Controller

(EMC)

Controller

External Memory

L2 Cache/

SRAM

1024KB

MSM

SRAM

2048KB

DDR3

SRAM

DMA Switch

Fabric

CFG Switch

Fabric

RSA

Cores1&2

only

98 C66x CorePac Copyright 2012 Texas Instruments Incorporated

32KB L1D

RSA

Cores1&2

only

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Multicore Fixed and Floating-Point System-on-Chip

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For more detailed information on the C66x CorePac in the C6670 device, see the C66x CorePac User Guide in

2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66.

SPRS689D—March 2012

5.1 Memory Architecture

Each CorePac of the TMS320C6670 device contains a 1024KB level-2 memory (L2), a 32KB level-1 program
memory (L1P), and a 32KB level-1 data memory (L1D). The device also contain a 2048KB multicore shared memory
(MSM). All memory on the C6670 has a unique location in the memory map (see Table 2-2 ‘‘Memory Map

Summary’’ on page 21.

After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache can be
reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PMODE) and the
L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a two-way
set-associative cache, while L1P is a direct-mapped cache.

The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the Bootloader
for the C66x DSP User Guide in 2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66.

For more information on the operation L1 and L2 caches, see the C66x DSP Cache User Guide in 2.9 ‘‘Related

Documentation from Texas Instruments’’ on page 66.

5.1.1 L1P Memory

The L1P memory configuration for the C6670 device is as follows:

• Region 0 size is 0K bytes (disabled)

• Region 1 size is 32K bytes with no wait states

Figure 5-2 shows the available SRAM/cache configurations for L1P.

Figure 5-2 L1P Memory Configurations

L1P Mode Bits

000 001 010 011 100

1/2

SRAM

3/4

SRAM

Direct

Mapped

Cache

Direct

Mapped

Cache

Direct

Mapped

Cache

All

SRAM

7/8

SRAM

DM

Cache

Block Base

Address

L1P Memory

00E0 0000h

16K bytes

00E0 4000h

8K bytes

00E0 6000h

4Kbytes

00E0 7000h

4Kbytes

00E0 8000h

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5.1.2 L1D Memory

The L1D memory configuration for the C6670 device is as follows:

• Region 0 size is 0K bytes (disabled)

• Region 1 size is 32K bytes with no wait states

Figure 5-3 shows the available SRAM/cache configurations for L1D.

Figure 5-3 L1D Memory Configurations

www.ti.com

L1D Mode Bits

000 001 010 011 100

1/2

SRAM

3/4

SRAM

2-Way
Cache

2-Way
Cache

2-Way
Cache

All

SRAM

7/8

SRAM

2-Way
Cache

L1D Memory

16K bytes

8K bytes

4Kbytes

4Kbytes

Block Base

Address

00F0 0000h

00F0 4000h

00F0 6000h

00F0 7000h

00F0 8000h

100 C66x CorePac Copyright 2012 Texas Instruments Incorporated

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