Texas Instruments TMS320C6457 User Manual

TMS320C6457 DSP Host Port Interface (HPI)

User's Guide

Literature Number: SPRUGK7A

March 2009–Revised July 2010

SPRUGK7A–March 2009–Revised July 2010

Preface ....................................................................................................................................... 6

1 Introduction to the HPI ......................................................................................................... 7

1.1 Summary of the HPI Registers ........................................................................................ 8

1.2 Summary of the HPI Signals ........................................................................................... 9

2 Using the Address Registers .............................................................................................. 11

2.1 Single-HPIA Mode ..................................................................................................... 11

2.2 Dual-HPIA Mode ....................................................................................................... 11

3 HPI Operation ................................................................................................................... 12

3.1 Host-HPI Signal Connections ........................................................................................ 12

3.2 HPI Configuration and Data Flow .................................................................................... 14

3.3 HDS2, HDS1, and HCS: Data Strobing and Chip Selection ..................................................... 15

3.4 HCNTL[1:0] and HR/W: Indicating the Cycle Type ................................................................ 16

3.5 HHWIL: Identifying the First and Second Halfwords in 16-Bit Multiplexed Mode ............................. 17

3.6 HAS: Forcing the HPI to Latch Control Information Early ........................................................ 17

3.7 Performing a Multiplexed Access Without HAS .................................................................... 20

3.8 Single-Halfword HPIC Cycle in the 16-Bit Multiplexed Mode .................................................... 22

3.9 Hardware Handshaking Using the HPI-Ready (HRDY) Signal .................................................. 22

4 Software Handshaking Using the HPI Ready (HRDY) Bit ........................................................ 29

4.1 Polling the HRDY Bit .................................................................................................. 29

5 Interrupts Between the Host and the CPU ............................................................................. 30

5.1 DSPINT Bit: Host-to-CPU Interrupts ................................................................................ 30

5.2 HINT Bit: CPU-to-Host Interrupts .................................................................................... 30

6 FIFOs and Bursting ............................................................................................................ 32

6.1 Read Bursting .......................................................................................................... 32

6.2 Write Bursting .......................................................................................................... 33

6.3 FIFO Flush Conditions ................................................................................................ 34

6.4 FIFO Behavior When a Hardware Reset or Software Reset Occurs ........................................... 34

7 Emulation and Reset Considerations ................................................................................... 35

7.1 Emulation Modes ...................................................................................................... 35

7.2 Software Reset Considerations ...................................................................................... 35

7.3 Hardware Reset Considerations ..................................................................................... 35

8 HPI Registers .................................................................................................................... 36

8.1 Introduction ............................................................................................................. 36

8.2 Power and Emulation Management Register (PWREMU_MGMT) .............................................. 37

8.3 Host Port Interface Control Register (HPIC) ....................................................................... 38

8.4 Host Port Interface Address Registers (HPIAW and HPIAR) .................................................... 40

8.5 Data Register (HPID) .................................................................................................. 41

Appendix A Revision History ...................................................................................................... 42

SPRUGK7A–March 2009–Revised July 2010 Table of Contents

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List of Figures

1 HPI Position in the Host-DSP System ................................................................................... 7

2 Example of Host-DSP Signal Connections When Using the HAS Signal in the 32-Bit Multiplexed Mode .... 12

3 Example of Host-DSP Signal Connections When the HAS Signal is Tied High in the 32-Bit Multiplexed

Mode ........................................................................................................................ 13

4 Example of Host-DSP Signal Connections When Using the HAS Signal in the 16-Bit Multiplexed Mode .... 13

5 Example of Host-DSP Signal Connections When the HAS Signal is Tied High in the 16-Bit Multiplexed

Mode ........................................................................................................................ 14

6 HPI Strobe and Select Logic............................................................................................. 15

7 16-Bit Multiplexed Mode Host Read Cycle Using HAS .............................................................. 18

8 16-Bit Multiplexed Mode Host Write Cycle Using HAS .............................................................. 19

9 16-Bit Multiplexed Mode Host Read Cycle With HAS Tied High.................................................... 20

10 16-Bit Multiplexed Mode Host Write Cycle With HAS Tied High.................................................... 21

11 16-Bit Multiplexed Mode Single-Halfword HPIC Cycle with HAS Tied High....................................... 22

12 HRDY Behavior During an HPIC or HPIA Read Cycle in the 16-Bit Multiplexed Mode.......................... 23

13 HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 1: HPIA Write

Cycle Followed by Nonautoincrement HPID Read Cycle) ........................................................... 23

14 HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 2: HPIA Write

Cycle Followed by Autoincrement HPID Read Cycles) .............................................................. 23

15 HRDY Behavior During an HPIC Write Cycle in the 16-Bit Multiplexed Mode.................................... 24

16 HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode (Case 1: No

Autoincrementing)......................................................................................................... 24

17 HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode(Case 2: Autoincrementing

Selected, FIFO Empty Before Write).................................................................................... 24

18 HRDY Behavior During a Data Write Operation in the 16-Bit Multiplexed Mode(Case 3: Autoincrementing

Selected, FIFO Not Empty Before Write)............................................................................... 25

19 HRDY Behavior During an HPIC or HPIA Read Cycle in the 32-Bit Multiplexed Mode.......................... 25

20 HRDY Behavior During a Data Read Operation in the 16-Bit Multiplexed Mode (Case 1: HPIA Write

Cycle Followed by Nonautoincrement HPID Read Cycle) ........................................................... 26

21 HRDY Behavior During a Data Read Operation in the 32-Bit Multiplexed Mode (Case 2: HPIA Write

Cycle Followed by Autoincrement HPID Read Cycles) .............................................................. 26

22 HRDY Behavior During an HPIC Write Cycle in the 32-Bit Multiplexed Mode.................................... 27

23 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 1: No

Autoincrementing)......................................................................................................... 27

24 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 2:

Autoincrementing Selected, FIFO Empty Before Write).............................................................. 28

25 HRDY Behavior During a Data Write Operation in the 32-Bit Multiplexed Mode (Case 3:

Autoincrementing Selected, FIFO Not Empty Before Write)......................................................... 28

26 Host-to-CPU Interrupt State Diagram................................................................................... 30

27 CPU-to-Host Interrupt State Diagram................................................................................... 31

28 FIFOs in the HPI........................................................................................................... 32

29 Power and Emulation Management Register (PWREMU_MGMT) ................................................. 37

30 Host Access Permissions ................................................................................................ 38

31 CPU Access Permissions ................................................................................................ 38

32 Format of an Address Register (HPIAW or HPIAR) - Host Access Permissions ................................. 40

33 Format of an Address Register (HPIAW or HPIAR) - CPU Access Permissions................................. 40

34 Data Register (HPID) (Host access permissions, CPU cannot access HPID) .................................... 41

List of Figures SPRUGK7A–March 2009–Revised July 2010

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1 Summary of HPI Registers ................................................................................................ 9

2 HPI Signals .................................................................................................................. 9

3 Options for Connecting Host and HPI Data Strobe Pins ............................................................. 15

4 Access Types Selectable by the HCNTL Signals..................................................................... 16

5 Cycle Types Selectable With the HCNTL and HR/W Signals ....................................................... 16

6 Host Port Interface (HPI) Registers ..................................................................................... 36

7 Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions........................... 37

8 Host Port Interface Control Register (HPIC) Field Descriptions..................................................... 38

9 Host Port Interface Address Registers (HPIAW or HPIAR) Field Descriptions ................................... 40

10 Data Register (HPID) Field Descriptions............................................................................... 41

11 TMS320C6457 HPI Revision History................................................................................... 42

List of Tables

SPRUGK7A–March 2009–Revised July 2010 List of Tables

About This Manual

This guide describes the host port interface (HPI) on the TMS320C6457 digital signal processors (DSPs). The HPI enables an external host processor (host) to directly access the internal or external memory of the DSP using a 16-bit (HPI16) or 32-bit (HPI32) interface.

Notational Conventions

This document uses the following conventions.

• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40

hexadecimal (decimal 64): 40h.

• Registers in this document are shown in figures and described in tables.

– Each register figure shows a rectangle divided into fields that represent the fields of the register.

Each field is labeled with its bit name, its beginning and ending bit numbers above, and its

read/write properties below. A legend explains the notation used for the properties.

– Reserved bits in a register figure designate a bit that is used for future device expansion.

Preface

SPRUGK7A–March 2009–Revised July 2010

Read This First

Related Documentation From Texas Instruments

The following documents describe the C6000™ devices and related support tools. Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.

SPRU189 — TMS320C6000 DSP CPU and Instruction Set Reference Guide. Describes the CPU

architecture, pipeline, instruction set, and interrupts for the TMS320C6000 digital signal processors

(DSPs).

SPRU198 — TMS320C6000 Programmer's Guide. Describes ways to optimize C and assembly code for

the TMS320C6000™ DSPs and includes application program examples.

SPRU301 — TMS320C6000 Code Composer Studio Tutorial. Introduces the Code Composer Studio™

integrated development environment and software tools.

SPRU321 — Code Composer Studio Application Programming Interface Reference Guide.

Describes the Code Composer Studio™ application programming interface (API), which allows you

to program custom plug-ins for Code Composer.

SPRU871 — TMS320C64x+ Megamodule Reference Guide. Describes the TMS320C64x+ digital signal

processor (DSP) megamodule. Included is a discussion on the internal direct memory access

(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth

management, and the memory and cache.

C6000, TMS320C6000, Code Composer Studio are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

Preface SPRUGK7A–March 2009–Revised July 2010

HPID

R/W FIFOs

HPIA

Increment

HPIC

Access

type

HD[31:0]/HD[15:0]

HDS1, HDS2

HR/W

HAS

HCNTL0 HCNTL1

(optional)

HINT HRDY

HPI

Host

Data

Address

ALE R/W

IRQ

Ready

HCS

Chip select

DSP

HPI DMA logic

HHWIL

(if needed)

Data strobes

Switched

central

resource

C64x+

megamodule

External memory

I/F

Other

peripherals

EDMA3

Internal

memory

This guide describes the host port interface (HPI) on the TMS320C6457 digital signal processors (DSPs). The HPI enables an external host processor (host) to directly access DSP resources (including internal and external memory) using a 16-bit (HPI16) or 32-bit (HPI32) interface.

1 Introduction to the HPI

The HPI provides a parallel port interface through which an external host processor (host) can access DSP resources. The HPI enables a host device and CPU to exchange information via internal or external memory. Dedicated address and data registers (HPIA and HPID respectively) within the HPI provide the data path between the external host interface and the processor resources. An HPI control register (HPIC) is available to the host and the CPU for various configuration and interrupt functions.

Figure 1 is a high-level block diagram showing how the HPI connects a host (left side of figure) and the

DSP internal resources (right side of figure). The host functions as a master to the HPI. Host activity is asynchronous to the internal clock that drives the HPI. When HPI resources are temporarily busy or unavailable, the HPI informs the host by deasserting the HPI-ready (HRDY) output signal.

User's Guide

SPRUGK7A–March 2009–Revised July 2010

Host Port Interface (HPI)

Figure 1. HPI Position in the Host-DSP System

SPRUGK7A–March 2009–Revised July 2010 Host Port Interface (HPI)

Introduction to the HPI

The HPI uses multiplexed operation, meaning the data bus carries both address and data. When the host drives an address on the bus, the address is stored in the address register (HPIA) in the HPI, so that the bus can then be used for data.

The HPI supports two interface modes: HPI16 and HPI32 mode. DSP selects either HPI16 or HPI32 mode via the HPI_WIDTH device configuration pin at reset.

• 16-bit multiplexed mode (HPI16). The HPI is called HPI16 when operating as a 16-bit wide host port.

This mode is selected if the HPI_WIDTH configuration pin of the DSP is sampled low at reset. In this mode, a 16-bit data bus (HD[15:0]) carries both addresses and data. HPI16 combines successive 16-bit transfers to provide 32-bit data to the CPU. The halfword identification line (HHWIL) input is used on the HPI16 to identify the first or second half word of a word transfer.

• 32-bit multiplexed mode (HPI32). HPI operates in this mode as a 32-bit wide host port. This mode is

selected if the HPI_WIDTH configuration pin of the DSP is sampled high at reset. In this mode, a 32-bit data bus (HD[31:0]) carries both addresses and data. HHWIL is not applicable for HPI32 mode.

The HPI contains two HPIAs (HPIAR and HPIAW), which can be used as separate address registers for read accesses and write accesses (for details, see Section 2).

A 32-bit control register (HPIC) is accessible by the DSP CPU and the host. The CPU can use HPIC to send an interrupt request to the host, to clear an interrupt request from the host, and to monitor the HPI. The host can use HPIC to configure and monitor the HPI, to send an interrupt request to the CPU, and to clear an interrupt request from the CPU.

Data flow between the host and the HPI uses a temporary storage register, the 32-bit data register (HPID). Data arriving from the host is held in HPID until the data can be stored elsewhere in the DSP. Data to be sent to the host is held in HPID until the HPI is ready to perform the transfer. When address autoincrementing is used, read and write FIFOs are used to store burst data. If autoincrementing is not used, the FIFO memory acts as a single register (only one location is used).

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NOTE: To manage data transfers between HPID and the internal memory, the DSP contains

dedicated HPI DMA logic. The HPI DMA logic is not programmable. It automatically stores or fetches data using the address provided by the host. The HPI DMA logic is independent of the EDMA3 controller included in the DSP.

In the DSP system, master and slave peripherals communicate with each other via the Switched Central Resource (SCR). By definition, master peripherals are capable of initiating read and write transfers in the system and may not solely rely on the EDMA3 controller for their data transfers. Slave peripherals rely on the EDMA3 controller to perform transfers. The HPI is a master peripheral; it uses its DMA logic to directly communicate with the rest of the system via the SCR and does not rely on the EDMA3 controller for its data transfers. Note that the HPI cannot access all DSP resources or peripherals; see the device-specific data manual for a list of resources accessible through the HPI.

1.1 Summary of the HPI Registers

Table 1 summarizes the registers inside the HPI, including access permissions and access requirements

from the perspective of the host and the DSP CPU. See Section 8 for detailed descriptions of all these registers. Section 2 describes the two address registers (HPIAW and HPIAR) and describes the two HPIA modes that determine how the host uses these registers.

The host can only access HPIC, HPIAW, HPIAR, and HPID. By driving specific levels on the HCNTL[1:0] signals, the host indicates whether it is performing an HPIC, HPIA, or HPID access. For an HPID access, the HCNTL signals also indicate whether or not the HPI should perform an automatic address increment after the access. Section 3.4 describes the effects of the HCNTL[1:0] signals. The HR/W signal indicates whether the host is reading or writing.

The DSP CPU cannot access HPID but has limited access to HPIC, HPIAR, and HPIAW. The CPU has full access to the power and emulation management register, which selects an emulation mode for the HPI.

HPI registers accessible by the CPU have an address in the DSP memory map. Table 1 shows the offset addresses for various HPI registers. See the device-specific data manual for the base addresses of the HPI registers.

Host Port Interface (HPI) SPRUGK7A–March 2009–Revised July 2010

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(1)

Introduction to the HPI

Table 1. Summary of HPI Registers

Host Access CPU Access

PWREMU_MGMT Power and Emulation None - Read/Write 04h

Management Register

HPIC Host Port Interface Control Read/Write HCNTL1 low Read: All bits 30h

HPIAW Host Port Interface Write Address Read/Write HCNTL1 high Read only 34h

HPIAR Host Port Interface Read Address Read/Write HCNTL1 high Read only 38h

HPID Host Port Interface Data Register Read/Write With autoincrementing: None None

The single-HPIA mode and the dual-HPIA mode are described in Section 2.

Read/Write Access Requirements Read/Write Offset

and DSPINT bits only

Single-HPIA mode, or dual-HPIA mode with HPIAW selected

Single-HPIA mode, or dual-HPIA mode with HPIAR selected

HCNTL1 low HCNTL0 high No autoincrementing: HCNTL1 high HCNTL0 high

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1.2 Summary of the HPI Signals

Table 2 summarizes each of the HPI signals. It provides the signal name, the possible states for the signal

(input, output, or high-impedance), the connection(s) to be made on the host side of the interface, and a description of the signal’s function.

Note that the encoding of HCNTL0 and HCNTL1 for the different types of HPI accesses varies on many TI DSPs; therefore, you should use caution to ensure that the correct encoding of these inputs is used for your device. The encoding of these signals as described in this document applies only to C6457 DSPs.

Signal State

HCS I Chip select pin HPI chip select. HCS must be low for the HPI to be

HDS1 and I Read strobe and write strobe pins or HPI data strobe pins. These pins are used for strobing HDS2 any data strobe pin data in and out of the HPI (for data strobing details,

(1)

Host Connection Description

CAUTION

Table 2. HPI Signals

selected by the host. HCS can be kept low between accesses. HCS normally precedes an active HDS (data strobe) signal, but can be connected to an HDS pin for simultaneous select and strobe activity.

see Section 3.3). The direction of the data transfer depends on the logic level of the HR/W signal. The HDS signals are also used to latch control information (if HAS is tied high) on the falling edge. During an HPID write access, data is latched into the HPID register on the rising edge of HDS. During read operations, these pins act as output-enable pins of the host data bus.

(1)

I = Input, O = Output, Z = High Impedance.

SPRUGK7A–March 2009–Revised July 2010 Host Port Interface (HPI)

Introduction to the HPI

Signal State

HCNTL[1:0] I Address or control pins The HPI latches the logic levels of these pins on the

HR/W I R/W strobe pin HPI read/write. On the falling edge of HAS or internal

HHWIL I Address or control pins Halfword identification control input. This bit identifies

HAS I ALE (address latch enable) or Address strobe. A host with a multiplexed address/data

HD[31:0] I/O/Z Data bus The HPI data bus carries the data to/from the HPI. HD[15:0] HD[31:0] applies to HPI32 and HD[15:0] applies to

HRDY O/Z Asynchronous ready pin When the HPI drives HRDY low, the host has

HINT O/Z Interrupt pin The DSP can interrupt the host processor by writing a

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Table 2. HPI Signals (continued)

(1)

Host Connection Description

falling edge of HAS or internal HSTRB (for details about internal HSTRB, see Section 3.3). The four binary states of these pins determine the access type of the current transfer (HPIC, HPID with autoincrementing, HPIA, or HPID without autoincrementing).

HSTRB, HR/W indicates whether the current access is to be a read or write operation. Driving HR/W high indicates the transfer is a read from the HPI, while driving HR/W low indicates a write to the HPI.

the first and second halfwords of a dual halfword cycle operation. HHWIL=0 identifies the first cycle and HHWIL=1 identifies the second cycle. HHWIL applies only to HPI16 mode and not to HPI32 mode.

address strobe pin bus can have HAS connected to its ALE pin. The

falling edge of HAS latches the logic levels of the HR/W, HCNTL1, and HCNTL0 pins, which are typically connected to host address lines. When used, the HAS signal must precede the falling edge of the internal HSTRB signal.

HPI16.

permission to complete the current host cycle. When the HPI drives HRDY high, the HPI is not ready for the current host cycle to complete.

1 to the HINT bit of HPIC. Before subsequent HINT interrupts can occur, the host must clear previous interrupts by writing a 1 to the HINT bit. This pin is active-low and inverted from the HINT bit value in HPIC.

Host Port Interface (HPI) SPRUGK7A–March 2009–Revised July 2010

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2 Using the Address Registers

The HPI contains two 32-bit address registers: one for read operations (HPIAR) and one for write operations (HPIAW). These roles are unchanging from the position of the HPI DMA logic. HPI DMA logic collects the address from HPIAR when reading from DSP internal/external memory and collects the address from HPIAW when writing to DSP internal/external memory.

However, unlike the HPI DMA logic, the host can choose how to interact with the two HPIA registers. Using the DUALHPIA bit of HPIC, the host determines whether HPIAR and HPIAW act as a single 32-bit register (single-HPIA mode) or as two independent 32-bit registers (dual-HPIA mode).

The host must always write a word address to the HPIAs. For example, L2 memory has a base byte address of 80 0000h that corresponds to a word address of 20 0000h. A host must write 20 0000h to the HPIA register to point the HPI to the base of L2 memory.

2.1 Single-HPIA Mode

If DUALHPIA = 0 in HPIC, HPIAR and HPIAW become a single HPIA register for the host. In this mode:

• A host HPIA write cycle (HCNTL[1:0] = 10b, HR/W = 0) updates HPIAR and HPIAW with the same

value.

• Both HPIA registers are incremented during autoincrement read/write cycles (HCNTL[1:0] = 01b).

• An HPIA read cycle (HCNTL[1:0] = 10b, HR/W = 1) returns the contents of HPIAR, which should be

identical to the contents of HPIAW.

To maintain consistency between the contents of HPIAR and HPIAW, the host should always re-initialize the HPIA registers after changing the state of the DUALHPIA bit. In addition, when DUALHPIA = 0, the host must always re-initialize the HPIA registers when it changes the data direction (from an HPID read cycle to an HPID write cycle, or vice versa). Otherwise, the memory location accessed by the HPI DMA logic might not be the host's intended location.

Using the Address Registers

CAUTION

2.2 Dual-HPIA Mode

The host can take advantage of two independent HPIA registers by choosing the dual-HPIA mode (DUALHPIA = 1 in HPIC). In this mode:

• A host HPIA access (HCNTL[1:0] = 10b) reads/updates either HPIAR or HPIAW, depending on the

value of the HPIA read/write select (HPIARWSEL) bit of HPIC. This bit is programmed by the host. While HPIARWSEL = 1, only HPIAR is read or updated by the host. While HPIARWSEL = 0, only HPIAW is read or updated by the host. The HPIARWSEL bit is only meaningful in the dual-HPIA mode.

NOTE: The HPIARWSEL bit does not affect the HPI DMA logic. Regardless of the value of

HPIARWSEL, the HPI DMA logic uses HPIAR when reading from memory and HPIAW when writing to memory.

• A host HPID access with autoincrementing (HCNTL[1:0] = 01b) causes only the relevant HPIA value to

be incremented to the next consecutive memory address. In an autoincrement read cycle, HPIAR is incremented after it has been used to perform the current read from memory. In an autoincrement write cycle, HPIAW is incremented after it has been used for the write operation.

SPRUGK7A–March 2009–Revised July 2010 Host Port Interface (HPI)

Address or I/O

Read/Write

Chip select

Data strobe

Data/address

Interrupt

Ready

HCNTL[1:0]

HR/W

HCS HDS1

HDS2

HD[31:0]

HINT

HRDY

HPI

Host

Address latch enable HAS

No connect HHWIL

Logic high

DSP

HPI Operation

3 HPI Operation

3.1 Host-HPI Signal Connections

Figure 2 and Figure 3 show examples of signal connections for the 32-bit multiplexed mode. Figure 4 and Figure 5 show similar examples for the 16-bit multiplexed mode. In Figure 2 and Figure 4, the HAS signal

is used as described in Section 3.6. In Figure 3 and Figure 5, HAS is tied high (not used). Note the following key comparisons between the signal connections in the two interface modes:

• The HPI_WIDTH configuration pin of the DSP must be held high at reset for the 32-bit multiplexed

mode (HPI32) or low at reset for the 16-bit multiplexed mode (HPI16).

• The address strobe (HAS) of the HPI is optional for both modes.

• The halfword identification control line (HHWIL) of the HPI is not used in the 32-bit multiplexed mode,

but is required in the 16-bit multiplexed mode.

Figure 2. Example of Host-DSP Signal Connections When Using the HAS Signal

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CAUTION

in the 32-Bit Multiplexed Mode

A Data strobing options are given in Section 3.3.

Host Port Interface (HPI) SPRUGK7A–March 2009–Revised July 2010

Address or I/O

Read/Write

Chip select

Data strobe

Data/address

Interrupt

Ready

HCNTL[1:0]

HR/W

HCS HDS1

HDS2

HD[31:0]

HINT

HRDY

HPIHost

Logic high HAS

No connect HHWIL

Logic high

DSP

Read/Write Chip select

Data strobe

Data/address

Interrupt

Ready

HCNTL[1:0]

HR/W HCS

HDS1 HDS2

HD[15:0]

HINT

HRDY

HPI

DSP

Host

Address latch enable HAS

HHWIL

Logic

high

HD[31:16]

connect

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HPI Operation

Figure 3. Example of Host-DSP Signal Connections When the HAS Signal is Tied High

in the 32-Bit Multiplexed Mode

A Data strobing options are given in Section 3.3.

Figure 4. Example of Host-DSP Signal Connections When Using the HAS Signal

in the 16-Bit Multiplexed Mode

A Data strobing options are given in Section 3.3.

SPRUGK7A–March 2009–Revised July 2010 Host Port Interface (HPI)

+ 30 hidden pages

Texas Instruments TMS320C6457 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

SPRUGK7A–March 2009–Revised July 2010 Table of Contents

Preface

1 Introduction to the HPI

1.1 Summary of the HPI Registers

1.2 Summary of the HPI Signals

2 Using the Address Registers

2.1 Single-HPIA Mode

2.2 Dual-HPIA Mode

3 HPI Operation

3.1 Host-HPI Signal Connections