Texas Instruments TMS320C6452 DSP User Manual
TMS320C6452 DSP
VLYNQ Port
User's Guide
Literature Number: SPRUF89
October 2007
2 SPRUF89 – October 2007
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Contents
Preface ............................................................................................................................... 7
1 Introduction .............................................................................................................. 10
1.1 Purpose of the Peripheral ..................................................................................... 10
1.2 Features ......................................................................................................... 10
1.3 Functional Block Diagram ..................................................................................... 11
1.4 Industry Standard(s) Compliance Statement ............................................................... 11
2 Peripheral Architecture .............................................................................................. 12
2.1 Clock Control .................................................................................................... 12
2.2 Signal Descriptions ............................................................................................. 13
2.3 Pin Multiplexing ................................................................................................. 13
2.4 Protocol Description ............................................................................................ 13
2.5 VLYNQ Functional Description ............................................................................... 14
2.6 Initialization ...................................................................................................... 17
2.7 Auto Negotiation ................................................................................................ 17
2.8 Serial Interface Width Configuration ......................................................................... 17
2.9 Address Translation ............................................................................................ 17
2.10 Flow Control ..................................................................................................... 21
2.11 Reset Considerations .......................................................................................... 21
2.12 Interrupt Support ................................................................................................ 21
2.13 DMA Event Support ............................................................................................ 23
2.14 Power Management ............................................................................................ 24
2.15 Emulation Considerations ..................................................................................... 24
3 VLYNQ Port Registers ................................................................................................ 25
3.1 Revision Register (REVID) .................................................................................... 26
3.2 Control Register (CTRL) ....................................................................................... 27
3.3 Status Register (STAT) ........................................................................................ 29
3.4 Interrupt Priority Vector Status/Clear Register (INTPRI) .................................................. 31
3.5 Interrupt Status/Clear Register (INTSTATCLR) ............................................................ 31
3.6 Interrupt Pending/Set Register (INTPENDSET) ............................................................ 32
3.7 Interrupt Pointer Register (INTPTR) ......................................................................... 32
3.8 Transmit Address Map Register (XAM)...................................................................... 33
3.9 Receive Address Map Size 1 Register (RAMS1) .......................................................... 33
3.10 Receive Address Map Offset 1 Register (RAMO1) ........................................................ 34
3.11 Receive Address Map Size 2 Register (RAMS2) .......................................................... 34
3.12 Receive Address Map Offset 2 Register (RAMO2) ........................................................ 35
3.13 Receive Address Map Size 3 Register (RAMS3) .......................................................... 35
3.14 Receive Address Map Offset 3 Register (RAMO3) ........................................................ 36
3.15 Receive Address Map Size 4 Register (RAMS4) .......................................................... 36
3.16 Receive Address Map Offset 4 Register (RAMO4) ........................................................ 37
3.17 Chip Version Register (CHIPVER) ........................................................................... 37
3.18 Auto Negotiation Register (AUTNGO) ....................................................................... 38
3.19 Manual Negotiation Register (MANNGO) .................................................................. 38
3.20 Negotiation Status Register (NGOSTAT) ................................................................... 39
3.21 Interrupt Vector 3-0 Register (INTVEC0) .................................................................... 40
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3.22 Interrupt Vector 7-4 Register (INTVEC1) ................................................................... 42
4 Remote Configuration Registers ................................................................................. 44
Appendix A VLYNQ Protocol Specifications ........................................................................ 45
A.1 Special 8b/10b Code Groups ................................................................................. 45
A.2 Supported Ordered Sets ....................................................................................... 45
A.3 VLYNQ 2.0 Packet Format .................................................................................... 47
A.4 VLYNQ 2.X Packets ............................................................................................ 48
Appendix B Write/Read Performance .................................................................................. 50
B.1 Write Performance.............................................................................................. 50
B.2 Read Performance ............................................................................................. 53
4 Contents SPRUF89 – October 2007
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List of Figures
1 VLYNQ Port Functional Block Diagram ................................................................................. 11
2 External Clock Block Diagram ............................................................................................ 12
3 Internal Clock Block Diagram ............................................................................................. 12
4 VLYNQ Module Structure ................................................................................................. 14
5 Write Operations ........................................................................................................... 15
6 Read Operations ........................................................................................................... 16
7 Example Address Memory Map .......................................................................................... 18
8 Interrupt Generation Mechanism Block Diagram ....................................................................... 22
9 Revision Register (REVID) ................................................................................................ 26
10 Control Register (CTRL) ................................................................................................... 27
11 Status Register (STAT) .................................................................................................... 29
12 Interrupt Priority Vector Status/Clear Register (INTPRI) .............................................................. 31
13 Interrupt Status/Clear Register (INTSTATCLR) ........................................................................ 31
14 Interrupt Pending/Set Register (INTPENDSET) ........................................................................ 32
15 Interrupt Pointer Register (INTPTR) ..................................................................................... 32
16 Transmit Address Map Register (XAM) ................................................................................. 33
17 Receive Address Map Size 1 Register (RAMS1) ...................................................................... 33
18 Receive Address Map Offset 1 Register (RAMO1) .................................................................... 34
19 Receive Address Map Size 2 Register (RAMS2) ...................................................................... 34
20 Receive Address Map Offset 2 Register (RAMO2) .................................................................... 35
21 Receive Address Map Size 3 Register (RAMS3) ...................................................................... 35
22 Receive Address Map Offset 3 Register (RAMO3) .................................................................... 36
23 Receive Address Map Size 4 Register (RAMS4) ...................................................................... 36
24 Receive Address Map Offset 4 Register (RAMO4) .................................................................... 37
25 Chip Version Register (CHIPVER) ....................................................................................... 37
26 Auto Negotiation Register (AUTNGO) ................................................................................... 38
27 Manual Negotiation Register (MANNGO) ............................................................................... 38
28 Negotiation Status Register (NGOSTAT) ............................................................................... 39
29 Interrupt Vector 3-0 Register (INTVEC0) ................................................................................ 40
30 Interrupt Vector 7-4 Register (INTVEC1) ................................................................................ 42
A-1 Packet Format (10-bit Symbol Representation) ........................................................................ 47
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List of Tables
1 VLYNQ Port Pins ........................................................................................................... 13
2 Serial Interface Width ...................................................................................................... 17
3 Address Translation Example (Single Mapped Region) .............................................................. 19
4 Address Translation Example (Single Mapped Region) .............................................................. 19
5 VLYNQ Register Address Space ......................................................................................... 25
6 VLYNQ Port Controller Registers ........................................................................................ 25
7 Revision Register (REVID) Field Descriptions ......................................................................... 26
8 Control Register (CTRL) Field Descriptions ............................................................................ 27
9 Status Register (STAT) Field Descriptions ............................................................................. 29
10 Interrupt Priority Vector Status/Clear Register (INTPRI) Field Descriptions ........................................ 31
11 Interrupt Status/Clear Register (INTSTATCLR) Field Descriptions .................................................. 31
12 Interrupt Pending/Set Register (INTPENDSET) Field Descriptions ................................................. 32
13 Interrupt Pointer Register (INTPTR) Field Descriptions ............................................................... 32
14 Address Map Register (XAM) Field Descriptions ...................................................................... 33
15 Receive Address Map Size 1 Register (RAMS1) Field Descriptions ................................................ 33
16 Receive Address Map Offset 1 Register (RAMO1) Field Descriptions .............................................. 34
17 Receive Address Map Size 2 Register (RAMS2) Field Descriptions ................................................ 34
18 Receive Address Map Offset 2 Register (RAMO2) Field Descriptions .............................................. 35
19 Receive Address Map Size 3 Register (RAMS3) Field Descriptions ................................................ 35
20 Receive Address Map Offset 3 Register (RAMO3) Field Descriptions .............................................. 36
21 Receive Address Map Size 4 Register (RAMS4) Field Descriptions ................................................ 36
22 Receive Address Map Offset 4 Register (RAMO4) Field Descriptions .............................................. 37
23 Chip Version Register (CHIPVER) Field Descriptions................................................................. 37
24 Auto Negotiation Register (AUTNGO) Field Descriptions ............................................................ 38
25 Manual Negotiation Register (MANNGO) Field Descriptions ......................................................... 38
26 Negotiation Status Register (NGOSTAT) Field Descriptions ......................................................... 39
27 Interrupt Vector 3-0 Register (INTVEC0) Field Description ........................................................... 40
28 Interrupt Vector 7-4 Register (INTVEC1) Field Description ........................................................... 42
29 VLYNQ Port Remote Controller Registers .............................................................................. 44
A-1 Special 8b/10b Code Groups ............................................................................................. 45
A-2 Supported Ordered Sets .................................................................................................. 45
A-3 Packet Format (10-bit Symbol Representation) Description .......................................................... 47
B-1 Scaling Factors ............................................................................................................. 50
B-2 Expected Throughput (VLYNQ Interface Running at 99 MHz) ....................................................... 51
B-3 Expected Throughput (VLYNQ Interface Running at 76.5 MHz)..................................................... 52
B-4 Relative Performance with Various Latencies .......................................................................... 53
6 List of Tables SPRUF89 – October 2007
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About This Manual
Notational Conventions
Preface
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This document describes the VLYNQ™ communications interface port in the TMS320C6452 Digital Signal
Processor (DSP).
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Note: Acronyms 3PSW, CPSW, CPSW_3G, and 3pGSw are interchangeable and all refer to the 3
port gigabit switch.
TMS320C6452 DSP
Related Documents From Texas Instruments
The following documents describe the TMS320C6452 Digital Signal Processor (DSP). Copies of these
documents are available on the Internet at www.ti.com . Tip: Enter the literature number in the search box
provided at www.ti.com .
Data Manual—
SPRS371 — TMS320C6452 Digital Signal Processor Data Manual describes the signals, specifications
and electrical characteristics of the device.
CPU—
SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital
signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation
comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of
the C64x DSP with added functionality and an expanded instruction set.
Reference Guides—
SPRUF85 — TMS320C6452 DSP DDR2 Memory Controller User's Guide describes the DDR2 memory
controller in the TMS320C6452 Digital Signal Processor (DSP). The DDR2/mDDR memory
controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices and
standard Mobile DDR SDRAM devices.
SPRUF89 – October 2007 Preface 7
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TMS320C6452 DSP
SPRUF86 — TMS320C6452 Peripheral Component Interconnect (PCI) User's Guide describes the
SPRUF87 — TMS320C6452 DSP Host Port Interface (UHPI) User's Guide describes the host port
SPRUF89 — TMS320C6452 DSP VLYNQ Port User's Guide describes the VLYNQ port in the
SPRUF90 — TMS320C6452 DSP 64-Bit Timer User's Guide describes the operation of the 64-bit timer
SPRUF91 — TTMS320C6452 DSP Multichannel Audio Serial Port (McASP) User's Guide describes
peripheral component interconnect (PCI) port in the TMS320C6452 Digital Signal Processor (DSP).
The PCI port supports connection of the C642x DSP to a PCI host via the integrated PCI
master/slave bus interface. The PCI port interfaces to the DSP via the enhanced DMA (EDMA)
controller. This architecture allows for both PCI master and slave transactions, while keeping the
EDMA channel resources available for other applications.
interface (HPI) in the TMS320C6452 Digital Signal Processor (DSP). The HPI is a parallel port
through which a host processor can directly access the CPU memory space. The host device
functions as a master to the interface, which increases ease of access. The host and CPU can
exchange information via internal or external memory. The host also has direct access to
memory-mapped peripherals. Connectivity to the CPU memory space is provided through the
enhanced direct memory access (EDMA) controller.
TMS320C6452 Digital Signal Processor (DSP). The VLYNQ port is a high-speed point-to-point
serial interface for connecting to host processors and other VLYNQ compatible devices. It is a
full-duplex serial bus where transmit and receive operations occur separately and simultaneously
without interference.
in the TMS320C6452 Digital Signal Processor (DSP). The timer can be configured as a
general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a watchdog timer.
the multichannel audio serial port (McASP) in the TMS320C6452 Digital Signal Processor (DSP).
The McASP functions as a general-purpose audio serial port optimized for the needs of
multichannel audio applications. The McASP is useful for time-division multiplexed (TDM) stream,
Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission
(DIT).
SPRUF92 — TMS320C6452 DSP Serial Port Interface (SPI) User's Guide discusses the Serial Port
Interface (SPI) in the TMS320C6452 Digital Signal Processor (DSP). This reference guide provides
the specifications for a 16-bit configurable, synchronous serial peripheral interface. The SPI is a
programmable-length shift register, used for high speed communication between external
peripherals or other DSPs.
SPRUF93 — TMS320C6452 DSP Universal Asynchronous Receiver/Transmitter (UART) User's
Guide describes the universal asynchronous receiver/transmitter (UART) peripheral in the
TMS320C6452 Digital Signal Processor (DSP). The UART peripheral performs serial-to-parallel
conversion on data received from a peripheral device, and parallel-to-serial conversion on data
received from the CPU.
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inter-integrated circuit (I2C) peripheral in the TMS320C6452 Digital Signal Processor (DSP). The
I2C peripheral provides an interface between the DSP and other devices compliant with the
I2C-bus specification and connected by way of an I2C-bus. External components attached to this
2-wire serial bus can transmit and receive up to 8-bit wide data to and from the DSP through the
I2C peripheral. This document assumes the reader is familiar with the I2C-bus specification.
SPRUF95 — TMS320C6452 DSP General-Purpose Input/Output (GPIO) User's Guide describes the
general-purpose input/output (GPIO) peripheral in the TMS320C6452 Digital Signal Processor
(DSP). The GPIO peripheral provides dedicated general-purpose pins that can be configured as
either inputs or outputs. When configured as an input, you can detect the state of the input by
reading the state of an internal register. When configured as an output, you can write to an internal
register to control the state driven on the output pin.
8 Read This First SPRUF89 – October 2007
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SPRUF96 — TMS320C6452 DSP Telecom Serial Interface Port (TSIP) User's Guide is a multi-link
serial interface consisting of a maximum of two transmit data signals (or links), two receive data
signals (or links), two frame sync input signals, and two serial clock inputs. Internally the TSIP
offers single channel of timeslot data management and single DMA capability that allow individual
timeslots to be selectively processed.
SPRUF97 — TMS320C6452 DSP 3 Port Switch (3PSW) Ethernet Subsystem User's Guide describes
the operation of the 3 port switch (3PSW) ethernet subsystem in the TMS320C6452 Digital Signal
Processor (DSP). The 3 port switch gigabit ethernet subsystem provides ethernet packet
communication and can be configured as an ethernet switch. It provides the serial gigabit media
independent interface (SGMII), the management data input output (MDIO) for physical layer device
(PHY) management.
TMS320C6452 DSP
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1 Introduction
1.1 Purpose of the Peripheral
The VLYNQ™ communications interface port is a serial interface with a low pin count, high-speed
point-to-point serial interface in the device for connecting to host processors and other VLYNQ compatible
devices. The VLYNQ port is a full-duplex serial bus where transmit and receive operations occur
separately and simultaneously without interference.
VLYNQ enables the extension of an internal bus segment to one or more external physical devices. The
external devices are mapped to local physical address space and appear as if they are on the internal bus
of the device. The external devices must also have a VLYNQ interface.
VLYNQ uses a simple block code (8b/10b) packet format and supports in-band flow control so that no
extra terminals are needed to indicate that overflow conditions might occur.
The VLYNQ module on the device serializes a write transaction to the remote/external device and
transfers the write via the VLYNQ port (TX pins). The remote VLYNQ module deserializes the transaction
on the other side.
The read transactions to the remote/external device follow the same process, but the remote device's
VLYNQ module serializes the read return data and transfers it to the VLYNQ port (RX pins). The read
return data is finally deserialized and released to the device internal bus.
The external device can also initiate read and write transactions.
User's Guide
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VLYNQ Port
1.2 Features
The general features of the VLYNQ port are:
• Low pin count (10 pin interface, scalable to as low as 3 pins) .
• No tri-state signals:
– All signals are dedicated and driven by only one device.
– Necessary to allow support for high-speed PHYs.
• Simple packet-based transfer protocol for memory-mapped access:
– Write request/data packet.
– Read request packet.
– Read response data packet.
– Interrupt request packet.
• Auto width negotiation.
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Slave
config
bus
Interface
Master
config
Interface
bus
VLYNQmodule
VLYNQregister
access
CPU/EDMA initiated
transfersto
remotedevice
Offchip
(remote)
deviceaccess
CPU/EDMA
memory
System
VSCRUN
VCLK
VRXDx
VTXDx
GEMINTC
VLQINT
Inthesesignals,
x=anumberfrom3to0
• Symmetric Operation:
– Tx pins on first device connect to Rx pins on second device and vice versa.
– Data pin widths are automatically detected after reset (including connections to legacy VLYNQ
devices).
– Request packets, response packets, and flow control information are all multiplexed and sent
across the same physical pins.
– Supports both Host/Peripheral and Peer to Peer communication models.
• Simple block code packet formatting (8b/10b).
• Supports in-band and flow control:
– No extra pins are needed.
– Allows the receiver to momentarily throttle the transmitter back when overflow is about to occur.
– Uses the special built-in block code capability to interleave flow control information seamlessly with
user data.
• Automatic packet formatting optimizations.
• Internal loopback modes are provided.
• Connects to legacy VLYNQ devices.
1.3 Functional Block Diagram
Figure 1 shows a functional block diagram of the VLYNQ port.
Introduction
Figure 1. VLYNQ Port Functional Block Diagram
1.4 Industry Standard(s) Compliance Statement
VLYNQ is an interface defined by Texas Instruments and does not conform to any other industry standard.
SPRUF89 – October 2007 VLYNQ Port 11
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CLKDIR=0
VLYNQ
DMxxxdevice
VCLK
CLKDIR=0
VLYNQ
VLYNQdevice
CLKDIR=1
VLYNQ
DMxxxdevice
VLYNQ.CLK
CLKDIR=0
VLYNQ
VLYNQdevice
Don't
care
VLYNQ
internal
sysclk
Peripheral Architecture
2 Peripheral Architecture
2.1 Clock Control
This section discusses the architecture and basic functions of the VLYNQ peripheral.
The module's serial clock direction and frequency are software configurable through the CLKDIR and
CLKDIV bits in the VLYNQ control register (CTRL). The VLYNQ serial clock can be sourced from the
internal system clock (CLKDIR = 1) or by an external clock source (CLKDIR = 0) for its serial operations.
The CLKDIV bit can divide the serial clock (1/1 - 1/8) down when the internal clock is selected as the
source. The serial clock is not affected by the CLKDIV bit values, if the serial clock is externally sourced.
The reset value of the CLKDIR bit is 0 (external clock source).
The external clock source is shown in Figure 2 . The internal clock source is shown in Figure 3 .
Figure 2. External Clock Block Diagram
Figure 3. Internal Clock Block Diagram
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Peripheral Architecture
2.2 Signal Descriptions
The VLYNQ module on the device is configurable for a 1 to 4 bit-wide RX/TX. Chip-level pin multiplexing
registers control the configuration. See the pin multiplexing information in the device-specific data manual.
If the configured width does not match the number of transmit/receive lines that are available on the
remote device, negotiation between the two VLYNQ devices automatically configures the width (see
Section 2.7 ).
The VLYNQ interface signals are shown in Table 1 .
Table 1. VLYNQ Port Pins
Pin Name Signal Name I/O Description
VCLK VLYNQ serial clock I/O The VLYNQ reference clock supports the internally or externally generated
VSCRUN VLYNQ serial clock I/O The VLYNQ serial clock run request allows remote requests for the VLYNQ
run request serial clock to be turned off for system power management.
(Active low) Low: The request VLYNQ serial clock is active.
VRXD[3:0] VLYNQ receive data I VLYNQ receive data is synchronous with the VLYNQ serial clock.
VTXD[3:0] VLYNQ transmit data O VLYNQ transmit data is synchronous with the VLYNQ serial clock.
clock.
High: The VLYNQ serial clock is requested to be high when all transactions are
complete.
2.3 Pin Multiplexing
The VLYNQ signals share pins on the processor package with other processor functions. The VLYNQ
module pins are not enabled at reset. In order to change the default function of device pins at reset, the
pin multiplexing registers (PINMUX n) must be configured appropriately. See the pin multiplexing
information in the device-specific data manual for more detailed information on the processor pin
multiplexing and configuration registers.
2.4 Protocol Description
VLYNQ relies on 8b/10b block coding to minimize the number of serial pins and allows for in-band packet
delineation and control.
Appendix A provides general information on 8b/10b coding definitions and their implementation within the
VLYNQ module in the device.
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Address
translation
commands
Outbound
Outbound
command
FIFO
data
Return
FIFO
data
FIFO
Return
command
Inbound
FIFO
Registers
translation
Address
TxSM
8B/10B
encoding
Serializer
commands
Inbound
RxSM Deserializer
decoding
8B/10B
Serial
TxData
Serial
TxClk
Serial
RxClk
Serial
RxData
Master
configbus
interface
Systemclock VLYNQclock
Slave
configbus
interface
(FIFO3)
(FIFO2)
(FIFO0)
(FIFO1)
Peripheral Architecture
2.5 VLYNQ Functional Description
The VLYNQ core supports both host-to-peripheral and peer-to-peer communication models and is
symmetrical. The VLYNQ module structure is shown in Figure 4 .
Figure 4. VLYNQ Module Structure
The VLYNQ core module implements two 32-bit configuration bus interfaces. Transmit operations and
control register access require the slave configuration bus interface. The master configuration bus
interface is required for receive operations. Converting to and from the 32-bit bus to the external serial
interface requires serializer and deserializer blocks.
8b/10b block coding encodes data on the serial interface. Frame delineation, initialization, and flow control
use special overhead code groups.
FIFOs buffer the entire burst on the bus for maximum performance, thus minimizing bus latency. Using
write operations of each VLYNQ module interfaced is typically recommended to ensure the best
performance on both directions of the link.
2.5.1 Write Operations
Write requests that initiate from the slave configuration bus interface of the local device write to the
outbound command (CMD) FIFO. Data is subsequently read from the FIFO and encapsulated in a write
request packet. The address is translated, and the packet is encoded and serialized before being
transmitted to remote device. The remote device subsequently deserializes and decodes the receive data
and writes it into the inbound CMD FIFO. A write operation initiates on the remote device’s master
configuration bus interface after reading the address and data from the FIFO.
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The data flow between two VLYNQs that are connected is shown in Figure 5 . In the example shown in
Figure 5 , the write originates from the device.
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Address
translation
commands
Outbound
Outbound
command
FIFO
data
Return
FIFO
data
FIFO
Return
command
Inbound
FIFO
Registers
translation
Address
TxSM
8B/10B
encoding
Serializer
commands
Inbound
RxSM Deserializer
decoding
8B/10B
Serial
TxData
Serial
RxData
Systemclock
Address
translation
Registers
commands
Inbound
translation
Address
commands
Outbound
8B/10B
decoding
FIFO
FIFO
command
Inbound
data
Return
FIFO
RxSM Deserializer
RxData
Serial
encoding
8B/10B
VLYNQClock
command
Return
data
FIFO
Outbound
TxSM Serializer
TxData
Serial
Slave
configbus
interface
Systemclock VLYNQclock
LocalVLYNQ
RemoteVLYNQ
Master
configbus
interface
Master
configbus
interface
Slave
configbus
interface
Figure 5. Write Operations
Peripheral Architecture
2.5.2 Read Operations
Read requests from the slave configuration bus interface are written to the outbound CMD FIFO (similar to
the write requests). Data is subsequently read from the FIFO and encapsulated into a read request
packet. The packet is encoded and serialized before it is transmitted to the remote device. Next, the
remote device deserializes, decodes the receive data, and writes the receive data to the inbound CMD
FIFO. After reading the address from the FIFO, a master configuration bus interface read operation
initiates in the remote device. When the remote master configuration bus interface receives the read data,
the data is written to the return data FIFO before it is encoded and serialized. When the receive data
reaches the local VLYNQ module, it is deserialized, decoded, and written to the return data FIFO (local
device). Finally, the read data is transferred on the local device’s slave configuration interface.
The data flow between two connected VLYNQ devices with read requests that originate from the device is
shown in Figure 6 . The remote VLYNQ device returns the read data. Read data is shown with dotted
arrows.
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Address
translation
commands
Outbound
Outbound
command
FIFO
data
Return
FIFO
data
FIFO
Return
command
Inbound
FIFO
Registers
translation
Address
TxSM
8B/10B
encoding
Serializer
commands
Inbound
RxSM Deserializer
decoding
8B/10B
Serial
TxData
Serial
RxData
Systemclock
Address
translation
Registers
commands
Inbound
translation
Address
commands
Outbound
8B/10B
decoding
FIFO
FIFO
command
Inbound
data
Return
FIFO
RxSM Deserializer
RxData
Serial
encoding
8B/10B
VLYNQClock
command
Return
data
FIFO
Outbound
TxSM Serializer
TxData
Serial
Slave
configbus
interface
VLYNQClock
Systemclock
LocalVLYNC
RemoteVLYNQ
Master
configbus
interface
Slave
configbus
interface
Master
configbus
interface
Peripheral Architecture
Figure 6. Read Operations
Note: Not servicing read operations results in deadlock. The only way to recover from a deadlock
situation is to perform a hard reset. Read operations are typically not serviced due to read
requests that are issued to a non-existent remote VLYNQ device or they are not serviced
due to trying to perform reads on the VLYNQ memory map prior to establishing the link.
Generally, you should not use read operations to transfer data packets since the serial nature of the
interface could potentially result in longer latencies.
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Peripheral Architecture
2.6 Initialization
Since VLYNQ devices can be controlled solely over the serial interface (that is, no local CPU exists), an
automatic reliable initialization sequence (without user configuration) establishes a connection between
two VLYNQ devices, just after a VLYNQ module is enabled and auto-negotiation occurs. Auto-negotiation
is defined in Section 2.7 . The same sequence is used to recover from error conditions.
Bit 0 in the VLYNQ status register (LINK bit) is set to 1 when a link is established.
A link pulse timer generates a periodic link code every 2048 serial clock cycles. The link is lost when time
expires and no link code has been detected during a period of 4096 serial clock cycles.
2.7 Auto Negotiation
Auto-negotiation occurs after reset. It involves placing a negotiation protocol in the outbound data and
processing the inbound data to establish connection information. The width of the data pins on the serial
interface is automatically determined at reset as a part of the initialization sequence. For a connection
between two VLYNQ devices of version 2.0 and later (VLYNQ on the device is version 2.6), the
negotiation protocol using the available serial pins is used to convey the maximum width capability of each
device. The TXD data pins are not required to have the same width as the RXD data pins.
The auto width negotiation does not occur until after completion of the VLYNQ 1.x legacy width
configuration, which involves a period of 2000 VLYNQ 1.x system clock cycles for connection to VLYNQ
1.x devices. After the VLYNQ 1.x has determined its width, it receives the VLYNQ2.x auto width
negotiation protocol. The VLYNQ 1.x device does not recognize this protocol and transmits error codes
over the serial interface. The received error codes allow the VLYNQ 2.x devices to determine how many
serial pins are valid on the connected VLYNQ 1.x device.
Once the width is established, VLYNQ further identifies the version (version 1.x or version 2.x ) of the
remote VLYNQ. This better determines the capabilities of the connected VLYNQ device. This is software
readable via the VLYNQ auto-negotiation register (AUTNGO), bit 16 (0 = Ver 1.x , 1 = Ver 2.x), after the
link has been established.
2.8 Serial Interface Width Configuration
The VLYNQWD bit in the pin multiplexing register 0 (PINMUX0) controls the data width on the device,
thus allowing you to program the serial interface width (as shown in Table 2 ).
For detailed information on the processor pin multiplexing and configuration register, see the pin
multiplexing information in the device-specific data manual.
2.9 Address Translation
Remote VLYNQ device(s) are memory mapped to the local (host) device’s address space when a link is
established (this is similar to any other on-chip peripherals). Enumerating the VLYNQ devices (single or
multiple) into a coherent memory map for accessing each device is part of the initialization sequence.
After the enumeration, the host (local) device can access the remote device address map using local
device addresses. The VLYNQ module in the host device manages the address translation of the local
address to the remote address. A remote VLYNQ device is mapped to the local device’s address via the
address map registers (TX address map, RX address map size n, RX address map offset n, where n = 1
to 4). The transmit side has a contiguous map; the size of the map is the same as the remote device map.
Figure 7 illustrates this mapping.
Table 2. Serial Interface Width
VLYNQWD VLYNQ Data Width
00 VLYNQ TXD[0] , VLYNQ RXD[0]
01 VLYNQ TXD[0:1] , VLYNQ RXD[0:1]
11 VLYNQ TXD[0:2] , VLYNQ RXD[0:2]
10 VLYNQ TXD[0:3] , VLYNQ RXD[0:3]
SPRUF89 – October 2007 VLYNQ Port 17
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