Texas Instruments TMS320C642X User Manual
TMS320C642x DSP
Inter-Integrated Circuit (I2C) Peripheral
User's Guide
Literature Number: SPRUEN0D
March 2011
2
SPRUEN0D–March 2011
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Preface ....................................................................................................................................... 6
1 Introduction ........................................................................................................................ 7
1.1 Purpose of the Peripheral .............................................................................................. 7
1.2 Features .................................................................................................................. 7
1.3 Functional Block Diagram .............................................................................................. 8
1.4 Industry Standard(s) Compliance Statement ........................................................................ 8
2 Peripheral Architecture ........................................................................................................ 9
2.1 Bus Structure ............................................................................................................ 9
2.2 Clock Generation ...................................................................................................... 10
2.3 Clock Synchronization ................................................................................................. 11
2.4 Signal Descriptions .................................................................................................... 11
2.5 START and STOP Conditions ....................................................................................... 12
2.6 Serial Data Formats ................................................................................................... 13
2.7 Endianness Considerations .......................................................................................... 15
2.8 Operating Modes ....................................................................................................... 15
2.9 NACK Bit Generation .................................................................................................. 16
2.10 Arbitration ............................................................................................................... 17
2.11 Reset Considerations .................................................................................................. 18
2.12 Initialization ............................................................................................................. 18
2.13 Interrupt Support ....................................................................................................... 21
2.14 DMA Events Generated by the I2C Peripheral .................................................................... 21
2.15 Power Management ................................................................................................... 21
2.16 Emulation Considerations ............................................................................................. 22
3 Registers .......................................................................................................................... 22
3.1 I2C Own Address Register (ICOAR) ................................................................................ 23
3.2 I2C Interrupt Mask Register (ICIMR) ................................................................................ 24
3.3 I2C Interrupt Status Register (ICSTR) .............................................................................. 25
3.4 I2C Clock Divider Registers (ICCLKL and ICCLKH) .............................................................. 28
3.5 I2C Data Count Register (ICCNT) ................................................................................... 29
3.6 I2C Data Receive Register (ICDRR) ................................................................................ 30
3.7 I2C Slave Address Register (ICSAR) ............................................................................... 30
3.8 I2C Data Transmit Register (ICDXR) ............................................................................... 31
3.9 I2C Mode Register (ICMDR) ......................................................................................... 32
3.10 I2C Interrupt Vector Register (ICIVR) ............................................................................... 36
3.11 I2C Extended Mode Register (ICEMDR) ........................................................................... 37
3.12 I2C Prescaler Register (ICPSC) ..................................................................................... 38
3.13 I2C Peripheral Identification Register (ICPID1) .................................................................... 39
3.14 I2C Peripheral Identification Register (ICPID2) .................................................................... 39
Appendix A Revision History ...................................................................................................... 40
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List of Figures
1 I2C Peripheral Block Diagram............................................................................................. 8
2 Multiple I2C Modules Connected ......................................................................................... 9
3 Clocking Diagram for the I2C Peripheral............................................................................... 10
4 Synchronization of Two I2C Clock Generators During Arbitration .................................................. 11
5 Bit Transfer on the I2C-Bus .............................................................................................. 12
6 I2C Peripheral START and STOP Conditions......................................................................... 12
7 I2C Peripheral Data Transfer ............................................................................................ 13
8 I2C Peripheral 7-Bit Addressing Format (FDF = 0, XA = 0 in ICMDR)............................................. 13
9 I2C Peripheral 10-Bit Addressing Format With Master-Transmitter Writing to Slave-Receiver (FDF = 0,
XA = 1 in ICMDR) ......................................................................................................... 14
10 I2C Peripheral Free Data Format (FDF = 1 in ICMDR) .............................................................. 14
11 I2C Peripheral 7-Bit Addressing Format With Repeated START Condition (FDF = 0, XA = 0 in ICMDR) .... 14
12 Arbitration Procedure Between Two Master-Transmitters ........................................................... 17
13 I2C Own Address Register (ICOAR).................................................................................... 23
14 I2C Interrupt Mask Register (ICIMR).................................................................................... 24
15 I2C Interrupt Status Register (ICSTR).................................................................................. 25
16 I2C Clock Low-Time Divider Register (ICCLKL) ...................................................................... 28
17 I2C Clock High-Time Divider Register (ICCLKH) ..................................................................... 28
18 I2C Data Count Register (ICCNT)....................................................................................... 29
19 I2C Data Receive Register (ICDRR).................................................................................... 30
20 I2C Slave Address Register (ICSAR)................................................................................... 30
21 I2C Data Transmit Register (ICDXR) ................................................................................... 31
22 I2C Mode Register (ICMDR)............................................................................................. 32
23 Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit..................................... 35
24 I2C Interrupt Vector Register (ICIVR)................................................................................... 36
25 I2C Extended Mode Register (ICEMDR)............................................................................... 37
26 I2C Prescaler Register (ICPSC)......................................................................................... 38
27 I2C Peripheral Identification Register 1 (ICPID1) ..................................................................... 39
28 I2C Peripheral Identification Register 2 (ICPID2) ..................................................................... 39
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List of Figures SPRUEN0D–March 2011
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1 Operating Modes of the I2C Peripheral ................................................................................ 15
2 Ways to Generate a NACK Bit........................................................................................... 16
3 Descriptions of the I2C Interrupt Events................................................................................ 21
4 Inter-Integrated Circuit (I2C) Registers ................................................................................. 22
5 I2C Own Address Register (ICOAR) Field Descriptions ............................................................. 23
6 I2C Interrupt Mask Register (ICIMR) Field Descriptions ............................................................. 24
7 I2C Interrupt Status Register (ICSTR) Field Descriptions............................................................ 25
8 I2C Clock Low-Time Divider Register (ICCLKL) Field Descriptions ................................................ 28
9 I2C Clock High-Time Divider Register (ICCLKH) Field Descriptions ............................................... 28
10 I2C Data Count Register (ICCNT) Field Descriptions ................................................................ 29
11 I2C Data Receive Register (ICDRR) Field Descriptions ............................................................. 30
12 I2C Slave Address Register (ICSAR) Field Descriptions ............................................................ 30
13 I2C Data Transmit Register (ICDXR) Field Descriptions............................................................. 31
14 I2C Mode Register (ICMDR) Field Descriptions....................................................................... 32
15 Master-Transmitter/Receiver Bus Activity Defined by RM, STT, and STP Bits ................................... 34
16 How the MST and FDF Bits Affect the Role of TRX Bit.............................................................. 35
17 I2C Interrupt Vector Register (ICIVR) Field Descriptions ............................................................ 36
18 I2C Extended Mode Register (ICEMDR) Field Descriptions......................................................... 37
19 I2C Prescaler Register (ICPSC) Field Descriptions................................................................... 38
20 I2C Peripheral Identification Register 1 (ICPID1) Field Descriptions............................................... 39
21 I2C Peripheral Identification Register 2 (ICPID2) Field Descriptions............................................... 39
22 Document Revision History .............................................................................................. 40
List of Tables
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About This Manual
This document describes the inter-integrated circuit (I2C) peripheral in the TMS320C642x Digital Signal
Processor (DSP). The I2C peripheral provides an interface between the DSP and other devices that are
compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by
way of an I2C-bus. The scope of this document assumes that you are familiar with the I2C-bus
specification.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Preface
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Read This First
Related Documentation From Texas Instruments
The following documents describe the TMS320C642x Digital Signal Processor (DSP). Copies of these
documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box
provided at www.ti.com.
The current documentation that describes the C642x DSP, related peripherals, and other technical
collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.
SPRUEM3 — TMS320C642x DSP Peripherals Overview Reference Guide. Provides an overview and
briefly describes the peripherals available on the TMS320C642x Digital Signal Processor (DSP).
SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the
Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The
objective of this document is to indicate differences between the two cores. Functionality in the
devices that is identical is not included.
SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital
signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation
comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of
the C64x DSP with added functionality and an expanded instruction set.
SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access
(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth
management, and the memory and cache.
6
Preface SPRUEN0D–March 2011
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1 Introduction
This document describes the operation of the inter-integrated circuit (I2C) peripheral in the TMS320C642x
Digital Signal Processor (DSP). The scope of this document assumes that you are familiar with the Philips
Semiconductors Inter-IC bus (I2C-bus) specification version 2.1.
1.1 Purpose of the Peripheral
The I2C peripheral provides an interface between the TMS320C642x DSP and other devices that are
compliant with the I2C-bus specification and connected by way of an I2C-bus. External components that
are attached to this two-wire serial bus can transmit and receive data that is up to eight bits wide both to
and from the DSP through the I2C peripheral.
1.2 Features
The I2C peripheral has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for byte format transfer
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers mode
– Support for multiple slave-transmitters and master-receivers mode
– Combined master transmit/receive and receive/transmit mode
– I2C data transfer rate of from 10 kbps up to 400 kbps (Philips I2C rate)
• 2 to 8 bit format transfer
• Free data format mode
• One read DMA event and one write DMA event that the DMA can use
• Seven interrupts that the CPU can use
• Peripheral enable/disable capability
User's Guide
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Inter-Integrated Circuit (I2C) Peripheral
1.2.1 Features Not Supported
• High-speed mode
• CBUS-compatibility mode
• The combined format in 10-bit addressing mode (the I2C sends the slave address the second byte
every time it sends the slave address the first byte).
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ICXSR ICDXR
ICRSR ICDRR
Clock
synchronizer
Prescaler
Noise filters
Arbitrator
I2C INT
ICREVT
Peripheral data bus
Interrupt
to CPU
Sync events to
EDMA controller
SDA
SCL
Control/status
registers
CPU
EDMA
I2C peripheral
ICXEVT
Introduction
1.3 Functional Block Diagram
A block diagram of the I2C peripheral is shown in Figure 1. Refer to Section 2 for detailed information
about the architecture of the I2C peripheral.
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Figure 1. I2C Peripheral Block Diagram
1.4 Industry Standard(s) Compliance Statement
The I2C peripheral is compliant with the Philips Semiconductors Inter-IC bus (I2C-bus) specification
version 2.1.
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TI device
I2C
I2C
EPROM
I2C
I2C
TI device
V
DD
Pull-up
resistors
Serial data (SDA)
Serial clock (SCL)
controller
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2 Peripheral Architecture
The I2C peripheral consists of the following primary blocks:
• A serial interface: one data pin (SDA) and one clock pin (SCL)
• Data registers to temporarily hold receive data and transmit data traveling between the SDA pin and
the CPU or the EDMA controller
• Control and status registers
• A peripheral data bus interface to enable the CPU and the EDMA controller to access the I2C
peripheral registers
• A clock synchronizer to synchronize the I2C input clock (from the processor clock generator) and the
clock on the SCL pin, and to synchronize data transfers with masters of different clock speeds
• A prescaler to divide down the input clock that is driven to the I2C peripheral
• A noise filter on each of the two pins, SDA and SCL
• An arbitrator to handle arbitration between the I2C peripheral (when it is a master) and another master
• Interrupt generation logic, so that an interrupt can be sent to the CPU
• EDMA event generation logic, so that activity in the EDMA controller can be synchronized to data
reception and data transmission in the I2C peripheral
Figure 1 shows the four registers used for transmission and reception. The CPU or the EDMA controller
writes data for transmission to ICDXR and reads received data from ICDRR. When the I2C peripheral is
configured as a transmitter, data written to ICDXR is copied to ICXSR and shifted out on the SDA pin one
bit a time. When the I2C peripheral is configured as a receiver, received data is shifted into ICRSR and
then copied to ICDRR.
Peripheral Architecture
2.1 Bus Structure
Figure 1 shows how the I2C peripheral is connected to the I2C bus. The I2C bus is a multi-master bus
that supports a multi-master mode. This allows more than one device capable of controlling the bus that is
connected to it. A unique address recognizes each I2C device. Each I2C device can operate as either
transmitter or receiver, depending on the function of the device. Devices that are connected to the I2C bus
can be considered a master or slave when performing data transfers, in addition to being a transmitter or
receiver.
NOTE: A master device is the device that initiates a data transfer on the bus and generates the
clock signals to permit that transfer. Any device that is addressed by this master is
considered a slave during this transfer.
An example of multiple I2C modules that are connected for a two-way transfer from one device to other
devices is shown in Figure 2.
Figure 2. Multiple I2C Modules Connected
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d
7
6
5
PLL1
I2C
prescaler
Prescaled module clock
−−MUST be set to 6.7 to 13.3 MHz
I2C input clock
External
input clock
Register bits
(ICPSC[IPSC])
I2C clock
dividers
Register bits
(ICCLKL[ICCL]),
(ICCLKH[ICCH])
Prescaled module clock frequency =
I2C input clock frequency
(IPSC + 1)
I2C module
I2C serial clock on SCL pin
To I2C bus
I2C serial clock frequency =
prescaled module clock frequency
(ICCL + d) + (ICCH + d)
Where d depends on IPSC value in ICPSC:
IPSC value
0
1
2h−FFh
Peripheral Architecture
2.2 Clock Generation
As shown in Figure 3, PLL1 receives a signal from an external clock source and produces an I2C input
clock. A programmable prescaler (IPSC bit in ICPSC) in the I2C module divides down the I2C input clock
to produce a prescaled module clock. The prescaled module clock must be operated within the range of
6.7 to 13.3 MHz. The I2C clock dividers divide-down the high (ICCH bit in ICCLKH) and low portions
(ICCL bit in ICCLKL) of the prescaled module clock signal to produce the I2C serial clock, which appears
on the SCL pin when the I2C module is configured to be a master on the I2C bus.
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Figure 3. Clocking Diagram for the I2C Peripheral
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CAUTION
Prescaled Module Clock Frequency Range:
The I2C module must be operated with a prescaled module clock frequency of
6.7 to 13.3 MHz. The I2C prescaler register (ICPSC) must be configured to this
frequency range.
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Wait
state
Start HIGH
period
SCL from
device #1
SCL from
device #2
Bus line
SCL
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The prescaler (IPSC bit in ICPSC) must only be initialized while the I2C module is in the reset state
(IRS = 0 in ICMDR). The prescaled frequency only takes effect when the IRS bit in ICMDR is changed to
1. Changing the IPSC bit in ICPSC while IRS = 1 in ICMDR has no effect. Likewise, you must configure
the I2C clock dividers (ICCH bit in ICCLKH and ICCL bit in ICCLKL) while the I2C module is still in reset
(IRS = 0 in ICMDR).
2.3 Clock Synchronization
Only one master device generates the clock signal (SCL) under normal conditions. However, there are
two or more masters during the arbitration procedure; and, you must synchronize the clock so that you
can compare the data output. Figure 4 illustrates the clock synchronization. The wired-AND property of
SCL means that a device that first generates a low period on SCL (device #1) overrules the other devices.
At this high-to-low transition, the clock generators of the other devices are forced to start their own low
period. The SCL is held low by the device with the longest low period. The other devices that finish their
low periods must wait for SCL to be released before starting their high periods. A synchronized signal on
SCL is obtained, where the slowest device determines the length of the low period and the fastest device
determines the length of the high period.
If a device pulls down the clock line for a longer time, the result is that all clock generators must enter the
wait state. This way, a slave slows down a fast master and the slow device creates enough time to store a
received data word or to prepare a data word that you are going to transmit.
Figure 4. Synchronization of Two I2C Clock Generators During Arbitration
Peripheral Architecture
2.4 Signal Descriptions
The I2C peripheral has a serial data pin (SDA) and a serial clock pin (SCL) for data communication, as
shown in Figure 1. These two pins carry information between the C642x device and other devices that are
connected to the I2C-bus. The SDA and SCL pins both are bi-directional. They each must be connected to
a positive supply voltage using a pull-up resistor. When the bus is free, both pins are high. The driver of
these two pins has an open-drain configuration to perform the required wired-AND function.
See the device-specific data manual for additional timing and electrical specifications for these pins.
2.4.1 Input and Output Voltage Levels
The master device generates one clock pulse for each data bit that is transferred. Due to a variety of
different technology devices that can be connected to the I2C-bus, the levels of logic 0 (low) and logic 1
(high) are not fixed and depend on the associated power supply level. See the device-specific data
manual for more information.
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Data line
stable data
Change of data
allowed
SDA
SCL
SDA
SCL
START
condition (S)
condition (P)
STOP
Peripheral Architecture
2.4.2 Data Validity
The data on SDA must be stable during the high period of the clock (see Figure 5). The high or low state
of the data line, SDA, can change only when the clock signal on SCL is low.
Figure 5. Bit Transfer on the I2C-Bus
2.5 START and STOP Conditions
The I2C peripheral can generate START and STOP conditions when the peripheral is configured to be a
master on the I2C-bus, as shown in Figure 6:
• The START condition is defined as a high-to-low transition on the SDA line while SCL is high. A
master drives this condition to indicate the start of a data transfer.
• The STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. A master
drives this condition to indicate the end of a data transfer.
The I2C-bus is considered busy after a START condition and before a subsequent STOP condition. The
bus busy (BB) bit of ICSTR is 1. The bus is considered free between a STOP condition and the next
START condition. The BB is 0.
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The master mode (MST) bit and the START condition (STT) bit in ICMDR must both be 1 for the I2C
peripheral to start a data transfer with a START condition. The STOP condition (STP) bit must be set to 1
for the I2C peripheral to end a data transfer with a STOP condition. A repeated START condition
generates when BB is set to 1 and STT is also set to 1. See Section 3.9 for a description of ICMDR
(including the MST, STT, and STP bits).
Figure 6. I2C Peripheral START and STOP Conditions
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SDA
SCL
MSB
Acknowledgement
bit from slave
(No-)Acknowledgement
bit from receiver
1 2 7 8 9 1 2 8 9
Slave address
ACK
START
condition (S)
STOP
condition (P)
R/W ACK
Data
S Slave address R/W ACK Data ACK Data ACK P
7 n n
1 1 1 1 1 1
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2.6 Serial Data Formats
Figure 7 shows an example of a data transfer on the I2C-bus. The I2C peripheral supports 1-bit to 8-bit
data values. Figure 7 is shown in an 8-bit data format (BC = 000 in ICMDR). Each bit put on the SDA line
is equivalent to one pulse on the SCL line. The data is always transferred with the most-significant bit
(MSB) first. The number of data values that can be transmitted or received is unrestricted; however, the
transmitters and receivers must agree on the number of data values being transferred.
The I2C peripheral supports the following data formats:
• 7-bit addressing mode
• 10-bit addressing mode
• Free data format mode
Peripheral Architecture
Figure 7. I2C Peripheral Data Transfer
2.6.1 7-Bit Addressing Format
In the 7-bit addressing format (Figure 8), the first byte after a START condition (S) consists of a 7-bit slave
address followed by a R/W bit. The R/W bit determines the direction of the data.
• R/W = 0: The master writes (transmits) data to the addressed slave.
• R/W = 1: The master reads (receives) data from the slave.
An extra clock cycle dedicated for acknowledgment (ACK) is inserted after the R/W bit. If the slave inserts
the ACK bit, n bits of data from the transmitter (master or slave, depending on the R/W bit) follow it. n is a
number from 1 to 8 that the bit count (BC) bits of ICMDR determine. The receiver inserts an ACK bit after
the data bits have been transferred.
Write a 0 to the expanded address enable (XA) bit of ICMDR to select the 7-bit addressing format.
Figure 8. I2C Peripheral 7-Bit Addressing Format (FDF = 0, XA = 0 in ICMDR)
n = The number of data bits (from 1 to 8) specified by the bit count (BC) field of ICM DR.
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