Texas Instruments TMS320C6418 Datasheet
TMS320C6418 Fixed-Point Digital
Signal Processor
Data Manual
Literature Number: SPRS241D
August 2004 − Revised January 2006
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
This page intentionally left blank
Revision History
Revision History
This data manual revision history highlights the technical changes made to the SPRS241C device-specific data
manual to make it a SPRS241D revision.
Scope: Applicable updates to the C64x device family, specifically relating to the TMS320C6418 device, have
been incorporated.
Added the device-specific information supporting the TMS320C6418 silicon revision 1.1 device, which is now in
the production data (PD) stage of development (see ADDS/CHANGES/DELETES).
PAGE(s)
NO.
15 Features, 32−Bit External Memory Interface (EMIF) section:
Changed “1024M−Byte Total Addressable Memory Space” to “512M−Byte Total Addressable Memory Space”
24 Functional Overview, Memory Map Summary, TMS320C6418 Memory Map Summary table:
Updated Table
47 Device Configurations, Device Configuration at Device Reset, section:
Added Note
48 Device Configurations, Device Configuration at Device Reset, C6418 Device Configuration Pins (TOUT1/LENDIAN,
AEA[22:19], TOUT0/HPI_EN
Updated AEA(22:21) Configuration Functional Description for 11 to “EMIFA 8−bit ROM boot”
55 Device Configurations, Device Status Register Description, Device Status (DEVSTAT) Register Selection Bit Descriptions
table:
Updated BOOTMODE1 and BOOTMODE0 Description for 11 to “EMIFA 8−bit ROM boot”
57 Device Configurations, Debugging Considerations section:
Deleted paragraphs and added Note
60 Device Configurations, Terminal Functions, Terminal Functions table, CLOCK/PLL CONFIGURATION section:
OSCV
Changed Description from “Power for crystal oscillator (1.2 V), Do not connect to board power 1.4 V; “ to “Power for crystal
oscillator (1.2 V), Do not connect to board power CVDD; “
61 Device Configurations, Terminal Functions, Terminal Functions table, RESETS, INTERRUPTS, AND GENERAL−PURPOSE
INPUT/OUTPUTS section, NMI Signal Name:
Updated Description
Signal Name:
DD
, HD5, CLKINSEL, and OSC_DIS) table:
ADDS/CHANGES/DELETES
63 Terminal Functions table, EMIFA (32 BIT) − ADDRESS section:
Description for AEA22 to AEA3:
Added Note
Updated AEA(22:3) Description for Boot mode (AEA[21:22]) − 11 to “EMIFA 8−bit ROM boot”
68 Terminal Functions table, Supply Voltage Pins section:
Updated Description for DV
90 Peripherals Detailed Description, IEEE 1149.1 JTAG Compatibility Statement section:
Updated paragraphs for clarity
92 Device Electrical Specifications, Absolute Maximum Ratings Over Operating Case Temperature Range section:
Updated Operating Case Temperature Rance, T
Updated Package Temperature Cycling Number of Cycles from “GTS and ZTS” to “GTS and GTSA”
92 Device Electrical Specifications, Recommended Operating Conditions table:
Updated V
Added V
August 2004 − Revised January 2006 SPRS241D
Maximum voltage during overshoot row
OS,
Minimum voltage during undershoot row
US,
DD
from “−40_C to 105_C” to “0_C to 90_C”
C
3
Revision History
PAGE(s)
NO.
ADDS/CHANGES/DELETES
95 Parameter Measurement Information, AC transient rise/fall time specifications section:
Added AC Transient Specification Rise Time figure
Added AC Transient Specification Fall Time figure
100 Peripheral Electrical Specification, Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for
the EMIFA Module table:
Updated Parameter No. 6 from “t
d(EKIH-EKO2L)”
to “t
d(EKIL-EKO2L)”
Updated Parameter No. 6 from “Delay time, ECLKIN high to AECLKOUT2 low” to Delay time ECLKIN low to AECLKOUT2
low”
100 Peripheral Electrical Specification, AECLKOUT2 Timing for the EMIFA Module figure:
Updated Figure
116 Peripheral Electrical Specifications, Reset Timing section:
Added Note
121, 122 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING section:
Updated McASP Input and Output drawings
4
August 2004 − Revised January 2006SPRS241D
This page intentionally left blank
Revision History
August 2004 − Revised January 2006 SPRS241D
5
Contents
Contents
Section Page
1 Features 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Functional Overview 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 GTS and ZTS BGA Packages (Bottom View) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Description 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Device Characteristics 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Functional Block Diagram 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 CPU (DSP Core) Description 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Memory Map Summary 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1 L2 Architecture Expanded 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Peripheral Register Descriptions 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 EDMA Channel Synchronization Events 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Interrupt Sources and Interrupt Selector 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Signal Groups Description 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Device Configurations 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Device Configuration at Device Reset 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Peripheral Configuration at Device Reset 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Peripheral Selection After Device Reset 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Peripheral Configuration Lock 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Device Status Register Description 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 JTAG ID Register Description 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Multiplexed Pins 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Debugging Considerations 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 Configuration Examples 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Terminal Functions 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Development Support 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 Device Support 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.1 Device and Development-Support Tool Nomenclature 72. . . . . . . . . . . . . . . . . . . . .
3.12.2 Documentation Support 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
August 2004 − Revised January 2006SPRS241D
Contents
Section Page
4 Peripherals Detailed Description (Device-Specific) 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Clock PLL and Oscillator 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Host-Port Interface (HPI) Peripheral 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Multichannel Audio Serial Port (McASP) Peripheral 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1 McASP Block Diagram 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 I2C 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Viterbi-Decoder Coprocessor (VCP) 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 General-Purpose Input/Output (GPIO) 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Power-Down Modes Logic 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.1 Triggering, Wake-up, and Effects 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7.2 C64x Power-Down Mode with an Emulator 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Power-Supply Sequencing 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8.1 Power-Supply Design Considerations 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Power-Supply Decoupling 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Peripheral Power-Down Operation 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 IEEE 1149.1 JTAG Compatibility Statement 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 EMIF Device Speed 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13 Bootmode 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Reset 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Device Electrical Specifications 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Absolute Maximum Ratings Over Operating Case Temperature Range 92. . . . . . . . . . . . . . . . . .
5.2 Recommended Operating Conditions 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Case Temperature 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Recommended Clock and Control Signal Transition Behavior 93. . . . . . . . . . . . . . . . . . . . . . . . . .
6 Parameter Information 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Signal Transition Levels 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Signal Transition Rates 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 AC transient rise/fall time specifications 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Timing Parameters and Board Routing Analysis 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
August 2004 − Revised January 2006 SPRS241D
7
Contents
Section Page
7 Peripheral Electrical Specifications 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Input and Output Clocks 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2 Asynchronous Memory Timing 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Programmable Synchronous Interface Timing 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 Synchronous DRAM Timing 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 HOLD
/HOLDA Timing 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 BUSREQ Timing 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7 Reset Timing 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8 External Interrupt Timing 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9 Multichannel Audio Serial Port (McASP) Timing 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.10 Inter-Integrated Circuits (I2C) Timing 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.11 Host-Port Interface (HPI) Timing 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12 Multichannel Buffered Serial Port (McBSP) Timing 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13 Timer Timing 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14 General-Purpose Input/Output (GPIO) Port Timing 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.15 JTAG Test-Port Timing 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Mechanical Data 140. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 Thermal Data 140. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Packaging Information 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
August 2004 − Revised January 2006SPRS241D
Figures
List of Figures
Figure Page
2−1 GTS and ZTS BGA Packages (Bottom View) 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 Functional Block Diagram 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 TMS320C64xE CPU (DSP Core) Data Paths 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 TMS320C6418 L2 Architecture Memory Configuration 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 CPU and Peripheral Signals 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Peripheral Signals 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000] 50. . . . . . . . . . . . . . . . . .
3−2 Peripheral Enable/Disable Flow Diagram 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] − Read/Write Accesses 53. . . . . . . .
3−4 Device Status Register (DEVSTAT) Description − 0x01B3 F004 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 JTAG ID Register Description − TMS320C6418 Register Value − 0x0007 902F 55. . . . . . . . . . . . . . . . . .
3−6 Configuration Example A
(HPI16 + 2 McASPs + 2 McBSPs +2 I2Cs + EMIF + 3 Timers + GPIO) 58. . . . . . . . . . . . . . . . . . . . . . . .
3−7 TMS320C6418 DSP Device Nomenclature 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode 76. . . . . . . . . . . . . . . . . . . . . .
4−2 McASP0 and McASP1 Configuration 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 I2Cx Module Block Diagram 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 GPIO Enable Register (GPEN) [Hex Address: 01B0 0000] 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004] 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 Power-Down Mode Logic 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 PWRD Field of the CSR Register 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 Schottky Diode Diagram 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 Test Load Circuit for AC Timing Measurements 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2 Input and Output Voltage Reference Levels for AC Timing Measurements 94. . . . . . . . . . . . . . . . . . . . . .
6−3 Rise and Fall Transition Time Voltage Reference Levels 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−6 Board-Level Input/Output Timings 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−1 CLKIN Timing 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−2 CLKOUT4 Timing 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−3 CLKOUT6 Timing 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−4 AECLKIN Timing for EMIFA 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−5 AECLKOUT1 Timing for the EMIFA Module 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−6 AECLKOUT2 Timing for the EMIFA Module 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−7 Asynchronous Memory Read Timing for EMIFA 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−8 Asynchronous Memory Write Timing for EMIFA 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−9 Programmable Synchronous Interface Read Timing for EMIFA
(With Read Latency = 2) 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−10 Programmable Synchronous Interface Write Timing for EMIFA
(With Write Latency = 0) 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−11 Programmable Synchronous Interface Write Timing for EMIFA
(With Write Latency = 1) 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−12 SDRAM Read Command (CAS Latency 3) for EMIFA 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
August 2004 − Revised January 2006 SPRS241D
9
Figures
Figure Page
7−13 SDRAM Write Command for EMIFA 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−14 SDRAM ACTV Command for EMIFA 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−15 SDRAM DCAB Command for EMIFA 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−16 SDRAM DEAC Command for EMIFA 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−17 SDRAM REFR Command for EMIFA 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−18 SDRAM MRS Command for EMIFA 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−19 SDRAM Self-Refresh Timing for EMIFA 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−20 HOLD/HOLDA Timing for EMIFA 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−21 BUSREQ Timing for EMIFA 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−22 Reset Timing† 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−23 External/NMI Interrupt Timing 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−28 I2C Receive Timings 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−29 I2C Transmit Timings 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−30 HPI16 Read Timing (HAS Not Used, Tied High) 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−31 HPI16 Read Timing (HAS Used) 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−32 HPI16 Write Timing (HAS Not Used, Tied High) 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−33 HPI16 Write Timing (HAS Used) 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−34 HPI32 Read Timing (HAS Not Used, Tied High) 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−35 HPI32 Read Timing (HAS Used) 128. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−36 HPI32 Write Timing (HAS Not Used, Tied High) 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−37 HPI32 Write Timing (HAS Used) 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−38 McBSP Timing 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−39 FSR Timing When GSYNC = 1 132
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−40 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 133. . . . . . . . . . . . . . . . . . . . . . . . . .
7−41 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 134. . . . . . . . . . . . . . . . . . . . . . . . . .
7−42 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 135. . . . . . . . . . . . . . . . . . . . . . . . . .
7−43 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 136. . . . . . . . . . . . . . . . . . . . . . . . . .
7−44 Timer Timing 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−45 GPIO Port Timing 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−46 JTAG Test-Port Timing 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
August 2004 − Revised January 2006SPRS241D
Tables
List of Tables
Table Page
2−1 Characteristics of the C6418 Processor 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 TMS320C6418 Memory Map Summary 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 EMIFA Registers 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 L2 Cache Registers (C64x) 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 Quick DMA (QDMA) and Pseudo Registers 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 EDMA Registers (C64x) 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 EDMA Parameter RAM (C64x)† 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 Interrupt Selector Registers (C64x) 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 Device Configuration Registers 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 McBSP 0 Registers 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 McBSP 1 Registers 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−12 Timer 0 Registers 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−13 Timer 1 Registers 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−14 Timer 2 Registers 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−15 HPI Registers 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−16 GP0 Registers 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−17 McASP0 and McASP1 Control Registers 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−18 McASP0 Data Registers 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−19 McASP1 Data Registers 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−20 I2C0 and I2C1 Registers 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−21 VCP Registers 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−22 TMS320C6418 EDMA Channel Synchronization Events 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−23 C6418 DSP Interrupts 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 C6418 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], TOUT0/HPI_EN,
HD5, CLKINSEL, and OSC_DIS) 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 TOUT0/HPI_EN and HD5 Peripheral Selection (HPI or McASP1 and Select GP0 Pins) 49. . . . . . . . . . .
3−3 Peripheral Configuration (PERCFG) Register Selection Bit Descriptions 51. . . . . . . . . . . . . . . . . . . . . . .
3−4 PCFGLOCK Register Selection Bit Descriptions − Read Accesses 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 PCFGLOCK Register Selection Bit Descriptions − Write Accesses 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Device Status (DEVSTAT) Register Selection Bit Descriptions 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 JTAG ID Register Selection Bit Descriptions 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 C6418 Device Multiplexed Pins 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 Terminal Functions 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 TMS320C6418 PLL Multiply Factor Options, Clock Frequency Ranges,
and Typical Lock Time for −600 Devices 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 TMS320C6418 PLL Multiply Factor Options, Clock Frequency Ranges,
and Typical Lock Time for −500 Devices 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 Crystal and Tank Circuit Recommendations 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 Characteristics of the Power-Down Modes 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 Board-Level Timing Example 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−1 Timing Requirements for External Crystal Oscillator Input (OSCIN and OSCOUT) 97. . . . . . . . . . . . . . .
7−2 Timing Requirements for CLKIN 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−3 Switching Characteristics Over Recommended Operating Conditions for CLKOUT4 98. . . . . . . . . . . . . .
7−4 Switching Characteristics Over Recommended Operating Conditions for CLKOUT6 98. . . . . . . . . . . . . .
7−5 Timing Requirements for AECLKIN for EMIFA 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−6 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for
the EMIFA Module 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
August 2004 − Revised January 2006 SPRS241D
11
Tables
Table Page
7−7 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2
for the EMIFA Module 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−8 Timing Requirements for Asynchronous Memory Cycles for EMIFA Module 101. . . . . . . . . . . . . . . . . . . .
7−9 Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−10 Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module 104. . . . . . .
7−11 Switching Characteristics Over Recommended Operating Conditions for Programmable
Synchronous Interface Cycles for EMIFA Module 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−12 Timing Requirements for Synchronous DRAM Cycles for EMIFA Module 108. . . . . . . . . . . . . . . . . . . . . .
7−13 Switching Characteristics Over Recommended Operating Conditions for Synchronous
DRAM Cycles for EMIFA Module 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−14 Timing Requirements for the HOLD
/HOLDA Cycles for EMIFA Module 114. . . . . . . . . . . . . . . . . . . . . . . .
7−15 Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
Cycles for EMIFA Module 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−16 Switching Characteristics Over Recommended Operating Conditions for the BUSREQ
Cycles for EMIFA Module 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−17 Timing Requirements for Reset 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−18 Switching Characteristics Over Recommended Operating Conditions During Reset 117. . . . . . . . . . . . .
7−19 Timing Requirements for External Interrupts 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−20 Timing Requirements for McASP 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−21 Switching Characteristics Over Recommended Operating Conditions for McASP 120. . . . . . . . . . . . . . .
7−22 Timing Requirements for I2C Timings 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−23 Switching Characteristics for I2C Timings 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−24 Timing Requirements for Host-Port Interface Cycles 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−25 Switching Characteristics Over Recommended Operating Conditions During Host-Port
Interface Cycles 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−26 Timing Requirements for McBSP 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−27 Switching Characteristics Over Recommended Operating Conditions for McBSP 131. . . . . . . . . . . . . . .
7−28 Timing Requirements for FSR When GSYNC = 1 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−29 Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 0 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−30 Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 133. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−31 Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 11b, CLKXP = 0 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−32 Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 134. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−33 Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 10b, CLKXP = 1 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−34 Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−35 Timing Requirements for McBSP as SPI Master or Slave:
CLKSTP = 11b, CLKXP = 1 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−36 Switching Characteristics Over Recommended Operating Conditions for McBSP as
SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 136. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−37 Timing Requirements for Timer Inputs 137. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−38 Switching Characteristics Over Recommended Operating Conditions for Timer Outputs 137. . . . . . . . .
7−39 Timing Requirements for GPIO Inputs 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−40 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs 138. . . . . . . . .
7−41 Timing Requirements for JTAG Test Port 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−42 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port 139. . . . . . . .
12
August 2004 − Revised January 2006SPRS241D
Tables
Table Page
8−1 Thermal Resistance Characteristics (S-PBGA Package) [GTS] 140. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8−2 Thermal Resistance Characteristics (S-PBGA Package) [ZTS] 140. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
August 2004 − Revised January 2006 SPRS241D
13
Tables
This page intentionally left blank
14
August 2004 − Revised January 2006SPRS241D
1 Features
D
High-Performance Fixed-Point Digital
Signal Processor (TMS320C6418)
− Commercial Temperature Device
− 1.67-ns Instruction Cycle Time
− 600-MHz Clock Rate
− 4800 MIPS
− Extended Temperature Device
− 2-ns Instruction Cycle Time
− 500-MHz Clock Rate
− 4000 MIPS
− Eight 32-Bit Instructions/Cycle
− Fully Software-Compatible With C64x
D VelociTI.2 Extensions to VelociTI
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x DSP Core
− Eight Highly Independent Functional
Units With VelociTI.2 Extensions:
− Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
− Load-Store Architecture With
Non-Aligned Support
− 64 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
D Instruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− V elociTI.2 Increased Orthogonality
D VelociTI.2 Extensions to VelociTI
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x DSP Core
D Viterbi Decoder Coprocessor (VCP)
− Supports Over 500 7.95-Kbps AMR Voice
Channels
− Programmable Code Parameters
Features
D L1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 4M-Bit (512K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible RAM/Cache Allocation)
D Endianess: Little Endian, Big Endian
D 32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
− 512M-Byte Total Addressable External
Memory Space
D Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
D Host-Port Interface (HPI) [32-/16-Bit]
D Two Multichannel Audio Serial Ports
(McASPs) - with Six Serial Data Pins each
D Two Inter-Integrated Circuit (I
− Additional GPIO Capability
2
C) Buses
D Two Multichannel Buffered Serial Ports
D Three 32-Bit General-Purpose Timers
D Sixteen General-Purpose I/O (GPIO) Pins
D Flexible PLL Clock Generator
D On-Chip Fundamental Oscillator
D IEEE-1149.1 (JTAG
Boundary-Scan-Compatible
†
)
D 288-Pin Ball Grid Array (BGA) Package
(GTS and ZTS Suffixes), 1.0-mm Ball Pitch
D 0.13-µm/6-Level Cu Metal Process (CMOS)
D 3.3-V I/Os, 1.4-V Internal (-600)
D 3.3-V I/Os, 1.2-V Internal (A-500)
VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
August 2004 − Revised January 2006 SPRS241D
15
Functional Overview
2 Functional Overview
2.1 GTS and ZTS BGA Packages (Bottom View)
GTS and ZTS 288-PIN BALL GRID ARRAY (BGA) PACKAGES
(BOTTOM VIEW)
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
21
19
17
15
13
11
5431
2
9
10
876
14
12
18
16
22
20
Figure 2−1. GTS and ZTS BGA Packages (Bottom View)
16
August 2004 − Revised January 2006SPRS241D
2.2 Description
The TMS320C64x DSPs (including the TMS320C6418 device) are the highest-performance fixed-point
DSP generation in the TMS320C6000 DSP platform. The TMS320C6418 (C6418) device is based on the
second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture
(VelociTI.2) developed by Texas Instruments (TI). The high-performance, lower-cost C6418 DSP enables
customers to reduce system costs for telecom, software radio, Digital Terrestrial Television Broadcasting
(DTTB), and digital Broadcast Satellite/Communication Satellite (BS/CS) applications. The C64x is a
code-compatible member of the C6000 DSP platform.
With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C6418
device offers cost-effective solutions to high-performance DSP programming challenges. The C6418 DSP
possesses the operational flexibility of high-speed controllers and the numerical capability of array
processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight
highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)—
with V elociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions
to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI
architecture. The C6418 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of
2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6418
DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar
to the other C6000 DSP platform devices.
The C6418 device has a high-performance embedded coprocessor [Viterbi Decoder Coprocessor (VCP)] that
significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4
can decode over 500 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports
constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating
hard decisions or soft decisions. Communications between the VCP and the CPU are carried out through the
EDMA controller.
Description
The C6418 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The
Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit
2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 4-Mbit memory space that is
shared between program and data space. L2 memory can be configured as mapped memory, cache (up to
256K bytes), or combinations of the two. The peripheral set includes: two multichannel buffered audio serial
ports (McASPs); two inter-integrated circuit bus modules (I2Cs) ; two multichannel buffered serial ports
(McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface
(HPI16/HPI32); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event
generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing
to synchronous and asynchronous memories and peripherals.
Each McASP port supports one transmit and one receive clock zone, with six serial data pins which can be
individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin
from 2 to 32 time slots. The C6418 has sufficient bandwidth to support all six serial data pins transmitting a
192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins
simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I
2
S) format.
In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430
encoded data channels simultaneously , with a single RAM containing the full implementation of user data and
channel status fields.
McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit
for each high-frequency master clock which verifies that the master clock is within a programmed frequency
range.
The I2C ports on the TMS320C6418 allows the DSP to easily control peripheral devices and communicate
with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to
communicate with serial peripheral interface (SPI) mode peripheral devices.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
August 2004 − Revised January 2006 SPRS241D
17
Device Characteristics
Not all peripherals pins
Not all peripherals pins
are available at the
Configuration section).
Voltage
The C6418 has a complete set of development tools which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows debugger interface for visibility into source code
execution.
2.3 Device Characteristics
Table 2−1, provides an overview of the C6418 DSP. The tables show significant features of the C6418 device,
including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin
count.
Table 2−1. Characteristics of the C6418 Processor
HARDWARE FEATURES C6418
EMIFA (32-bit bus width)
(clock source = AECLKIN, CLKOUT4, or CLKOUT6)
Peripherals
are available at the
same time (For more
detail, see the Device
Decoder Coprocessor VCP (clock source = CPU/2 clock frequency) 1
On-Chip Memory
CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x0C01
JTAG BSDL_ID JTAGID register (address location: 0x01B3F008) 0x0007902F
Frequency MHz
Cycle Time ns
Voltage
PLL Options CLKIN frequency multiplier
BGA Package 23 x 23 mm 288-Pin Flip-Chip Plastic BGA (GTS and ZTS)
Process Technology µm 0.13 µm
Product Status
†
On this C64x device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device
speed portion of this data sheet.
‡
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
‡
EDMA (64 independent channels) 1
McASPs (use Peripheral Clock and AUXCLK) 2
I2Cs (use Peripheral Clock) 2
HPI (32- or 16-bit user selectable) 1 (HPI16 or HPI32)
McBSPs
(internal clock source = CPU/4 clock frequency)
32-Bit Timers
(internal clock source = CPU/8 clock frequency)
General-Purpose Input/Output Port (GP0) 16
Size (Bytes) 544K
16K-Byte (16KB) L1 Program (L1P) Cache
Organization
Core (V)
I/O (V) 3.3 V
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
16KB L1 Data (L1D) Cache
512KB Unified Mapped RAM/Cache (L2)
500 (GTSA, ZTSA)
1.67 ns (GTS, ZTS)
[600 MHz CPU, 133 MHz EMIF†]
2 ns (GTSA, ZTSA)
[500 MHz CPU, 100 MHz EMIF†]
1.2v (GTSA, ZTSA)
Bypass (x1), x5, x6, x7, x8, x9, x10, x11, x12, x16,
x18, x19, x20, x21, x22, and x24
1
2
3
600 (GTS, ZTS)
1.4 V (GTS, ZTS)
PD
18
August 2004 − Revised January 2006SPRS241D
2.3.1 Functional Block Diagram
Figure 2−2 shows the functional block diagram of the C6418 device.
Functional Block Diagram
SDRAM
SBSRAM
ZBT SRAM
FIFO
SRAM
ROM/FLASH
I/O Devices
32
EMIF A
VCP
L1P Cache
Direct-Mapped
16K Bytes Total
TMS320C6418
Timer 2
Timer 1
Timer 0
McBSP0
McBSP1
Instruction Fetch
Instruction Dispatch
Advanced Instruction Packet
Instruction Decode
Data Path A
A Register File
A31−A16
A15−A0
C64x DSP Core
Data Path B
B Register File
B31−B16
B15−B0
Control
Registers
Control
Logic
Test
Advanced
In-Circuit
Emulation
McASP0
Interrupt
Control
McASP1
and
HPI16
Enhanced
DMA
Controller
(edma)
.L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2
L2
Cache
Memory
512kBytes
L1D Cache 2-Way Set-Associative
16K Bytes Total
or
HPI32
I2C0
I2C1
16
16
†
McBSPs: Framing Chips − H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs
‡
GP0[15:8] pins are muxed with the HPI HD[15:8] pins and GP0[2:1] pins are muxed with CLKOUT6 and CLKOUT4,
GP0
GP0
‡
OSCILLATOR
and PLL
(x1, x5 − x12, x16,
x18, x19 − x22, x24)
Boot Configuration
Power-Down
Logic
respectively.
Figure 2−2. Functional Block Diagram
August 2004 − Revised January 2006 SPRS241D
19
CPU (DSP Core) Description
2.4 CPU (DSP Core) Description
The CPU fetches VelociTI advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to
eight 32-bit instructions to the eight functional units during every clock cycle. The V elociTI VLIW architecture
features controls by which all eight units do not have to be supplied with instructions if they are not ready to
execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute
packet as the previous instruction, or whether it should be executed in the following clock as a part of the next
execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other
VLIW architectures. The C64x VelociTI.2 extensions add enhancements to the TMS320C62x DSP
VelociTI architecture. These enhancements include:
• Register file enhancements
• Data path extensions
• Quad 8-bit and dual 16-bit extensions with data flow enhancements
• Additional functional unit hardware
• Increased orthogonality of the instruction set
• Additional instructions that reduce code size and increase register flexibility
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register
files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the
packed 16-bit and 32-/40-bit fixed-point data types found in the C62x VelociTI VLIW architecture, the
C64x register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional
units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP
core) diagram, and Figure 2−3]. The four functional units on each side of the CPU can freely share the 32
registers belonging to that side. Additionally, each side features a “data cross path”—a single data bus
connected to all the registers on the other side, by which the two sets of functional units can access data from
the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock
cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in
the same execute packet. All functional units in the C64x CPU can access operands via the data cross path.
Register access by functional units on the same side of the CPU as the register file can service all the units
in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read
a register via a data cross path if that register was updated in the previous clock cycle.
In addition to the C62x DSP fixed-point instructions, the C64x DSP includes a comprehensive collection
of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2 extensions allow the C64x CPU
to operate directly on packed data to streamline data flow and increase instruction set efficiency.
Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file.
The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single
instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits)
with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access
words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes
using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most
can access any one of the 64 registers. Some registers, however, are singled out to support specific
addressing modes or to hold the condition for conditional instructions (if the condition is not automatically
“true”).
TMS320C62x and C62x are trademarks of Texas Instruments.
20
August 2004 − Revised January 2006SPRS241D
CPU (DSP Core) Description
The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two
16 × 16-bit multiplies or four 8 × 8-bit multiplies per clock cycle. The .M unit can also perform 16 × 32-bit multiply
operations, dual 16 × 16-bit multiplies with add/subtract operations, and quad 8 × 8-bit multiplies with add
operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies,
and bidirectional variable shift hardware.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual
16-bit, and quad 8-bit operations.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. A C64x DSP device enhancement
now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x/TMS320C67x DSP
devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in
the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the
C64x DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the
NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute
packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective
functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the
execute packets from the current fetch packet have been dispatched. After decoding, the instructions
simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock
cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes,
half-words, or doublewords. All load and store instructions are byte-, half-word-, word-, or
doubleword-addressable.
For more details on the C64x CPU functional units enhancements, see the following documents:
• TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189)
• TMS320C64x Technical Overview (literature number SPRU395)
TMS320C67x is a trademark of Texas Instruments.
August 2004 − Revised January 2006 SPRS241D
21
CPU (DSP Core) Description
ST1b (Store Data)
ST1a (Store Data)
Data Path A
LD1b (Load Data)
LD1a (Load Data)
DA1 (Address)
32 MSBs
32 LSBs
32 MSBs
32 LSBs
src1
.L1
src2
long dst
long src
long src
long dst
src1
.S1
src2
long dst
long dst
src1
.M1
src2
src2
src1
.D1
src2
dst
dst
dst
dst
dst
8
8
8
8
Register
File A
(A0−A31)
See Note A
See Note A
2X
Data Path B
DA2 (Address)
LD2a (Load Data)
LD2b (Load Data)
ST2a (Store Data)
ST2b (Store Data)
32 LSBs
32 MSBs
32 MSBs
32 LSBs
src2
.D2
src1
src2
src1
.M2
long dst
src2
.S2
src1
long dst
long src
long src
long dst
src2
.L2
src1
dst
dst
dst
dst
1X
See Note A
See Note A
Register
File B
(B0− B31)
8
8
8
8
Control Register
File
NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs.
Figure 2−3. TMS320C64x CPU (DSP Core) Data Paths
22
August 2004 − Revised January 2006SPRS241D
2.5 Memory Map Summary
Table 2−2 shows the memory map address ranges of the C6418 device. Internal memory is always located
at address 0 and can be used as both program and data memory. The external memory address ranges in
the C6418 device begin at the hex address location 0x8000 0000 for EMIFA.
Table 2−2. TMS320C6418 Memory Map Summary
Memory Map Summary
MEMORY BLOCK DESCRIPTION
Internal RAM (L2) [C6418] 512K
Reserved [C6418] 512K
Reserved 15M
Reserved 8M
External Memory Interface A (EMIFA) Registers 256K
L2 Registers 256K
HPI Registers 256K
McBSP 0 Registers 256K
McBSP 1 Registers 256K
Timer 0 Registers 256K
Timer 1 Registers 256K
Interrupt Selector Registers 256K
EDMA RAM and EDMA Registers 256K
Reserved 512K
Timer 2 Registers 256K
GP0 Registers 256K minus 4K
Device Configuration Registers 4K
I2C0 Data and Control Registers 16K
I2C1 Data and Control Registers 16K
Reserved 16K
McASP0 Control Registers 16K
McASP1 Control Registers 16K
Reserved 176K
VCP Control Registers 128K
Reserved 128K
Emulation 256K
Reserved 528K
Reserved 3.5M
QDMA Registers 52
Reserved 928M minus 52
McBSP 0 Data 64M
McBSP 1 Data 64M
Reserved 64M
McASP0 Data 1M
McASP1 Data 1M
Reserved 62M
BLOCK SIZE
(BYTES)
HEX ADDRESS RANGE
0000 0000 – 0007 FFFF
0008 0000 – 000F FFFF
0010 0000 – 00FF FFFF
0100 0000 – 017F FFFF
0180 0000 – 0183 FFFF
0184 0000 – 0187 FFFF
0188 0000 – 018B FFFF
018C 0000 – 018F FFFF
0190 0000 – 0193 FFFF
0194 0000 – 0197 FFFF
0198 0000 – 019B FFFF
019C 0000 – 019F FFFF
01A0 0000 – 01A3 FFFF
01A4 0000 – 01AB FFFF
01AC 0000 – 01AF FFFF
01B0 0000 – 01B3 EFFF
01B3 F000 – 01B3 FFFF
01B4 0000 – 01B4 3FFF
01B4 4000 – 01B4 7FFF
01B4 8000 – 01B4 BFFF
01B4 C000 – 01B4 FFFF
01B5 0000 – 01B5 3FFF
01B5 4000 – 01B7 FFFF
01B8 0000 – 01B9 FFFF
01BA 0000 – 01BB FFFF
01BC 0000 – 01BF FFFF
01C0 0000 – 01C8 3FFF
01C8 4000 – 01FF FFFF
0200 0000 – 0200 0033
0200 0034 – 2FFF FFFF
3000 0000 – 33FF FFFF
3400 0000 – 37FF FFFF
3800 0000 – 3BFF FFFF
3C00 0000 – 3C0F FFFF
3C10 0000 – 3C1F FFFF
3C20 0000 – 3FFF FFFF
August 2004 − Revised January 2006 SPRS241D
23
Memory Map Summary
Table 2−2. TMS320C6418 Memory Map Summary (Continued)
MEMORY BLOCK DESCRIPTION HEX ADDRESS RANGE
Reserved 1G
EMIFA CE0 128M
Reserved 128M
EMIFA CE1 128M
Reserved 128M
EMIFA CE2 128M
Reserved 128M
EMIFA CE3 128M
Reserved 128M
Reserved 1G
BLOCK SIZE
(BYTES)
4000 0000 – 7FFF FFFF
8000 0000 – 87FF FFFF
8800 0000 – 8FFF FFFF
9000 0000 – 97FF FFFF
9800 0000 – 9FFF FFFF
A000 0000 – A7FF FFFF
A800 0000 – AFFF FFFF
B000 0000 – B7FF FFFF
B800 0000 – BFFF FFFF
C000 0000 – FFFF FFFF
24
August 2004 − Revised January 2006SPRS241D
2.5.1 L2 Architecture Expanded
Figure 2−4 shows the detail of the L2 architecture on the TMS320C6418 device. For more information on the
L2MODE bits, see the cache configuration (CCFG) register bit field descriptions in the TMS320C64x
Two-Level Internal Memory Reference Guide (literature number SPRU610).
L2MODE L2 Memory Block Base Address
Memory Map Summary
000
512K SRAM (All)
480K SRAM
011010001 111
448K SRAM
384K SRAM
256K SRAM
256K-Byte SRAM
128K-Byte RAM
0x0000 0000
0x0003 FFFF
0x0004 0000
0x0005 FFFF
0x0006 0000
64K-Byte RAM
32K-Byte RAM
32K-Byte RAM
0x0006 FFFF
0x0007 0000
0x0007 7FFF
0x0007 8000
0x0007 FFFF
64K Cache
(4 Way)
32K Cache
(4 Way)
256K Cache (4 Way)
128K Cache (4 Way)
Figure 2−4. TMS320C6418 L2 Architecture Memory Configuration
August 2004 − Revised January 2006 SPRS241D
25
Peripheral Register Descriptions
2.6 Peripheral Register Descriptions
Table 2−3 through Table 2−21 identify the peripheral registers for the C6418 device by their register names,
acronyms, and hex address or hex address range. For more detailed information on the register contents, bit
names and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP
Peripherals Overview Reference Guide (literature number SPRU190).
Table 2−3. EMIFA Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0180 0000 GBLCTL EMIFA global control
0180 0004 CECTL1 EMIFA CE1 space control
0180 0008 CECTL0 EMIFA CE0 space control
0180 000C − Reserved
0180 0010 CECTL2 EMIFA CE2 space control
0180 0014 CECTL3 EMIFA CE3 space control
0180 0018 SDCTL EMIFA SDRAM control
0180 001C SDTIM EMIFA SDRAM refresh control
0180 0020 SDEXT EMIFA SDRAM extension
0180 0024 − 0180 003C − Reserved
0180 0040 PDTCTL Peripheral device transfer (PDT) control
0180 0044 CESEC1 EMIFA CE1 space secondary control
0180 0048 CESEC0 EMIFA CE0 space secondary control
0180 004C − Reserved
0180 0050 CESEC2 EMIFA CE2 space secondary control
0180 0054 CESEC3 EMIFA CE3 space secondary control
0180 0058 − 0183 FFFF – Reserved
Table 2−4. L2 Cache Registers (C64x)
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
0184 0000 CCFG Cache configuration register
0184 0004 − 0184 0FFC − Reserved
0184 1000 EDMAWEIGHT L2 EDMA access control register
0184 1004 − 0184 1FFC − Reserved
0184 2000 L2ALLOC0 L2 allocation register 0
0184 2004 L2ALLOC1 L2 allocation register 1
0184 2008 L2ALLOC2 L2 allocation register 2
0184 200C L2ALLOC3 L2 allocation register 3
0184 2010 − 0184 3FFC − Reserved
0184 4000 L2WBAR L2 writeback base address register
0184 4004 L2WWC L2 writeback word count register
0184 4010 L2WIBAR L2 writeback invalidate base address register
0184 4014 L2WIWC L2 writeback invalidate word count register
0184 4018 L2IBAR L2 invalidate base address register
0184 401C L2IWC L2 invalidate word count register
0184 4020 L1PIBAR L1P invalidate base address register
0184 4024 L1PIWC L1P invalidate word count register
0184 4030 L1DWIBAR L1D writeback invalidate base address register
26
August 2004 − Revised January 2006SPRS241D
Table 2−4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE COMMENTSREGISTER NAMEACRONYM
0184 4034 L1DWIWC L1D writeback invalidate word count register
0184 4038 − 0184 4044 − Reserved
0184 4048 L1DIBAR L1D invalidate base address register
0184 404C L1DIWC L1D invalidate word count register
0184 4050 − 0184 4FFC − Reserved
0184 5000 L2WB L2 writeback all register
0184 5004 L2WBINV L2 writeback invalidate all register
0184 5008 − 0184 7FFC − Reserved
0184 8000 −0184 81FC
0184 8200 MAR128 Controls EMIFA CE0 range 8000 0000 − 80FF FFFF
0184 8204 MAR129 Controls EMIFA CE0 range 8100 0000 − 81FF FFFF
0184 8208 MAR130 Controls EMIFA CE0 range 8200 0000 − 82FF FFFF
0184 820C MAR131 Controls EMIFA CE0 range 8300 0000 − 83FF FFFF
0184 8210 MAR132 Controls EMIFA CE0 range 8400 0000 − 84FF FFFF
0184 8214 MAR133 Controls EMIFA CE0 range 8500 0000 − 85FF FFFF
0184 8218 MAR134 Controls EMIFA CE0 range 8600 0000 − 86FF FFFF
0184 821C MAR135 Controls EMIFA CE0 range 8700 0000 − 87FF FFFF
0184 8220 MAR136 Controls EMIFA CE0 range 8800 0000 − 88FF FFFF
0184 8224 MAR137 Controls EMIFA CE0 range 8900 0000 − 89FF FFFF
0184 8228 MAR138 Controls EMIFA CE0 range 8A00 0000 − 8AFF FFFF
0184 822C MAR139 Controls EMIFA CE0 range 8B00 0000 − 8BFF FFFF
0184 8230 MAR140 Controls EMIFA CE0 range 8C00 0000 − 8CFF FFFF
0184 8234 MAR141 Controls EMIFA CE0 range 8D00 0000 − 8DFF FFFF
0184 8238 MAR142 Controls EMIFA CE0 range 8E00 0000 − 8EFF FFFF
0184 823C MAR143 Controls EMIFA CE0 range 8F00 0000 − 8FFF FFFF
0184 8240 MAR144 Controls EMIFA CE1 range 9000 0000 − 90FF FFFF
0184 8244 MAR145 Controls EMIFA CE1 range 9100 0000 − 91FF FFFF
0184 8248 MAR146 Controls EMIFA CE1 range 9200 0000 − 92FF FFFF
0184 824C MAR147 Controls EMIFA CE1 range 9300 0000 − 93FF FFFF
0184 8250 MAR148 Controls EMIFA CE1 range 9400 0000 − 94FF FFFF
0184 8254 MAR149 Controls EMIFA CE1 range 9500 0000 − 95FF FFFF
0184 8258 MAR150 Controls EMIFA CE1 range 9600 0000 − 96FF FFFF
0184 825C MAR151 Controls EMIFA CE1 range 9700 0000 − 97FF FFFF
0184 8260 MAR152 Controls EMIFA CE1 range 9800 0000 − 98FF FFFF
0184 8264 MAR153 Controls EMIFA CE1 range 9900 0000 − 99FF FFFF
0184 8268 MAR154 Controls EMIFA CE1 range 9A00 0000 − 9AFF FFFF
0184 826C MAR155 Controls EMIFA CE1 range 9B00 0000 − 9BFF FFFF
0184 8270 MAR156 Controls EMIFA CE1 range 9C00 0000 − 9CFF FFFF
0184 8274 MAR157 Controls EMIFA CE1 range 9D00 0000 − 9DFF FFFF
0184 8278 MAR158 Controls EMIFA CE1 range 9E00 0000 − 9EFF FFFF
0184 827C MAR159 Controls EMIFA CE1 range 9F00 0000 − 9FFF FFFF
0184 8280 MAR160 Controls EMIFA CE2 range A000 0000 − A0FF FFFF
MAR0 to
MAR127
Reserved
Peripheral Register Descriptions
August 2004 − Revised January 2006 SPRS241D
27
Peripheral Register Descriptions
Table 2−4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE COMMENTSREGISTER NAMEACRONYM
0184 8284 MAR161 Controls EMIFA CE2 range A100 0000 − A1FF FFFF
0184 8288 MAR162 Controls EMIFA CE2 range A200 0000 − A2FF FFFF
0184 828C MAR163 Controls EMIFA CE2 range A300 0000 − A3FF FFFF
0184 8290 MAR164 Controls EMIFA CE2 range A400 0000 − A4FF FFFF
0184 8294 MAR165 Controls EMIFA CE2 range A500 0000 − A5FF FFFF
0184 8298 MAR166 Controls EMIFA CE2 range A600 0000 − A6FF FFFF
0184 829C MAR167 Controls EMIFA CE2 range A700 0000 − A7FF FFFF
0184 82A0 MAR168 Controls EMIFA CE2 range A800 0000 − A8FF FFFF
0184 82A4 MAR169 Controls EMIFA CE2 range A900 0000 − A9FF FFFF
0184 82A8 MAR170 Controls EMIFA CE2 range AA00 0000 − AAFF FFFF
0184 82AC MAR171 Controls EMIFA CE2 range AB00 0000 − ABFF FFFF
0184 82B0 MAR172 Controls EMIFA CE2 range AC00 0000 − ACFF FFFF
0184 82B4 MAR173 Controls EMIFA CE2 range AD00 0000 − ADFF FFFF
0184 82B8 MAR174 Controls EMIFA CE2 range AE00 0000 − AEFF FFFF
0184 82BC MAR175 Controls EMIFA CE2 range AF00 0000 − AFFF FFFF
0184 82C0 MAR176 Controls EMIFA CE3 range B000 0000 − B0FF FFFF
0184 82C4 MAR177 Controls EMIFA CE3 range B100 0000 − B1FF FFFF
0184 82C8 MAR178 Controls EMIFA CE3 range B200 0000 − B2FF FFFF
0184 82CC MAR179 Controls EMIFA CE3 range B300 0000 − B3FF FFFF
0184 82D0 MAR180 Controls EMIFA CE3 range B400 0000 − B4FF FFFF
0184 82D4 MAR181 Controls EMIFA CE3 range B500 0000 − B5FF FFFF
0184 82D8 MAR182 Controls EMIFA CE3 range B600 0000 − B6FF FFFF
0184 82DC MAR183 Controls EMIFA CE3 range B700 0000 − B7FF FFFF
0184 82E0 MAR184 Controls EMIFA CE3 range B800 0000 − B8FF FFFF
0184 82E4 MAR185 Controls EMIFA CE3 range B900 0000 − B9FF FFFF
0184 82E8 MAR186 Controls EMIFA CE3 range BA00 0000 − BAFF FFFF
0184 82EC MAR187 Controls EMIFA CE3 range BB00 0000 − BBFF FFFF
0184 82F0 MAR188 Controls EMIFA CE3 range BC00 0000 − BCFF FFFF
0184 82F4 MAR189 Controls EMIFA CE3 range BD00 0000 − BDFF FFFF
0184 82F8 MAR190 Controls EMIFA CE3 range BE00 0000 − BEFF FFFF
0184 82FC MAR191 Controls EMIFA CE3 range BF00 0000 − BFFF FFFF
0184 8300 −0184 83FC
0184 8400 −0187 FFFF − Reserved
MAR192 to
MAR255
Reserved
28
August 2004 − Revised January 2006SPRS241D
Table 2−5. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0200 0000 QOPT QDMA options parameter register
0200 0004 QSRC QDMA source address register
0200 0008 QCNT QDMA frame count register
0200 000C QDST QDMA destination address register
0200 0010 QIDX QDMA index register
0200 0014 − 0200 001C Reserved
0200 0020 QSOPT QDMA pseudo options register
0200 0024 QSSRC QDMA psuedo source address register
0200 0028 QSCNT QDMA psuedo frame count register
0200 002C QSDST QDMA destination address register
0200 0030 QSIDX QDMA psuedo index register
Table 2−6. EDMA Registers (C64x)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01A0 0800 − 01A0 FF98 − Reserved
01A0 FF9C EPRH Event polarity high register
01A0 FFA4 CIPRH Channel interrupt pending high register
01A0 FFA8 CIERH Channel interrupt enable high register
01A0 FFAC CCERH Channel chain enable high register
01A0 FFB0 ERH Event high register
01A0 FFB4 EERH Event enable high register
01A0 FFB8 ECRH Event clear high register
01A0 FFBC ESRH Event set high register
01A0 FFC0 PQAR0 Priority queue allocation register 0
01A0 FFC4 PQAR1 Priority queue allocation register 1
01A0 FFC8 PQAR2 Priority queue allocation register 2
01A0 FFCC PQAR3 Priority queue allocation register 3
01A0 FFDC EPRL Event polarity low register
01A0 FFE0 PQSR Priority queue status register
01A0 FFE4 CIPRL Channel interrupt pending low register
01A0 FFE8 CIERL Channel interrupt enable low register
01A0 FFEC CCERL Channel chain enable low register
01A0 FFF0 ERL Event low register
01A0 FFF4 EERL Event enable low register
01A0 FFF8 ECRL Event clear low register
01A0 FFFC ESRL Event set low register
01A1 0000 − 01A3 FFFF – Reserved
Peripheral Register Descriptions
August 2004 − Revised January 2006 SPRS241D
29
Peripheral Register Descriptions
Table 2−7. EDMA Parameter RAM (C64x)
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
01A0 0000 − 01A0 0017 − Parameters for Event 0 (6 words)
01A0 0018 − 01A0 002F − Parameters for Event 1 (6 words)
01A0 0030 − 01A0 0047 − Parameters for Event 2 (6 words)
01A0 0048 − 01A0 005F − Parameters for Event 3 (6 words)
01A0 0060 − 01A0 0077 − Parameters for Event 4 (6 words)
01A0 0078 − 01A0 008F − Parameters for Event 5 (6 words)
01A0 0090 − 01A0 00A7 − Parameters for Event 6 (6 words)
01A0 00A8 − 01A0 00BF − Parameters for Event 7 (6 words)
01A0 00C0 − 01A0 00D7 − Parameters for Event 8 (6 words)
01A0 00D8 − 01A0 00EF − Parameters for Event 9 (6 words)
01A0 00F0 − 01A0 00107 − Parameters for Event 10 (6 words)
01A0 0108 − 01A0 011F − Parameters for Event 11 (6 words)
01A0 0120 − 01A0 0137 − Parameters for Event 12 (6 words)
01A0 0138 − 01A0 014F − Parameters for Event 13 (6 words)
01A0 0150 − 01A0 0167 − Parameters for Event 14 (6 words)
01A0 0168 − 01A0 017F − Parameters for Event 15 (6 words)
01A0 0150 − 01A0 0197 − Parameters for Event 16 (6 words)
01A0 0168 − 01A0 01AF − Parameters for Event 17 (6 words)
... ...
01A0 05D0 − 01A0 05E7 − Parameters for Event 62 (6 words)
01A0 05E8 − 01A0 05FF − Parameters for Event 63 (6 words)
01A0 0600 − 01A0 0617 − Reload/link parameters for Event 0 (6 words)
01A0 0618 − 01A0 062F − Reload/link parameters for Event 1 (6 words)
... ...
01A0 07E0 − 01A0 07F7 − Reload/link parameters for Event 20 (6 words)
01A0 07F8 − 01A0 080F − Reload/link parameters for Event 21 (6 words)
01A0 0810 − 01A0 0827 − Reload/link parameters for Event 22 (6 words)
... ...
01A0 13C8 − 01A0 13DF − Reload/link parameters for Event 147 (6 words)
01A0 13E0 − 01A0 13F7 − Reload/link parameters for Event 148 (6 words)
01A0 13F8 − 01A0 13FF − Scratch pad area (2 words)
01A0 1400 − 01A3 FFFF − Reserved
†
The C6418 device has 213 EDMA parameters total: 64-Event/Reload channels and 149-Reload only parameter sets [six (6) words each] that
can be used to reload/link EDMA transfers.
†
Parameters for Event 0
(6 words) or Reload/Link
Parameters for other Event
Reload/Link Parameters for
other Event 0−15
30
August 2004 − Revised January 2006SPRS241D
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