Texas instruments TMS320C5505 DATASHEET

TMS320C5505

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TMS320C5505 Fixed-Point Digital Signal Processor

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1 Fixed-Point Digital Signal Processor

1.1 Features

• HIGHLIGHTS:

• High-Perf/Low-Power, C55x™ Fixed-Point DSP – 16.67/13.33/10/8.33/6.66-ns Instruction Cycle

Time

– 60-, 75-, 100-, 120-, 150-MHz Clock Rate

• 320K Bytes On-Chip RAM

• 16-/8-Bit External Memory Interface (EMIF)

• Two MultiMedia Card/Secure Digital I/Fs

• Serial-Port I/F (SPI) With Four Chip-Selects

• Four Inter-IC Sound (I2S Bus™)

• USB 2.0 Full- and High-Speed Device

• LCD Bridge With Asynchronous Interface

• Tightly-Coupled FFT Hardware Accelerator

• 10-Bit 4-Input Successive Approximation (SAR) ADC

• Real-Time Clock (RTC) With Crystal Input

• Four Core Isolated Power Supply Domains

• Four I/O Isolated Power Supply Domains

• One Integrated LDO

• Industrial Temperature Devices Available

• 1.05-V Core, 1.8/2.5/2.75/3.3-V I/Os

• 1.3-V Core, 1.8/2.5/2.75/3.3-V I/Os

• 1.4-V Core, 1.8/2.5/2.75/3.3-V I/Os

• FEATURES:

• High-Performance, Low-Power, TMS320C55x™ Fixed-Point Digital Signal Processor

– 16.67-, 13.33-, 10-, 8.33-, 6.66-ns Instruction

Cycle Time – 60-, 75-, 100-, 120-, 150-MHz Clock Rate – One/Two Instruction(s) Executed per Cycle – Dual Multipliers [Up to 200, 240, or 300

Million Multiply-Accumulates per Second

(MMACS)] – Two Arithmetic/Logic Units (ALUs)

SPRS660B–AUGUST 2010–REVISED AUGUST 2010

– Three Internal Data/Operand Read Buses

and Two Internal Data/Operand Write Buses – Software-Compatible With C55x Devices – Industrial Temperature Devices Available

• 320K Bytes Zero-Wait State On-Chip RAM, Composed of:

– 64K Bytes of Dual-Access RAM (DARAM),

8 Blocks of 4K x 16-Bit

– 256K Bytes of Single-Access RAM (SARAM),

32 Blocks of 4K x 16-Bit

• 128K Bytes of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit)

• 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM)

• 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to:

– 8-/16-Bit NAND Flash, 1- and 4-Bit ECC – 8-/16-Bit NOR Flash – Asynchronous Static RAM (SRAM) – 16-bit SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and

3.3-V)

• Direct Memory Access (DMA) Controller – Four DMA With 4 Channels Each

(16-Channels Total)

• Three 32-Bit General-Purpose Timers – One Selectable as a Watchdog and/or GP

• Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces

• Universal Asynchronous Receiver/Transmitter (UART)

• Serial-Port Interface (SPI) With Four Chip-Selects

• Master/Slave Inter-Integrated Circuit (I2C Bus™)

• Four Inter-IC Sound (I2S Bus™) for Data Transport

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testingof all parameters.

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SPRS660B–AUGUST 2010–REVISED AUGUST 2010

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• Device USB Port With Integrated 2.0 • Up to 26 General-Purpose I/O (GPIO) Pins High-Speed PHY that Supports: (Multiplexed With Other Device Functions)

– USB 2.0 Full- and High-Speed Device • 196-Terminal Pb-Free Plastic BGA (Ball Grid

• LCD Bridge With Asynchronous Interface

• Tightly-Coupled FFT Hardware Accelerator

• 10-Bit 4-Input Successive Approximation (SAR) ADC

• Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain, Separate Power Supply

• Four Core Isolated Power Supply Domains:

Array) (ZCH Suffix)

• 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os

• 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V, or 3.3-V I/Os

• 1.4-V Core (150 MHz), 1.8-V, 2.5-V, 2.75-V or

3.3-V I/Os

• Applications:

Analog, RTC, CPU and Peripherals, and USB – Wireless Audio Devices (e.g., Headsets,

• Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DV

DDIO

Microphones, Speakerphones, etc.)

– Echo Cancellation Headphones

• One integrated LDO (ANA_LDO) to power DSP – Portable Medical Devices PLL (V

DDA_PLL

• Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator

• On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM

• IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible

) and 10-bit SAR ADC (V

DDA_ANA

)

– Voice Applications – Industrial Controls – Fingerprint Biometrics – Software Defined Radio

• Community Resources – TI E2E Community – TI Embedded Processors Wiki

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1.2 Description

The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications.

The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

SPRS660B–AUGUST 2010–REVISED AUGUST 2010

The general-purpose input and output functions along with the 10-bit SAR ADC provide sufficient pins for status, interrupts, and bit I/O for LCD displays, keyboards, and media interfaces. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface.

The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

In addition, the device includes a tightly-coupled FFT Hardware Accelerator. The tightly-coupled FFT Hardware Accelerator supports 8 to 1024-point (in power of 2) real and complex-valued FFTs.

The device includes one integrated LDO (ANA_LDO) to provide regulated 1.3 V to the DSP PLL (V

DDA_PLL

) and 10-bit SAR ADC(V

DDA_ANA

). Note: ANA_LDO can only provide a regulated 1.3 V. When the DSP PLL requires 1.4 V (PLLOUT > 120 MHz), an external supply is required to supply 1.4 V to the DSP PLL (V

DDA_PLL

The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.

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PLL/Clock Generator

Power

Management

Multiplexing

JTAG Interface

64 KB DARAM

256 KB SARAM

128 KB ROM

Switched Central Resource (SCR)

Input

Clock(s)

FFT Hardware

Accelerator

C55x™ DSP CPU

DSP System

LCD

Bridge

Display

I S

(x4)

I C

SPI

UART

Serial Interfaces

10-Bit

SAR ADC

App-Spec

USB 2.0 PHY (HS) [DEVICE]

Connectivity

Peripherals

DMA

(x4)

Interconnect

NAND, NOR,

SRAM,

SDRAM/mSDRAM

Program/Data Storage

MMC/SD

(x2)

System

GP Timer

(x2)

RTC

GP Timer

or WD

LDO

TMS320C5505

SPRS660B–AUGUST 2010–REVISED AUGUST 2010

1.3 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.

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Figure 1-1. Functional Block Diagram

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1 Fixed-Point Digital Signal Processor ............... 1 6 Peripheral Information and Electrical

1.1 Features .............................................. 1

1.2 Description ........................................... 3

1.3 Functional Block Diagram ............................ 4

2 Revision History ......................................... 6

3 Device Overview ........................................ 9

3.1 Device Characteristics ............................... 9

3.2 C55x CPU .......................................... 11

3.3 Memory Map Summary ............................. 15

3.4 Pin Assignments .................................... 16

3.5 Terminal Functions ................................. 17

3.6 Device Support ..................................... 42

4 Device Configuration ................................. 45

4.1 System Registers ................................... 45

4.2 Power Considerations .............................. 46

4.3 Clock Considerations ............................... 47

4.4 Boot Sequence ..................................... 49

4.5 Configurations at Reset ............................ 52

4.6 Configurations After Reset ......................... 52

4.7 Multiplexed Pin Configurations ..................... 55

4.8 Debugging Considerations ......................... 59

5 Device Operating Conditions ....................... 61

5.1 Absolute Maximum Ratings Over Operating Case

Temperature Range (Unless Otherwise Noted) .... 61

5.2 Recommended Operating Conditions .............. 62

5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating

Temperature (Unless Otherwise Noted) ............ 63

Specifications .......................................... 66

6.1 Parameter Information .............................. 66

6.2 Recommended Clock and Control Signal Transition

Behavior ............................................ 66

6.3 Power Supplies ..................................... 67

6.4 External Clock Input From RTC_XI, CLKIN, and

USB_MXI Pins ...................................... 70

6.5 Clock PLLs ......................................... 74

6.6 Direct Memory Access (DMA) Controller ........... 77

6.7 Reset ............................................... 78

6.8 Interrupts and XF ................................... 80

6.9 External Memory Interface (EMIF) ................. 82

6.10 Multimedia Card/Secure Digital (MMC/SD) ........ 97

6.11 Real-Time Clock (RTC) ........................... 102

6.12 Inter-Integrated Circuit (I2C) ...................... 106

6.13 Universal Asynchronous Receiver/Transmitter

(UART) ............................................ 110

6.14 Inter-IC Sound (I2S) ............................... 112

6.15 Liquid Crystal Display Controller (LCDC) ......... 119

6.16 10-Bit SAR ADC ................................... 128

6.17 Serial Port Interface (SPI) ......................... 129

6.18 Universal Serial Bus (USB) 2.0 Controller ........ 132

6.19 General-Purpose Timers .......................... 139

6.20 General-Purpose Input/Output .................... 141

6.21 IEEE 1149.1 JTAG ................................ 145

7 Mechanical Packaging and Orderable

Information ............................................ 147

7.1 Thermal Data for ZCH ............................. 147

7.2 Packaging Information ............................ 147

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2 Revision History

This data manual revision history highlights the technical changes made to the SPRS660A device-specific data manual to make it an SPRS660B revision.

Scope: Applicable updates to the TMS320C5000 device family, specifically relating to the TMS320C5505 device (Silicon Revisions 2.0) which is now in the production data (PD) stage of development have been incorporated.

• 1.4-V Digital Core Voltage Supply at 150 MHz is now supported

SEE ADDITIONS/MODIFICATIONS/DELETIONS

Global

Section 1.1, Features

Section 3.1 Table 3-1, Characteristics of the C5505 Processor:

Device Characteristics

Section 3.5 Table 3-5, Oscillator/PLL Terminal Functions:

Terminal Functions

Section 3.6.2 Figure 3-3, Device Nomenclature:

Device and Development-Support Tool Nomenclature

Section 4.2, Power Section 4.2.1.2, LDO Outputs:

Considerations

Section 4.5.1 Table 4-2, Default Functions Affected by Device Configuration Pins:

Device and Peripheral Configurations at Device Reset

Section 5 Section 5.1, Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted):

Device Operating Conditions

• The device now supports 150 MHz

• Added 1.4-V Digital Core Voltage Supply at 150 MHz

• Added 6.66 ns to Instruction Cycle Time

• Added 150 MHz to Clock Rate

• Added 1.4-V Core, 1.8/2.5/2.75/3.3-V I/Os bullet

• Added 300 MMAC for Dual Multipliers

• Deleted Flash Cards row

• Updated Timers row

• Updated MMC/SD row

• Added 1.4-V Core row to CPU Frequency

• Added 1.4-V Core row to Cycle Time

• Added 1.4-V row to Voltage Core

• Updated Power Characterization to support 1.4 V

• Updated associated footnote

• Updated V

Table 3-19, Regulators and Power Management Terminal Functions:

• Updated DSP_LDOO description

• Updated LDOI description

Table 3-21, Supply Voltage Terminal Functions:

• Added 1.4-V Digital Core supply voltage to CVDDrow

• Updated V

• Updated/Changed figure

• Updated first paragraph

• Updated Note:

• Updated DSP_LDO_EN Functional Description

• Updated Device Operating Life Power-On Hours (POH) row

• Added footnote to Device Operating Life Power-On Hours (POH) row

Section 5.2, Recommended Operating Conditions:

• Added 150 MHz to CVDDrow

• Changed CVDDRTC max value from 1.43 to 1.47 V

• Updated V

• Updated F

• Added "For the device maximum..." footnote

row to reflect 1.4 V addition

DDA_PLL

description

DDA_PLL DDA_ANA

DDA_PLL

SYSCLK

description

row

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SEE ADDITIONS/MODIFICATIONS/DELETIONS

Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating

Temperature (Unless Otherwise Noted):

• Updated I

• Changed Analog PLL (V

• Deleted MAX value for Analog PLL (V

• Changed SAR Analog (V

Core supply current to support 1.4 V

CDD

Analog PLL supply current for to support 1.4 V

CDD

) supply current test condition voltage from 1.37 to 1.3 V

DDA_PLL

DDA_ANA

) supply current test condition voltage from 1.37 to 1.3 V

DDA_PLL

) supply current

Section 6.3 Figure 6-4, 32.768-kHz RTC Oscillator:

Power Supplies

• Updated figure by adding 1.4 V

Figure 6-5, LVCMOS-Compatible Clock Input With RTC Oscillator Enabled:

• Updated figure by adding 1.4 V

Figure 6-6, LVCMOS-Compatible Clock Input With RTC Oscillator Disabled:

• Updated figure by adding 1.4 V

Section 6.3.1, Power-Supply Sequencing:

• Deleted LDOI from first and third paragraphs

Section 6.4

External Clock Input From

• Updated first bullet

RTC_XI, CLKIN, and USB_MXI Pins:

Section 6.4.3 Figure 6-8, Connections when USB Oscillator is Permanently Disabled:

USB On-Chip Oscillator With External Crystal

Section 6.5.1

PLL Device-Specific Information

• Added figure

• Deleted CLKIN from first sentence in first paragraph.

Table 6-3, PLLC1 Clock Frequency Ranges:

• Updated table to support 1.4 V

• Added footnote

Section 6.5.3 Table 6-4, Timing Requirements for CLKIN:

Clock PLL Electrical Data/Timing (Input and Output Clocks)

• Updated table to support 1.4 V

Table 6-5, Switching Characteristics Over Recommended Operating Conditions for CLKOUT:

• Updated table to support 1.4 V

Section 6.7.4 Table 6-6, Timing Requirements for Reset:

Reset Electrical Data/Timing

• Updated table to support 1.4 V

Section 6.8.1 Table 6-7, Timing Requirements for Interrupts:

Interrupts Electrical Data/Timing

• Updated table to support 1.4 V

Section 6.8.2 Table 6-8, Timing Requirements for Wake-Up From IDLE:

Wake-Up From IDLE Electrical Data/Timing

• Updated table to support 1.4 V

Table 6-9, Switching Characteristics Over Recommended Operating Conditions For Wake-Up From IDLE:

• Updated table to support 1.4 V

Section 6.8.3 Table 6-10, Switching Characteristics Over Recommended Operating Conditions For XF:

XF Electrical Data/Timing

Section 6.9.2

EMIF Non-Mobile and Mobile Synchronous DRAM

• Updated table to support 1.4 V

• Updated sixth bullet in first list

• Updated second bullet in last list in section to support 1.4 V Memory Supported

Section 6.9.5 Table 6-16, Timing Requirements for EMIF SDRAM/mSDRAM Interface:

EMIF Electrical Data/Timing CVDD= 1.3/1.4 V, DV V

= 3.3/2.75/2.5/1.8

DDEMIF

• Updated table to support 1.4 V

Table 6-18, Switching Characteristics Over Recommended Operating Conditions for EMIF SDRAM/mSDRAM

Interface:

• Added table to support 1.4 V

Table 6-19, Timing Requirements for EMIF Asynchronous Memory:

• Updated table to support 1.4 V

Table 6-20, Switching Characteristics Over Recommended Operating Conditions for EMIF Asynchronous

Memory

• Updated table to support 1.4 V

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SEE ADDITIONS/MODIFICATIONS/DELETIONS

Section 6.10.2 Table 6-23, Timing Requirements for MMC/SD:

MMC/SD Electrical Data/Timing

Section 6.11

Real-Time Clock (RTC)

Section 6.12.2 Table 6-28, Timing Requirements for I2C Timings:

I2C Electrical Data/Timing

Section 6.13.2 Table 6-31, Timing Requirements for UART Receive:

UART Electrical Data/Timing [Receive/Transmit]

Section 6.14.2 Table 6-37, Timing Requirements for I2S [I/O = 3.3 V, 2.75 V, and 2.5 V]:

I2S Electrical Data/Timing

Section 6.15.2 Table 6-42, Timing Requirements for LCD LIDD Mode:

LCDC Electrical Data/Timing

Section 6.16.2 Table 6-45, Switching Characteristics Over Recommended Operating Conditions for ADC Characteristics:

SAR ADC Electrical Data/Timing

Section 6.17.2 Table 6-47, Timing Requirements for SPI inputs:

SPI Electrical Data/Timing

Section 6.18.2 Table 6-50, Switching Characteristics Over Recommended Operating Conditions for USB 2.0:

USB 2.0 Electrical Data/Timing

Section 6.20.2 Table 6-56, Timing Requirements for GPIO Inputs:

GPIO Peripheral Input/Output Electrical Data/Timing

Section 6.20.3 Table 6-58, Timing Requirements for GPIO Input Latency:

GPIO Peripheral Input Latency Electrical Data/Timing

Section 6.21.2 Table 6-61, Timing Requirements for JTAG Test Port:

JTAG Test_port Electrical Data/Timing

• Updated table to support 1.4 V

Table 6-24, Switching Characteristics Over Recommended Operating Conditions for MMC Output:

• Updated table to support 1.4 V

• Updated second sentence in first paragraph

Section 6.11.1, RTC Only Mode:

• Added new subsection

• Updated table to support 1.4 V

Table 6-29, Switching Characteristics for I2C Timings:

• Updated table to support 1.4 V

Table 6-32, Switching Characteristics Over Recommended Operating Conditions for UART Transmit:

• Updated table to support 1.4 V

Table 6-38, Timing Requirements for I2S [I/O = 1.8 V]:

• Updated table to support 1.4 V

Table 6-39, Switching Characteristics Over Recommended Operating Conditions for I2S Output [I/O = 3.3 V,

2.75 V, or 2.5 V]:

• Updated table to support 1.4 V

Table 6-40, Switching Characteristics Over Recommended Operating Conditions for I2S Output [I/O = 1.8 V]:

• Updated table to support 1.4 V

Table 6-43, Switching Characteristics Over Recommended Operating Conditions for LCD LIDD Mode:

• Updated table to support 1.4 V

• Updated No. 6 parameter

• Updated table to support 1.4 V

Table 6-48, Switching Characteristics Over Recommended Operating Conditions for SPI Outputs:

• Updated table to support 1.4 V

Table 6-57, Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs:

• Updated table to support 1.4 V

Table 6-62, Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port:

• Updated table to support 1.4 V

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3 Device Overview

3.1 Device Characteristics

Table 3-1, provides an overview of the TMS320C5505 DSP. The tables show significant features of the

device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. For more detailed information on the actual device part number and maximum device operating frequency, see Section 3.6.2, Device and Development-Support Tool Nomenclature.

Table 3-1. Characteristics of the C5505 Processor

HARDWARE FEATURES C5505

Peripherals Asynchronous (8/16-bit bus width) SRAM, Not all peripheral pins are

available at the same time (for more detail, see the Device Configurations section).

On-Chip Memory

JTAG BSDL_ID see Figure 6-44

CPU Frequency MHz 1.3-V Core 100 or 120 MHz

Cycle Time ns 1.3-V Core 10, 8.33 ns

Voltage

LDOs DSP_LDO 1.3 V or 1.05 V, 250 mA max current for DSP CPU (CVDD)

(1) For more information on SDRAM devices support, see Section 6.9, External Memory Interface (EMIF).

External Memory Interface (EMIF) Flash (NOR, NAND),

DMA

Timers 1 Additional Timer Configurable as a 32-Bit GP Timer and/or a

UART 1 (with RTS/CTS flow control) SPI 1 with 4 chip selects I2C 1 (Master/Slave) I2S 4 (Two Channel, Full Duplex Communication) USB 2.0 (Device only) High- and Full-Speed Device

MMC/SD LCD Bridge 1 (8-bit or 16-bit asynchronous parallel bus)

ADC (Successive Approximation [SAR]) 1 (10-bit, 4-input, 16-ms conversion time) Real-Time Clock (RTC) 1 (Crystal Input, Separate Clock Domain and Power Supply) FFT Hardware Accelerator 1 (Supports 8 to 1024-point 16-bit real and complex FFT)

General-Purpose Input/Output Port (GPIO) Size (Bytes) 320KB RAM, 128KB ROM

Organization

JTAGID Register (Value is: 0x1B8F E02F)

1.05-V Core 60 or 75 MHz

1.4-V Core 150 MHz

1.05-V Core 16.67, 13.3 ns

1.4-V Core 6.66 ns

Core (V) 1.3 V (100, 120 MHz)

I/O (V) 1.8 V, 2.5 V, 2.75 V, 3.3 V

ANA_LDO

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SDRAM and Mobile SDRAM (16-bit bus width)

Four DMA controllers each with four channels,

2 MMC/SD, 256 byte read/write buffer, max 50-MHz clock for

SD cards, and signaling for DMA transfers

Up to 26 pins (with 1 Additional General-Purpose Output (XF)

and 4 Special-Purpose Outputs for Use With SAR)

• 64KB On-Chip Dual-Access RAM (DARAM)

• 256KB On-Chip Single-Access RAM (SARAM)

• 128KB On-Chip Single-Access ROM (SAROM)

1.3 V, 4 mA max current for PLL (V

for a total of 16 channels

2 32-Bit General-Purpose (GP) Timers

Watchdog

1.05 V (60, 75 MHz)

1.4 V (150 MHz)

), SAR, and power

management circuits (V

DDA_PLL

DDA_ANA

(1)

)

TMS320C5505

SPRS660B–AUGUST 2010–REVISED AUGUST 2010

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Table 3-1. Characteristics of the C5505 Processor (continued)

HARDWARE FEATURES C5505

USB_LDO

Power Characterization 25% ADD (Typical Sine Wave Data 0.22 mW/MHz @ 1.3 V, 100 or 120 MHz

PLL Options Software Programmable Multiplier x4 to x4099 multiplier BGA Package 10 x 10 mm 196-Pin BGA (ZCH) Process Technology mm 0.09 mm

Product Status

(2) PRODUCT PREVIEW information concerns experimental products (designated as TMX) that are in the formative or design phase of

development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(2)

Active @ Room Temp 25°C, 75% DMAC + 0.15 mW/MHz @ 1.05 V, 60 or 75 MHz Switching) 0.27 mW/MHz @ 1.4 V, 150 MHz

Active @ Room Temp 25°C, 75% DMAC + 0.14 mW/MHz @ 1.05 V, 60 or 75MHz 25% NOP (Typical Sine Wave Data 0.22 mW/MHz @ 1.3 V, 100 or 120 MHz Switching) 0.26 mW/MHz @ 1.4 V, 150 MHz

Standby (Master Clock Disabled) @ Room 0.26 mW @ 1.05 V Temp 25°C (DARAM and SARAM in Active 0.44 mW @ 1.3 V Mode) 0.72 mW @ 1.4 V

Standby (Master Clock Disabled) @ Room 0.23 mW @ 1.05 V Temp 25°C (DARAM in Retention and 0.40 mW @ 1.3 V SARAM in Active Mode) 0.66 mW @ 1.4 V

Standby (Master Clock Disabled) @ Room 0.15 mW @ 1.05 V Temp 25°C (DARAM in Active Mode and 0.28 mW @ 1.3 V SARAM in Retention) 0.53 mW @ 1.4 V

Product Preview (PP), Advance Information (AI), or Production Data (PD)

1.3 V, 25 mA max current for USB core digital (USB_V and PHY circuits (USB_V

PD(All other device speeds)

PP (150-MHz devices)

DDA1P3

)

DD1P3

)

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3.2 C55x CPU

The TMS320C5505 fixed-point digital signal processor (DSP) is based on the C55x CPU 3.3 generation processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, three data read buses (one 32-bit data read bus and two 16-bit data read buses), two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four data reads and two data writes in a single cycle. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory, stores them in a 128-byte Instruction Buffer Queue, and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instruction calls.

For more detailed information on the CPU, see the TMS320C55x CPU 3.0 CPU Reference Guide (literature number SWPU073).

SPRS660B–AUGUST 2010–REVISED AUGUST 2010

The C55x core of the device can address 16M bytes of unified data and program space. It also addresses 64K words of I/O space and includes three types of on-chip memory: 128 KB read-only memory (ROM), 256 KB single-access random access memory (SARAM), 64 KB dual-access random access memory (DARAM). The memory map is shown in Figure 3-1.

3.2.1 On-Chip Dual-Access RAM (DARAM)

The DARAM is located in the byte address range 000000h − 00FFFFh and is composed of eight blocks of 4K words each (see Table 3-2). Each DARAM block can perform two accesses per cycle (two reads, two writes, or a read and a write). The DARAM can be accessed by the internal program, data, or DMA buses.

Table 3-2. DARAM Blocks

CPU DMA CONTROLLER

BYTE ADDRESS RANGE BYTE ADDRESS RANGE

000000h – 001FFFh 0001 0000h – 0001 1FFFh DARAM 0 002000h – 003FFFh 0001 2000h – 0001 3FFFh DARAM 1 004000h – 005FFFh 0001 4000h – 0001 5FFFh DARAM 2 006000h – 007FFFh 0001 6000h – 0001 7FFFh DARAM 3

008000h – 009FFFh 0001 8000h – 0001 9FFFh DARAM 4 00A000h – 00BFFFh 0001 A000h – 0001 BFFFh DARAM 5 00C000h – 00DFFFh 0001 C000h – 0001 DFFFh DARAM 6 00E000h – 00FFFFh 0001 E000h – 0001 FFFFh DARAM 7

(1) The first 192 bytes are reserved for memory-mapped registers (MMRs). See Figure 3-1, Memory Map

Summary.

MEMORY BLOCK

(1)

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3.2.2 On-Chip Single-Access RAM (SARAM)

The SARAM is located at the byte address range 010000h – 04FFFFh and is composed of 32 blocks of 4K words each (see Table 3-3). Each SARAM block can perform one access per cycle (one read or one write). SARAM can be accessed by the internal program, data, or DMA buses. SARAM is also accessed by the USB and LCD DMA buses.

Table 3-3. SARAM Blocks

CPU DMA/USB CONTROLLER

BYTE ADDRESS RANGE BYTE ADDRESS RANGE

010000h − 011FFFh 0009 0000h – 0009 1FFFh SARAM 0

012000h − 013FFFh 0009 2000h – 0009 3FFFh SARAM 1

014000h − 015FFFh 0009 4000h – 0009 5FFFh SARAM 2

016000h − 017FFFh 0009 6000h – 0009 7FFFh SARAM 3

018000h − 019FFFh 0009 8000h – 0009 9FFFh SARAM 4 01A000h − 01BFFFh 0009 A000h – 0009 BFFFh SARAM 5 01C000h − 01DFFFh 0009 C000h – 0009 DFFFh SARAM 6 01E000h − 01FFFFh 0009 E000h – 0009 FFFFh SARAM 7

020000h − 021FFFh 000A 0000h – 000A 1FFFh SARAM 8

022000h − 023FFFh 000A 2000h – 000A 3FFFh SARAM 9

024000h − 025FFFh 000A 4000h – 000A 5FFFh SARAM 10

026000h − 027FFFh 000A 6000h – 000A 7FFFh SARAM 11

028000h − 029FFFh 000A 8000h – 000A 9FFFh SARAM 12 02A000h − 02BFFFh 000A A000h – 000A BFFFh SARAM 13 02C000h − 02DFFFh 000A C000h – 000A DFFFh SARAM 14 02E000h − 02FFFFh 000A E000h – 000A FFFFh SARAM 15

030000h − 031FFFh 000B 0000h – 000B 1FFFh SARAM 16

032000h − 033FFFh 000B 2000h – 000B 3FFFh SARAM 17

034000h − 035FFFh 000B 4000h – 000B 5FFFh SARAM 18

036000h − 037FFFh 000B 6000h – 000B 7FFFh SARAM 19

038000h − 039FFFh 000B 8000h – 000B 9FFFh SARAM 20 03A000h − 03BFFFh 000B A000h – 000B BFFFh SARAM 21 03C000h − 03DFFFh 000B C000h – 000B DFFFh SARAM 22 03E000h − 03FFFFh 000B E000h – 000B FFFFh SARAM 23

040000h – 041FFFh 000C 0000h – 000C 1FFFh SARAM 24

042000h – 043FFFh 000C 2000h – 000C 3FFFh SARAM 25

044000h – 045FFFh 000C 4000h – 000C 5FFFh SARAM 26

046000h – 047FFFh 000C 6000h – 000C 7FFFh SARAM 27

048000h – 049FFFh 000C 8000h – 000C 9FFFh SARAM 28 04A000h – 04BFFFh 000C A000h – 000C BFFFh SARAM 29 04C000h – 04DFFFh 000C C000h – 000C DFFFh SARAM 30 04E000h – 04FFFFh 000C E000h – 000C FFFFh SARAM 31

(1) SARAM31 (byte address range: 0x4E000 – 0x4EFFF) is reserved for the bootloader. After the boot

process is complete, this memory space can be used.

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MEMORY BLOCK

(1)

3.2.3 On-Chip Read-Only Memory (ROM)

The zero-wait-state ROM is located at the byte address range FE0000h – FFFFFFh. The ROM is composed of four 16K-word blocks, for a total of 128K bytes of ROM. The ROM address space can be mapped by software to the external memory or to the internal ROM.

The standard device includes a Bootloader program resident in the ROM.

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When the MPNMC bit field of the ST3 status register is cleared (by default), the byte address range FE0000h – FFFFFFh is reserved for the on-chip ROM. When the MPNMC bit field of the ST3 status register is set through software, the on-chip ROM is disabled and not present in the memory map, and byte address range FE0000h – FFFFFFh is directed to external memory space. A hardware reset always clears the MPNMC bit, so it is not possible to disable the ROM at reset. However, the software reset instruction does not affect the MPNMC bit. The ROM can be accessed by the program and data buses. Each on-chip ROM block is a one cycle per word access memory.

3.2.4 External Memory

The external memory space of the device is located at the byte address range 050000h – FFFFFFh. The external memory space is divided into five chip select spaces: one dedicated to SDRAM and mobile SDRAM (EMIF CS0 or CS[1:0] space), and the remainder (EMIF CS2 through CS5 space) dedicated to asynchronous devices including flash. Each chip select space has a corresponding chip select pin (called EMIF_CSx) that is activated during an access to the chip select space.

The external memory interface (EMIF) provides the means for the DSP to access external memories and other devices including: mobile single data rate (SDR) synchronous dynamic RAM (SDRAM and mSDRAM), NOR Flash, NAND Flash, and asynchronous static RAM (SRAM). Before accessing external memory, you must configure the EMIF through its memory-mapped registers.

The EMIF provides a configurable 16- or 8-bit data bus, an address bus width of up to 21-bits, and 5 dedicated chip selects, along with memory control signals. To maximize power savings, the I/O pin of the EMIF can be operated at an independent voltage from the other I/O pins on the device.

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3.2.5 I/O Memory

The device DSP includes a 64K byte I/O space for the memory-mapped registers of the DSP peripherals and system registers used for idle control, status monitoring and system configuration. I/O space is separate from program/memory space and is accessed with separate instruction opcodes or via the DMA's.

Table 3-4 lists the memory-mapped registers of the device. Note that not all addresses in the 64K byte I/O

space are used; these addresses should be treated as RESERVED and not accessed by the CPU nor DMA. For the expanded tables of each peripheral, see Section 6, Peripheral Information and Electrical Specifications of this document.

Some DMA controllers have access to the I/O-Space memory-mapped registers of the following peripherals registers: I2C, UART, I2S, MMC/SD, EMIF, USB, and SAR ADC.

Before accessing any peripheral memory-mapped register, make sure the peripheral being accessed is not held in reset via the Peripheral Reset Control Register (PRCR) and its internal clock is enabled via the Peripheral Clock Gating Control Registers (PCGCR1 and PCGCR2).

0x0005 – 0x000D through 0x0803 – 0x0BFF Reserved

Table 3-4. Peripheral I/O-Space Control Registers

WORD ADDRESS PERIPHERAL

0x0000 – 0x0004 Idle Control

0x0C00 – 0x0C7F DMA0 0x0C80 – 0x0CFF Reserved 0x0D00 – 0x0D7F DMA1 0x0D80 – 0x0DFF Reserved 0x0E00 – 0x0E7F DMA2 0x0E80 – 0x0EFF Reserved

0x0F00 – 0x0F7F DMA3 0x0F80 – 0x0FFF Reserved

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Table 3-4. Peripheral I/O-Space Control Registers (continued)

WORD ADDRESS PERIPHERAL

0x1000 – 0x10DD EMIF

0x10EE – 0x10FF through 0x1300 – 0x17FF Reserved

0x1800 – 0x181F Timer0 0x1820 – 0x183F Reserved 0x1840 – 0x185F Timer1 0x1860 – 0x187F Reserved 0x1880 – 0x189F Timer2 0x1900 – 0x197F RTC 0x1980 – 0x19FF Reserved

0x1A00 – 0x1A6C I2C

0x1A6D – 0x1AFF Reserved

0x1B00 – 0x1B1F UART 0x1B80 – 0x1BFF Reserved 0x1C00 – 0x1CFF System Control

0x1D00 – 0x1FFF through 0x2600 – 0x27FF Reserved

0x2800 – 0x2840 I2S0

0x2900 – 0x2940 I2S1 0x2A00 – 0x2A40 I2S2 0x2B00 – 0x2B40 I2S3

0x2C41 – 0x2DFF Reserved

0x2E00 – 0x2E40 LCD

0x2E41 – 0x2FFF Reserved

0x3000 – 0x300F SPI 0x3010 – 0x39FF Reserved

0x3A00 – 0x3A1F MMC/SD0 0x3A20 – 0x3AFF Reserved 0x3B00 – 0x3B1F MMC/SD1 0x3B2F – 0x6FFF Reserved

0x7000 – 0x70FF SAR and Analog Control Registers 0x7100 – 0x7FFF Reserved 0x8000 – 0xFFFF USB

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0001 0000h

64K Minus 192 Bytes

DARAM

(D)

0009 0000h

SARAM

256K Bytes

External-CS2 Space

(C)

0200 0000h

0300 0000h

0400 0000h

0500 0000h

050E 0000h

128K Bytes Asynchronous (if MPNMC=1) 128K Bytes ROM (if MPNMC=0)

External-CS3 Space

(C)

External-CS4 Space

(C)

External-CS5 Space

(C)

BLOCK SIZE

DMA/USB/LCD

BYTE ADDRESS

(A)

ROM

(if MPNMC=0)

External-CS5

f MPNMC=1)

(C)

Space

1M Minus 128K Bytes Asynchronous

1M Bytes Asynchronous

2M Bytes Asynchronous

4M Bytes Asynchronous

MEMORY BLOCKS

0001 00C0h

MMR (Reserved)

(B)

0100 0000h

External-CS0 Space

(C)(E)

8M Minus 320K Bytes SDRAM/mSDRAM

050F FFFFh

000000h

010000h

800000h

C00000h

E00000h

F00000h

FE0000h

CPU BYTE

ADDRESS

(A)

0000C0h

050000h

FFFFFFh

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3.3 Memory Map Summary

The device provides 16M bytes of total memory space composed of on-chip RAM, on-chip ROM, and external memory space supporting a variety of memory types. The on-chip, dual-access RAM allows two accesses to a given block during the same cycle. It also supports 8 blocks of 4K words of dual-access RAM. The on-chip, single-access RAM allows one access to a given block per cycle. In addition, the device supports 32 blocks of 4K words of single-access RAM.

The remainder of the memory map is divided into five external spaces, and on-chip ROM. Each external space has a chip select decode signal (called CS0, CS[2:5]) that indicates an access to the selected space. The external memory interface (EMIF) supports access to asynchronous memories such as SRAM, NAND, or NOR and Flash, and mobile single data rate (mSDR) and single data rate (SDR) SDRAM.

The DSP memory is accessible by different master modules within the DSP, including the C55x CPU, the four DMA controllers, LCD, and USB (see Figure 3-1).

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A. Address shown represents the first byte address in each block. B. The first 192 bytes are reserved for memory-mapped registers (MMRs). C. Out of the four DMA controllers, only DMA controller 3 has access to the external memory space. D. The USB and LCD controllers do not have access to DARAM. E. The CS0 space can be accessed by CS0 only or by CS0 and CS1.

Figure 3-1. Memory Map Summary

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DDEMIF

EM_CS5

EM_CS1

EM_SDRAS

CLKOUT

CLKIN

1 2

8 9

11 12

EM_BA[0]

EM_BA[1]

EM_A[4]

EM_A[5]

EM_A[2]

EM_A[6]

EM_WAIT4

EM_A[7] EM_D[7]

EM_WAIT5

EM_WE

EM_A[8]

EM_A[12]/

(CLE)

EM_A[13]

EM_A[14]

EM_A[15]/

GP[21]

EM_DQM1

DDEMIF

DDIO

CLK_SEL

RESET

TMS

TDO

TDI

TCK

TRST

EMU1

EMU0

WAKEUP

RSV0

EM_A[20]/

GP[26]

EM_A[19]/

GP[25]

EM_A[18]/

GP[24]

EM_A[17]/

GP[23]

EM_A[16]/

GP[22]

EM_A[11]/

(ALE)

EM_A[10]

EM_A[9]

EM_A[3]

EM_A[1]

EM_A[0]

EM_D[15]

EM_D[14]

EM_D[13]

EM_D[12]

EM_D[11]

EM_D[10]

EM_D[9]

EM_D[8]

EM_D[6]

EM_D[5]

EM_D[4]

EM_D[3]

EM_D[2]

EM_D[1]

EM_D[0]

EM_CS4

EM_OE

EM_R/W

EM_CS3

EM_CS2

EM_CS0

EM_SDCLK

EM_SDCKE

EM_SDCAS

SCL SDA

MMC0_D0/

I2S0_DX/

GP[2]

MMC0_CLK/

I2S0_CLK/

GP[0]

MMC0_D1/

I2S0_RX/

GP[3]

MMC0_CMD/

I2S0_FS/

GP[1]

MMC1_D0/

I2S1_DX/

GP[8]

MMC1_CLK/

I2S1_CLK/

GP[6]

MMC1_D1/

I2S1_RX/

GP[9]

MMC1_CMD/

I2S1_FS/

GP[7]

LCD_D[11]/

I2S2_DX/

GP[27]/ SPI_TX

LCD_D[8]/ I2S2_CLK/

GP[18]/

SPI_CLK

LCD_D[10]/

I2S2_RX/

GP[20]/ SPI_RX

LCD_D[9]/

I2S2_FS/

GP[19]/

SPI_CS0

LCD_D[15]/

UART_TXD/

GP[31]/

I2S3_DX

LCD_D[12]/

UART_RTS/

GP[28]/

I2S3_CLK

LCD_D[14]/

UART_RXD/

GP[30]/

I2S3_RX

LCD_D[13]/

UART_CTS/

GP[29]/

I2S3_FS

LCD_

CS0_E0/

SPI_CS0

LCD_

CS1_EN1/

SPI_CS1

LCD_

RW_WRB/

SPI_CS2

LCD_RS/ SPI_CS3

LCD_ EN_RDB/ SPI_CLK

LCD_D[1]/

SPI_TX

LCD_D[0]/

SPI_RX

LCD_D[2]/

GP[12]

LCD_D[5]/

GP[15]

LCD_D[3]/

GP[13]

LCD_D[4]/

GP[14]

LCD_D[6]/

GP[16]

MMC0_D3/

GP[5]

MMC0_D2/

GP[4]

MMC1_D3/

GP[11]

MMC1_D2/

GP[10]

RSV1 RSV2

USB_VBUS

LCD_D[7]/

GP[17]

INT0

EM_DQM0

EM_WAIT3

EM_WAIT2

INT1

USB_V

DD1P3

USB_DM

USB_

DDA1P3

USB_

SSA3P3

USB_

DDA3P3

USB_V

SS1P3

USB_DP

USB_

SSA

1P3

USB_V

DDPLL

USB_R1 USB_V

SSREF

USB_V

SSPLL

USB_V

DDOSC

USB_M12XI USB_M12XO

USB_V

SSOSC

USB_LDOO

LDOI

DDRTC

LDOI

DSP_LDOO

RTC_

CLKOUT

SSA_PLL

GPAIN0

DSP_

LDO_EN

RSV16

RSV3

SSRTC

DDA_PLL

GPAIN3

DDRTC

SSA_ANA

GPAIN2

RTC_XI

RTC_XO

DDA_ANA

GPAIN1

ANA_LDOO

LDOI

RSV5 RSV4

BG_CAP

SSA_ANA

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3.4 Pin Assignments

Extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using software programmable register settings. For more information on pin muxing, see Section 4.7, Multiplexed Pin Configurations of this document.

3.4.1 Pin Map (Bottom View)

Figure 3-2 shows the bottom view of the package pin assignments.

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A. Shading denotes pins not supported on this device. To ensure proper device operation, these pins must be hooked

up properly, see Table 3-19, Regulators and Power Management Terminal Functions.

Figure 3-2. Pin Map

(A)

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3.5 Terminal Functions

The terminal functions tables (Table 3-5 through Table 3-22) identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors or bus-holders, and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device Configuration section of this data manual.

For proper device operation, external pullup/pulldown resistors may be required on some pins.

Section 4.8.1, Pullup/Pulldown Resistors discusses situations where external pullup/pulldown resistors are

required.

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Table 3-5. Oscillator/PLL Terminal Functions

SIGNAL

NAME NO.

CLKOUT A7 O/Z DV

CLKIN A8 I DV

CLK_SEL C7 I DV

DDA_PLL

SSA_PLL

C10 PWR MHz).

D9 GND Analog PLL ground for the system clock generator.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, BH = Bus Holder (2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

see Section 5.2,

–

DDIO

–

DDIO

–

DDIO

ROC

(2) (3)

DESCRIPTION

DSP clock output signal. For debug purposes, the CLKOUT pin can be used to tap different clocks within the DSP clock generator. The SRC bits in the CLKOUT Control Source Register (CCSSR) can be used to specify the CLKOUT pin source. Additionally, the slew rate of the CLKOUT pin can be controlled by the Output Slew Rate Control Register (OSRCR) [0x1C16].

The CLKOUT pin is enabled/disabled through the CLKOFF bit in the CPU ST3_55 register. When disabled, the CLKOUT pin is placed in high-impedance (Hi-Z). At reset the CLKOUT pin is enabled until the beginning of the boot sequence, when the on-chip Bootloader sets CLKOFF = 1 and the CLKOUT pin is disabled (Hi-Z). For more information on the ST3_55 register, see the TMS320C55x 3.0 CPU Reference Guide (literature number: SWPU073).

Input clock. This signal is used to input an external clock when the 32-KHz on-chip oscillator is not used as the DSP clock (pin CLK_SEL = 1). For boot purposes, the CLKIN frequency is assumed to be either 11.2896, 12, or 12.288 MHz.

The CLK_SEL pin (C7) selects between the 32-KHz crystal clock or CLKIN. When the CLK_SEL pin is low, this pin should be tied to ground (VSS). When

CLK_SEL is high, this pin should be driven by an external clock source. If CLK_SEL is high, this pin is used as the reference clock for the clock generator

and during bootup the bootloader bypasses the PLL and assumes the CLKIN frequency is one of the following frequencies: 11.2896-, 12-, or 12.288-MHz. With these frequencies in mind, the bootloader sets the SPI clock rates at 500 KHz and the I2C clock rate at 400 KHz.

Clock input select. This pin selects between the 32-KHz crystal clock or CLKIN. 0 = 32-KHz on-chip oscillator drives the RTC timer and the DSP clock generator

while CLKIN is ignored. 1 = CLKIN drives the DSP clock generator and the 32-KHz on-chip oscillator

drives only the RTC timer. This pin is not allowed to change during device operation; it must be tied high or

low at the board. This signal can be powered from the ANA_LDOO pin.

1.3-V Analog PLL power supply for the system clock generator (PLLOUT ≤ 120

1.4-V Analog PLL power supply for the system clock generator (PLLOUT > 120 MHz).ote: When V

DDA_PLL

requires 1.4V, V

must be powered externally.

DDA_PLL

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Table 3-6. Real-Time Clock (RTC) Terminal Functions

SIGNAL

NAME NO.

RTC_XO A9 I CV

RTC_XI B9 I

RTC_CLKOUT D8 O/Z

WAKEUP E8 I/O/Z

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

(2) (3)

OTHER

DESCRIPTION

Real-time clock oscillator output. This pin operates at the RTC core voltage,

–

DDRTC

CV If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to

(see Section 5.2, Recommended Operating Conditions).

, and supports a 32.768-kHz crystal.

DDRTC

and RTC_XO to ground (VSS). A voltage must still be applied to CV

DDRTC

Note: When RTC oscillator is disabled, the RTC registers (I/O address range

1900h – 197Fh) are not accessible. Real-time clock oscillator input.

If the RTC oscillator is not used, it can be disabled by connecting RTC_XI to

– CV

DDRTC

(see Section 5.2, Recommended Operating Conditions).

and RTC_XO to ground (VSS). A voltage must still be applied to CV

DDRTC

Note: When RTC oscillator is disabled, the RTC registers (I/O address range 1900h – 197Fh) are not accessible.

– RTC_CLKOUT pin is enabled/disabled through the RTCCLKOUTEN bit in the RTC

Real-time clock output pin. This pin operates at DV

DDRTC

Power Management Register (RTCPMGT). At reset, the RTC_CLKOUT pin is disabled (high-impedance [Hi-Z]).

DDRTC

voltage. The

The pin is used to WAKEUP the CPU from idle instruction. This pin defaults to an

– input at reset, but can also be configured as an active-low open-drain output signal

DDRTC

to wakeup an external device from an RTC alarm by setting the WU_DIR bit in the RTCPMGT [1930h].

DDRTC

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Table 3-7. RESET, Interrupts, and JTAG Terminal Functions

SIGNAL

NAME NO.

XF M8 O/Z DV

RESET D6 I DV

[For more detailed information on emulation header design guidelines, see the XDS560 Emulator Technical Reference (literature number:

SPRU589).]

TMS L8 I DV

TDO M7 O/Z DV

TDI L7 I DV

TYPE

(1)

OTHER

(2) (3)

DESCRIPTION

RESET

External Flag Output. XF is used for signaling other processors in multiprocessor configurations or XF can be used as a fast general-purpose output pin.

XF is set high by the BSET XF instruction and XF is set low by the BCLR XF instruction or by writing to bit 13 of the ST1_55 register. At reset, the XF pin will be high. For more information on the ST1_55

–

DDIO

Device reset. RESET causes the DSP to terminate execution and loads the program counter with the contents of the reset vector. When RESET is brought to a high level, the reset vector in ROM at FFFF00h

IPU

DDIO

forces the program execution to branch to the location of the on-chip ROM bootloader.

RESET affects the various registers and status bits. The IPU resistor on this pin can be enabled or disabled via the

PDINHIBR2 register but will be forced ON when RESET is asserted.

JTAG

IEEE standard 1149.1 test mode select. This serial control input is clocked into the TAP controller on the rising edge of TCK.

If the emulation header is located greater than 6 inches from the device, TMS must be buffered. In this case, the input buffer for TMS

IPU needs a pullup resistor connected to DV

DDIO

BH 4.7 kΩ or greater is suggested. For board design guidelines related to

known value when the emulator is not connected. A resistor value of

to hold the signal at a

DDIO

the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589).

The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance (Hi-Z) state except when the scanning of data is in progress.

For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589).

–

DDIO

If the emulation header is located greater than 6 inches from the device, TDO must be buffered.

IEEE standard 1149.1 test data input. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.

If the emulation header is located greater than 6 inches from the

IPU device, TDI must be buffered. In this case, the input buffer for TDI

DDIO

BH known value when the emulator is not connected. A resistor value of

needs a pullup resistor connected to DV

to hold this signal at a

DDIO

4.7 kΩ or greater is suggested. The IPU resistor on this pin can be enabled or disabled via the

PDINHIBR2 register.

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

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Table 3-7. RESET, Interrupts, and JTAG Terminal Functions (continued)

SIGNAL

NAME NO.

TCK M6 I DV

TRST M9 I DV

EMU1 M5 I/O/Z DV

EMU0 L6 I/O/Z DV

INT1 E7 I DV

INT0 C6 I DV

TYPE

(1)

OTHER

EXTERNAL INTERRUPTS

SPRS660B–AUGUST 2010–REVISED AUGUST 2010

(2) (3)

DESCRIPTION

IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK.

IPU

DDIO

If the emulation header is located greater than 6 inches from the device, TCK must be buffered.

For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589).

The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

IEEE standard 1149.1 reset signal for test and emulation logic. TRST, when high, allows the IEEE standard 1149.1 scan and emulation logic to take control of the operations of the device. If TRST is not connected or is driven low, the device operates in its functional mode, and the

IPD

DDIO

BH For board design guidelines related to the emulation header, see the

IEEE standard 1149.1 signals are ignored. The device will not operate properly if this reset pin is never asserted low.

XDS560 Emulator Technical Reference (literature number: SPRU589). It is recommended that an external pulldown resistor be used in

addition to the IPD -- especially if there is a long trace to an emulation header.

Emulator 1 pin. EMU1 is used as an interrupt to or from the emulator system and is defined as input/output by way of the emulation logic.

For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589).

IPU

DDIO

An external pullup to DV less than 10 msec. A 4.7-kΩ resistor is suggested for most applications.

is required to provide a signal rise time of

DDIO

For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589).

The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

Emulator 0 pin. When TRST is driven low and then high, the state of the EMU0 pin is latched and used to connect the JTAG pins (TCK, TMS, TDI, TDO) to either the IEEE1149.1 Boundary-Scan TAP (when the latched value of EMU0 = 0) or to the DSP Emulation TAP (when the latched value of EMU0 = 1). Once TRST is high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output

IPU by way of the emulation logic.

DDIO

An external pullup to DV less than 10 msec. A 4.7-kΩ resistor is suggested for most applications.

is required to provide a signal rise time of

DDIO

For board design guidelines related to the emulation header, see the XDS560 Emulator Technical Reference (literature number: SPRU589).

The IPU resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

IPU External interrupt inputs (INT1 and INT0). These pins are maskable via

DDIO

BH mode bit. The pins can be polled and reset by their specific Interrupt

IPU

DDIO

their specific Interrupt Mask Register (IMR1, IMR0) and the interrupt Flag Register (IFR1, IFR0).

The IPU resistor on these pins can be enabled or disabled via the PDINHIBR2 register.

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Table 3-8. External Memory Interface (EMIF) Terminal Functions

SIGNAL

NAME NO.

EM_A[20]/GP[26] J3 I/O/Z DV

EM_A[19]/GP[25] G4 I/O/Z DV

EM_A[18]/GP[24] G2 I/O/Z DV

EM_A[17]/GP[23] F2 I/O/Z DV

EM_A[16]/GP[22] E2 I/O/Z DV

EM_A[15]/GP[21] N1 I/O/Z DV

EM_A[14] M1 I/O/Z This pin is the EMIF external address pin 14.

EM_A[13] L1 I/O/Z This pin is the EMIF external address pin 13.

EM_A[12]/(CLE) K1 I/O/Z

EM_A[11]/(ALE) K2 I/O/Z

EM_A[10] L2 I/O/Z This pin is the EMIF external address pin 10.

EM_A[9] J2 I/O/Z This pin is the EMIF external address pin 9.

EM_A[8] J1 I/O/Z This pin is the EMIF external address pin 8.

EM_A[7] H2 I/O/Z This pin is the EMIF external address pin 7.

EM_A[6] F1 I/O/Z This pin is the EMIF external address pin 6.

TYPE

(1)

OTHER

(2) (3)

EMIF FUNCTIONAL PINS: ASYNC (NOR, SRAM, and NAND)

Note: When accessing 8-bit Asynchronous memory, pins EM_A[20:0] should be

connected to memory address pins [22:2] and EM_BA[1:0] should be connected to memory address pins [1:0]. For 16-bit Asynchronous memory, pins EM_A[20:0] should be connected to memory address pins [20:1] and EM_BA[1] should be connected to memory address pin [0].

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

IPD

DDEMIF

external address pin 20. Mux control via the A20_MODE bit in the EBSR (see Figure 4-2). The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

IPD

DDEMIF

external address pin 19. Mux control via the A19_MODE bit in the EBSR (see Figure 4-2). The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

IPD

DDEMIF

external address pin 18. Mux control via the A18_MODE bit in the EBSR (see Figure 4-2). The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

IPD

DDEMIF

external address pin 17. Mux control via the A17_MODE bit in the EBSR (see Figure 4-2). The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

IPD

DDEMIF

external address pin 16. Mux control via the A16_MODE bit in the EBSR (see Figure 4-2). The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

This pin is multiplexed between EMIF and GPIO. For EMIF, this pin is the EMIF

IPD

DDEMIF

external address pin 15. Mux control via the A15_MODE bit in the EBSR (see Figure 4-2). The IPD resistor on this pin can be enabled or disabled via the PDINHIBR2 register.

DDEMIF

BH this pin also acts as Command Latch Enable (CLE).

DDEMIF

BH this pin also acts as Address Latch Enable (ALE).

DDEMIF

This pin is the EMIF external address pin 12. When interfacing with NAND Flash,

This pin is the EMIF external address pin 11. When interfacing with NAND Flash,

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DESCRIPTION

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

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Table 3-8. External Memory Interface (EMIF) Terminal Functions (continued)

SIGNAL

NAME NO.

EM_A[5] D1 I/O/Z This pin is the EMIF external address pin 5.

EM_A[4] C1 I/O/Z This pin is the EMIF external address pin 4.

EM_A[3] D2 I/O/Z This pin is the EMIF external address pin 3.

EM_A[2] E1 I/O/Z This pin is the EMIF external address pin 2.

EM_A[1] C2 I/O/Z This pin is the EMIF external address pin 1.

EM_A[0] B2 I/O/Z This pin is the EMIF external address pin 0.

EM_D[15] J4 EM_D[14] K3 EM_D[13] K4 EM_D[12] L3 EM_D[11] C4 EM_D[10] D3

EM_D[9] F4 EM_D[8] E3 EM_D[7] H3 EM_D[6] K5 EM_D[5] M2 EM_D[4] L4 EM_D[3] D4 EM_D[2] F3 EM_D[1] E5 EM_D[0] G3

EM_CS5 A3 O/Z

EM_CS4 C3 O/Z

EM_CS3 M4 O/Z

EM_CS2 C5 O/Z

EM_WE H1 O/Z EMIF asynchronous memory write enable output

EM_OE E4 O/Z EMIF asynchronous memory read enable output

EM_R/W B6 O/Z EMIF asynchronous read/write output

EM_DQM1 P1 O/Z

EM_DQM0 B5 O/Z

(1)

TYPE

I/O/Z EMIF 16-bit bi-directional bus.

(2) (3)

OTHER

DDEMIF

BH NAND flash, or SRAM).

DDEMIF

BH NAND flash, or SRAM).

DDEMIF

BH flash, NAND flash, or SRAM).

DDEMIF

BH flash, NAND flash, or SRAM).

DDEMIF

EMIF chip select 5 output for use with asynchronous memories (i.e., NOR flash,

EMIF chip select 4 output for use with asynchronous memories (i.e., NOR flash,

EMIF NAND chip select 3 output for use with asynchronous memories (i.e., NOR

EMIF NAND chip select 2 output for use with asynchronous memories (i.e., NOR

EMIF asynchronous data write strobes and byte enables or EMIF SDRAM and mSDRAM data mask bits.

DESCRIPTION

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Table 3-8. External Memory Interface (EMIF) Terminal Functions (continued)

SIGNAL

NAME NO.

EM_BA[1] B1 O/Z

EM_BA[0] A1 O/Z

EM_WAIT5 H4 I EMIF wait state extension input 5 for EM_CS5

EM_WAIT4 G1 I EMIF wait state extension input 4 for EM_CS4

EM_WAIT3 K6 I EMIF wait state extension input 3 for EM_CS3

EM_WAIT2 D5 I EMIF wait state extension input 2 for EM_CS2

EM_CS1 A4 O/Z EMIF SDRAM/mSDRAM chip select 1 output

EM_CS0 B3 O/Z EMIF SDRAM/mSDRAM chip select 0 output

EM_SDCLK M3 O/Z EMIF SDRAM/mSDRAM clock

EM_SDCKE N2 O/Z EMIF SDRAM/mSDRAM clock enable

EM_SDRAS A6 O/Z EMIF SDRAM/mSDRAM row address strobe

EM_SDCAS B4 O/Z EMIF SDRAM/mSDRAM column strobe

TYPE

(1)

OTHER

DDEMIF

(2) (3)

EMIF asynchronous bank address 16-bit wide memory: EM_BA[1] forms the device address[0] and BA[0] forms device

address [23].

DDEMIF

8-bit wide memory: EM_BA[1] forms the device address[1] and BA[0] forms device address [0].

EMIF SDRAM and mSDRAM bank address.

DDEMIF

EMIF FUNCTIONAL PINS: SDRAM and mSDRAM ONLY

DDEMIF

DESCRIPTION

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Table 3-9. Inter-Integrated Circuit (I2C) Terminal Functions

SIGNAL

NAME NO.

SCL B7 I/O/Z

SDA B8 I/O/Z

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

(2) (3)

OTHER

DDIO

BH on this pin.

DDIO

BH is required on this pin.

This pin is the I2C clock output. Per the I2C standard, an external pullup is required

This pin is the I2C bidirectional data signal. Per the I2C standard, an external pullup

DESCRIPTION

I2C

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Table 3-10. Inter-IC Sound (I2S0 – I2S3) Terminal Functions

SIGNAL

NAME NO.

MMC0_D0/ IPD

I2S0_DX/ L9 I/O/Z DV

GP[2] BH

MMC0_CLK/ IPD

I2S0_CLK/ L10 I/O/Z DV

GP[0] BH

MMC0_D1/ IPD

I2S0_RX/ M10 I/O/Z DV

GP[3] BH

MMC0_CMD/ IPD

I2S0_FS/ M11 I/O/Z DV

GP[1] BH

MMC1_D0/ IPD

2S1_DX/ M14 I/O/Z DV

GP[8] BH

MMC1_CLK/ IPD

I2S1_CLK/ M13 I/O/Z DV

GP[6] BH

MMC1_D1/ IPD

I2S1_RX/ M12 I/O/Z DV

GP[9] BH

MMC1_CMD/ IPD

I2S1_FS/ L14 I/O/Z DV

GP[7] BH

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

DDIO

(2) (3)

DESCRIPTION

Interface 0 (I2S0)

This pin is multiplexed between MMC0, I2S0, and GPIO. For I2S, it is I2S0 transmit data output I2S0_DX. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between MMC0, I2S0, and GPIO.

For I2S, it is I2S0 clock input/output I2S0_CLK. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between MMC0, I2S0, and GPIO.

For I2S, it is I2S0 receive data input I2S0_RX. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between MMC0, I2S0, and GPIO.

For I2S, it is I2S0 frame synchronization input/output I2S0_FS. Mux control via the SP0MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register.

Interface 1 (I2S1)

This pin is multiplexed between MMC1, I2S1, and GPIO. For I2S, it is I2S1 transmit data output I2S1_DX. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between MMC1, I2S1, and GPIO.

For I2S, it is I2S1 clock input/output I2S1_CLK. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between MMC1, I2S1, and GPIO.

For I2S, it is I2S1 receive data input I2S1_RX. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register. This pin is multiplexed between MMC1, I2S2, and GPIO.

For I2S, it is I2S1 frame synchronization input/output I2S1_FS. Mux control via the SP1MODE bits in the EBSR. The IPD resistor on this pin can be

enabled or disabled via the PDINHIBR1 register.

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Table 3-10. Inter-IC Sound (I2S0 – I2S3) Terminal Functions (continued)

SIGNAL

NAME NO.

LCD_D[11]/

I2S2_DX/ For I2S, it is I2S2 transmit data output I2S2_DX.

GP[27]/

P12 I/O/Z DV

SPI_TX

LCD_D8]/

I2S2_CLK/ For I2S, it is I2S2 clock input/output I2S2_CLK.

GP[18]/

N10 I/O/Z DV

SPI_CLK

LCD_D[10]/

I2S2_RX/ For I2S, it is I2S2 receive data input I2S2_RX.

GP[20]/

N11 I/O/Z DV

SPI_RX

LCD_D[9]/

I2S2_FS/ For I2S, it is I2S2 frame synchronization input/output I2S2_FS.

GP[19]/

P11 I/O/Z DV

SPI_CS0

LCD_D[15]/

UART_TXD/ For I2S, it is I2S3 transmit data output I2S3_DX.

GP[31]/

P14 I/O/Z DV

I2S3_DX

LCD_D[12]/

UART_RTS/ For I2S, it is I2S3 clock input/output I2S3_CLK.

GP[28]/

N12 I/O/Z DV

I2S3_CLK

LCD_D[14]/

UART_RXD/ For I2S, it is I2S3 receive data input I2S3_RX.

GP[30]/

N13 I/O/Z DV

I2S3_RX

LCD_D[13]/

UART_CTS/ For I2S, it is I2S3 frame synchronization input/output I2S3_FS.

GP[29]/

P13 I/O/Z DV

I2S3_FS

TYPE

(1)

OTHER

IPD

DDIO

(2) (3)

DESCRIPTION

Interface 2 (I2S2)

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge, I2S2, and GPIO.

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

Interface 3 (I2S3)

This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

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Table 3-11. Serial Peripheral Interface (SPI) Terminal Functions

SIGNAL

NAME NO.

LCD_CS0_E0/ DV

SPI_CS0 BH

P4 I/O/Z Mux control via the PPMODE bits in the EBSR.

LCD_D[9]/

I2S2_FS/

GP[19]/

P11 I/O/Z DV

SPI_CS0

LCD_CS1_E1/ DV

SPI_CS1 BH

LCD_RW_WRB/ DV

SPI_CS2 BH

LCD_RS/ DV

SPI_CS3 BH

LCD_EN_RDB/ DV

SPI_CLK BH

N4 I/O/Z Mux control via the PPMODE bits in the EBSR.

P5 I/O/Z

N5 I/O/Z

N3 O/Z

LCD_D8]/

I2S2_CLK/

GP[18]/

N10 I/O/Z DV

SPI_CLK

LCD_D[1]/ DV

SPI_TX BH

N6 I/O/Z

LCD_D[11]/

I2S2_DX/

GP[27]/

P12 I/O/Z DV

SPI_TX

LCD_D[0]/ DV

SPI_RX BH

P6 I/O/Z

LCD_D[10]/

I2S2_RX/

GP[20]/

N11 I/O/Z DV

SPI_RX

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

IPD

DDIO

(2) (3)

DESCRIPTION

Serial Port Interface (SPI)

This pin is multiplexed between LCD Bridge and SPI.

For SPI, this pin is SPI chip select SPI_CS0. This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI chip select SPI_CS0. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge and SPI.

For SPI, this pin is SPI chip select SPI_CS1. This pin is multiplexed between LCD Bridge and SPI.

Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI chip select SPI_CS2.

This pin is multiplexed between LCD Bridge and SPI. Mux control via the PPMODE bits in the EBSR.

For SPI, this pin is SPI chip select SPI_CS3. This pin is multiplexed between LCD Bridge and SPI.

Mux control via the PPMODE bits in the EBSR. For SPI, this pin is clock output SPI_CLK.

This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI. Mux control via the PPMODE bits in the EBSR. For SPI, this pin is clock output SPI_CLK. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge and SPI. Mux control via the PPMODE bits in the EBSR.

For SPI, this pin is SPI transmit data output. This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

Mux control via the PPMODE bits in the EBSR. For SPI, this pin is SPI transmit data output. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge and SPI. Mux control via the PPMODE bits in the EBSR.

For SPI this pin is SPI receive data input. This pin is multiplexed between LCD Bridge, I2S2, GPIO, and SPI.

Mux control via the PPMODE bits in the EBSR. For SPI this pin is SPI receive data input. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

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Table 3-12. UART Terminal Functions

SIGNAL

NAME NO.

LCD_D[14]/

UART_RXD/ When used by UART, it is the receive data input UART_RXD.

GP[30]/

N13 I/O/Z DV

I2S3_RX

LCD_D[15]/

UART_TXD/ In UART mode, it is the transmit data output UART_TXD.

GP[31]/

P14 I/O/Z DV

I2S3_DX

LCD_D[13]/

UART_CTS/ In UART mode, it is the clear to send input UART_CTS.

GP[29]/

P13 I/O/Z DV

I2S3_FS

LCD_D[12]/

UART_RTS/ In UART mode, it is the ready to send output UART_RTS.

GP[28]/

N12 I/O/Z DV

I2S3_CLK

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal

TYPE

(1)

OTHER

IPD

DDIO

(2) (3)

DESCRIPTION

UART

This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge, UART, GPIO, and I2S3.

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge,UART, GPIO, and I2S3.

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

This pin is multiplexed between LCD Bridge,UART, GPIO, and I2S3.

Mux control via the PPMODE bits in the EBSR. The IPD resistor on this pin can be enabled or disabled via the PDINHIBR3 register.

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SIGNAL

NAME NO.

TYPE

(1)

OTHER

USB_MXI G13 I USB_V

USB_MXO G14 O USB_V

USB_V

DDOSC

SSOSC

G12 S Section 5.2,

F11 S Section 5.2,

USB_VBUS J12 A I/O Section 5.2,

USB_DP H14 A I/O USB_V

USB_DM J14 A I/O USB_V

USB_R1 G9 A I/O USB_V

USB_V

SSREF

DDA3P3

SSA3P3

DDA1P3

G10 GND Section 5.2,

H12 S Section 5.2,

H11 GND Section 5.2, Analog ground for USB PHY.

H10 S Section 5.2,

SPRS660B–AUGUST 2010–REVISED AUGUST 2010

Table 3-13. USB2.0 Terminal Functions

see

ROC

see

ROC

see

ROC

see

ROC

see

ROC

see

ROC

see

ROC

(2) (3)

DDOSC

DDA3P3

USB 2.0

12-MHz crystal oscillator input. When the USB peripheral is not used, USB_MXI should be connected to ground

(VSS). When using an external 12-MHz oscillator, the external oscillator clock signal should

be connected to the USB_MXI pin and the amplitude of the oscillator clock signal must meet the VIHrequirement (see Section 5.2, Recommended Operating Conditions). The USB_MXO is left unconnected and the USB_V connected to board ground (VSS).

12-MHz crystal oscillator output. When the USB peripheral is not used, USB_MXO should be left unconnected. When using an external 12-MHz oscillator, the external oscillator clock signal should

3.3-V power supply for USB oscillator. When the USB peripheral is not used, USB_V

(VSS). Ground for USB oscillator. When using a 12-MHz crystal, this pin is a local ground

for the crystal and must not be connected to the board ground (See Figure 6-7). When using an external 12-MHz oscillator, the external oscillator clock signal should

USB power detect. 5-V input that signifies that VBUS is connected. When the USB peripheral is not used, the USB_VBUS signal should be connected

to ground (VSS). USB bi-directional Data Differential signal pair [positive/negative].

When the USB peripheral is not used, the USB_DP and USB_DM signals should both be tied to ground (VSS).

External resistor connect. Reference current output. This must be connected via a 10-kΩ ±1% resistor to USB_V possible.

When the USB peripheral is not used, the USB_R1 signal should be connected via a 10-kΩ resistor to USB_V

Ground for reference current. This must be connected via a 10-kΩ ±1% resistor to USB_R1.

When the USB peripheral is not used, the USB_V directly to ground (Vss).

Analog 3.3 V power supply for USB PHY. When the USB peripheral is not used, the USB_V

connected to ground (VSS).

Analog 1.3 V power supply for USB PHY. [For high-speed sensitive analog circuits] When the USB peripheral is not used, the USB_V

connected to ground (VSS).

SSREF

DESCRIPTION

and be placed as close to the device as

SSOSC

should be connected to ground

DDOSC

SSOSC

signal should be connected

SSREF

signal should be

DDA3P3

signal should be

DDA1P3

signal is

pullup/pulldown resistors are required, see Section 4.8.1, Pullup/Pulldown Resistors.

(3) Specifies the operating I/O supply voltage for each signal

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SPRS660B–AUGUST 2010–REVISED AUGUST 2010

Table 3-13. USB2.0 Terminal Functions (continued)

SIGNAL

NAME NO.

USB_V

SSA1P3

USB_V

DD1P3

USB_V

SS1P3

USB_V

DDPLL

USB_V

SSPLL

H9 GND Section 5.2, Analog ground for USB PHY [For high speed sensitive analog circuits].

J13 S Section 5.2,

H13 GND Section 5.2, Digital core ground for USB phy.

G8 S Section 5.2,

G11 GND Section 5.2, USB Analog PLL ground.

TYPE

(1)

OTHER

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ROC

see

ROC

see

ROC

see

ROC

(2) (3)

1.3-V digital core power supply for USB PHY. When the USB peripheral is not used, the USB_V

to ground (VSS).

3.3 V USB Analog PLL power supply. When the USB peripheral is not used, the USB_V

to ground (VSS).

DESCRIPTION

signal should be connected

DD1P3

signal should be connected

DDPLL

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Specifications and Main Features

Frequently Asked Questions

User Manual

1 Fixed-Point Digital Signal Processor

1.1 Features

1.2 Description

1.3 Functional Block Diagram

2 Revision History

3 Device Overview

3.1 Device Characteristics

3.2 C55x CPU

3.2.1 On-Chip Dual-Access RAM (DARAM)

3.2.2 On-Chip Single-Access RAM (SARAM)

3.2.3 On-Chip Read-Only Memory (ROM)

3.2.4 External Memory

3.2.5 I/O Memory

3.3 Memory Map Summary

3.4 Pin Assignments

3.4.1 Pin Map (Bottom View)

3.5 Terminal Functions