Texas Instruments TMS320C3x User Manual

TMS320C3x

User’s Guide

Literature Number: SPRU031E

2558539-9761 revision L

July 1997

Printed on Recycled Paper

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TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty . T esting and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

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About This Manual

Preface

Read This First

This user’s guide serves as an applications reference book for the TMS320C3x generation of digital signal processors (DSPs). These include the TMS320C30, TMS320C31, TMS320LC31, and TMS320C32. Throughout the book, all references to ’C3x refer collectively to the ’C30, ’C31, ’LC31 and ’C32.

This book provides information to assist managers and hardware/software engineers in application development. It includes example code and hardware connections for various applications.

The guide shows how to use the instructions set, the architecture, and the ’C3x interface. It presents examples for frequently used applications and discusses more involved examples and applications. It also defines the principles involved in many applications and gives the corresponding assembly language code for instructional purposes and for immediate use. Whenever the detailed explanation of the underlying theory is too extensive to be included in this manual, appropriate references are given for further information.

Notational Conventions

This document uses the following conventions.

Program listings, program examples, and interactive displays are shown in a special typeface. Examples use a bold version of the special typeface for emphasis; interactive displays use a bold version of the special typeface to distinguish commands that you enter from items that the system displays (such as prompts, command output, error messages, etc.).

Here is a sample program listing:

0011 0005 0001 .field 1, 2 0012 0005 0003 .field 3, 4 0013 0005 0006 .field 6, 3 0014 0006 .even

Here is an example of a system prompt and a command that you might enter:

C: csr –a /user/ti/simuboard/utilities

iii

Notational Conventions

In syntax descriptions, the instruction, command, or directive is in bold typeface and parameters are in an

italic typeface

. Portions of a syntax that are in bold must be entered as shown; portions of a syntax that are in describe the type of information that must be entered. Here is an example of a directive syntax:

italics

.asect ”

The directive .asect has two parameters, indicated by

address

section name

”,

address

section name

. When you use .asect, the first parameter is an actual section

name, enclosed in double quotes; the second parameter is an address.

Square brackets ( [ and ] ) identify an optional parameter. If you use an optional parameter, you specify the information within the brackets; you do not enter the brackets themselves. Here is an example of an instruction that has an optional parameter:

LALK

16-bit constant [, shift]

The LALK instruction has two parameters. The first parameter,

constant

, is required. The second parameter,

shift

, is optional. As this syntax shows, if you use the optional second parameter, you must precede it with a comma.

Square brackets are also used as part of the pathname specification for VMS pathnames; in this case, the brackets are actually part of the pathname (they are not optional).

Braces ( { and } ) indicate a list. The symbol | (read as or) separates items within the list. Here is an example of a list:

and

16-bit

{ * | *+ | *– }

This provides three choices: *, *+, or *–. Unless the list is enclosed in square brackets, you must choose one item

from the list.

Some directives can have a varying number of parameters. For example, the .byte directive can have up to 100 parameters. The syntax for this directive is:

.byte

value1 [, ... , valuen]

This syntax shows that .byte has at least one value parameter, but you may supply additional value parameters, separated by commas.

Information About Cautions / Related Documentation from Texas Instruments

Information About Cautions

This book contains cautions.

This is an example of a caution statement. A caution statement describes a situation that could potentially

damage your software or equipment.

The information in a caution is provided for your protection. Please read each caution carefully.

References

TMS320C3x C Source Debugger User’s Guide

(literature number SPRU053) tells you how to invoke the ’C3x emulator , evaluation module, and simulator versions of the C source debugger interface. This book discusses various aspects of the debugger interface, including window management, command entry , code execution, data management, and breakpoints. It also includes a tutorial that introduces basic debugger functionality.

TMS320 DSP Development Support Reference Guide

(literature number SPRU011) describes the TMS320 family of digital signal processors and the tools that support these devices. Included are code-generation tools (compilers, assemblers, linkers, etc.) and system integration and debug tools (simulators, emulators, evaluation modules, etc.). Also covered are available documentation, seminars, the university program, and factory repair and exchange.

TMS320 Third-Party Support Reference Guide

(literature number SPRU052) alphabetically lists over 100 third parties that provide various products that serve the family of TMS320 digital signal processors. A myriad of products and applications are offered—software and hardware development tools, speech recognition, image processing, noise cancellation, modems, etc.

The publications in the following reference list contain useful information regarding functions, operations, and applications of digital signal processing (DSP). These books also provide other references to many useful technical papers. The reference list is organized into categories of general DSP , speech, image processing, and digital control theory and is alphabetized by author.

General Digital Signal Processing

Antoniou, Andreas,

Digital Filters: Analysis and Design

. New York, NY:

McGraw-Hill Company, Inc., 1979. Bateman, A., and Y ates, W.,

Digital Signal Processing Design

. Salt Lake

City, Utah: W. H. Freeman and Company, 1990. Brigham, E. Oran,

The Fast Fourier Transform.

Englewood Cliffs, NJ:

Prentice-Hall, Inc., 1974. Burrus, C.S., and Parks, T .W .,

DFT/FFT and Convolution Algorithms.

New

York, NY: John Wiley and Sons, Inc., 1984. Chassaing, R., and Horning, D.,

TMS320C25.

New York, NY: John Wiley and Sons, Inc., 1990.

Digital Signal Processing Applications with the TMS320 Family , Vol. I.

Digital Signal Processing with the

Tex-

as Instruments, 1986; Prentice-Hall, Inc., 1987.

References

Digital Signal Processing Applications with the TMS320 Family, Vol. III.

Texas Instruments, 1990; Prentice-Hall, Inc., 1990. Gold, Bernard, and Rader, C.M.

NY: McGraw-Hill Company, Inc., 1969. Hamming, R.W.,

1977. Hutchins, B., and Parks, T.,

the TMS320C25

IEEE ASSP DSP Committee (Editor), New York, NY: IEEE Press, 1979.

Jackson, Leland B., Kluwer Academic Publishers, 1986.

Jones, D.L., and Parks, T.W .,

the TMS32010.

Lim, Jae, and Oppenheim, Alan V. (Editors),

Processing

Morris, L. Robert, Carleton University, 1983.

Oppenheim, Alan V. (Editor), Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978.

Oppenheim, Alan V ., and Schafer, R.W ., wood Cliffs, NJ: Prentice-Hall, Inc., 1975.

Oppenheim, Alan V ., and Schafer, R.W ., Englewood Cliffs, NJ: Prentice-Hall, Inc., 1989.

Oppenheim, Alan V., and Willsky, A.N., with Young, I.T.,

Systems.

Parks, T .W., and Burrus, C.S., and Sons, Inc., 1987.

Rabiner, Lawrence R., and Gold, Bernard,

Signal Processing

Treichler , J.R., Johnson, Jr., C.R., and Larimore, M.G.,

of Adaptive Filters

Digital Filters

. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1990.

Digital Filters and Signal Processing.

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987.

. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1988.

Digital Signal Processing Software.

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1983.

. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975.

. New York, NY: John Wiley and Sons, Inc., 1987.

, Digital Processing of Signals.

. Englewood Cliffs, NJ: Prentice-Hall, Inc.,

New Y ork,

A Digital Signal Processing Laboratory Using

Programs for Digital Signal Processing.

Hingham, MA:

A Digital Signal Processing Laboratory Using

Advanced Topics in Signal

Ottawa, Canada:

Applications of Digital Signal Processing.

Digital Signal Processing.

Engle-

Discrete-Time Signal Processing.

Signals and

Digital Filter Design.

New Y or k, NY : John Wi ley

Theory and Application of Digital

Theory and Design

Speech

Gray , A.H., and Markel, J.D., Springer-Verlag, 1976.

Jayant, N.S., and Noll, Peter, Cliffs, NJ: Prentice-Hall, Inc., 1984.

Papamichalis, Panos, wood Cliffs, NJ: Prentice-Hall, Inc., 1987.

Linear Prediction of Speech

Digital Coding of Waveforms

Practical Approaches to Speech Coding.

. New Y ork, NY :

Read This First

. Englewood

Engle-

vii

References

Parsons, Thomas.,

Voice and Speech Processing.

McGraw Hill Company, Inc., 1987. Rabiner, Lawrence R., and Schafer, R.W.,

Signals.

Shaughnessy , Douglas.,

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978.

Speech Communication.

Digital Processing of Speech

Wesley, 1987.

Image Processing

Andrews, H.C., and Hunt, B.R.,

Digital Image Restoration

Cliffs, NJ: Prentice-Hall, Inc., 1977. Gonzales, Rafael C., and Wintz, Paul,

Digital Image Processing.

MA: Addison-Wesley Publishing Company, Inc., 1977. Pratt, William K.,

Digital Image Processing

. New Y ork, NY: John Wiley and

Sons, 1978.

Multirate DSP

Crochiere, R.E., and Rabiner, L.R.,

Multirate Digital Signal Processing

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1983. V aidyanathan, P .P .,

Multirate Systems and Filter Banks

NJ: Prentice-Hall, Inc.

Digital Control Theory

New York, NY:

Reading, MA: Addison-

. Englewood

Reading,

. Englewood Cliffs,

viii

Dote, Y .,

Servo Motor and Motion Control Using Digital Signal Processors

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1990. Jacquot, R.,

Modern Digital Control Systems.

New Y ork, NY: Marcel Dekker,

Inc., 1981. Katz, P.,

Digital Control Using Microprocessors

. Englewood Cliffs, NJ:

Prentice-Hall, Inc., 1981. Kuo, B.C.,

Digital Control Systems.

New York, NY: Holt, Reinholt and

Winston, Inc., 1980. Moroney , P .,

tors.

Cambridge, MA: The MIT Press, 1983.

Phillips, C., and Nagle, H.,

Issues in the Implementation of Digital Feedback Compensa-

Digital Control System Analysis and Design.

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984.

Adaptive Signal Processing

Haykin, S.,

Adaptive Filter Theory.

Englewood Cliffs, NJ: Prentice-Hall,

Inc., 1991. Widrow, B., and Stearns, S.D.

Adaptive Signal Processing.

Englewood

Cliffs, NJ: Prentice-Hall, Inc., 1985.

Array Signal Processing

References

Haykin, S., Justice, J.H., Owsley, N.L., Y en, J.L., and Kak, A.C.

Processing.

Hudson, J.E.

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1985.

Adaptive Array Principles.

New York, NY: John Wiley and

Sons, 1981. Monzingo, R.A., and Miller, J.W.

Introduction to Adaptive Arrays.

NY: John Wiley and Sons, 1980.

Array Signal

New Y or k,

Read This First

If You Need Assistance

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Read This First

Contents

1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A general description of the TMS320C30, TMS320C31, and TMS320C32, their key features, and typical applications.

1.1 TMS320C3x Devices 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.1 TMS320C3x Key Specifications 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.2 TMS320C30 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.3 TMS320C31 and TMS320LC31 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.4 TMS320C32 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Typical Applications 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Architectural Overview 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional block diagram, ’C3x design description, hardware components, device operation, and instruction set summary.

2.1 Overview 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Central Processing Unit (CPU) 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Floating-Point/Integer Multiplier 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Arithmetic Logic Unit (ALU) and Internal Buses 2-8. . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3 Auxiliary Register Arithmetic Units (ARAUs) 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 CPU Primary Register File 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Other Registers 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Memory Organization 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1 RAM, ROM, and Cache 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2 Memory Addressing Modes 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Internal Bus Operation 2-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 External Memory Interface 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.1 TMS320C32 16- and 32-Bit Program Memory 2-19. . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.2 TMS320C32 8-, 16-, and 32-Bit Data Memory 2-20. . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Interrupts 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Peripherals 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.1 Timers 2-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.2 Serial Ports 2-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10 Direct Memory Access (DMA) 2-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 TMS320C30, TMS320C31, and TMS320C32 Differences 2-26. . . . . . . . . . . . . . . . . . . . . . .

xiii

Contents

3 CPU Registers 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Description of the registers in the CPU register file.

3.1 CPU Multiport Register File 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.1 Extended-Precision Registers (R7–R0) 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.2 Auxiliary Registers (AR7–AR0) 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.3 Data-Page Pointer (DP) 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.4 Index Registers (IR0, IR1) 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.5 Block Size (BK) Register 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.6 System-Stack Pointer (SP) 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.7 Status (ST) Register 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.8 CPU/DMA Interrupt-Enable (IE) Register 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.9 CPU Interrupt Flag (IF) Register 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.10 I/O Flag (IOF) Register 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.11 Repeat-Counter (RC) and Block-Repeat (RS, RE) Registers 3-17. . . . . . . . . . . . .

3.2 Other Registers 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Program-Counter (PC) Register 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2 Instruction Register (IR) 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Reserved Bits and Compatibility 3-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Memory and the Instruction Cache 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Description of memory maps with explanation of instruction cache architecture, algorithm, and control bits.

4.1 Memory 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1 Memory Maps 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.2 Peripheral Bus Memory Map 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Reset/Interrupt/Trap Vector Map 4-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Instruction Cache 4-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1 Instruction-Cache Architecture 4-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.2 Instruction-Cache Algorithm 4-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.3 Cache Control Bits 4-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Data Formats and Floating-Point Operation 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Description of signed and unsigned integer and floating-point formats. Discussion of floatingpoint multiplication, addition, subtraction, normalization, rounding, and conversions.

5.1 Integer Formats 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.1 Short-Integer Format 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.2 Single-Precision Integer Format 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Unsigned-Integer Formats 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.1 Short Unsigned-Integer Format 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.2 Single-Precision Unsigned-Integer Format 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Floating-Point Formats 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.1 Short Floating-Point Format 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.2 TMS320C32 Short Floating-Point Format for External 16-Bit Data 5-6. . . . . . . . .

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5.3.3 Single-Precision Floating-Point Format 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.4 Extended-Precision Floating-Point Format 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.5 Determining the Decimal Equivalent of a TMS320C3x

Floating-Point Format 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.6 Conversion Between Floating-Point Formats 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Floating-Point Conversion (IEEE Std. 754) 5-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.1 Converting IEEE Format to 2s-Complement TMS320C3x

Floating-Point Format 5-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.2 Converting 2s-Complement TMS320C3x Floating-Point Format

to IEEE Format 5-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Floating-Point Multiplication 5-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Floating-Point Addition and Subtraction 5-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 Normalization Using the NORM Instruction 5-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8 Rounding (RND Instruction) 5-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9 Floating-Point to Integer Conversion (FIX Instruction) 5-41. . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10 Integer to Floating-Point Conversion (FLOAT Instruction) 5-43. . . . . . . . . . . . . . . . . . . . . . .

5.11 Fast Logarithms on a Floating-Point Device 5-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11.1 Example of Fast Logarithm on a Floating-Point Device 5-45. . . . . . . . . . . . . . . . . .

5.11.2 Points to Consider 5-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Addressing Modes 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operation, encoding, and implementation of addressing modes; format descriptions; system stack management.

6.1 Addressing Types 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Register Addressing 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Direct Addressing 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Indirect Addressing 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5 Immediate Addressing 6-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6 PC-Relative Addressing 6-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.7 Circular Addressing 6-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8 Bit-Reversed Addressing 6-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.9 Aligning Buffers With the TMS320 Floating-Point DSP Assembly Language Tools 6-28. . . .

6.10 System and User Stack Management 6-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.10.1 System-Stack Pointer 6-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.10.2 Stacks 6-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.10.3 Queues 6-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Program Flow Control 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Software control of program flow with repeat modes and branching; interlocked operations; reset and interrupts.

7.1 Repeat Modes 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.1 Repeat-Mode Control Bits 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.2 Repeat-Mode Operation 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.3 RPTB Instruction 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

7.1.4 RPTS Instruction 7-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.5 Repeat-Mode Restrictions 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.6 RC Register Value After Repeat Mode Completes 7-7. . . . . . . . . . . . . . . . . . . . . . .

7.1.7 Nested Block Repeats 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 Delayed Branches 7-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 Calls, Traps, and Returns 7-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 Interlocked Operations 7-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.1 Interrupting Interlocked Operations 7-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.2 Using Interlocked Operations 7-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.3 Pipeline Effects of Interlocked Instructions 7-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5 Reset Operation 7-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6 Interrupts 7-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.1 TMS320C30 and TMS320C31 Interrupt Vector Table 7-26. . . . . . . . . . . . . . . . . . . .

7.6.2 TMS320C32 Interrupt Vector Table 7-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.3 Interrupt Prioritization 7-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.4 CPU Interrupt Control Bits 7-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.5 Interrupt Flag Register Behavior 7-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.6 Interrupt Processing 7-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.7 CPU Interrupt Latency 7-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.8 External Interrupts 7-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7 DMA Interrupts 7-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7.1 DMA Interrupt Control Bits 7-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7.2 DMA Interrupt Processing 7-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7.3 CPU/DMA Interaction 7-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7.4 TMS320C3x Interrupt Considerations 7-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7.5 TMS320C30 Interrupt Considerations 7-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8 Traps 7-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8.1 Initialization of Traps and Interrupts 7-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8.2 Operation of Traps 7-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.9 Power Management Modes 7-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.9.1 IDLE2 Power-Down Mode 7-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.9.2 LOPOWER 7-51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 Pipeline Operation 8-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Discussion of the pipeline of operations on the TMS320C3x

8.1 Pipeline Structure 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2 Pipeline Conflicts 8-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.1 Branch Conflicts 8-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.2 Register Conflicts 8-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2.3 Memory Conflicts 8-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3 Resolving Register Conflicts 8-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4 Memory Access for Maximum Performance 8-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.5 Clocking Memory Accesses 8-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.5.1 Program Fetches 8-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.5.2 Data Loads and Stores 8-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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9 TMS320C30 and TMS320C31 External-Memory Interface 9-1. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Description of primary and expansion interfaces for the ’C30 and ’C31; external interface timing diagrams; programmable wait-states and bank switching.

9.1 Overview 9-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2 Memory Interface Signals 9-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2.1 TMS320C30 Memory Interface Signals 9-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.2.2 TMS320C31 Memory Interface Signals 9-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3 Memory Interface Control Registers 9-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3.1 Primary-Bus Control Register 9-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3.2 Expansion-Bus Control Register 9-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.4 Programmable Wait States 9-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.5 Programmable Bank Switching 9-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.6 External Memory Interface Timing 9-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.6.1 Primary-Bus Cycles 9-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.6.2 Expansion-Bus I/O Cycles 9-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.6.3 Hold Cycles 9-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 TMS320C32 Enhanced External Memory Interface 10-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Description of primary and expansion interfaces for the ’C32; external interface timing diagrams; programmable wait-states and bank switching.

10.1 TMS320C32 Memory Features 10-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2 TMS320C32 Memory Overview 10-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2.1 External Memory Interface Overview 10-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2.2 Program Memory Access 10-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2.3 Data Memory Access 10-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3 Configuration 10-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3.1 External Interface Control Registers 10-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3.2 Using Physical Memory Width and Data-Type Size Fields 10-13. . . . . . . . . . . . .

10.4 Programmable Wait States 10-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.5 Programmable Bank Switching 10-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.6 32-Bit-Wide Memory Interface 10-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.7 16-Bit-Wide Memory Interface 10-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.8 8-Bit-Wide Memory Interface 10-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.9 External Ready Timing Improvement 10-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.10 Bus Timing 10-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.10.1 STRB0

10.10.2 IOSTRB

and STRB1 Bus Cycles 10-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus Cycles 10-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.10.3 Inactive Bus States 10-51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11 Using the TMS320C31 and TMS320C32 Boot Loaders 11-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Description of the boot loader operations for the ’C31 and ’C32.

11.1 TMS320C31 Boot Loader 11-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1.1 TMS320C31 Boot-Loader Description 11-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1.2 TMS320C31 Boot-Loader Mode Selection 11-2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

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11.1.3 TMS320C31 Boot-Loading Sequence 11-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1.4 TMS320C31 Boot Data Stream Structure 11-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1.5 Interrupt and Trap-Vector Mapping 11-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1.6 TMS320C31 Boot-Loader Precautions 11-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2 TMS320C32 Boot Loader 11-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2.1 TMS320C32 Boot-Loader Description 11-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2.2 TMS320C32 Boot-Loader Mode Selection 11-14. . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2.3 TMS320C32 Boot-Loading Sequence 11-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2.4 TMS320C32 Boot Data Stream Structure 11-20. . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2.5 Boot-Loader Hardware Interface 11-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2.6 TMS320C32 Boot-Loader Precautions 11-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12 Peripherals 12-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Description of the DMA controller, timers, and serial ports.

12.1 Timers 12-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1.1 Timer Pins 12-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1.2 Timer Control Registers 12-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1.3 Timer Global-Control Register 12-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1.4 Timer-Period and Counter Registers 12-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1.5 Timer Pulse Generation 12-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1.6 Timer Operation Modes 12-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1.7 Using TCLKx as General-Purpose I/O Pins 12-12. . . . . . . . . . . . . . . . . . . . . . . . . .

12.1.8 Timer Interrupts 12-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1.9 Timer Initialization/Reconfiguration 12-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2 Serial Ports 12-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.1 Serial-Port Global-Control Register 12-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.2 FSX/DX/CLKX Port-Control Register 12-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.3 FSR/DR/CLKR Port-Control Register 12-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.4 Receive/Transmit Timer-Control Register 12-25. . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.5 Receive/Transmit Timer-Counter Register 12-27. . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.6 Receive/Transmit Timer-Period Register 12-28. . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.7 Data-Transmit Register 12-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.8 Data-Receive Register 12-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.9 Serial-Port Operation Configurations 12-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.10 Serial-Port Timing 12-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.11 Serial-Port Interrupt Sources 12-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.12 Serial-Port Functional Operation 12-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.13 Serial-Port Initialization/Reconfiguration 12-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.14 TMS320C3x Serial-Port Interface Examples 12-41. . . . . . . . . . . . . . . . . . . . . . . . .

12.3 DMA Controller 12-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3.1 DMA Functional Description 12-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3.2 DMA Basic Operation 12-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3.3 DMA Registers 12-51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3.4 CPU/DMA Interrupt-Enable Register 12-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xviii

Contents

12.3.5 TMS320C32 DMA Internal Priority Schemes 12-62. . . . . . . . . . . . . . . . . . . . . . . . .

12.3.6 CPU and DMA Controller Arbitration 12-63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3.7 DMA and Interrupts 12-64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3.8 DMA Memory Transfer Timing 12-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3.9 DMA Initialization/Reconfiguration 12-73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3.10 Hints for DMA Programming 12-73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.3.11 DMA Programming Examples 12-74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13 Assembly Language Instructions 13-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional listing of instructions. Condition codes defined. Alphabetized individual instruction set with examples.

13.1 Instruction Set 13-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.1 Load and Store Instructions 13-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.2 2-Operand Instructions 13-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.3 3-Operand Instructions 13-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.4 Program-Control Instructions 13-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.5 Low-Power Control Instructions 13-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.6 Interlocked-Operations Instructions 13-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.7 Parallel-Operations Instructions 13-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.1.8 Illegal Instructions 13-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.2 Instruction Set Summary 13-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.3 Parallel Instruction Set Summary 13-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4 Group Addressing Mode Instruction Encoding 13-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4.1 General Addressing Modes 13-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4.2 3-Operand Addressing Modes 13-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4.3 Parallel Addressing Modes 13-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.4.4 Conditional-Branch Addressing Modes 13-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.5 Condition Codes and Flags 13-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.6 Individual Instructions 13-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.6.1 Symbols and Abbreviations 13-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.6.2 Optional Assembler Syntax 13-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13.6.3 Individual Instruction Descriptions 13-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A Instruction Opcodes A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of the opcode fields for the TMS320C3x instructions.

B TMS320C31 Boot Loader Source Code B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C TMS320C32 Boot Loader Source Code C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C.1 Boot-Loader Source Code Description C-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C.2 Boot-Loader Source Code Listing C-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D Glossary D-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xix

Figures

1–1 TMS320C3x Devices Block Diagram 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 TMS320C30 Block Diagram 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 TMS320C31 Block Diagram 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 TMS320C32 Block Diagram 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 Central Processing Unit (CPU) 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Memory Organization of the TMS320C30 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Memory Organization of the TMS320C31 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Memory Organization of the TMS320C32 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 TMS320C32-Supported Data Types and Sizes and External Memory Widths 2-20. . . . . . . .

2–9 Peripheral Modules 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–10 DMA Controller 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Extended-Precision Register Floating-Point Format 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Extended-Precision Register Integer Format 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 Status Register (TMS320C30 andTMS320C31) 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 Status Register (TMS320C32 Only) 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 CPU/DMA Interrupt-Enable (IE) Register (TMS320C30 and TMS320C31) 3-9. . . . . . . . . . .

3–6 CPU/DMA Interrupt-Enable (IE) Register (TMS320C32) 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–7 TMS320C30 CPU Interrupt Flag (IF) Register 3-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–8 TMS320C31 CPU Interrupt Flag (IF) Register 3-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–9 TMS320C32 CPU Interrupt Flag (IF) Register 3-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–10 Effective Base Address of the Interrupt-Trap Vector Table 3-14. . . . . . . . . . . . . . . . . . . . . . . . .

3–11 Interrupt and Trap Vector Locations 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–12 I/O Flag (IOF) Register 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 TMS320C30 Memory Maps 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 TMS320C31 Memory Maps 4-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 TMS320C32 Memory Maps 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 TMS320C30 Peripheral Bus Memory-Mapped Registers 4-10. . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 TMS320C31 Peripheral Bus Memory-Mapped Registers 4-11. . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 TMS320C32 Peripheral Bus Memory-Mapped Registers 4-13. . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 Reset, Interrupt, and Trap Vector Locations for the TMS320C30 4–8 Reset, Interrupt, and Trap Vector Locations for theTMS320C31

4–9 Interrupt and Trap Branch Instructions for the TMS320C31 Microcomputer Mode 4-17. . . . .

4–10 Interrupt and Trap Vector Locations for TMS320C32 4-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–11 Address Partitioning for Cache Control Algorithm 4-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–12 Instruction-Cache Architecture 4-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Microprocessor Mode 4-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Microprocessor Mode 4-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figures

5–1 Short-Integer Format and Sign-Extension of Short Integers 5-2. . . . . . . . . . . . . . . . . . . . . . . . .

5–2 Single-Precision Integer Format 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 Short Unsigned-Integer Format and Zero Fill 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–4 Single-Precision Unsigned-Integer Format 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–5 General Floating-Point Format 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–6 Short Floating-Point Format 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–7 TMS320C32 Short Floating-Point Format for External 16-Bit Data 5-6. . . . . . . . . . . . . . . . . . .

5–8 Single-Precision Floating-Point Format 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–9 Extended-Precision Floating-Point Format 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–10 Converting from Short Floating-Point Format to Single-Precision

Floating-Point Format 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11 Converting from Short Floating-Point Format to Extended-Precision

Floating-Point Format 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–12 Converting from Single-Precision Floating-Point Format to Extended-Precision

Floating-Point Format 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–13 Converting from Extended-Precision Floating-Point Format to Single-Precision

Floating-Point Format 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–14 IEEE Single-Precision Std. 754 Floating-Point Format 5-14. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–15 TMS320C3x Single-Precision 2s-Complement Floating-Point Format 5-15. . . . . . . . . . . . . . .

5–16 Flowchart for Floating-Point Multiplication 5-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–17 Flowchart for Floating-Point Addition 5-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–18 Flowchart for NORM Instruction Operation 5-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–19 Flowchart for Floating-Point Rounding by the RND Instruction 5-40. . . . . . . . . . . . . . . . . . . . .

5–20 Flowchart for Floating-Point to Integer Conversion by FIX Instruction 5-42. . . . . . . . . . . . . . .

5–21 Flowchart for Integer to Floating-Point Conversion by FLOAT Instruction 5-43. . . . . . . . . . . .

5–22 Tabulated Values for Mantissa 5-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–23 Fast Logarithm for FFT Displays 5-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 Direct Addressing 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 Indirect Addressing Operand Encoding 6-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–3 Encoding for 24-Bit PC-Relative Addressing Mode 6-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–4 Logical and Physical Representation of Circular Buffer 6-21. . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–5 Logical and Physical Representation of Circular Buffer after Writing Three Values 6-21. . . .

6–6 Logical and Physical Representation of Circular Buffer after Writing Eight Values 6-22. . . . .

6–7 Circular Buffer Implementation 6-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–8 Data Structure for FIR Filters 6-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–9 System Stack Configuration 6-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–10 Implementations of High-to-Low Memory Stacks 6-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–11 Implementations of Low-to-High Memory Stacks 6-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–1 CALL Response Timing 7-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2 Multiple TMS320C3xs Sharing Global Memory 7-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3 Zero-Logic Interconnect of TMS320C3x Devices 7-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4 Effective Base Address of the Interrupt-Trap-Vector Table 7-29. . . . . . . . . . . . . . . . . . . . . . . . .

7–5 IF Register Modification 7-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–6 CPU Interrupt Processing 7-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–7 Interrupt Logic Functional Diagram 7-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xxi

Figures

7–8 DMA Interrupt Processing 7-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–9 Parallel CPU and DMA Interrupt Processing 7-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–10 Flow of Traps 7-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–11 IDLE2 Timing 7-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–12 Interrupt Response Timing After IDLE2 Operation 7-51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–13 LOPOWER Timing 7-52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–14 MAXSPEED Timing 7-52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–1 TMS320C3x Pipeline Structure 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–2 Minor Clock Periods 8-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–3 2-Operand Instruction Word 8-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–4 3-Operand Instruction Word 8-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–5 Multiply or CPU Operation With a Parallel Store 8-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–6 Two Parallel Stores 8-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–7 Parallel Multiplies and Adds 8-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–1 Memory-Mapped External Interface Control Registers 9-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–2 Primary-Bus Control Register 9-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–3 Expansion-Bus Control Register 9-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–4 BNKCMP Example 9-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–5 Bank-Switching Example 9-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–6 Read-Read-Write for (M)STRB

= 0 9-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–7 Write-Write-Read for (M)STRB = 0 9-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–8 Use of Wait States for Read for (M)STRB = 0 9-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–9 Use of Wait States for Write for (M)STRB = 0 9-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–10 Read and Write for IOSTRB

= 0 9-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–11 Read With One Wait State for IOSTRB = 0 9-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–12 Write With One Wait State for IOSTRB = 0 9-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–13 Memory Read and I/O Write for Expansion Bus 9-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–14 Memory Read and I/O Read for Expansion Bus 9-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–15 Memory Write and I/O Write for Expansion Bus 9-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–16 Memory Write and I/O Read for Expansion Bus 9-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–17 I/O Write and Memory Write for Expansion Bus 9-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–18 I/O Write and Memory Read for Expansion Bus 9-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–19 I/O Read and Memory Write for Expansion Bus 9-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–20 I/O Read and Memory Read for Expansion Bus 9-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–21 I/O Write and I/O Read for Expansion Bus 9-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–22 I/O Write and I/O Write for Expansion Bus 9-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–23 I/O Read and I/O Read for Expansion Bus 9-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–24 Inactive Bus States for IOSTRB 9–25 Inactive Bus States for STRB

and MSTRB 9-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–26 HOLD and HOLDA Timing 9-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–1 Memory Address Spaces 10-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–2 Status Register 10-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–3 Memory-Mapped External Interface Control Registers 10-7. . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–4 STRB0

Control Register 10-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xxii

Figures

10–5 STRB1 Control Register 10-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–6 IOSTRB

Control Register 10-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–7 STRB Configuration 10-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–8 BNKCMP Example 10-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–9 Bank-Switching Example 10-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–10 TMS320C32 External Memory Interface for 32-Bit SRAMs 10-20. . . . . . . . . . . . . . . . . . . . . . .

10–1 1 Functional Diagram for 8-Bit Data-Type Size and 32-Bit External-Memory . . . . . . . . . . . . . . . .

Width 10-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–12 Functional Diagram for 16-Bit Data-Type Size and 32-Bit External-Memory . . . . . . . . . . . . .

Width 10-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–13 Functional Diagram for 32-Bit Data Size and 32-Bit External-Memory Width 10-24. . . . . . . .

10–14 External-Memory Interface for 16-Bit SRAMs 10-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–15 Functional Diagram for 8-Bit Data-Type Size and 16-Bit External-Memory Width 10-27. . . .

10–16 Functi onal Diagram for 16-Bit Data-Type Size and 16-Bit External-Memory Width 10-29. . . . .

10–17 Functi onal Diagram for 32-Bit Data-Type Size and 16-Bit External-Memory Width 10-30. . . . .

10–18 External Memory Interface for 8-Bit SRAMs 10-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–19 Functional Diagram for 8-Bit Data-Type Size and 8-Bit External-Memory Width 10-33. . . . . .

10–20 Functional Diagram for 16-Bit Data-Type Size and 8-Bit External-Memory Width 10-34. . . .

10–21 Functional Diagram for 32-Bit Data-Type Size and 8-Bit External-Memory Width 10-36. . . .

10–22 RDY

Timing for Memory Read 10-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–23 Read-Read-Write Sequence for STRBx Active 10-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–24 Write-Write-Read Sequence for STRBx Active 10-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–25 One Wait-State Read Sequence for STRBx

Active 10-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–26 One Wait-State Write Sequence for STRBx Active 10-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–27 Zero Wait-State Read and Write Sequence for IOSTRB

Active 10-43. . . . . . . . . . . . . . . . . . . .

10–28 One Wait-State Read Sequence for IOSTRB Active 10-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–29 One Wait-State Write Sequence for IOSTRB Active 10-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–30 STRBx Read and IOSTRB Write 10-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–31 STRBx

Read and IOSTRB Read 10-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–32 STRBx Write and IOSTRB Write 10-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–33 STRBx

Write and IOSTRB Read 10-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–34 IOSTRB Write and STRBx Write 10-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–35 IOSTRB

Write and STRBx Read 10-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–36 IOSTRB Read and STRBx Write 10-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–37 IOSTRB Read and STRBx Read 10-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–38 IOSTRB

Write and Read 10-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–39 IOSTRB Write and Write 10-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–40 IOSTRB

Read and Read 10-51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–41 Inactive Bus States Following IOSTRB Bus Cycle 10-51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–42 Inactive Bus States Following STRBx Bus Cycle 10-52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–1 TMS320C31 Boot-Loader Mode-Selection Flowchart 11-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–2 Boot-Loader Memory-Load Flowchart 11-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–3 Boot-Loader Serial-Port Load-Mode Flowchart 11-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–4 TMS320C32 Boot-Loader Mode-Selection Flowchart 11-17. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xxiii

Figures

11–5 Boot-Loader Serial-Port Load Flowchart 11-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–6 Boot-Loader Memory-Load Flowchart 11-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–7 Handshake Data-Transfer Operation 11-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–8 External Memory Interface for Source Data Stream Memory Boot Load 11-23. . . . . . . . . . . .

12–1 Timer Block Diagram 12-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–2 Memory-Mapped Timer Locations 12-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–3 Timer Global-Control Register 12-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–4 Timer Timing 12-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–5 Timer Configuration with CLKSRC = 1 and FUNC = 0 12-10. . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–6 Timer Configuration with CLKSRC = 1 and FUNC = 1 12-11. . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–7 Timer Configuration with CLKSRC = 0 and FUNC = 0 12-11. . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–8 Timer Configuration with CLKSRC = 0 and FUNC = 1 12-12. . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–9 TCLK as an Input (I/O = 0) 12-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–10 TCLK as an Output (I/O = 1) 12-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–11 Serial Port Block Diagram 12-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–12 Memory-Mapped Locations for the Serial Ports 12-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–13 Serial-Port Global-Control Register 12-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–14 FSX/DX/CLKX Port-Control Register 12-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–15 FSR/DR/CLKR Port-Control Register 12-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–16 Receive/Transmit Timer-Control Register 12-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–17 Receive/Transmit Timer-Counter Register 12-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–18 Receive/Transmit Timer-Period Register 12-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–19 Transmit Buffer Shift Operation 12-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–20 Receive Buffer Shift Operation 12-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–21 Serial-Port Clocking in I/O Mode 12-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–22 Serial-Port Clocking in Serial-Port Mode 12-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–23 Data Word Format in Handshake Mode 12-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–24 Single 0 Sent as an Acknowledge Bit 12-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–25 Direct Connection Using Handshake Mode 12-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–26 Fixed Burst Mode 12-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–27 Fixed Standard Mode With Back-to-Back Frame Sync 12-37. . . . . . . . . . . . . . . . . . . . . . . . . . .

12–28 Fixed Continuous Mode Without Frame Sync 12-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–29 Exiting Fixed Continuous Mode Without Frame Sync, FSX Internal 12-39. . . . . . . . . . . . . . . .

12–30 Variable Burst Mode 12-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–31 Variable Standard Mode With Back-to-Back Frame Syncs 12-40. . . . . . . . . . . . . . . . . . . . . . . .

12–32 Variable Continuous Mode Without Frame Sync 12-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–33 TMS320C3x Zero-Glue-Logic Interface to TLC320C4x Example 12-45. . . . . . . . . . . . . . . . . .

12–34 DMA Basic Operation 12-51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–35 Memory-Mapped Locations for DMA Channels 12-52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–36 TMS320C30 and TMS320C31 DMA Global-Control Register 12-53. . . . . . . . . . . . . . . . . . . . .

12–37 TMS320C32 DMA0 Global-Control Register 12-53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–38 TMS320C32 DMA1 Global-Control Register 12-53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–39 DMA Controller Address Generation 12-57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–40 Transfer-Counter Operation 12-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xxiv

Figures

12–41 TMS320C30 and TMS320C31 CPU/DMA Interrupt-Enable Register 12-60. . . . . . . . . . . . . . .

12–42 TMS320C32 CPU/DMA Interrupt-Enable Register 12-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–43 Mechanism for No DMA Synchronization 12-65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–44 Mechanism for DMA Source Synchronization 12-66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–45 Mechanism for DMA Destination Synchronization 12-66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–46 Mechanism for DMA Source and Destination Synchronization 12-67. . . . . . . . . . . . . . . . . . . .

12–47 DMA Timing When Destination is On Chip 12-69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–48 DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus 12-70. . . . . . . . . .

12–49 DMA Timing When Destination is an IOSTRB Bus 12-72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–1 Encoding for General Addressing Modes 13-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–2 Encoding for 3-Operand Addressing Modes 13-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–3 Encoding for Parallel Addressing Modes 13-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–4 Encoding for Extended Parallel Addressing Instructions 13-26. . . . . . . . . . . . . . . . . . . . . . . . . .

13–5 Encoding for Conditional-Branch Addressing Modes 13-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–6 Status Register 13-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C–1 Boot-Loader Flow Chart C-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xxv

Tables

1–1 TMS320C30, TMS320C31, TMS320LC31, and TMS320C32 Comparison 1-5. . . . . . . . . . . .

1–2 Typical Applications of the TMS320 Family 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 Primary CPU Registers 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Feature Set Comparison 2-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 CPU Registers 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Status Register Bits 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 IE Bits and Functions 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 IF Bits and Functions 3-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 IOF Bits and Functions 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 Combined Effect of the CE and CF Bits 4-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 Converting IEEE Format to 2s-Complement Floating-Point Format 5-15. . . . . . . . . . . . . . . . .

5–2 Converting 2s-Complement Floating-Point Format to IEEE Format 5-21. . . . . . . . . . . . . . . . .

5–3 Squaring Operation of F0 = 1.5 5-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 CPU Register Address/Assembler Syntax and Function 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 Indirect Addressing 6-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–3 Index Steps and Bit-Reversed Addressing 6-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–1 Repeat-Mode Registers 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2 Interlocked Operations 7-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3 TMS320C3x Pin Operation at Reset 7-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4 Reset, Interrupt, and Trap-Vector Locations for the TMS320C30/TMS320C31 7–5 Reset, Interrupt, and Trap-Branch Locations for the TMS320C31

7–6 Interrupt and Trap-Vector Locations for the TMS320C32 7-30. . . . . . . . . . . . . . . . . . . . . . . . . .

7–7 Reset and Interrupt Vector Priorities 7-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–8 Interrupt Latency 7-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–9 Pipeline Operation with PUSH ST 7-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–10 Pipeline Operation with Load Followed by Interrupt 7-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–1 One Program Fetch and One Data Access for Maximum Performance 8-22. . . . . . . . . . . . . .

8–2 One Program Fetch and Two Data Accesses for Maximum Performance 8-23. . . . . . . . . . . .

9–1 Primary Bus Interface Signals 9-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–2 Expansion Bus Interface Signals 9-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–3 Primary-Bus Control Register Bits 9-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–4 Expansion-Bus Control Register Bits 9-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–5 Wait-State Generation 9-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9–6 BNKCMP and Bank Size 9-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–1 STRB0

Microprocessor Mode 7-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Microcomputer Boot Mode 7-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

, STRB1, and IOSTRB Control Register Bits 10-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xxvi

Tables

10–2 Data-Access Sequence for a Memory Configuration with Two Banks 10-14. . . . . . . . . . . . . . .

10–3 Wait-State Generation 10-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–4 BNKCMP and Bank Size 10-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–5 Strobe Byte-Enable for 32-Bit-Wide Memory With 8-Bit Data-T ype Size 10-21. . . . . . . . . . . .

10–6 Example of 8-Bit Data-Type Size 10-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10–7 Strobe Byte-Enable for 32-Bit-Wide Memory With 16-Bit Data-T ype Size 10-22. . . . . . . . . . .

10–8 Example of 16-Bit Data-Type Size and 32-Bit-Wide External Memory 10-23. . . . . . . . . . . . . .

10–9 Example of 32-Bit-Wide Memory With 32-Bit Data-Type Size 10-25. . . . . . . . . . . . . . . . . . . . .

10–10 Strobe-Byte Enable Behavior for 16-Bit-Wide Memory with 8-Bit Data-Type Size 10-27. . . .

10–11 Example of 8-Bit Data-Type Size and 16-Bit-Wide External Memory 10-28. . . . . . . . . . . . . . .

10–12 Example of 16-Bit-Wide Memory With 16-Bit Data-Type Size 10-29. . . . . . . . . . . . . . . . . . . . .

10–13 Example of 16-Bit-Wide Memory With 32-Bit Data-Type Size 10-31. . . . . . . . . . . . . . . . . . . . .

10–14 Example of 8-Bit-Wide Memory With 8-Bit Data-Type Size 10-33. . . . . . . . . . . . . . . . . . . . . . . .

10–15 Example of 8-Bit-Wide Memory With 16-Bit Data-Type Size 10-35. . . . . . . . . . . . . . . . . . . . . . .

10–16 Example of 32-Bit Data-Type Size and 8-Bit-Wide Memory 10-37. . . . . . . . . . . . . . . . . . . . . . .

11–1 Boot-Loader Mode Selection 1 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–2 Source Data Stream Structure 11-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–3 Byte-Wide Configured Memory 11-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–4 16-Bit-Wide Configured Memory 11-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–5 32-Bit-Wide Configured Memory 11-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–6 TMS320C31 Interrupt and Trap Memory Maps 11-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–7 Boot-Loader Mode Selection 11-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11–8 Source Data Stream Structure 11-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–1 Timer Global-Control Register Bits Summary 12-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–2 Serial-Port Global-Control Register Bits Summary 12-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–3 FSX/DX/CLKX Port-Control Register Bits Summary 12-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–4 FSR/DR/CLKR Port-Control Register Bits Summary 12-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–5 Receive/Transmit Timer-Control Register Register Bits Summary 12-25. . . . . . . . . . . . . . . . .

12–6 DMA Global-Control Register Bits Summary 12-54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–7 CPU/DMA Interrupt-Enable Register Bits 12-61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–8 TMS320C32 DMA PRI Bits and CPU/DMA Arbitration Rules 12-64. . . . . . . . . . . . . . . . . . . . . .

13–1 Load and Store Instructions 13-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–2 2-Operand Instructions 13-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–3 3-Operand Instructions 13-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–4 Program-Control Instructions 13-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–5 Low-Power Control Instructions 13-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–6 Interlocked-Operations Instructions 13-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–7 Parallel Instructions 13-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–8 Instruction Set Summary 13-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–9 Parallel Instruction Set Summary 13-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–10 Indirect Addressing 13-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–11 Output Value Formats 13-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–12 Condition Codes and Flags 13-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–13 Instruction Symbols 13-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13–14 CPU Register Syntax 13-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–1 TMS320C3x Instruction Opcodes A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xxvii

Examples

4–1 Pipeline Effects of Modifying the Cache Control Bits 4-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 Positive Number 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 Negative Number 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 Fractional Number 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–4 IEEE-to-TMS320C3x Conversion (Fast Version) 5-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–5 IEEE-to-TMS320C3x Conversion (Complete Version) 5-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–6 TMS320C3x-to-IEEE Conversion (Fast Version) 5-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–7 TMS320C3x-to-IEEE Conversion (Complete Version) 5-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–8 Floating-Point Multiply (Both Mantissas = –2.0) 5-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–9 Floating-Point Multiply (Both Mantissas = 1.5) 5-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–10 Floating-Point Multiply (Both Mantissas = 1.0) 5-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11 Floating-Point Multiply Between Positive and Negative Numbers 5-31. . . . . . . . . . . . . . . . . . .

5–12 Floating-Point Multiply by 0 5-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–13 Floating-Point Addition 5-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–14 Floating-Point Subtraction 5-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–15 Floating-Point Addition With a 32-Bit Shift 5-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–16 Floating-Point Addition/Subtraction With Floating-Point 0 5-36. . . . . . . . . . . . . . . . . . . . . . . . .

5–17 NORM Instruction 5-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 Direct Addressing 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 Auxiliary Register Indirect 6-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–3 Indirect Addressing With Predisplacement Add 6-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–4 Indirect Addressing With Predisplacement Subtract 6-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–5 Indirect Addressing With Predisplacement Add and Modify 6-10. . . . . . . . . . . . . . . . . . . . . . . .

6–6 Indirect Addressing With Predisplacement Subtract and Modify 6-10. . . . . . . . . . . . . . . . . . . .

6–7 Indirect Addressing With Postdisplacement Add and Modify 6-11. . . . . . . . . . . . . . . . . . . . . . .

6–8 Indirect Addressing With Postdisplacement Subtract and Modify 6-11. . . . . . . . . . . . . . . . . . .

6–9 Indirect Addressing With Postdisplacement Add and Circular Modify 6-12. . . . . . . . . . . . . . . .

6–10 Indirect Addressing With Postdisplacement Subtract and Circular Modify 6-12. . . . . . . . . . . .

6–11 Indirect Addressing With Preindex Add 6-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–12 Indirect Addressing With Preindex Subtract 6-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–13 Indirect Addressing With Preindex Add and Modify 6-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–14 Indirect Addressing With Preindex Subtract and Modify 6-14. . . . . . . . . . . . . . . . . . . . . . . . . . .

6–15 Indirect Addressing With Postindex Add and Modify 6-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–16 Indirect Addressing With Postindex Subtract and Modify 6-15. . . . . . . . . . . . . . . . . . . . . . . . . .

6–17 Indirect Addressing With Postindex Add and Circular Modify 6-16. . . . . . . . . . . . . . . . . . . . . . .

6–18 Indirect Addressing With Postindex Subtract and Circular Modify 6-16. . . . . . . . . . . . . . . . . . .

xxviii

Examples

6–19 Indirect Addressing With Postindex Add and Bit-Reversed Modify 6-17. . . . . . . . . . . . . . . . . .

6–20 Short-Immediate Addressing 6-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–21 Long-Immediate Addressing 6-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–22 PC-Relative Addressing 6-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–23 Examples of Formula 2K > R 6-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–24 Circular Addressing 6-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–25 FIR Filter Code Using Circular Addressing 6-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–26 Bit-Reversed Addressing 6-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–1 Repeat-Mode Control Algorithm 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2 RPTB Operation 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3 Incorrectly Placed Standard Branch 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4 Incorrectly Placed Delayed Branch 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5 Pipeline Conflict in an RPTB Instruction 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–6 Incorrectly Placed Delayed Branches 7-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–7 Delayed Branch Execution 7-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–8 Busy-Waiting Loop 7-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–9 Multiprocessor Counter Manipulation 7-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–10 Implementation of V(S) 7-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–11 Implementation of P(S) 7-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–12 Code to Synchronize T wo TMS320C3x Devices at the Software Level 7-19. . . . . . . . . . . . . .

7–13 Pipeline Delay of XF Pin Configuration 7-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–14 Incorrect Use of Interlocked Instructions 7-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–15 Pending Interrupt 7-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–1 Standard Branch 8-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–2 Delayed Branch 8-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–3 Write to an AR Followed by an AR for Address Generation 8-7. . . . . . . . . . . . . . . . . . . . . . . . .

8–4 A Read of ARs Followed by ARs for Address Generation 8-8. . . . . . . . . . . . . . . . . . . . . . . . . . .

8–5 Program Wait Until CPU Data Access Completes 8-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–6 Program Wait Due to Multicycle Access 8-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–7 Multicycle Program Memory Fetches 8-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–8 Single Store Followed by Two Reads 8-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–9 Parallel Store Followed by Single Read 8-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–10 Interlocked Load 8-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–11 Busy External Port 8-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–12 Multicycle Data Reads 8-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–13 Conditional Calls and Traps 8-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–14 Address Generation Update of an AR Followed by an AR for Address Generation 8-19. . . .

8–15 Write to an AR Followed by an AR for Address Generation Without

a Pipeline Conflict 8-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–16 Write to DP Followed by a Direct Memory Read Without a Pipeline Conflict 8-21. . . . . . . . . .

8–17 Dummy sr2 Read 8-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–18 Operand Swapping Alternative 8-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–1 Timer Output Generation Examples 12-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–2 Maximum Frequency Timer Clock Setup 12-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xxix

Examples

12–3 Serial-Port Register Setup #1 12-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–4 Serial-Port Register Setup #1 12-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–5 Serial-Port Register Setup #2 12-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–6 CPU Transfer With Serial Port Transmit Polling Method 12-44. . . . . . . . . . . . . . . . . . . . . . . . . .

12–7 TMS320C3x Zero-Glue-Logic Interface to Burr Brown A/D and D/A 12-46. . . . . . . . . . . . . . . .

12–8 Array Initialization With DMA 12-75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–9 DMA Transfer With Serial-Port Receive Interrupt 12-76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12–10 DMA Transfer With Serial-Port Transmit Interrupt 12-77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xxx

Chapter 1

Introduction

The TMS320C3x generation of digital signal processors (DSPs) are highperformance CMOS 32-bit floating-point devices in the TMS320 family of single-chip DSPs.

The ’C3x generation integrates both system control and math-intensive functions on a single controller. This system integration allows fast, easy data movement and high-speed numeric processing performance. Extensive internal busing and a powerful DSP instruction set provide the devices with the speed and flexibility to execute at up to 60 million floating-point operations per second (MFLOPS). The devices also feature a high degree of on-chip parallelism that allows users to perform up to 11 operations in a single instruction.

Topic Page

1.1 TMS320C3x Devices 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Typical Applications 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

+ 727 hidden pages

Texas Instruments TMS320C3x User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

IMPORTANT NOTICE

About This Manual

Read This First

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Related Documentation From Texas Instruments

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Introduction