Texas Instruments TMS320C28x Reference Manual

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TMS320C28x DSP

CPU and Instruction Set

Reference Guide

Literature Number: SPRU430D

August 2001 − Revised March 2004

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Preface

Read This First

About This Manual

This manual describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x 32-bit fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs. A summary of the chapters and appendixes follows:

Chapter 1 Architectural Overview

This chapter introduces the T320C2800 DSP core that is at the heart of each TMS320C28x DSP. The chapter includes a memory map and a high-level description of the memory interface that connects the core with memory and peripheral devices.

Chapter 2 Central Processing Unit

This chapter describes the architecture, registers, and primary functions of the CPU. The chapter includes detailed descriptions of the flag and control bits in the most important CPU registers, status registers ST0 and ST1.

Chapter 3 Interrupts and Reset

This chapter describes the interrupts and how they are handled by the CPU. The chapter also explains the effects of a reset on the CPU and includes discussion of the automatic context save performed by the CPU prior to servicing an interrupt.

Chapter 4 Pipeline

This chapter describes the phases and operation of the instruction pipeline. The chapter is primarily for readers interested in increasing the efficiency of their programs by preventing pipeline delays.

Chapter 5 Addressing Modes

This chapter explains the modes by which the assembly language instructions accept data and access register and memory locations. The chapter includes a description of how addressing-mode information is encoded in opcodes.

Chapter 6 Assembly Language Instructions

This chapter provides summaries of the instruction set and detailed descriptions (including examples) for the instructions. The chapter includes an explanation of how 32-bit accesses are aligned to even addresses.

iiiRead This First

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Notational Conventions

About This Manual / Notational Conventions

Chapter 7 Emulation Features

This chapter describes the TMS320C28x emulation features that can be used with only a JTAG port and two additional emulation pins.

Appendix A Register Quick Reference

This appendix is a concise central resource for information about the status and control registers of the CPU. The chapter includes figures that summarize the bit fields of the registers.

Appendix B Submitting ROM Codes to TI

This appendix describes the procedures for getting code-customized ROM in a Texas Instruments (TI) DSP.

Appendix C C2xLP and C28x Architectural Differences

This appendix describes the differences in the architecture of the C2xLP and the C28x.

Appendix D Migration From C2xLP

This appendix explains how to migrate code from the C2xLP to the C28x.

Appendix E C2xLP Instruction Set Compatibility

This appendix describes the instruction set compatibility with the C2xLP.

Appendix F Migration From C27x to C28x

This appendix explains how to migrate code from the C27x to the C28x.

Appendix G Glossary

This appendix explains abbreviations, acronyms, and special terminology used throughout this document.

Notational Conventions

This document uses the following conventions:

- The device number TMS320C28x is very often abbreviated as ’28x.

- Program examples are shown in a special typeface. Here is a sam-

ple line of program code:

PUSH IER

- Portions of an instruction syntax that are in bold should be entered as

shown; portions of a syntax that are in italics are variables indicating information that should be entered. Here is an example of an instruction syntax:

MOV ARx, *−SP[6bit]

MOV is the instruction mnemonic. This instruction has two operands, indicated by ARx and *−SP[6bit]. Where the variable x appears, you type a

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Notational Conventions

value from 0 to 5; where the 6bit appears, you type a 6-bit constant. The rest of the instruction, including the square brackets, must be entered as shown.

- When braces or brackets enclose an operand, as in {operand}, the oper-

and is optional. If you use an optional operand, you specify the information within the braces; you do not enter the braces themselves. In the following syntax, the operand << shift is optional:

MOV ACC, *−SP[6bit] {<<shift}

MOV ACC, *−SP{6bit} {<<shift}

For example, you could use either of the following instructions:

MOV ACC, *−SP[5]

MOV ACC, *−SP[5]<< 4

- In most cases, hexadecimal numbers are shown with a subscript of 16. For

example, the hexadecimal number 40 would be shown as 40

. An excep-

tion to this rule is a hexadecimal number in a code example; these hexadecimal numbers have the suffix h. For example, the number 40 in the following code is a hexadecimal 40.

MOVB AR0,#40h

Similarly, binary numbers usually are shown with a subscript of 2. For example, the binary number 4 would be shown as 0100

. Binary numbers in

example code have the suffix b. For example, the following code uses a binary 4.

MOVB AR0,#0100b

- Bus signals and bits are sometimes represented with the following nota-

tions:

Notation Description Example

Bus(n:m) Signals n through m of bus PRDB(31:0) represents the 32

signals of the program-read data bus (PRDB).

nificant bits of the T register.

Bit n of register IER(4) represents bit 4 of the in-

terrupt enable register (IER).

vRead This First

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Related Documentation From Texas Instruments

Notational Conventions / Related Documentation From Texas Instruments

Concatenated values are represented with the following notation:

Notation Description Example

x:y x concatenated with y AR1:AR0 is the concatenation of

- If a signal is from an active-low pin, the name of the signal is qualified with

an overbar (for example, INT1

). If a signal is from an active-high pin or from hardware inside the the DSP (in which case, the polarity is irrelevant), the name of the signal is left unqualified (for example, DLOGINT).

Trademarks

TMS320C28x Serial Communication Interface (SCI) Reference Guide (lit-

erature number SPRU051) describes the SCI that is a two-wire asynchronous serial port, commonly known as a UART. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format.

TMS320C28x Serial Peripheral Interface (SPI) Reference Guide (literature

number SPRU059) describes the SPI − a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit−transfer rate. The SPI is used for communications be- tween the DSP controller and external peripherals or another controller.

TMS320C28x System Control and Interrupts Reference Guide (literature

number SPRU078) describes the various interrupts and system control features of the 28x digital signal processors (DSPs).

Trademarks

320 Hotline On-line is a trademark of Texas Instruments Incorporated.

HP-UX is a trademark of Hewlett-Packard Company.

IBM and PC are trademarks of International Business Machines Corporation.

Intel is a trademark of Intel Corporation.

MS-DOS is a registered trademark of Microsoft Corporation.



is a registered trademark of Advanced Micro Devices, Inc.

PAL

SunOS is a trademark of Sun Microsystems, Inc.

C2xLP, C27x, C28x, TMS320C28x, and XDS510 are trademarks of Texas Instruments Incorporated.

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Contents

1 Architectural Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Introduces the architecture and memory map of the T320C28x DSP CPU.

1.1 Introduction to the CPU 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.1 Compatibility With Other TMS320 CPUs 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.2 Switching to C28x Mode From Reset 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Components of the CPU 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.1 Central Processing Unit (CPU) 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.2 Emulation Logic 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.3 Signals 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Memory Map 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.1 On-Chip Program/Data 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.2 Reserved 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.3 CPU Interrupt Vectors 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Memory Interface 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.1 Address and Data Buses 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.2 Special Bus Operations 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.3 Alignment of 32-Bit Accesses to Even Addresses 1-11. . . . . . . . . . . . . . . . . . . . . . .

2 Central Processing Unit 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the registers and primary functions of the TMS320C28x CPU.

2.1 CPU Architecture 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 CPU Registers 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Accumulator (ACC, AH, AL) 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Multiplicand Register (XT) 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3 Product Register (P, PH, PL) 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4 Data Page Pointer (DP) 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.5 Stack Pointer (SP) 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.6 Auxiliary Registers (XAR0−XAR7, AR0−AR7) 2-12. . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.7 Program Counter (PC) 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.8 Return Program Counter (RPC) 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.9 Status Registers (ST0, ST1) 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.10 Interrupt-Control Registers (IFR, IER, DBGIER) 2-14. . . . . . . . . . . . . . . . . . . . . . . .

2.3 Status Register (ST0) 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Status Register ST1 2-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Program Flow 2-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Contents

2.5.1 Interrupts 2-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2 Branches, Calls, and Returns 2-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.3 Repeating a Single Instruction 2-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.4 Instruction Pipeline 2-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Multiply Operations 2-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.1 16-bit X 16-bit Multiplication 2-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.2 32-Bit X 32-Bit Multiplication 2-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Shift Operations 2-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 CPU Interrupts and Reset 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the TMS320C28x interrupts and how they are handled by the CPU. Also explains the effects of a hardware reset.

3.1 CPU Interrupts Overview 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 CPU Interrupt Vectors and Priorities 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT 3-6. . . . . . . . . . . . . . . . . . . . .

3.3.1 CPU Interrupt Flag Register (IFR) 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.2 CPU Interrupt Enable Register (IER) and

CPU Debug Interrupt Enable Register (DBGIER) 3-8. . . . . . . . . . . . . . . . . . . . . . . .

3.4 Standard Operation for Maskable Interrupts 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Nonmaskable Interrupts 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1 INTR Instruction 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.2 TRAP Instruction 3-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.3 Hardware Interrupt NMI 3-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Illegal-Instruction Trap 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Hardware Reset (RS) 3-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Pipeline 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the phases and operation of the instruction pipeline.

4.1 Pipelining of Instructions 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1 Decoupled Pipeline Segments 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.2 Instruction-Fetch Mechanism 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.3 Address Counters FC, IC, and PC 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Visualizing Pipeline Activity 4-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Freezes in Pipeline Activity 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1 Wait States 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.2 Instruction-Not-Available Condition 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Pipeline Protection 4-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.1 Protection During Reads and Writes to the Same Data-Space Location 4-12. . . .

4.4.2 Protection Against Register Conflicts 4-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Avoiding Unprotected Operations 4-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.1 Unprotected Program-Space Reads and Writes 4-16. . . . . . . . . . . . . . . . . . . . . . . .

4.5.2 An Access to One Location That Affects Another Location 4-16. . . . . . . . . . . . . . .

4.5.3 Write Followed By Read Protection Mode 4-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 C28x Addressing Modes 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the addressing modes of the C28x.

5.1 Types of Addressing Modes 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Contents

5.2 Addressing Modes Select Bit (AMODE) 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Assembler/Compiler Tracking of AMODE Bit 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Direct Addressing Modes (DP) 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Stack Addressing Modes (SP) 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Indirect Addressing Modes 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6.1 C28x Indirect Addressing Modes (XAR0 to XAR7) 5-10. . . . . . . . . . . . . . . . . . . . . .

5.6.2 C2xLP Indirect Addressing Modes (ARP, XAR0 to XAR7) 5-12. . . . . . . . . . . . . . . .

5.6.3 Circular Indirect Addressing Modes (XAR6, XAR1) 5-21. . . . . . . . . . . . . . . . . . . . . .

5.7 Register Addressing Modes 5-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.1 32-Bit Register Addressing Modes 5-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.2 16-Bit Register Addressing Modes 5-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8 Data/Program/IO Space Immediate Addressing Modes 5-28. . . . . . . . . . . . . . . . . . . . . . . . .

5.9 Program Space Indirect Addressing Modes 5-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.10 Byte Addressing Modes 5-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.11 Alignment of 32-Bit Operations 5-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 C28x Assembly Language Instructions 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Presents summaries of the instruction set, defines special symbols and notations used, and describes each instruction in detail in alphabetical order.

6.1 Instruction Set Summary (Organized by Function) 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Register Operations 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Emulation Features 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Explains features supported by the T320C2800 CPU for testing and debugging programs.

7.1 Overview of Emulation Features 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 Debug Interface 7-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 Debug Terminology 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 Execution Control Modes 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.1 Stop Mode 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.2 Real-Time Mode 7-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.3 Summary of Stop Mode and Real-Time Mode 7-11. . . . . . . . . . . . . . . . . . . . . . . . . .

7.5 Aborting Interrupts With the ABORTI Instruction 7-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6 DT-DMA Mechanism 7-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7 Analysis Breakpoints, Watchpoints, and Counter(s) 7-19. . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7.1 Analysis Breakpoints 7-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7.2 Watchpoints 7-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7.3 Benchmark Counter/Event Counter(s) 7-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7.4 Typical Analysis Unit Configurations 7-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8 Data Logging 7-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8.1 Creating a Data Logging Transfer Buffer 7-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8.2 Accessing the Emulation Registers Properly 7-26. . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8.3 Data Log Interrupt (DLOGINT) 7-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.8.4 Examples of Data Logging 7-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.9 Sharing Analysis Resources 7-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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7.10 Diagnostics and Recovery 7-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A Register Quick Reference A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Is a concise, central resource for information about the status and control registers of the TMS320C28x CPU.

A.1 Reset Values of and Instructions for Accessing the Registers A-2. . . . . . . . . . . . . . . . . . . . .

A.2 Register Figures A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B Submitting ROM Codes to TI B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Explains the process for submitting custom program code to TI for designing masks for the onchip ROM on a TMS320 DSP.

B.1 Introduction B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.2 Code Submission B-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.3 ROM Layout B-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B.4 ROM Code Generation Flow B-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C C2xLP and C28x Architectural Differences C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C.1 Summary of Architecture Differences Between C2xLP and C28x C-2. . . . . . . . . . . . . . . . . .

C.1.1 Enhancements of the C28x over the C2xLP: C-2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

C.2 Registers C-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C.2.1 CPU Register Changes C-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C.2.2 Data Page (DP) Pointer Changes C-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C.2.3 Status Register Changes C-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C.2.4 Register Reset Conditions C-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C.3 Memory Map C-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D C2xLP Migration Guidelines D-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D.1 Introduction D-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D.2 Recommended Migration Flow D-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D.3 Mixing C2xLP and C28x Assembly D-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D.4 Code Examples D-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D.4.1 Boot Code for C28x operating mode initalization D-7. . . . . . . . . . . . . . . . . . . . . . . . .

D.4.2 IER/IFR Code D-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D.4.3 Context Save/Restore D-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D.5 Reference Tables for C2xLP Code Migration Topics D-10. . . . . . . . . . . . . . . . . . . . . . . . . . . .

E C2xLP Instruction Set Compatibility E-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the instruction set compatibility between the C2xLP and the C28x.

E.1 Condition Tests on Flags E-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E.2 C2xLP vs. C28x Mnemonics E-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E.3 Repeatable Instructions E-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F Migration From C27x to C28x F-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F.1 Architecture Changes F-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F.1.1 Changes to Registers F-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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F.1.2 Full Context Save and Restore F-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F.1.3 B0/B1 Memory Map Consideration F-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F.1.4 C27x Object Compatibility F-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F.2 Moving to a C28x Object F-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F.2.1 Caution When Changing OJBMODE F-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F.3 Migrating to C28x Object Code F-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F.3.1 Instruction Syntax Changes F-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F.3.2 Repeatable Instructions F-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F.3.3 Changes to the SUBCU Instruction F-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F.4 Compiling C28x Source Code F-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Figures

1−1. High-Level Conceptual Diagram of the CPU 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−2. TMS320C28x High-Level Memory Map 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−1. Conceptual Block Diagram of the CPU 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2. C28x Registers 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−3. Individually Accessible Portions of the Accumulator 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4. Individually Accessible Halves of the XT Register 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−5. Individually Accessible Halves of the P Register 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−6. Pages of Data Memory 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−7. Address Reach of the Stack Pointer 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−8. XAR0 − XAR7 Registers 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−9. XAR0 − XAR7 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−10. Bit Fields of Status Register (ST0) 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−11. Bit Fields of Status Register 1 (ST1) 2-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−12. Conceptual Diagram of Components Involved in 16 X16-Bit Multiplication 2-42. . . . . . . . . . .

2−13. Conceptual Diagram of Components Involved in 32 X 32-Bit Multiplication 2-43. . . . . . . . . . .

3−1. Interrupt Flag Register (IFR) 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2. Interrupt Enable Register (IER) 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3. Debug Interrupt Enable Register (DBGIER) 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4. Standard Operation for CPU Maskable Interrupts 3-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5. Functional Flow Chart for an Interrupt Initiated by the TRAP Instruction 3-18. . . . . . . . . . . . .

5−1. Circular Buffer with AMODE = 0 5-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2. Circular Buffer with AMODE = 1 5-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−1. JTAG Header to Interface a Target to the Scan Controller 7-3. . . . . . . . . . . . . . . . . . . . . . . . . .

7−2. Stop Mode Execution States 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−3. Real-time Mode Execution States 7-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−4. Stop Mode Versus Real-Time Mode 7-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−5. Process for Handling a DT-DMA Request 7-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−6. ADDRL (at Data-Space Address 00 083816) 7-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−7. ADDRH (at Data-Space Address 00 083916) 7-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−8. REFL (at Data-Space Address 00 084A16) 7-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−9. REFH (at Data-Space Address 00 084B16) 7-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−10. Valid Combinations of Analysis Resources 7-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A−1. Status register ST0 A-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A−2. Status register ST1, Bits15−8 A-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A−3. Status Register ST1, Bits 7−0 A-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A−4. Interrupt flag register (IFR) A-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Figures

A−5. Interrupt enable register (IER) A-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A−6. Debug interrupt enable register (DBGIER) A-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B−1. TMS320 ROM Code Prototype and Production Flowchart B-3. . . . . . . . . . . . . . . . . . . . . . . . . .

C−1. Register Changes From C2xLP to C28x C-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C−2. Direct Addressing Mode Mapping C-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C−3. Status Register Comparison Between C2xLP and C28x C-7. . . . . . . . . . . . . . . . . . . . . . . . . . . .

C−4. Memory Map Comparison (See Note A) C-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D−1. Flow Chart of Recommended Migration Steps D-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−1. C28x Registers F-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−2. Full Context Save/Restore F-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−3. Code for a Full Context Save/Restore for C28x vs C27x F-6. . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−4. Mapping of Memory Blocks B0 and B1 on C27x F-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−5. C27x Compatible Mapping of Blocks M0 and M1 F-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−6. Building a C27x Object File From C27x Source F-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−7. Building a C28x Object File From Mixed C27x/C28x Source F-9. . . . . . . . . . . . . . . . . . . . . . . .

F−8. Compiling C28x Source F-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Tables

1−1. Compatibility Modes 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−2. Summary of Bus Use During Data-Space and Program-Space Accesses 1-10. . . . . . . . . . . .

1−3. Special Bus Operations 1-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−1. CPU Register Summary 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2. Available Operations for Shifting Values in the Accumulator 2-8. . . . . . . . . . . . . . . . . . . . . . . . .

2−3. Product Shift Modes 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4. Instructions That Affect OVC/OVCU 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−5. Instructions Affected by the PM Bits 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−6. Instructions Affected by V flag 2-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−7. Negative Flag Under Overflow Conditions 2-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−8. Bits Affected by the C Bit 2-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−9. Instructions That Affect the TC Bit 2-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−10. Instructions Affected by SXM 2-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−11. Shift Operations 2-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1. Interrupt Vectors and Priorities 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2. Requirements for Enabling a Maskable Interrupt 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3. Register Pairs Saved and SP Positions for Context Saves 3-14. . . . . . . . . . . . . . . . . . . . . . . .

3−4. Register Pairs Saved and SP Positions for Context Saves 3-20. . . . . . . . . . . . . . . . . . . . . . . .

3−5. Registers After Reset 3-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1. Addressing Modes for “loc16” or “loc32” 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−1. Instruction Set Summary (Organized by Function) 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−2. Register Operations 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−1. 14-Pin Header Signal Descriptions 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−2. Selecting Device Operating Modes By Using TRST, EMU0, and EMU1 7-5. . . . . . . . . . . . . . .

7−3. Interrupt Handling Information By Mode and State 7-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−4. Start Address and DMA Registers 7-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−5. End-Address Registers 7-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−6. Analysis Resources 7-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A−1. Reset Values of the Status and Control Registers A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B−1. Checksum Computation Memory Locations B-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C−1. General Features C-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C−2. C2xLP Product Mode Shifter C-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C−3. C28x Product Mode Shifter C-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C−4. Reset Conditions of Internal Registers C-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C−5. Status Register Bits C-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C−6. B0 Memory Map C-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xvi

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Tables

D−1. Code to Save Contents Of IMR (IER) And Disabling Lower Priority Interrupts At

Beginning Of ISR D-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D−2. Code to Disable an Interrupt D-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D−3. Code to Enable an Interrupt D-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D−4. Code to Clear the IFR Register D-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D−5. Full Context Save/Restore Comparison D-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D−6. C2xLP and C28x Differences in Interrupts D-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D−7. C2xLP and C28x Differences in Status Registers D-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D−8. C2xLp and C28x Differences in Memory Maps D-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D−9. C2xLP and C28x Differences in Instructions and Registers D-13. . . . . . . . . . . . . . . . . . . . . . .

D−10. Code Generation Tools and Syntax Differences D-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E−1. C28x and C2xLP Flags E-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E−2. C2xLP Instructions and C28x Equivalent Instructions E-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

E−3. Repeatable Instructions for the C2xLP and C28x E-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−1. ST0 Register Bits F-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−2. ST1 Register Bits F-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

F−3. Instruction Syntax Change F-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xviiContents

Page 18

Examples

3−1. Typical ISR 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1. Relationship Between Pipeline and Address Counters FC, IC, and PC 4-6. . . . . . . . . . . . . . .

4−2. Diagramming Pipeline Activity 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−3. Simplified Diagram of Pipeline Activity 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−4. Conflict Between a Read From and a Write to Same Memory Location 4-13. . . . . . . . . . . . . .

4−5. Register Conflict 4-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7−1. Initialization Code for Data Logging With Word Counter 7-28. . . . . . . . . . . . . . . . . . . . . . . . . . .

7−2. Initialization Code for Data Logging With End Address 7-29. . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Chapter 1

Architectural Overview

The TMS320C28xt is one of several fixed-point generations of digital signal processors (DSPs) in the TMS320 family. The C28xt is source-code and object-code compatible with the C27xt. In addition, much of the code written for the C2xLP CPU can be reassembled to run on a C28x device.

The C2xLP CPU is used in all TMS320F24xx and TMS320C20x DSPs and their derivatives. This document refers to C2xLP as a generic name for the DSP CPU used in these devices.

This chapter provides an overview of the architectural structure and components of the C28x CPU.

Topic Page

1.1 Introduction to the CPU 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Components of the CPU 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Memory Map 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Memory Interface 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1

Page 20

Introduction to the CPU

1.1 Introduction to the CPU

The CPU is a low-cost 32-bit fixed-point digital signal processor (DSP). This device draws from the best features of digital signal processing; reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets. The DSP features include a modified Harvard architecture and circular addressing. The RISC features are single-cycle instruction execution, register-to-register operations, and modified Harvard architecture (usable in Von Neumann mode). The microcontroller features include ease of use through an intuitive instruction set, byte packing and unpacking, and bit manipulation.

The modified Harvard architecture of the CPU enables instruction and data fetches to be performed in parallel. The CPU can read instructions and data while it writes data simultaneously to maintain the single-cycle instruction operation across the pipeline. The CPU does this over six separate address/data buses.

1.1.1 Compatibility With Other TMS320 CPUs

The C28x DSP features compatibility modes that minimize the migration effort from the C27x and C2xLP CPUs. The operating mode of the device is determined by a combination of the OBJMODE and AMODE bits in status register 1 (ST1) as shown in Table 1−1. The OBJMODE bit allows you to select between code compiled for a C28x (OBJMODE == 1) and code compiled for a C27x (OBJMODE == 0). The AMODE bit allows you to select between C28x/C27x instruction addressing modes (AMODE == 0) and C2xLP compatible instruction addressing modes (AMODE == 1).

Table 1−1. Compatibility Modes

C28x Mode 1 0

C2xLP Source-compatible Mode 1 1

C27x Object-compatible Mode

†

The C28x is in C27x-compatible mode at reset.

- C28x Mode: In C28x mode, you can take advantage of all the C28x native

features, addressing modes, and instructions. To operate in C28x mode from reset, your code must first set the OBJMODE bit by using the ”C28OBJ” (or ”SETC OBJMODE”) instruction. This book assumes you are operating in C28x mode unless stated otherwise.

- C2xLP Source-Compatible Mode: C2xLP source-compatible mode al-

lows you to run C2xLP source code which has been reassembled using

1-2

OBJMODE AMODE

†

0 0

Page 21

the C28x code-generation tools. For more information on operating in this mode and migration from a C2xLP CPU, see Appendices C, D, and E.

- C27x Object-Compatible Mode: At reset, the C28x CPU operates in C27x

object-compatible mode. In this mode, the C28x is 100% object-code and cycle-count compatible with the C27x CPU. For detailed information on operating in C27x object-compatible mode and migrating from the C27x, see Appendix F.

1.1.2 Switching to C28x Mode From Reset

At reset, the C28x CPU is in C27x Object-Compatible Mode (OBJMODE == 0, AMODE == 0) and is 100% compatible with the C27x CPU. To take advantage of the enhanced C28x instruction set, you must instead operate the device in C28x mode. To do this, after a reset your code must first set the OBJMODE bit in ST1 by using the ”C28OBJ” (or ”SETC OBJMODE”) instruction.

Introduction to the CPU

1-3Architectural Overview

Page 22

Components of the CPU

1.2 Components of the CPU

As shown in Figure 1−1, the CPU contains:

- A CPU for generating data- and program-memory addresses; decoding

and executing instructions; performing arithmetic, logical, and shift operations; and controlling data transfers among CPU registers, data memory, and program memory

- Emulation logic for monitoring and controlling various parts and functiona-

lities of the DSP and for testing device operation

- Signals for interfacing with memory and peripherals, clocking and control-

ling the CPU and the emulation logic, showing the status of the CPU and the emulation logic, and using interrupts

The CPU does not contain memory, a clock generator, or peripheral devices. For information about interfacing to these items, see the C28x Peripheral User’s Guide (literature number SPRU566) and the data sheet that corresponds to your DSP.

Figure 1−1. High-Level Conceptual Diagram of the CPU

1.2.1 Central Processing Unit (CPU)

The CPU is discussed in more detail in Chapter 2, but following is a list of its major features:

- Protected pipeline. The CPU implements an 8-phase pipeline that pre-

vents a write to and a read from the same location from occurring out of order.

- Independent register space. The CPU contains registers that are not

mapped to data space. These registers function as system-control

C28x CPU

Memory-interface signals

CPU

Clock and control signals

Reset and interrupt signals

Emulation

logic

Emulation signals

1-4

Page 23

- Arithmetic logic unit (ALU). The 32-bit ALU performs 2s-complement arith-

- Address register arithmetic unit (ARAU). The ARAU generates data-

- Barrel shifter. This shifter performs all left and right shifts of data. It can shift

- Multiplier. The multiplier performs 32-bit × 32-bit 2s-complement multi-

1.2.2 Emulation Logic

Components of the CPU

registers, math registers, and data pointers. The system-control registers are accessed by special instructions. The other registers are accessed by special instructions or by a special addressing mode (register addressing mode).

metic and Boolean logic operations.

memory addresses and increments or decrements pointers in parallel with ALU operations.

data to the left by up to 16 bits and to the right by up to 16 bits.

plication with a 64-bit result. The multiplication can be performed with two signed numbers, two unsigned numbers, or one signed number and one unsigned number.

The emulation logic includes the following features. For more details about these features, see Chapter 7, Emulation Features.

- Debug-and-test direct memory access (DT-DMA). A debug host can gain

direct access to the content of registers and memory by taking control of the memory interface during unused cycles of the instruction pipeline.

- Data logging. The emulation logic enables application-initiated transfers

of memory contents between the C28x and a debug host.

- A counter for performance benchmarking

- Multiple debug events. Any of the following debug events can cause a

break in program execution:

J A breakpoint initiated by the ESTOP0 or ESTOP1 instruction

J An access to a specified program-space or data-space location

J A request from the debug host or other hardware

When a debug event causes the C28x to enter the debug-halt state, the event is called a break event.

- Real-time mode of operation. When the C28x is in this mode and a break

event occurs, the main body of program code comes to a halt, but time-critical interrupts can still be serviced.

1-5Architectural Overview

Page 24

Components of the CPU

1.2.3 Signals

The CPU has four main types of signals:

- Memory-interface signals. These signals transfer data among the CPU,

memory, and peripherals; indicate program-memory accesses and datamemory accesses; and differentiate between accesses of different sizes (16-bit or 32-bit).

- Clock and control signals. These provide clocking for the CPU and the

emulation logic, and they are used to control and monitor the CPU.

- Reset and interrupt signals. These are used for generating a hardware re-

set and interrupts, and for monitoring the status of interrupts.

- Emulation signals. These signals are used for testing and debugging.

1-6

Page 25

1.3 Memory Map

The CPU contains no memory, but can access memory elsewhere on the C28x DSP or outside the DSP.

The C28x uses 32-bit data addresses and 22-bit program addresses. This allows for a total address reach of 4G words (1 word = 16 bits) in data space and 4M words in program space. Memory blocks on all C28x designs are uniformly mapped to both program and data space. Figure 1−2 shows a high-level view of how addresses are allocated in program space and data space.

The memory map in Figure 1−2 has been divided into the following segments:

- On-chip program/data

- Reserved

- CPU interrupt vectors

For specific details about each of the map segments, see the data sheet for your DSP. See Appendix D for more information on the C2xLP compatible memory space.

1.3.1 On-Chip Program/Data

All C28x-based CPU devices contain two blocks of single access on-chip memory referred to as M0 and M1. Each of these blocks is 1K words in size. M0 is mapped at addresses 00 0000 dresses 00 0400 vices, M0 and M1 are mapped to both program and data space. Therefore, you can use M0 and M1 to execute code or for data variables. At reset, the stack pointer is set to the top of block M1.

Memory Map

− 00 03FF16 and M1 is mapped at ad-

− 00 07FF16. Like all other memory blocks on the C28x de-

Depending on the device, it may also have additional random-access memory (RAM), read-only memory (ROM), or flash memory.

1.3.2 Reserved

Addresses 0000 0800−0000 09FF in data space are reserved for CPU Emulation Registers on all C28x designs.

1.3.3 CPU Interrupt Vectors

Sixty-four addresses in program space are set aside for a table of 32 CPU interrupt vectors. The CPU vectors can be mapped to the top or bottom of program space by way of the VMAP bit. For more information about the CPU vectors, see Section 3.2, Interrupt Vectors and Priorities on page 3-4.

For devices with a peripheral interrupt expansion (PIE) block, the interrupt vectors will reside in the PIE vector table and this memory can be used as program memory.

1-7Architectural Overview

Page 26

Memory Map

Figure 1−2. TMS320C28x High-Level Memory Map

High 64K

C2xLP

Compatible

Program

Space

0000

3FF

400

7FF

3F 0000

Program

Vectors in RAM M0

(VMAP = 0)

Block M0 1 K × 16

Block M1 1 K × 16

Reserved

Memory or

Peripherals

Data

Vectors in RAM M0

(VMAP = 0)

Block M0 1 K × 16

Block M1 1 K × 16

Reserved

Memory or

Peripherals

<−SP

(Reset)

800 9FF

1000

A000

Low 64K

C2xLP Compatible Data Space

1-8

3F FFFF

Vectors (VMAP = 1)

FFFF FFFF

See the data sheet for your specific device for details of the exact memory map.

Page 27

1.4 Memory Interface

The C28x memory map is accessible outside the CPU by the memory interface, which connects the CPU logic to memories, peripherals, or other interfaces. The memory interface includes separate buses for program space and data space. This means an instruction can be fetched from program memory while data memory is being accessed.

The interface also includes signals that indicate the type of read or write being requested by the CPU. These signals can select a specified memory block or peripheral for a given bus transaction. In addition to 16-bit and 32-bit accesses, the C28x supports special byte-access instructions which can access the least significant byte (LSByte) or most significant byte (MSByte) of an addressed word. Strobe signals indicate when such an access is occurring on a data bus.

1.4.1 Address and Data Buses

The memory interface has three address buses:

PAB Program address bus. The PAB carries addresses for reads and

writes from program space. PAB is a 22-bit bus.

Memory Interface

DRAB Data-read address bus. The 32-bit DRAB carries addresses for

reads from data space.

DWAB Data-write address bus. The 32-bit DWAB carries addresses for

writes to data space.

The memory interface also has three data buses:

PRDB Program-read data bus. The PRDB carries instructions or data dur-

ing reads from program space. PRDB is a 32-bit bus.

DRDB Data-read data bus. The DRDB carries data during reads from data

space. PRDB is a 32-bit bus.

DWDB Data-/Program-write data bus. The 32-bit DWDB carries data during

writes to data space or program space.

1-9Architectural Overview

Page 28

Memory Interface

Table 1−2 summarizes how these buses are used during accesses.

Table 1−2. Summary of Bus Use During Data-Space and Program-Space Accesses

Access Type

Read from program space PAB

Read from data space

Write to program space PAB DWDB

Write to data space

A program-space read and a program-space write cannot happen simultaneously because both use the PAB. Similarly, a program-space write and a data-space write cannot happen simultaneously because both use the DWDB. Transactions that use different buses can happen simultaneously. For example, the CPU can read from program space (using PAB and PRDB), read from data space (using DRAB and DRDB), and write to data space (using DWAB and DWDB) at the same time.

1.4.2 Special Bus Operations

Typically, PAB and PRDB are used only for reading instructions from program space, and DWDB is used only for writing data to data space. However, the instructions in Table 1−3 are exceptions to this behavior. For more details about using these instructions, see Chapter 6, Assembly Language Instruc- tions.

Address Bus

DRAB

DWAB DWDB

Data Bus

PRDB

DRDB

1-10

Page 29

Table 1−3. Special Bus Operations

Memory Interface

Instruction

PREAD

ÁÁ

PWRITE

ÁÁ

MAC

ÁÁ

DMAC

ÁÁ

QMACL IMACL

ÁÁ

XMAC

ÁÁ

XMACD

ÁÁ

Special Bus Operation

This instruction reads a data value rather than an instruction from pro-

ББББББББББББББББББ

gram space. It then transfers that value to data space or a register.

ББББББББББББББББББ

For the read from program space, the CPU places the source address on the program address bus (PAB), sets the appropriate program-

ББББББББББББББББББ

space select signals, and reads the data value from the program-read

ББББББББББББББББББ

data bus (PRDB).

This instruction writes a data value to program space. The value is

ББББББББББББББББББ

read from from data space or a register.

ББББББББББББББББББ

For the write to program space, the CPU places the destination address on the program address bus (PAB), sets the appropriate pro-

ББББББББББББББББББ

gram-space select signals, and writes the data value to the data-/pro-

ББББББББББББББББББ

gram-write data bus (DWDB).

As part of their operation, these instructions multiply two data values,

ББББББББББББББББББ

one of which is read from program space.

ББББББББББББББББББ

For the read from program space, the CPU places the program-space

ББББББББББББББББББ

source address on the program address bus (PAB), sets the appropriate program-space select signals, and reads the program data value

ББББББББББББББББББ

from the program read data bus (PRDB).

ББББББББББББББББББ

1.4.3 Alignment of 32-Bit Accesses to Even Addresses

The C28x CPU expects memory wrappers or peripheral-interface logic to align any 32-bit read or write to an even address. If the address-generation logic generates an odd address, the CPU must begin reading or writing at the previous even address. This alignment does not affect the address values generated by the address-generation logic.

Most instruction fetches from program space are performed as 32-bit read operations and are aligned accordingly. However, alignment of instruction fetches are effectively invisible to a programmer. When instructions are stored to program space, they do not have to be aligned to even addresses. Instruction boundaries are decoded within the CPU.

You need to be concerned with alignment when using instructions that perform 32-bit reads from or writes to data space.

1-11Architectural Overview

Page 30

1-12

Page 31

Chapter 2

Central Processing Unit

The central processing unit (CPU) is responsible for controlling the flow of a program and the processing of instructions. It performs arithmetic, Booleanlogic, multiply, and shift operations. When performing signed math, the CPU uses 2s-complement notation. This chapter describes the architecture, registers, and primary functions of the CPU.

Topic Page

2.1 CPU Architecture 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 CPU Registers 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Status Register ST0 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Status Register ST1 2-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Program Flow 2-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Multiply Operations 2-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Shift Operations 2-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2-1

Page 32

CPU Architecture

2.1 CPU Architecture

All C28x devices contain a central processing unit (CPU), emulation logic, and signals for interfacing with memory and peripherals. Included with these signals are three address buses and three data buses. Figure 2−1 shows the major blocks and data paths of the C28x CPU. It does not reflect the actual silicon implementation. The shaded buses are memory-interface buses that are external to the CPU. The operand bus supplies the values for multiplier, shifter, and ALU operations, and the result bus carries the results to registers and memory. The main blocks of the CPU are:

- Program and data control logic. This logic stores a queue of instructions

- Real-Time emulation and visibility

- Address register arithmetic unit (ARAU). The ARAU generates ad-

that have been fetched from program memory.

dresses for values that must be fetched from data memory. For a data read, it places the address on the data-read address bus (DRAB); for a data write, it loads the data-write address bus (DWAB). The ARAU also increments or decrements the stack pointer (SP) and the auxiliary registers (XAR0, XAR1, XAR2, XAR3, XAR4, XAR5, XAR6, and XAR7).

- Atomic arithmetic logic unit (ALU). The 32-bit ALU performs 2s-com-

plement arithmetic and Boolean logic operations. Before doing its calculations, the ALU accepts data from registers, from data memory, or from the program control logic. The ALU saves results to a register or to data memory.

- Prefetch queue and instruction decode

- Address generators for program and data

- Fixed-point MPY/ALU. The multiplier performs 32-bit × 32-bit 2s-comple-

ment multiplication with a 64-bit result. In conjunction with the multiplier, the ’28xx uses the 32-bit multiplicand register (XT), the 32-bit product register (P), and the 32-bit accumulator (ACC). The XT register supplies one of the values to be multiplied. The result of the multiplication can be sent to the P register or to ACC.

- Interrupt processing

2-2

Page 33

Figure 2−1. Conceptual Block Diagram of the CPU

Program-read data bus, PRDB(0:31)

Program address bus, PAB(0:21)

Data-read address bus, DRAB(0:31)

CPU Architecture

Data-read data bus, DRDB(0:31)

Data-read buffer register

Operand bus

ARAU

XAR0 XAR1 XAR2 XAR3 XAR4 XAR5 XAR6 XAR7

DP SP

ST1

Address

from stack

Registers

AH:AL PH:PL

DBGIER

XAR7

T:TL

IER

IFR

ST0

RPC

Program-address

generation logic

MUX

Immediate

Program control

logic

MUX

address

Immediate

data

Immediate

data

Multiplier,

barrel shifter,

and

ALU

Result bus

RESULT BUS

Data-/program-write data bus, DWDB(0:31)

Data-write address bus, DWAB(0:31)

Data-write buffer register

2-3Central Processing Unit

Page 34

CPU Registers

2.2 CPU Registers

Table 2−1 lists the main CPU registers and their values after reset. Sections

2.2.1 through 2.2.10 describe the registers in more detail. Figure 2−2 shows the registers.

Table 2−1. CPU Register Summary

ACC 32 bits Accumulator 0x00000000

AH 16 bits High half of ACC 0x0000

AL 16 bits Low half of ACC 0x0000

XAR0 16 bits Auxiliary register 0 0x00000000

XAR1 32 bits Auxiliary register 1 0x00000000

XAR2 32 bits Auxiliary register 2 0x00000000

XAR3 32 bits Auxiliary register 3 0x00000000

XAR4 32 bits Auxiliary register 4 0x00000000

XAR5 32 bits Auxiliary register 5 0x00000000

XAR6 32 bits Auxiliary register 6 0x00000000

XAR7 32 bits Auxiliary register 7 0x00000000

AR0 16 bits Low half of XAR0 0x0000

AR1 16 bits Low half of XAR1 0x0000

AR2 16 bits Low half of XAR2 0x0000

AR3 16 bits Low half of XAR3 0x0000

AR4 16 bits Low half of XAR4 0x0000

AR5 16 bits Low half of XAR5 0x0000

AR6 16 bits Low half of XAR6 0x0000

AR7

16 bits Low half of XAR7 0x0000

2-4

Page 35

Table 2−1. CPU Register Summary (Continued)

DP 16 bits Data-page pointer 0x0000

IFR 16 bits Interrupt flag register 0x0000

IER 16 bits Interrupt enable register 0x0000 (INT1 to INT14, DLOGINT,

CPU Registers

RTOSINT disabled)

DBGIER 16 bits Debug interrupt enable

0x0000 (INT1 to INT14, DLOGINT, RTOSINT disabled)

P 32 bits Product register 0x00000000

PH 16 bits High half of P 0x0000

PL 16 bits Low half of P 0x0000

PC 22 bits Program counter 0x3FFFC0

RPC 22 bits Return program counter 0x00000000

SP 16 bits Stack pointer 0x0400

ST0 16 bits Status register 0 0x0000

ST1 16 bits Status register 1 0x080B

†

XT 32 bits Multiplicand register 0x00000000

T 16 bits High half of XT 0x0000

†

Reset value shown is for devices without the VMAP signal and MOM1MAP signal pinned out. On these devices both of these signals are tied high internal to the device.

16 bits Low half of XT 0x0000

2-5Central Processing Unit

Page 36

CPU Registers

Figure 2−2. C28x Registers

T[16]

PH[16]

AR0H[16]

AR1H[16]

AR2H[16]

AR3H[16]

AR4H[16]

AR5H[16]

AR6H[16]

AR7H[16]

DP[16]

PC[22]

RPC[22]

TL[16]

PL[16]

AL[16]AH[16]

SP[16]

AR0[16]

AR1[16]

AR2[16]

AR3[16]

AR4[16]

AR5[16]

AR6[16]

AR7[16]

6/7-bit offset

XT[32]

P[32]

ACC[32]

†

XAR0[32]

XAR1[32]

XAR2[32]

XAR3[32]

XAR4[32]

XAR5[32]

XAR6[32]

XAR7[32]

†

A 6-bit offset is used when operating in C28x mode or C27x object-compatible mode. A 7-bit offset is used when operating in C2xLP source-compatible mode. The least significant bit of the DP is ignored when operating in this mode.

2.2.1 Accumulator (ACC, AH, AL)

The accumulator (ACC) is the main working register for the device. It is the destination for all ALU operations except those which operate directly on memory or registers. ACC supports single-cycle move, add, subtract, and

2-6

ST0[16]

ST1[16]

IER[16]

DBGIER[16]

IFR[16]

Page 37

compare operations from 32-bit-wide data memory. It can also accept the 32-bit result of a multiplication operation.

The halves and quarters of the ACC can also be accessed (see Figure 2−3). ACC can be treated as two independent 16-bit registers: AH (high 16 bits) and AL (low 16 bits). The bytes within AH and AL can also be accessed independently. Special byte-move instructions load and store the most significant byte or least significant byte of AH or AL. This enables efficient byte packing and unpacking.

Figure 2−3. Individually Accessible Portions of the Accumulator

AH AL

ACC

CPU Registers

AH.MSB

AH = ACC (31:16) AH.MSB = ACC (31:24) AH.LSB = ACC (23:16)

AH.LSB AL.MSB AL.LSB

AL = ACC (15:0) AL.MSB = ACC (15:8) AL.LSB = ACC (7:0)

The accumulator has the following associated status bits. For the details on these bits, see section 2.3, Status Register ST0.

- Overflow mode bit (OVM)

- Sign-extension mode bit (SXM)

- Test/control flag bit (TC)

- Carry bit (C)

- Zero flag bit (Z)

- Negative flag bit (N)

- Latched overflow flag bit (V)

- Overflow counter bits (OVC)

Table 2−2 shows the ways to shift the content of AH, AL, or ACC.

2-7Central Processing Unit

Page 38

CPU Registers

Table 2−2. Available Operations for Shifting Values in the Accumulator

ACC Left Logical LSL or LSLL

Rotation ROL

Right Arithmetic SFR with SXM = 1

or ASRL

Logical SFR with SXM = 0

or LSRL

Rotation ROR

AH or AL Left Logical LSL

Right Arithmetic ASR

Logical LSR

2.2.2 Multiplicand Register (XT)

The multiplicand register (XT register) is used primarily to store a 32-bit signed integer value prior to a 32-bit multiply operation.

The lower 16-bit portion of the XT register is referred to as the TL register. This register can be loaded with a signed 16-bit value that is automatically sign-extended to fill the 32-bit XT register.

The upper 16-bit portion of the XT register is referred to as the T register. The T register is mainly used to store a 16-bit integer value prior to a 16-bit multiply operation.

The T register is also used to specify the shift value for some shift operations. In this case, only a portion of the T register is used, depending on the instruction.

For example:

ASR AX, T performs an arithmetic shift right

based on the four least significant bits of T: T(3:0) = 0...15

ASRL ACC, T performs an arithmetic shift right by

the five least significant bits of T: T(4:0) 0...31

For these operations, the most significant bits of T are ignored.

2-8

Page 39

Figure 2−4. Individually Accessible Halves of the XT Register

T = XT(16:31) TL = XT(15:0)

2.2.3 Product Register (P, PH, PL)

The product register (P register) is typically used to hold the 32-bit result of a multiplication. It can also be loaded directly from a 16- or 32-bit data-memory location, a 16-bit constant, the 32-bit ACC, or a 16-bit or a 32-bit addressable CPU register. The P register can be treated as a 32-bit register or as two independent 16-bit registers: PH (high 16 bits) and PL (low 16 bits); see Figure 2−5.

Figure 2−5. Individually Accessible Halves of the P Register

PH = P(31:16) PL = P(15:0)

CPU Registers

When some instructions access P, PH, or PL, all 32-bits are copied to the ALUshifter block, where the barrel shifter may perform a left shift, a right shift, or no shift. The action of the shifter for these instructions is determined by the product shift mode (PM) bits in status register ST0. Table 2−3 shows the possible PM values and the corresponding product shift modes. When the barrel shifter performs a left shift, the low order bits are filled with zeros. When the shifter performs a right shift, the P register value is sign extended. Instructions that use PH or PL as operands ignore the product shift mode.

For a complete list of instructions affected by PM bits, see Table 2−5 on page 2-20.

2-9Central Processing Unit

Page 40

CPU Registers

Table 2−3. Product Shift Modes

PM Value Product Shift Mode

2.2.4 Data Page Pointer (DP)

In the direct addressing modes, data memory is addressed in blocks of 64 words called data pages. The lower 4M words of data memory consists of 65536 data pages labeled 0 through 65535, as shown in Figure 2−6. In DP direct addressing mode, the 16-bit data page pointer (DP) holds the current data page number. You change the data page by loading the DP with a new number. For information about the direct addressing modes, see section 5.4 on page 5-8.

000

001

010

011

100

101

110

111

Left shift by 1

No shift

Right shift by 1

Right shift by 2

Right shift by 3

Right shift by 4 (if AMODE = 1, left 4)

Right shift by 5

Right shift by 6

2-10

Page 41

Figure 2−6. Pages of Data Memory

CPU Registers

00 0000 0000 0000 00

00 0000 0000 0000 00 00 0000 0000 0000 01

00 0000 0000 0000 01 00 0000 0000 0000 10

00 0000 0000 0000 10

11 1111 1111 1111 11

. . .

. . . . . .

. . .

OffsetData page

00 0000

. . .

11 1111 00 0000

. . .

11 1111 00 0000

. . .

11 1111

. . . . . .

00 0000

. . .

11 1111

Page 0:

Page 1:

Page 2:

Page 65535:

. . . . . .

Data memory

00000000−0000003F

00000040−0000007F

00000080−000000BF

. . . . . .

003FFFC0−003FFFFF

Data memory above 4M words is not accessible using the DP.

When operating in C2xLP source-compatible mode, a 7-bit offset is used and the least significant bit of the DP register is ignored. See Appendix C for more details.

2.2.5 Stack Pointer (SP)

The stack pointer (SP) enables the use of a software stack in data memory. The stack pointer has only 16 bits and can only address the low 64K of data space (see Figure 2−7). When the SP is used, the upper six bits of the 32-bit address are forced to 0. (For information about addressing modes that use the SP, see section 5.5 on page 5-9.). After reset, SP points to address 00000400

2-11Central Processing Unit

Page 42

CPU Registers

Figure 2−7. Address Reach of the Stack Pointer

Data memory

Range accessible

by way of SP

Range not accessible

by way of SP

00000000−0000FFFF

00010000−FFFFFFFF

The operation of the stack is as follows:

- The stack grows from low memory to high memory.

- The SP always points to the next empty location in the stack.

- At reset, the SP is initialized, so that it points to address 0000 0400

- When 32-bit values are saved to the stack, the least significant 16 bits are

saved first, and the most significant 16 bits are saved to the next higher address (little endian format).

- When 32-bit operations read or write a 32-bit value, the C28x CPU expects

the memory wrapper or peripheral-interface logic to align that read or write to an even address. For example, if the SP contains the odd address 0000 0083

, a 32-bit read operation reads from addresses 0000 0082

and 0000 008316.

- The SP overflows if its value is increased beyond FFFF

below 0000 from 0000

. When the SP increases past FFFF16, it counts forward

. For example, if SP = FFFE16 and an instruction adds 3 to the

SP, the result is 000116. When the SP decreases past 000016, it counts backward from FFFF

. For example, if SP = 000216 and an instruction

subtracts 4 from SP, the result is FFFE16.

- When values are being saved to the stack, the SP is not forced to align with

even or odd addresses. Alignment is forced by the memory wrapper or peripheral-interface logic.

2.2.6 Auxiliary Registers (XAR0−XAR7, AR0−AR7)

The CPU provides eight 32-bit registers that can be used as pointers to memory or as general-purpose registers (see Section 5.6, Indirect Addressing

2-12

or decreased

Page 43

Modes, on page 5-10 . The auxiliary registers are: XAR0, XAR1, XAR2, XAR3, XAR4, XAR5, XAR6, and XAR7.

Many instructions allow you to access the 16 LSBs of XAR0−XAR7. As shown in Figure 2−8, the 16 LSBs of the auxiliary registers are referred to as AR0−AR7. AR0−AR7 can be used as general purpose registers for loop con- trol and for efficient 16-bit comparisons.

When accessing AR0−AR7, the upper 16 bits of the register (known as AR0H− AR7H) may or may not be modified, depending on the instruction used (see Chapter 6 for information on the behavior of particular instructions). AR0H− AR7H are accessed only as part of XAR0−XAR7 and are not individually accessible.

Figure 2−8. XAR0 − XAR7 Registers

CPU Registers

n = number 0 through 7

For ACC operations, all 32 bits are valid (@XARn). For 16-bit operations, the lower 16 bits are used and upper 16 bits are ignored (@ARn).

XAR0 − XAR7 can also be used by some instructions to point to any value in program memory; see Section 5.6, Indirect Addressing Modes.

Many instructions allow you to access the 16 least significant bits (LSBs) of XAR0 as one auxiliary register of AR0

Figure 2−9. XAR0 − XAR7

ARnH = XARn(31:16)

XARn(31:0)

−XAR7. As shown in Figure 2−9, 16 LSBs of XAR0−XAR7 are known

−AR7.

XAR0(32:0)

ARn = XARn(15:0)

AR0 = XAR0(15:0)

XAR7(32:0)

AR7 = XAR7(15:0)

2-13Central Processing Unit

Page 44

CPU Registers

2.2.7 Program Counter (PC)

When the pipeline is full, the 22-bit program counter (PC) always points to the instruction that is currently being processed — the instruction that has just reached the decode 2 phase of the pipeline. Once an instruction reaches this phase of the pipeline, it cannot be flushed from the pipeline by an interrupt. It is executed before the interrupt is taken. The pipeline is discussed in Chapter 4.

2.2.8 Return Program Counter (RPC)

When a call operation is performed using the LCR instruction, the return address is saved in the RPC register and the old value in the RPC is saved on the stack (in two 16-bit operations). When a return operation is performed using the LRETR instruction, the return address is read from the RPC register and the value on the stack is written into the RPC register (in two 16-bit operations). Other call instructions do not use the RPC register. For more information, see the instructions in Chapter 6.

2.2.9 Status Registers (ST0, ST1)

The C28x has two status registers, ST0 and ST1, which contain various flag bits and control bits. These registers can be stored into and loaded from data memory, enabling the status of the machine to be saved and restored for subroutines.

The status bits have been organized according to when the bit values are modified in the pipeline. Bits in ST0 are modified in the execute phase of the pipeline; bits in ST1 are modified in the decode 2 phase. (For details about the pipeline, see Chapter 4.) The status bits are described in detail in sections 2.3 (ST0) and 2.4 (ST1). Also, ST0 and ST1 are included in Appendix A, Register Quick Reference.

2.2.10 Interrupt-Control Registers (IFR, IER, DBGIER)

The C28x CPU has three registers dedicated to the control of interrupts:

- Interrupt flag register (IFR)

- Interrupt enable register (IER)

- Debug interrupt enable register (DBGIER)

These registers handle interrupts at the CPU level. Devices with a peripheral interrupt expansion (PIE) block will have additional interrupt control as part of the PIE module.

The IFR contains flag bits for maskable interrupts (those that can be enabled and disabled with software). When one of these flags is set, by hardware or

2-14

Page 45

CPU Registers

software, the corresponding interrupt will be serviced if it is enabled. You enable or disable a maskable interrupt with its corresponding bit in the IER. The DBGIER indicates the time-critical interrupts that will be serviced (if enabled) while the DSP is in real-time emulation mode and the CPU is halted.

The C28x CPU interrupts and the interrupt-control registers are described in detail in Chapter 3, Interrupts. Also, the IFR, IER, and DBGIER are included in Appendix A, Register Quick Reference.

2-15Central Processing Unit

Page 46

Status Register (ST0)

2.3 Status Register (ST0)

The following figure shows the bit fields of status register (ST0). All of these bit fields are modified in the execute phase of the pipeline. Detailed descriptions of these bits follow the figure.

Figure 2−10. Bit Fields of Status Register (ST0)

15 10 9 7 6543210

OVC/OVCU

R/W-00 0000 R/W−0 RW−0 RW−0 RW−0 RW−0 RW−0 RW−0 RW−0

Note: R = Read access; W = Write access; value following dash (−) is value after reset.

PM V N Z C TC OVM SXM

OVC/OVCU

Bits15−10

Overflow counter. The overflow counter behaves differently for signed and unsigned operations.

For signed operations, the overflow counter is a 6-bit signed counter with a range of −32 to 31. When overflow mode is off (OVM = 0), ACC overflows normally, and OVC keeps track of overflows. When overflow mode is on (OVM = 1) and an overflow occurs in ACC, the OVC is not affected. Instead, the CPU automatically fills ACC with a positive or negative saturation value (see the description for OVM on page 2-32).

When ACC overflows in the positive direction (from 7FFFFFFF

to 80000000

), the



OVC is incremented by 1. When ACC overflows in the negative direction (from 80000000 to 7FFFFFFF

) the OVC is decremented by 1. The increment or decrement is performed



as the overflow affects the V flag.

For unsigned operations (OVCU), the counter increments for ADD when a Carry is generated and decrements for a SUB when a Borrow is generated (similar to a carry counter).

If OVC increments past its most positive value, 31, the counter wraps around to −32. If OVC decrements past its most negative value, −32, the counter wraps around to 31. At reset, OVC is cleared.

OVC is not affected by overflows in registers other than ACC and is not affected by compare instructions (CMP and CMPL). The table that follows explains how OVC may be affected by the saturate accumulator (SAT ACC) instruction.

Table 2−4 lists the instructions affecting OVC/OVCU. See the instruction set in Chapter 6 for a complete description of each instruction.

2-16

Page 47

Status Register (ST0)

Table 2−4. Instructions That Affect OVC/OVCU

Signed Addition Instructions Effect on OVC/OVCU

ADD ACC,loc16 << shift if(OVM == 0) Inc OVC on +ve signed

overflow

ADD ACC,#16bit << shift

ADD ACC,loc16 << T

ADD loc16,#16bitSigned

ADDB ACC,#8bit

ADDCL ACC,loc32

ADDCU ACC,loc16

ADDL ACC,loc32

ADDL loc32,ACC

ADDU ACC,loc16

DMAC ACC:P,loc32,*XAR7/++

INC loc16

MAC P,loc16,*XAR7/++

MAC P,loc16,0:pma

MOVA T,loc16

MOVAD T,loc16

MPYA P,loc16,#16bit

MPYA P,T,loc16

QMACL P,loc32,*XAR7/++

QMPYAL P,XT,loc32

SQRA loc16

XMAC P,loc16,*(pma)

XMACD P,loc16,*(pma)

Signed Subtraction Instructions Effect on OVC/OVCU

DEC loc16 if(OVM == 0) Dec OVC on −ve signed

overflow

MOVS T,loc16

2-17Central Processing Unit

Page 48

Status Register (ST0)

Table 2−4. Instructions That Affect OVC/OVCU (Continued)

Signed Addition Instructions Effect on OVC/OVCU

MPYS P,T,loc16

QMPYSL P,XT,loc32

SBBU ACC,loc16

SQRS loc16

SUB ACC,#16bit << shift

SUB ACC,loc16 << shift

SUB ACC,loc16 << T

SUBB ACC,#8bit

SUBBL ACC,loc32

SUBL ACC,loc32

SUBL loc32,ACC

SUBRL loc32,ACC

SUBU ACC,loc16

SUBUL ACC,loc32

SUBUL P,loc32

Unsigned Instructions Effect on OVC/OVCU

ADDUL ACC,loc32 Inc OVC/OVCU on unsigned carry

ADDUL P,loc32

IMPYAL P,XT,loc32

IMACL P,loc32,*XAR7/++

Misc Instructions Effect on OVC/OVCU

SAT ACC if(OVC > 0) Saturate +ve

if(OVC < 0) Saturate −ve

OVC = 0

SAT64 ACC:P

ZAPA OVC = 0

ZAP OVC

MOV OVC,loc16 OVC = [loc16(15:10)]

2-18

Page 49

Table 2−4. Instructions That Affect OVC/OVCU (Continued)

Signed Addition Instructions Effect on OVC/OVCU

MOVU OVC,loc16 OVC = [loc16(5:0)]

Condition Operation Performed by SAT ACC Instruction

Status Register (ST0)

OVC = 0

OVC > 0

OVC < 0

Bits 9−7

Leave ACC and OVC unchanged.

Saturate ACC in the positive direction (fill ACC with 7FFFFFFF

Saturate ACC in the negative direction (fill ACC with 8000000016), and clear OVC.

Product shift mode bits. This 3-bit value determines the shift mode for any output operation from the product (P) register. The shift modes are shown in the following table. The output can be to the ALU or to memory. All instructions that are affected by the product shift mode will sign extend the P register value during a right shift operation. At reset, PM is cleared (left shift by 1 bit is the default).

PM is summarized as follows:

000 Left shift by 1. During the shift, the low-order bit is zero filled. At reset, this mode

is selected.

001 No shift

010 Right shift by 1. During the shift, the lower bits are lost, and the shifted value is sign

extended.

011 Right shift by 2. During the shift, the lower bits are lost, and the shifted value is sign

extended.

100 Right shift by 3. During the shift, the lower bits are lost, and the shifted value is sign

extended.

101 Right shift by 4. During the shift, the lower bits are lost, and the shifted value is sign

extended. Note, if AMODE = 1, then 101 is a left shift by 4.

), and clear OVC.

110 Right shift by 5. During the shift, the lower bits are lost, and the shifted value is sign

extended.

111 Right shift by 6. During the shift, the lower bits are lost, and the shifted value is sign

extended.

Note: For performing unsigned arithmetic, you must use a product shift of 0 (PM = 001) to avoid sign extension and genera-

tion of incorrect results.

Table 2−5 lists instructions that are affected by the PM bits. See the instruction set in chapter 6 for a complete description of each instruction.

2-19Central Processing Unit

Page 50

Status Register (ST0)

Table 2−5. Instructions Affected by the PM Bits

Instruction Effect of PM

CMPL ACC,P << PM flags set on(ACC − P << PM)

DMAC ACC:P,loc32,*XAR7/++ ACC = ACC + MSW*MSW << PM

IMACL P,loc32,*XAR7/++ P = ([loc32] * Prog[*XAR7/++]) << PM

IMPYAL P,XT,loc32 P = (XT * [loc32]) << PM

IMPYL P,XT,loc32 P = (XT *[loc32]) << PM

IMPYSL P,XT,loc32 ACC = ACC − P unsigned

IMPYXUL P,XT,loc32 P = (XT sign * [loc32]uns) << PM

MAC P,loc16,*XAR7/++ ACC = ACC + P << PM

MAC P,loc16,0:pma ACC = ACC + P << PM

MOV loc16,P [loc16] = low(P << PM)

P = P + LSW*LSW << PM

P = (XT * [loc32]) << PM

MOVA T,loc16 ACC = ACC + P << PM

MOVAD T,loc16 ACC = ACC + P << PM

MOVH loc16,P [loc16] = high(P << PM)

MOVP T,loc16 ACC = P << PM

MOVS T,loc16 ACC = ACC − P << PM

MPYA P,loc16,#16bit ACC = ACC + P << PM

MPYA P,T,loc16 ACC = ACC + P << PM

MPYS P,T,loc16 ACC = ACC − P << PM

QMACL P,loc32,*XAR7 ACC = ACC + P << PM

QMACL P,loc32,*XAR7++ ACC = ACC + P << PM

QMPYAL P,XT,loc32 ACC = ACC + P << PM

QMPYSL P,XT,loc32 ACC = ACC − P << PM

SQRA loc16 ACC = ACC + P << PM

SQRS loc16 ACC = ACC − P << PM

XMAC P,loc16,*(pma) ACC = ACC + P << PM

XMACD P,loc16,*(pma) ACC = ACC + P << PM

2-20

Page 51

Status Register (ST0)

Bit 6

Overflow flag. If the result of an operation causes an overflow in the register holding the result, V is set and latched. If no overflow occurs, V is not modified. Once V is latched, it remains set until it is cleared by reset or by a conditional branch instruction that tests V. Such a conditional branch clears V regardless of whether the tested condition (V = 0 or V = 1) is true.

An overflow occurs in ACC (and V is set) if the result of an addition or subtraction does not fit within the signed numerical range −2

An overflow occurs in AH, AL, or another 16-bit register or data-memory location if the result of an addition or subtraction does not fit within the signed numerical range −2

1), or 8000

The instructions CMP, CMPB and CMPL do not affect the state of the V flag. Table 2−6 lists the instructions that are affected by V flag. See Chapter 6 for more details on instructions.

to 7FFF16.

to (+231 − 1), or 8000000016 to 7FFFFFFF16.

to (+215 −

V can be summarized as follows: 0

V has been cleared.

1 An overflow has been detected, or V has been set.

Table 2−6. Instructions Affected by V flag

Instruction Description

ABS ACC if(ACC == 0x8000 0000) V = 1

ABSTC ACC if(ACC == 0x8000 0000) V = 1

ADD ACC,#16bit << shift V = 1 on signed overflow

ADD ACC,loc16 << shift V = 1 on signed overflow

ADD ACC,loc16 << T V = 1 on signed overflow

ADD AX,loc16 V = 1 on signed overflow

ADD loc16,#16bitSigned V = 1 on signed overflow

ADD loc16,AX V = 1 on signed overflow

ADDB ACC,#8bit V = 1 on signed overflow

ADDB AX,#8bitSigned V = 1 on signed overflow

ADDCL ACC,loc32 V = 1 on signed overflow

ADDCU ACC,loc16 V = 1 on signed overflow

ADDL ACC,loc32 V = 1 on signed overflow

ADDL loc32,ACC V = 1 on signed overflow

ADDU ACC,loc16 V = 1 on signed overflow

ADDUL ACC,loc32 V = 1 on signed overflow

2-21Central Processing Unit

Page 52

Status Register (ST0)

Table 2−6. Instructions Affected by V flag (Continued)

Instruction Description

ADDUL P,loc32 V = 1 on signed overflow

B 16bitOff,COND V = 0 if tested

BF 16bitOff,COND V = 0 if tested

DEC loc16 V = 1 on signed overflow

DMAC ACC:P,loc32,*XAR7/++ V = 1 on signed overflow

IMACL P,loc32,*XAR7/++ V = 1 on signed overflow

IMPYAL P,XT,loc32 V = 1 on signed overflow

IMPYSL P,XT,loc32 V = 1 on signed overflow

INC loc16 V = 1 on signed overflow

MAC P,loc16,*XAR7/++ V = 1 on signed overflow

MAC P,loc16,0:pma V = 1 on signed overflow

MAX AX,loc16 if((AX − [loc16]) > 0) V = 1

MAXL ACC,loc32 if((ACC − [loc32]) > 0) V = 1

MIN AX,loc16 if((AX − [loc16]) < 0) V = 1

MINL ACC,loc32 if((ACC − [loc32]) < 0) V = 1

MOV loc16,AX,COND V = 0 if tested

MOVA T,loc16 V = 1 on signed overflow

MOVAD T,loc16 V = 1 on signed overflow

MOVB loc16,#8bit,COND V = 0 if tested

MOVL loc32,ACC,COND V = 0 if tested

MOVS T,loc16 V = 1 on signed overflow

MPYA P,loc16,#16bit V = 1 on signed overflow

MPYA P,T,loc16 V = 1 on signed overflow

MPYS P,T,loc16 V = 1 on signed overflow

NEG ACC if(ACC == 0x8000 0000) V = 1

NEG AX if(AX == 0x8000) V = 1

NEG64 ACC:P if(ACC:P == 0x80....00) V = 1

2-22

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Status Register (ST0)

Table 2−6. Instructions Affected by V flag (Continued)

Instruction Description

NEGTC ACC if(TC == 1)

if(ACC == 0x8000 0000) V = 1

QMACL P,loc32,*XAR7/++ V = 1 on signed overflow

QMPYAL P,XT,loc32 V = 1 on signed overflow

QMPYSL P,XT,loc32 V = 1 on signed overflow

SAT ACC if(OVC == 0) V = 0 else V = 1

SAT64 ACC:P if(OVC == 0) V = 0 else V = 1

SB 8bitOff,COND V = 0 if tested

SBBU ACC,loc16 V = 1 on signed overflow

SQRA loc16 V = 1 on signed overflow

SQRS loc16 V = 1 on signed overflow

SUB ACC,#16bit << shift V = 1 on signed overflow

SUB ACC,loc16 << shift V = 1 on signed overflow

SUB ACC,loc16 << T V = 1 on signed overflow

SUB AX,loc16 V = 1 on signed overflow

SUB loc16,AX V = 1 on signed overflow

SUBB ACC,#8bit V = 1 on signed overflow

SUBBL ACC,loc32 V = 1 on signed overflow

SUBL ACC,loc32 V = 1 on signed overflow

SUBL loc32,ACC V = 1 on signed overflow

SUBR loc16,AX V = 1 on signed overflow

SUBRL loc32,ACC V = 1 on signed overflow

SUBU ACC,loc16 V = 1 on signed overflow

SUBUL ACC,loc32 V = 1 on signed overflow

SUBUL P,loc32 V = 1 on signed overflow

XB pma,COND V = 0 if tested

XCALL pma,COND V = 0 if tested

XMAC P,loc16,*(pma) V = 1 on signed overflow

2-23Central Processing Unit

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Status Register (ST0)

Table 2−6. Instructions Affected by V flag (Continued)

Instruction Description

XMACD P,loc16,*(pma)

XRETC COND V = 0 if tested

V = 1 on signed overflow

Bit 5

Negative flag. During certain operations, N is set if the result of the operation is a negative number or cleared if the result is a positive number. At reset, N is cleared.

Results in ACC are tested for the negative condition. Bit 31 of ACC is the sign bit. If bit 31 is a 0, ACC is positive; if bit 31 is a 1, ACC is negative. N is set if a result in ACC is negative or cleared if a result is positive.

Results in AH, AL, and other 16-bit registers or data-memory locations are also tested for the negative condition. In these cases bit 15 of the value is the sign bit (1 indicates negative, 0 indicates positive). N is set if the value is negative or cleared if the value is positive.

The TEST ACC instruction sets N if the value in ACC is negative. Otherwise the instruction clears N.

As shown in Table 2−7, under overflow conditions, the way the N flag is set for compare operations is different from the way it is set for addition or subtraction operations. For addition or subtraction operations, the N flag is set to match the most significant bit of the truncated result. For compare operations, the N flag assumes infinite precision. This applies to operations whose result is loaded to ACC, AH, AL, another register, or a data-memory location.

Table 2−7. Negative Flag Under Overflow Conditions

†

Pos Neg

†

(A − B)

Neg

(due to overflow in positive direction)

Subtraction

N = 1 N = 0

Compare

‡

Pos

Neg Pos

†

For 32-bit data: Pos = Positive number from 0000000016 to 7FFFFFFF

ББББББББББББББББББББББББББББ

For 16-bit data: Pos = Positive number from 000016 to 7FFF

ББББББББББББББББББББББББББББ

‡

The compare instructions are CMP, CMPB, CMPL, MIN, MAX, MINL, and MAXL.

(due to overflow in negative direction)

Neg = Negative number from 8000000016 to FFFFFFFF

Neg = Negative number from 800016 to FFFF

N = 0 N = 1

N can be summarized as follows: 0

The tested number is positive, or N has been cleared.

1 The tested number is negative, or N has been set.

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Status Register (ST0)

Bit 4

Bit 3

Zero flag. Z is set if the result of certain operations is 0 or is cleared if the result is nonzero. This applies to results that are loaded into ACC, AH, AL, another register, or a data-memory location. At reset, Z is cleared.

The TEST ACC instruction sets Z if the value in ACC is 0. Otherwise, it clears Z.

Z can be summarized as follows: 0

The tested number is nonzero, or Z has been cleared.

1 The tested number is 0, or Z has been set.

Carry bit. This bit indicates when an addition or increment generates a carry or when a subtraction, compare, or decrement generates a borrow. It is also affected by rotate operations on ACC and barrel shifts on ACC, AH, and AL.

During additions/increments, C is set if the addition generates a carry; otherwise C is cleared. There is one exception: If you are using the ADD instruction with a shift of 16, the ADD instruction can set C but cannot clear C.

During subtractions/decrements/compares, C is cleared if the subtraction generates a carry; otherwise C is set. There is one exception: if you are using the SUB instruction with a shift of 16, the SUB instruction can clear C but cannot set C.

This bit can be individually set and cleared by the SETC C instruction and CLRC C instruction, respectively. At reset, C is cleared.

C can be summarized as follows: 0

A subtraction generated a borrow, an addition did not generate a carry, or C has been cleared. Exception: An ADD instruction with a shift of 16 cannot clear C.

1 An addition generated a carry, a subtraction did not generate a borrow, or C has

been set. Exception: A SUB instruction with a shift of 16 cannot set C.

Table 2−8 lists the bits that are affected by the C bit. For more information on instructions, see Chapter 6.

Table 2−8. Bits Affected by the C Bit

Instruction Affect of or Affect on C

ABS ACC C = 0

ABSTC ACC C = 0

ADD ACC,#16bit << shift C = 1 on carry else C = 0

ADD ACC,loc16 << shift if(shift == 16)

C = 1 on carry

if(shift != 16)

C = 1 on carry else C = 0

2-25Central Processing Unit

Page 56

Status Register (ST0)

Table 2−8. Bits Affected by the C Bit (Continued)

Instruction Affect of or Affect on C

ADD ACC,loc16 << T C = 1 on carry else C = 0

ADD AX,loc16 C = 1 on carry else C = 0

ADD loc16,#16bitSigned C = 1 on carry else C = 0

ADD loc16,AX C = 1 on carry else C = 0

ADDB ACC,#8bit C = 1 on carry else C = 0

ADDB AX,#8bitSigned C = 1 on carry else C = 0

ADDCL ACC,loc32 ACC = ACC + [loc32] + C

C = 1 on carry else C = 0

ADDCU ACC,loc16 ACC = ACC + [loc16] + C

C = 1 on carry else C = 0

ADDL ACC,loc32 C = 1 on carry else C = 0

ADDL loc32,ACC C = 1 on carry else C = 0

ADDU ACC,loc16 C = 1 on carry else C = 0

ADDUL ACC,loc32 C = 1 on carry else C = 0

ADDUL P,loc32 C = 1 on carry else C = 0

ASR AX,1..16 C = AX(bit(shift−1))

ASR AX,T if(T == 0) C = 0

else C = AX(bit(T−1))

ASR64 ACC:P,1..16 C = P(bit(shift−1))

ASR64 ACC:P,T if(T == 0) C = 0

else C = P(bit(T−1))

ASRL ACC,T if(T == 0) C = 0

else C = ACC(bit(T−1))

B 16bitOff,COND C bit used as test condition

BF 16bitOff,COND C bit used as test condition

CLRC C C = 0

CMP AX,loc16 C = 0 on borrow else C = 1

2-26

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Status Register (ST0)

Table 2−8. Bits Affected by the C Bit (Continued)

Instruction Affect of or Affect on C

CMP loc16,#16bitSigned for([loc16] − 16bitSigned)

C = 0 on borrow else C = 1

CMPB AX,#8bit

CMPL ACC,loc32 for(ACC − [loc32])

CMPL ACC,P << PM for(ACC − P << PM)

DEC loc16+ C = 0 on borrow else C = 1

DMAC ACC:P,loc32,*XAR7/++ C = 1 on carry else C = 0

IMACL P,loc32,*XAR7/++ C = 1 on carry else C = 0

IMPYAL P,XT,loc32 C = 1 on carry else C = 0

IMPYSL P,XT,loc32 C = 0 on borrow else C = 1

C = 0 on borrow else C = 1

INC loc16 C = 1 on carry else C = 0

LSL ACC,1..16 C = ACC(bit(32−shift))

LSL ACC,T if(T == 0) C = 0

else C = ACC(bit(32−T))

LSL AX,1..16 C = AX(bit(16−shift))

LSL AX,T if(T == 0) C = 0

else C = AX(bit(16−T))

LSL64 ACC:P,1..16 C = ACC(bit(32−shift))

LSL64 ACC:P,T if(T == 0) C = 0

else C = ACC(bit(32−T))

LSLL ACC,T if(T == 0) C = 0

else C = ACC(bit(32−T))

LSR AX,1..16 C = AX(bit(shift−1))

LSR AX,T if(T == 0) C = 0

else C = AX(bit(T−1))

LSR64 ACC:P,1..16 C = P(bit(shift−1))

2-27Central Processing Unit

Page 58

Status Register (ST0)

Table 2−8. Bits Affected by the C Bit (Continued)

Instruction Affect of or Affect on C

LSR64 ACC:P,T if(T == 0) C = 0

else C = P(bit(T−1))

LSRL ACC,T if(T == 0) C = 0

else C = ACC(bit(T−1))

MAC P,loc16,*XAR7/++ C = 1 on carry else C = 0

MAC P,loc16,0:pma C = 1 on carry else C = 0

MAX AX,loc16 for(AX − [loc16])

C = 0 on borrow else C = 1

MAXL ACC,loc32 for(ACC − [loc32])

C = 0 on borrow else C = 1

MIN AX,loc16 for(AX − [loc16])

C = 0 on borrow else C = 1

MINL ACC,loc32 for(ACC − [loc32])

C = 0 on borrow else C = 1

MOV loc16,AX,COND C bit used as test condition

MOVA T,loc16 C = 1 on carry else C = 0

MOVAD T,loc16 C = 1 on carry else C = 0

MOVB loc16,#8bit,COND C bit used as test condition

MOVL loc32,ACC,COND C bit used as test condition

MOVS T,loc16 C = 0 on borrow else C = 1

MPYA P,loc16,#16bit C = 1 on carry else C = 0

MPYA P,T,loc16 C = 1 on carry else C = 0

MPYS P,T,loc16 C = 0 on borrow else C = 1

NEG ACC if( ACC == 0) C = 1

else C = 0

NEG AX if(AX == 0) C = 1

else C = 0

NEG64 ACC:P if( ACC:P == 0) C = 1

else C = 0

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Status Register (ST0)

Table 2−8. Bits Affected by the C Bit (Continued)

Instruction Affect of or Affect on C

NEGTC ACC if(TC == 1)

if( ACC == 0) C = 1

else C = 0

QMACL P,loc32,*XAR7/++ C = 1 on carry else C = 0

QMPYAL P,XT,loc32 C = 1 on carry else C = 0

QMPYSL P,XT,loc32 C = 0 on borrow else C = 1

ROL ACC C <− (ACC << 1) <− C(before)

ROR ACC C(before) −> (ACC >> 1) −> C

SAT ACC C = 0

SAT64 ACC:P C = 0

SB 8bitOff,COND C bit used as test condition

SBBU ACC,loc16 ACC = ACC − ([loc16] + ~C)

C = 0 on borrow else C = 1

SETC C C = 1

SFR ACC,1..16 C = ACC(bit(shift−1))

SFR ACC,T if(T == 0) C = 0

else C = ACC(bit(T−1))

SQRA loc16 C = 1 on carry else C = 0

SQRS loc16 C = 0 on borrow else C = 1

SUB ACC,#16bit << shift C = 0 on borrow else C = 1

SUB ACC,loc16 << shift if(shift == 16)

C = 0 on borrow

if(shift != 16)

C = 0 on borrow else C = 1

SUB ACC,loc16 << T C = 0 on borrow else C = 1

SUB AX,loc16 C = 0 on borrow else C = 1

SUB loc16,AX C = 0 on borrow else C = 1

SUBB ACC,#8bit C = 0 on borrow else C = 1

2-29Central Processing Unit

Page 60

Status Register (ST0)

Table 2−8. Bits Affected by the C Bit (Continued)

Instruction Affect of or Affect on C

SUBBL ACC,loc32 ACC = ACC − ([loc32] + ~C)

C = 0 on borrow else C = 1

SUBCU ACC,loc16 for(ACC − [loc16]<<15)

C = 0 on borrow else C = 1

SUBCUL ACC,loc32 for(ACC<<1 + P(31) − [loc32])

C = 0 on borrow else C = 1

SUBL ACC,loc32 C = 0 on borrow else C = 1

SUBL loc32,ACC C = 0 on borrow else C = 1

SUBR loc16,AX C = 0 on borrow else C = 1

SUBRL loc32,ACC C = 0 on borrow else C = 1

SUBU ACC,loc16 C = 0 on borrow else C = 1

SUBUL ACC,loc32 C = 0 on borrow else C = 1

Bit 2

SUBUL P,loc32 C = 0 on borrow else C = 1

XB pma,COND C bit used as test condition

XCALL pma,COND C bit used as test condition

XMAC P,loc16,*(pma) C = 1 on carry else C = 0

XMACD P,loc16,*(pma) C = 1 on carry else C = 0

XRETC COND C bit used as test condition

Test/control flag. This bit shows the result of a test performed by either the TBIT (test bit) instruction or the NORM (normalize) instruction.

The TBIT instruction tests a specified bit. When TBIT is executed, the TC bit is set if the tested bit is 1 or cleared if the tested bit is 0.

When a NORM instruction is executed, TC is modified as follows: If ACC holds 0, TC is set. If ACC does not hold 0, the CPU calculates the exclusive-OR of ACC bits 31 and 30, and then loads TC with the result.

This bit can be individually set and cleared by the SETC TC instruction and CLRC TC instruction, respectively. At reset, TC is cleared.

Table 2−9 lists the instructions that affect the TC bit. See the instruction set in Chapter 6 for a complete description of each instruction.

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Page 61

Table 2−9. Instructions That Affect the TC Bit

Instruction Affect on the TC bit

ABSTC ACC if( ACC < 0 ) TC = TC ^ 1

B 16bitOff,COND TC bit used as test condition

BF 16bitOff,COND TC bit used as test condition

CLRC TC TC = 0

CMPR 0/1/2/3 TC = 0

CSB ACC TC = N flag

MOV loc16,AX,COND TC bit used as test condition

MOVB loc16,#8bit,COND TC bit used as test condition

Status Register (ST0)

0: if(AR(ARP) == AR0) TC = 1

1: if(AR(ARP) < AR0) TC = 1

2: if(AR(ARP) > AR0) TC = 1

3: if(AR(ARP) != AR0) TC = 1

MOVL loc32,ACC,COND TC bit used as test condition

NEGTC ACC TC bit used as test condition

NORM ACC,XARn++/−−

NORM ACC,*ind

SB 8bitOff,COND

if(ACC |= 0)

TC = ACC(31) ^ ACC(30)

else

TC = 1

TC bit used as test condition

SBF 8bitOff,TC/NTC TC bit used as test condition

SETC TC TC = 1

TBIT loc16,#bit TC = [loc16(bit)]

TBIT loc16,T TC = [loc16(15−T)]

TCLR loc16,#bit TC = [loc16(bit)]

TSET loc16,#bit TC = [loc16(bit)]

XB pma,COND TC bit used as test condition

XCALL pma,COND TC bit used as test condition

XRETC COND TC bit used as test condition

2-31Central Processing Unit

Page 62

Status Register (ST0)

OVM

Bit 1

SXM

Bit 0

Overflow mode bit. When ACC accepts the result of an addition or subtraction and the result causes an overflow, OVM determines how the CPU handles the overflow as follows:.

0 Results overflow normally in ACC. The OVC reflects the overflow (see the de-

scription for the OVC on page 2-16)

1 ACC is filled with either its most positive or most negative value as follows:

If ACC overflows in the positive direction (from 7FFFFFFF ACC is then filled with 7FFFFFFF

If ACC overflows in the negative direction (from 80000000 ACC is then filled with 80000000

to 80000000

to 7FFFFFFF



This bit can be individually set and cleared by the SETC OVM instruction and CLRC OVM instruction, respectively. At reset, OVM is cleared.

Sign-extension mode bit. SXM affects the MOV, ADD, and SUB instructions that use a 16-bit value in an operation on the 32-bit accumulator. When the 16-bit value is loaded into (MOV), added to (ADD), or subtracted from (SUB) the accumulator, SXM determines whether the value is sign extended during the operation as follows:

0 Sign extension is suppressed. (The value is treated as unsigned.)i

1 Sign extension is enabled. (The value is treated as signed.)

SXM also determines whether the accumulator is sign extended when it is shifted right by the SFR instruction. SXM does not affect instructions that shift the product register value; all right shifts of the product register value use sign extension.



This bit can be individually set and cleared by the SETC SXM instruction and CLRC SXM instruction, respectively. At reset, SXM is cleared. Table 2−10 lists the in- structions that are affected by SXM. See Chapter 6 for more details on instructions.

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Page 63

Table 2−10. Instructions Affected by SXM

Instruction Description

ADD ACC,#16bit << shift Affected By SXM

ADD ACC,loc16 << shift Affected By SXM

ADD ACC,loc16 << T Affected By SXM

CLRC SXM SXM = 0

MOV ACC,#16bit << shift Affected By SXM

MOV ACC,loc16 << shift Affected By SXM

MOV ACC,loc16 << T Affected By SXM

SETC SXM SXM = 1

SFR ACC,1..16 Affected By SXM

SFR ACC,T Affected By SXM

SUB ACC,#16bit << shift Affected By SXM

SUB ACC,loc16 << shift Affected By SXM

Status Register (ST0)

SUB ACC,loc16 << T Affected By SXM

2-33Central Processing Unit

Page 64

Status Register ST1

2.4 Status Register ST1

The following figure shows the bit fields of status register ST1. All of these bit fields are modified in the decode 2 phase of the pipeline. Detailed descriptions of these bits follow the figure.

Figure 2−11.Bit Fields of Status Register 1 (ST1)

15 13 12 11 10 9 8

ARP XF M0M1MAP Reserved OBJMODE AMODE

R/W-000 R/W−0 R/W−1 R/W−0 R/W−0 R/W−0

76543210

IDLESTAT

R−0 R/W−0R−0 R/W−0 R/W−1 R/W−0 R/W−1 R/W−1

EALLOW LOOP SPA VMAP PAGE0 DBGM INTM

ARP

Bits 15−13

Bit 12

Auxiliary register pointer. This 3-bit field points to the current auxiliary register. This is one of the 32-bit auxiliary registers (XAR0−XAR7). The mapping of ARP values to auxiliary registers is as follows:

ARP

000 XAR0 (selected at reset)

001 XAR1

010 XAR2

011 XAR3

100 XAR4

101 XAR5

110 XAR6

111

XF status bit. This bit reflects the current state of the XFS output signal, which is compatible to the C2XLP CPU. This bit is set by the ”SETC XF” instruction. This bit is cleared by the ”CLRC XF” instruction. The pipeline is not flushed when setting or clearing this bit using the given instructions. This bit can be saved and restored by interrupts and when restoring the ST1 register. This bit is set to 0 on reset.

Selected Auxiliary Register

XAR7

M0M1MAP

Bit 11

M0 and M1 mapping mode bit. The M0M1MAP bit should always remain set to 1 in the C28x object mode. This is the default value at reset. The M0M1MAP bit may be set low when operating in C27x-compatible mode. The effect of this bit, when low, is to swap the location of blocks M0 and M1 only in program space and to set the stack pointer default reset value to 0x000. C28x mode users should never set this bit to 0.

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Status Register ST1

Reserved

Bit 10

OBJMODE

Bit 9

AMODE

Bit 8

IDLESTAT

Bit 7

Reserved. This bit is reserved. Writes to this bit have no effect.

Object compatibility mode bit. This mode is used to select between C27x object

mode (OBJMODE == 0) and C28x object mode (OBJMODE == 1) compatibility. This bit is set by the ”C28OBJ” (or ”SETC OBJMODE”) instructions. This bit is cleared by the ”C27OBJ” (or ”CLRC OBJMODE”) instructions. The pipeline is flushed when setting or clearing this bit using the given instructions. This bit is saved and restored by interrupts and when restoring the ST1 register. This bit is set to 0 on reset.

Address mode bit. This mode, in conjunction with the PAGE0 mode bit, is used to select the appropriate addressing mode decodes. This bit is set by the “LPADDR” (”SETC AMODE”) instructions. This bit is cleared by the ”C28ADDR” (or ”CLRC AMODE”) instructions. The pipeline is not flushed when setting or clearing this bit using the given instructions. This bit is saved and restored by interrupts and when restoring the ST1 register. This bit is set to 0 on reset.

Note: Setting PAGE0 = AMODE = 1 will generate an illegal instruction trap ONLY for instructions that decode a memory or register addressing mode field (loc16 or loc32).

IDLE status bit. This ready-only bit is set when the IDLE instruction is executed. It is cleared by any one of the following events:

- An interrupt is serviced.

- An interrupt is not serviced but takes the CPU out of the IDLE state.

- A valid instruction enters the instruction register (the register that holds the instruction

currently being decoded).

EALLOW

Bit 6

LOOP

Bit 5

- A device reset occurs.

When the CPU services an interrupt, the current value of IDLESTAT is saved on the stack (when ST1 is saved on the stack), and then IDLESTAT is cleared. Upon return from the interrupt, IDLESTAT is not restored from the stack.

Emulation access enable bit. This bit, when set, enables access to emulation and other protected registers. Set this bit by using the EALLOW instruction and clear this bit by using the EDIS instruction. See the data sheet for a particular device to determine the registers that are protected.

When the CPU services an interrupt, the current value of EALLOW is saved on the stack (when ST1 is saved on the stack), and then EALLOW is cleared. Therefore, at the start of an interrupt service routine (ISR), access to protected registers is disabled. If the ISR must access protected registers, it must include an EALLOW instruction. At the end of the ISR, EALLOW can be restored by the IRET instruction.

Loop instruction status bit. LOOP is set when a loop instruction (LOOPNZ or LOOPZ) reaches the decode 2 phase of the pipeline. The loop instruction does not end until a specified condition is met. When the condition is met, LOOP is cleared. LOOP is a read-only bit; it is not affected by any instruction except a loop instruction.

2-35Central Processing Unit

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Status Register ST1

When the CPU services an interrupt, the current value of LOOP is saved on the stack (when ST1 is saved on the stack), and then LOOP is cleared. Upon return from the interrupt, LOOP is not restored from the stack.

SPA

Bits 4

VMAP

Bit 3

PAGE0

Bit 2

Stack pointer alignment bit. SPA indicates whether the CPU has previously aligned the stack pointer to an even address by the ASP instruction: 0 The stack pointer has not been aligned to an even address. 1 The stack pointer has been aligned to an even address.

When the ASP (align stack pointer) instruction is executed, if the stack pointer (SP) points to an odd address, SP is incremented by 1 so that it points to an even address, and SPA is set. If SP already points to an even address, SP is not changed, but SPA is cleared. When the NASP (unalign stack pointer) instruction is executed, if SPA is 1, SP is decremented by 1 and SPA is cleared. If SPA is 0, SP is not changed.

At reset, SPA is cleared.

Vector map bit. VMAP determines whether the CPU interrupt vectors (including the reset vector) are mapped to the lowest or highest addresses in program memory: 0 CPU interrupt vectors are mapped to the bottom of program memory, addresses

00 0000

1 CPU interrupt vectors are mapped to the top of program memory, addresses

3F FFC0

On C28x designs, the VMAP signal is tied high internally, forcing the VMAP bit to be set high on a reset.

This bit can be individually set and cleared by the SETC VMAP instruction and CLRC VMAP instruction, respectively.

PAGE0 addressing mode configuration bit. PAGE0 selects between two mutually-exclusive addressing modes: PAGE0 direct addressing mode and PAGE0 stack addressing mode. Selection of the modes is as follows: 0 PAGE0 stack addressing mode 1 PAGE0 direct addressing mode

−00 003F16.

−3F FFFF16.

Note: Illegal Instruction Trap

Setting PAGE0 = AMODE = 1 will generate an illegal instruction trap.

PAGE0 = 1 is included for compatibility with the C27x. the recommended operating mode for C28x is PAGE0 = 0.

This bit can be individually set and cleared by the SETC PAGE0 instruction and CLRC PAGE0 instruction, respectively. At reset, the PAGE0 bit is cleared (PAGE0 stack addressing mode is selected).

For details about the above addressing modes, see Chapter 5, Addressing Modes.

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Status Register ST1

DBGM

Bit 1

Debug enable mask bit. When DBGM is set, the emulator cannot accesss memory or registers in real time. The debugger cannot update its windows.

In the real-time emulation mode, if DBGM = 1, the CPU ignores halt requests or hardware breakpoints until DBGM is cleared. DBGM does not prevent the CPU from halting at a software breakpoint. One effect of this may be seen in real-time emulation mode. If you single-step an instruction in real time emulation mode and that instruction sets DBGM, the CPU continues to execute instructions until DBGM is cleared.

When you give the TI debugger the REALTIME command (to enter real-time mode), DBGM is forced to 0. Having DBGM = 0 ensures that debug and test direct memory accesses (DT-DMAs) are allowed; memory and register values can be passed to the host processor for updating debugger windows.

Before the CPU executes an interrupt service routine (ISR), it sets DBGM. When DBGM = 1, halt requests from the host processor and hardware breakpoints are ignored. If you want to single-step through or set breakpoints in a non-time-critical ISR, you must add a CLRC DBGM instruction at the beginning of the ISR.

DBGM is primarily used in emulation to block debug events in time-critical portions of program code. DBGM enables or disables debug events as follows:

0 Debug events are enabled.

1 Debug events are disabled.

When the CPU services an interrupt, the current value of DBGM is saved on the stack (when ST1 is saved on the stack), and then DBGM is set. Upon return from the interrupt, DBGM is restored from the stack.

This bit can be individually set and cleared by the SETC DBGM instruction and CLRC DBGM instruction, respectively. DBGM is also set automatically during interrupt operations. At reset, DBGM is set. Executing the ABORTI (abort interrupt) instruction also sets DBGM.

INTM

Bit 0

Interrupt global mask bit. This bit globally enables or disables all maskable CPU interrupts (those that can be blocked by software):

0 Maskable interrupts are globally enabled. To be acknowledged by the CPU, a

maskable interrupt must also be locally enabled by the interrupt enable register (IER).

1 Maskable interrupts are globally disabled. Even if a maskable interrupt is local-

ly enabled by the IER, it is not acknowledged by the CPU.

INTM has no effect on the nonmaskable interrupts, including a hardware reset or the hardware interrupt NMI mode, an interrupt enabled by the IER and the DBGIER will be serviced even if INTM is set to disable maskable interrupts.

. In addition, when the CPU is halted in real-time emulation

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Status Register ST1

When the CPU services an interrupt, the current value of INTM is saved on the stack (when ST1 is saved on the stack), and then INTM is set. Upon return from the interrupt, INTM is restored from the stack.

This bit can be individually set and cleared by the SETC INTM instruction and CLRC INTM instruction, respectively. At reset, INTM is set. The value in INTM does not cause modification to the interrupt flag register (IFR), the interrupt enable register (IER), or the debug interrupt enable register (DBGIER).

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2.5 Program Flow

2.5.1 Interrupts

Program Flow

The program control logic and program-address generation logic work together to provide proper program flow. Normally, the flow of a program is sequential: the CPU executes instructions at consecutive program-memory addresses. At times, a discontinuity is required; that is, a program must branch to a nonsequential address and then execute instructions sequentially at that new location. For this purpose, the ’28x supports interrupts, branches, calls, returns, and repeats.

Proper program flow also requires smooth flow at the instruction level. To meet this need, the ’28x has a protected pipeline and an instruction-fetch mechanism that attempts to keep the pipeline full.

Interrupts are hardware- or software-driven events that cause the CPU to suspend its current program sequence and execute a subroutine called an interrupt service routine. Interrupts are described in detail in Chapter 3.

2.5.2 Branches, Calls, and Returns

Branches, calls, and returns break the sequential flow of instructions by transferring control to another location in program memory. A branch only transfers control to the new location. A call also saves the return address (the address of the instruction following the call). Called subroutines or interrupt service routines are each concluded with a return instruction, which takes the return address from the stack or from XAR7 or RPC and places it into the program counter (PC).

The following branch instructions are conditional: B, BANZ, BAR, BF, SB, SBF, XBANZ, XCALL, and XRETC. They are executed only if a certain specified or predefined condition is met. For detailed descriptions of these instructions, see Chapter 6, Assembly Language Instructions.

2.5.3 Repeating a Single Instruction

The repeat (RPT) instruction allows the execution of a single instruction (N + 1) times, where N is specified as an operand of the RPT instruction. The instruction is executed once and then repeated N times. When RPT is executed, the repeat counter (RPTC) is loaded with N. RPTC is then decremented every time the repeated instruction is executed, until RPTC equals 0. For a description of RPT and a list of repeatable instructions, see Chapter 6, As- sembly Language Instructions.

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Program Flow

2.5.4 Instruction Pipeline

Each instruction passes through eight independent phases that form an instruction pipeline. At any given time, up to eight instructions may be active, each in a different phase of completion. Not all reads and writes happen in the same phases, but a pipeline-protection mechanism stalls instructions as needed to ensure that reads and writes to the same location happen in the order in which they are programmed.

To maximize pipeline efficiency, an instruction-fetch mechanism attempts to keep the pipeline full. Its role is to fill an instruction-fetch queue, which holds instructions in preparation for decoding and execution. The instruction-fetch mechanism fetches 32-bits at a time from program memory; it fetches one 32-bit instruction or two 16-bit instructions.

The instruction-fetch mechanism uses three program-address counters: the program counter (PC), the instruction counter (IC), and the fetch counter (FC). When the pipeline is full the PC will always point to the instruction in its decode 2 pipeline phase. The IC points to the next instruction to be processed. When the PC points to a 1-word instruction, IC = (PC+1); when the PC points to a 2-word instruction, IC = (PC+2). The value in the FC is the address from which the next fetch is to be made.

The pipeline and the instruction-fetch mechanism are described in more detail in Chapter 4, Pipeline.

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2.6 Multiply Operations

The C28x features a hardware multiplier that can perform 16-bit X 16-bit or 32-bit X 32-bit fixed-point multiplication. This functionality is enhanced by 16-bit X 16-bit multiply and accumulate (MAC), 32 X 32 MAC, and 16-bit X 16-bit dual MAC (DMAC) instructions. This section describes the components involved in each type of multiplication.

2.6.1 16-bit X 16-bit Multiplication

The C28x multiplier can perform a 16-bit X 16-bit multiplication to produce a signed or unsigned 32-bit product. Figure 2−12 shows the CPU components involved in this multiplication.

The multiplier accepts two 16-bit inputs:

- One input is from the upper 16 bits of the multiplicand register (T). Most

16 X 16 multiplication instructions require that you load T from a datamemory location or a register before you execute the instruction. However, the MAC and some versions of the MPY and MPYA instructions load T for you before the multiplication.

Multiply Operations

- The other input is from one of the following:

J A data-memory location or a register (depending on which you specify

in the multiply instruction).

J An instruction opcode. Some C28x multiply instructions allow you to

include a constant as an operation.

After the value has been multiplied by the second value, the 32-bit result is stored in one of two places, depending on the particular multiply instruction: the 32-bit product register (P) or the 32-bit accumulator (ACC).

One special 16-bit X 16-bit multiplication instruction takes two 32-bit input values as its operands. This instruction is the 16 X 16 DMAC instruction, which performs dual 16 X 16 MAC operations in one instruction. In this case, the ACC contains the result of multiplying and adding the upper word of the 32-bit operands. The P register contains the result of multiplying and adding the results of the lower word of the 32-bit operands.

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Multiply Operations

Figure 2−12. Conceptual Diagram of Components Involved in 16 X16-Bit Multiplication

From data memory or a register

From an instruction opcode

16 16

2.6.2 32-Bit X 32-Bit Multiplication

The C28x multiplier can also perform 32-bit by 32-bit multiplication. Figure 2−13 shows the CPU components involved n this multiplication. In this case, the multiplier accepts two 32-bit inputs:

- The first input is from one of the following:

MUX

Multiplier

MUX

ACC

J A program memory location. Some C28x 32 X 32 multiply MAC-type

instructions such as IMACL and QMACL take one data value directly from memory using the program-address bus.

J The 32-bit multiplicand register (XT). Most 32 X 32-bit multiplication

instructions require that you load XT from data memory or a register before you execute the instruction.

- A data-memory location or a register (depending on which you specify in

the multiply instruction).

After the two values have ben multiplied, 32 bits of the 64-bit result are stored in the product register (P). You can control which half is stored (upper 32 bits or lower 32 Bits) and whether the multiplication is signed or unsigned by the instruction used.

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Multiply Operations

If you need support for larger data values, the 32 X 32 multiplication instructions can be combined to implement 32 X 32 = 64-bit or 64 X 64 = 128-bit math.

Figure 2−13. Conceptual Diagram of Components Involved in 32 X 32-Bit Multiplication

From data memory or register

From

program

memory

MUX

From data

memory or register

32 32

upper 32

Multiplier

lower 32

MUX

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Shift Operations

2.7 Shift Operations

The shifter holds 64 bits and accepts either a 16-bit, 32-bit, or 64-bit input value. When the input value has 16 bits, the value is loaded into the 16 least significant bits (LSBs) of the shifter. When the input value has 32 bits, the value is loaded into the 32 LSBs of the shifter. Depending on the instruction that uses the shifter, the output of the shifter may be all of its 64 bits or just its 16 LSBs.

When a value is shifted right by an amount N, the N LSBs of the value are lost and the bits to the left of the value are filled with all 0s or all 1s. If sign extension is specified, the bits to the left are filled with copies of the sign bit. If sign extension is not specified, the bits to the left are filled with 0s, or zero filled.

When a value is shifted left by an amount N, the bits to the right of the shifted value are zero filled. If the value has 16 bits and sign extension is specified, the bits to the left are filled with copies of the sign bit. If the value has 16 bits and sign extension is not specified, the bits to the left are zero filled. If the value has 32 bits, the N MSBs of the value are lost, and sign extension is irrelevant.

Table 2−11 lists the instructions that use the shifter and provides an illustration of the corresponding shifter operation. The table uses the following graphical symbols:

Shift left

Sign

SXM

0/Sign

This symbol represents the 32-bit shifter. The text inside the box indicates the direction of the shift.

This symbol indicates zero filling.

This symbol indicates sign extending.

This symbol indicates that the MSBs of the shifter depend on the sign-extension mode bit (SXM). If SXM = 0, the MSBs are zero filled after the shift. If SXM = 1, the MSBs are filled with the sign of the shifted value.

This symbol indicates the carry bit (C).

For explanations of the instruction syntaxes listed in Table 2−11, see Chapter 6, Assembly Language Instructions.

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Table 2−11. Shift Operations

Operation Type Illustration

Shift Operations

Left shift of 16-bit value for ACC operation. Syntaxes:

ADD ACC, loc16 << 0...16

ADD ACC, #16Bit <<0...15

ADD ACC, loc16 <<T

SUB ACC, loc16 << 0...16

SUB ACC, #16Bit <<0 ...15

SUB ACC, loc16<<T

MOV ACC, loc16 << 0...16

MOV ACC, #16Bit <<0...15

MOV ACC, loc16, <<T

Store 16 LSBs of left-shifted ACC.

Syntax:

MOV loc16, ACC << 1...8

Store 16 MSBs of left-shifted ACC.

Syntax:

MOVH loc16, ACC <<1...8 Note: This instruction performs a single right shift by (16−shift1), where shift1 is a value from 0 to 8.

SXM

0/Sign

Discard

16-bit value to 16 LSBs

Shift left

32 bits to ALU

ACC

Shift left

16 LSBs to ALU

ACC

Shift right

16 LSBs to ALU

Discard

Logical left shift of ACC. The last bit to be shifted out fills the carry bit (C). Syntaxes:

LSL ACC, 1...16

LSL ACC, T (shift = T(3:0)) LSL ACC, T (shift = T(4:0)) Note: If T(3:0) = 0 or T(4:0) = 0, indicating a shift of 0, C is cleared.

Last bit out

Discard other bits

ACC

Shift left

32 bits to ACC

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Shift Operations

Table 2−11. Shift Operations (Continued)

Operation Type Illustration

Logical left shift of AH or AL. The last

bit to be shifted out fills the carry bit (C). Syntaxes:

LSL AX, 1...16

LSL AX, T (shift = T(3:0)) Note: If T(3:0) = 0, indicating a shift of 0, C is cleared.

Right shift of ACC. If SXM = 0, a logical shift is performed. If SXM = 1, an arithmetic shift is performed. The last bit to be shifted out fills the carry bit (C). Syntaxes:

SFR ACC, 1...16

SFR ACC, T Note: If T(3:0) = 0, indicating a shift of 0, C is cleared.

Logical right shift of AH or AL. The last bit to be shifted out fills the carry bit (C). Syntaxes:

LSR AX, shift

LSR AX, T (shift = T(3:0)) ARLACC, T (shift = T(4:0) Note: If T(4:0) = 0, indicating a shift of 0, C is cleared.

Last bit out

0/Sign

SXM

AH/AL to 16 LSBs

Shift left

16 LSBs to AH/AL

ACC

Shift right

32 bits to ACC

AH/AL to 16 LSBs

Shift right

16 LSBs to AH/AL

Last

bit out

Discard

other bits

Last

bit out

Discard other bits

Arithmetic right shift of AH or AL. The last bit to be shifted out fills the carry bit (C). Syntaxes:

ASR AX, shift

ASR AX, T Note: If T(4:0) = 0, indicating a shift of 0, C is cleared.

Rotate ACC left by 1 bit. Bit 31 of ACC fills the carry bit (C). C fills bit 0 of ACC. Syntax:

ROL ACC

2-46

Sign

AH/AL to 16 LSBs

Last

Shift right

16 LSBs to AH/AL

ACC

Rotate left

32 bits to ACC

bit out

Discard other bits

Page 77

Table 2−11. Shift Operations (Continued)

Operation Type Illustration

Shift Operations

Rotate ACC right by 1 bit. Bit 0 of ACC fills the carry bit (C). C fills bit 31 of ACC. Syntax:

ROR ACC

Logical right shift of ACC:P. Syntaxes:

LSR64 ACC:P, 1...16 LSR64, ACC:P, T shift = T(5:0)

Logical left shift of ACC:P. Syntaxes:

LSL64 ACC:P, 1...16 LSL64 ACC:P, T shift = T(5:0)

Arithmetic right shift of ACC:P.

Syntaxes:

ASR64 ACC:P, 1...16 ASR64, ACC:P, T shift = T(5:0)

Last bit out

Discard other bits

Sign

ACC

Rotate right

32 bits to ACC

ACC:P

Shift right

64 bits to ACC:P

ACC:P

Shift left

64 bits to ACC:P

ACC:P

Shift right

64 bits to ACC:P

Last

bit out

Discard other bits

Last

bit out

Discard other bits

Conditional shift of ACC by 1 bit.

Syntaxes:

NORM ACC, aux++

NORM ACC, aux−−

SUBCU ACC, loc

Discard

ACC

Shift left

32 bits to ACC

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Shift Operations

Table 2−11. Shift Operations (Continued)

Operation Type Illustration

Shift of P as per PM bits. Syntaxes:

ADD ACC, P

SUB ACC, P

CMP ACC, P

MAC P, loc, 0:pmem

MOV ACC, P

MOVA T, loc

MOVP T, loc

MOVS T, loc

MPYA P, loc, #16BitSigned

MPYA P, T, loc

MPYS P, T, loc

For PM = 0:

Discard

For PM = 1: No shift

For PM from 2−7:

Sign

Shift left

32 bits to ALU

Shift right

32 bits to ALU

Discard

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Table 2−11. Shift Operations (Continued)

Operation Type Illustration

Shift Operations

Store 16 LSBs of shifted P. P is shifted as per the PM bits. The 16 LSBs of shifter are stored. Syntax:

MOV loc16, P

Store 16 MSBs of shifted P. P is shifted as per the PM bits. The result is shifted right by 16 so that its 16 MSBs are in the 16 LSBs of the shifter. 16 LSBs of shifter are stored. Syntax:

MOVH loc16, P

For PM = 0:

Discard

For PM = 1: No shift

For PM from 2−7:

Sign

For PM = 0:

Discard

Shift left

16 LSBs to ALU

Shift right

16 LSBs to ALU

Shift left

Shift right by 16

Discard

For PM = 1: No shift

For PM from 2−7:

Sign

16 LSBs to ALU

Shift right

Shift right by 16

16 LSBs to ALU

Discard

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Chapter 3

CPU Interrupts and Reset

This chapter describes the available CPU interrupts and how they are handled by the CPU. It also explains how to control those interrupts that can be controlled through software. Finally, it describes how a hardware reset affects the CPU.

Topic Page

3.1 CPU Interrupts Overview 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 CPU Interrupt Vectors and Priorities 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Maskable Interrupts: INT1

3.4 Standard Operation for Maskable Interrupts 3-11. . . . . . . . . . . . . . . . . . . .

3.5 Nonmaskable Interrupts 3-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Illegal-Instruction Trap 3-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Hardware Reset (RS

−INT14, DLOGINT, and RTOSINT 3-6. . . . . . .

) 3-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

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CPU Interrupts Overview

3.1 CPU Interrupts Overview

Interrupts are hardware- or software-driven signals that cause the C28x CPU to suspend its current program sequence and execute a subroutine. Typically, interrupts are generated by peripherals or hardware devices that need to give data to or take data from the C28x (for example, A/D and D/A converters and other processors). Interrupts can also signal that a particular event has taken place (for example, a timer has finished counting).

On the C28x, interrupts can be triggered by software (the INTR, OR IFR, or TRAP instruction) or by hardware (a pin, an external peripheral, or on-chip peripheral/logic). If hardware interrupts are triggered at the same time, the C28x services them according to a set priority ranking.

Some 28x devices include a peripheral interrupt expansion (PIE) module that multiplexes interrupts from a number of peripherals into a single CPU interrupt. The PIE module provides additional control before an interrupt reaches the C28x CPU. See the TMS320C8x System and Interrupts Reference Guide (literature number SPRU078) for more details.

At the CPU level, each of the C28x interrupts, whether hardware or software, can be placed in one of the following two categories:

- Maskable interrupts.These are interrupts that can be blocked (masked)

or enabled (unmasked) through software.

- Nonmaskable interrupts. These interrupts cannot be blocked. The C28x

will immediately approve this type of interrupt and branch to the corresponding subroutine. All software-initiated interrupts are in this category.

The C28x handles interrupts in four main phases:

1) Receive the interrupt request. Suspension of the current program sequence must be requested by a software interrupt (from program code) or a hardware interrupt (from a pin or an on-chip device).

2) Approve the interrupt. The C28x must approve the interrupt request. If the interrupt is maskable, certain conditions must be met in order for the C28x to approve it. For nonmaskable hardware interrupts and for software interrupts, approval is immediate.

3) Prepare for the interrupt service routine and save register values. The main tasks performed in this phase are:

- Complete execution of the current instruction and flush from the pipe-

line any instructions that have not reached the decode 2 phase.

- Automatically save most of the current program context by saving the

following registers to the stack: ST0, T, AL, AH, PL, PH, AR0, AR1, DP, ST1, DBGSTAT, PC, and IER.

3-2

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CPU Interrupts Overview

Fetch the interrupt vector and load it into the program counter (PC).

For devices with a PIE module, the vector fetched will depend on the setting of the PIE enable and flag registers.

4) Execute the interrupt service routine. The C28x branches to its corresponding subroutine called an interrupt service routine (ISR). The C28x branches to the address (vector) you store at a predetermined vector location and executes the ISR you have written.

3-3CPU Interrupts and Reset

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CPU Interrupt Vectors and Priorities

Hard

3.2 CPU Interrupt Vectors and Priorities

The C28x supports 32 CPU interrupt vectors, including the reset vector. Each vector is a 22-bit address that is the start address for the corresponding interrupt service routine (ISR). Each vector is stored in 32 bits at two consecutive addresses. The location at the lower address holds the 16 least significant bits (LSBs) of the vector. The location at the higher address holds the 6 most significant bits (MSBs) right-justified. When an interrupt is approved, the 22-bit vector is fetched, and the 10 MSBs at the higher address are ignored.

For devices with a PIE module, this table is re-mapped and expanded into the PIE vector table.

Table 3−1 lists the available CPU interrupt vectors and their locations. The addresses are shown in hexadecimal form. The table also shows the priority of each of the hardware interrupts.

Table 3−1. Interrupt Vectors and Priorities

ББББББББББББББББББББББББББББ

Vector

RESET

Absolute Address (hexadecimal)

VMAP = 0

00 0000

VMAP = 1

3F FFC0

†

ware

Priority

1 (highest)

Description

Reset

INT1

INT2

ÁÁÁ

INT3

ÁÁÁ

INT4

INT5

INT6

INT7

ÁÁÁ

INT8

INT9

INT10

INT11

INT12

ÁÁÁ

INT13

INT14

†

For C28x catalog devices, VMAP = 1 at reset.

‡

Interrupts DLOGINT and RTOSINT are generated by the emulation logic internal to the CPU.

00 0002

00 0004

ÁÁÁÁ

00 0006

ÁÁÁÁ

00 0008

00 000A

00 000C

00 000E

ÁÁÁÁ

00 0010

00 0012

00 0014

00 0016

00 0018

ÁÁÁÁ

00 001A

00 001C

3F FFC2

3F FFC4

БББББ

3F FFC6

БББББ

3F FFC8

3F FFCA

3F FFCC

3F FFCE

БББББ

3F FFD0

3F FFD2

3F FFD4

3F FFD6

3F FFD8

БББББ

3F FFDA

3F FFDC

ÁÁÁÁ

Maskable interrupt 1

Maskable interrupt 2

ББББББББ

Maskable interrupt 3

ББББББББ

Maskable interrupt 4

Maskable interrupt 5

Maskable interrupt 6

Maskable interrupt 7

ББББББББ

Maskable interrupt 8

Maskable interrupt 9

Maskable interrupt 10

Maskable interrupt 11

Maskable interrupt 12

ББББББББ

Maskable interrupt 13

Maskable interrupt 14

3-4

Page 85

Table 3−1. Interrupt Vectors and Priorities (Continued)

CPU Interrupt Vectors and Priorities

Vector

DLOGINT

RTOSINT

ÁÁÁ

Reserved

ÁÁÁ

NMI

ILLEGAL

USER1

USER2

USER3

ÁÁÁ

USER4

USER5

USER6

USER7

USER8

ÁÁÁ

USER9

Absolute Address (hexadecimal)

VMAP = 0

‡

00 001E

00 0020

ÁÁÁÁ

00 0022

ÁÁÁÁ

00 0024

00 0026

00 0028

00 002A

00 002C

ÁÁÁÁ

00 002E

00 0030

00 0032

00 0034

00 0036

ÁÁÁÁ

00 0038

VMAP = 1

†

3F FFDE

3F FFE0

ÁÁÁÁ

3F FFE2

ÁÁÁÁ

3F FFE4

3F FFE6

3F FFE8

3F FFEA

3F FFEC

ÁÁÁÁ

3F FFEE

3F FFF0

3F FFF2

3F FFF4

3F FFF6

ÁÁÁÁ

3F FFF8

Hardware

Priority

19 (lowest)

БББББ

−

БББББ

−

БББББ

−

Description

Maskable data log interrupt

Maskable real-time operating

ББББББББ

system interrupt

Reserved

ББББББББ

Nonmaskable interrupt

Illegal-instruction trap

User-defined software interrupt

ББББББББ

User-defined software interrupt

ББББББББ

User-defined software interrupt

USER10

USER11

USER12

†

For C28x catalog devices, VMAP = 1 at reset.

ББББББББББББББББББББББББББББ

‡

Interrupts DLOGINT and RTOSINT are generated by the emulation logic internal to the CPU.

00 003A

00 003C

00 003E

3F FFFA

3F FFFC

3F FFFE

−

User-defined software interrupt

The vector table can be mapped to the top or bottom of program space, depending on the value of the vector map bit (VMAP) in status register ST1. (ST1 is described in section 2.4 on page 2-34.) If the VMAP bit is 0, the vectors are mapped beginning at address 00 0000 mapped beginning at address 3F FFC0

. If the VMAP bit is 1, the vectors are

. Table 3−1 lists the absolute ad-

dresses for VMAP = 0 and VMAP = 1.

The VMAP bit can be set by the SETC VMAP instruction and cleared by the CLRC VMAP instruction. The reset value of VMAP is 1.

3-5CPU Interrupts and Reset

Page 86

Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT

3.3 Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT

INT1−INT14 are 14 general-purpose interrupts. DLOGINT (the data log interrupt) and RTOSINT (the real-time operating system interrupt) are available for emulation purposes. These interrupts are supported by three dedicated registers: the CPU interrupt flag register (IFR), the CPU interrupt enable register (IER), and the CPU debug interrupt enable register (DBGIER).

The 16-bit IFR contains flag bits that indicate which of the corresponding interrupts are pending (waiting for approval from the CPU). The external input lines

−INT14 are sampled at every CPU clock cycle. If an interrupt signal is rec-

INT1 ognized, the corresponding bit in the IFR is set and latched. For DLOGINT or RTOSINT, a signal sent by the CPU on-chip analysis logic causes the corresponding flag bit to be set and latched. You can set one or more of the IFR bits at the same time by using the OR IFR instruction. More details about the IFR are given in section 3.3.1. The on-chip analysis resources are introduced in Chapter 7.

The interrupt enable register (IER) and the debug interrupt enable register (DBGIER) each contain bits for individually enabling or disabling the maskable interrupts. To enable one of the interrupts in the IER, you set the corresponding bit in the IER; to enable the same interrupt in the DBGIER, you set the corresponding bit in the DBGIER. The DBGIER indicates which interrupts can be serviced when the CPU is in the real-time emulation mode. The IER and the DBGIER are discussed more in section 3.3.2. Real-time mode is discussed in section 7.4.2 on page 7-9.

The maskable interrupts also share bit 0 in status register ST1. This bit, the interrupt global mask bit (INTM), is used to globally enable or globally disable these interrupts. When INTM = 0, these interrupts are globally enabled. When INTM = 1, these interrupts are globally disabled. You can set and clear INTM with the SETC INTM and CLRC INTM instructions, respectively. ST1 is described in section 2.4 on page 2-34.

After a flag has been latched in the IFR, the corresponding interrupt is not serviced until it is appropriately enabled by two of the following: the IER, the DBGIER, and the INTM bit. As shown in Table 3−2, the requirements for enabling the maskable interrupts depend on the interrupt-handling process used. In the standard process, which occurs in most circumstances, the DBGIER is ignored. When the C28x is in real-time emulation mode and the CPU is halted, a different process is used. In this special case, the DBGIER is used and the INTM bit is ignored. (If the DSP is in real-time mode and the CPU is running, the standard interrupt-handling process applies.)

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Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT

Once an interrupt has been requested and properly enabled, the CPU prepares for and then executes the corresponding interrupt service routine. For a detailed description of this process, see section 3.4.

Table 3−2. Requirements for Enabling a Maskable Interrupt

Interrupt-Handling Process Interrupt Enabled If ...

Standard INTM = 0 and bit in IER is 1

DSP in real-time mode and CPU halted Bit in IER is 1 and bit in DBGIER is 1

As an example of varying interrupt-enable requirements, suppose you want interrupt INT5

enabled. This corresponds to bit 4 in the IER and bit 4 in the DBGIER. Usually, INT5 is enabled if INTM = 0 and IER(4) = 1. In real-time emulation mode with the CPU halted, INT5 DBGIER(4) = 1.

3.3.1 CPU Interrupt Flag Register (IFR)

Figure 3−1 shows the IFR. If a maskable interrupt is pending (waiting for approval from the CPU), the corresponding IFR bit is 1; otherwise, the IFR bit is

0. To identify pending interrupts, use the PUSH IFR instruction and then test the value on the stack. Use the OR IFR instruction to set IFR bits, and use the AND IFR instruction to clear pending interrupts. When a hardware interrupt is serviced, or when an INTR instruction is executed, the corresponding IFR bit is cleared. All pending interrupts are cleared by the AND IFR, #0 instruction or by a hardware reset.

is enabled if IER(4) = 1 and

Notes:

When an interrupt is requested by the TRAP instruction, if the corresponding IFR bit is set, the CPU does not clear it automatically. If an application requires that the IFR bit be cleared, the bit must be cleared in the interrupt service routine.

Figure 3−1. Interrupt Flag Register (IFR)

RTOSINT

R/W−0

INT8

R/W−0

Note: R = Read access; W = Write access; value following dash (−) is value after reset.

DLOGINT

R/W−0

INT7

R/W−0

INT14

R/W−0

INT6

R/W−0

INT13

R/W−0

INT5

R/W−0

INT12

R/W−0

INT4

R/W−0

INT11

R/W−0

INT3

INT10

R/W−0

INT2

R/W−0

INT9

R/W−0

INT1

R/W−0

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Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT

Bits 15 and 14 of the IFR correspond to the interrupts RTOSINT and DLOGINT:

RTOSINT Real-time operating system interrupt flag

Bit 15 RTOSINT = 0 RTOSINT is not pending.

RTOSINT = 1 RTOSINT is pending.

DLOGINT Data log interrupt flag

Bit 14 DLOGINT = 0 DLOGINT is not pending.

DLOGINT = 1 DLOGINT is pending.

For bits INT1−INT14, the following general description applies:

INTx Interrupt x flag (x = 1, 2, 3, ..., or 14)

Bit (x−1) INTx = 0 INTx

INTx = 1 INTx

3.3.2 CPU Interrupt Enable Register (IER) and CPU Debug Interrupt Enable Register (DBGIER)

Figure 3−2 shows the IER. To enable an interrupt, set its corresponding bit to

1. To disable an interrupt, clear its corresponding bit to 0. Two syntaxes of the MOV instruction allow you to read from the IER and write to the IER. In addition, the OR IER instruction enables you to set IER bits, and the AND IER instruction enables you to clear IER bits. When a hardware interrupt is serviced, or when an INTR instruction is executed, the corresponding IER bit is cleared. At reset, all the IER bits are cleared to 0, disabling all the corresponding interrupts.

Note:

When an interrupt is requested by the TRAP instruction, if the corresponding IER bit is set, the CPU does not clear it automatically. If an application requires that the IER bit be cleared, the bit must be cleared in the interrupt service routine.

is not pending.

is pending.

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Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT

Figure 3−2. Interrupt Enable Register (IER)

RTOSINT

R/W−0

INT8

R/W−0

Note: R = Read access; W = Write access; value following dash (−) is value after reset.

DLOGINT

R/W−0

INT7

R/W−0

INT14

R/W−0

INT6

R/W−0

INT13

R/W−0

INT5

R/W−0

INT12

R/W−0

INT4

R/W−0

INT11

R/W−0

INT3

R/W−0

Note:

When using the AND IER and OR IER instructions, make sure that they do not modify the state of bit 15 (RTOSINT) unless a real-time operating system is present.

Bits 15 and 14 of the IER enable or disable the interrupts RTOSINT and DLOGINT:

RTOSINT Real-time operating system interrupt enable bit

Bit 15 RTOSINT = 0 RTOSINT is disabled.

RTOSINT = 1 RTOSINT is enabled.

INT10

R/W−0

INT2

R/W−0

INT9

R/W−0

INT1

R/W−0

DLOGINT Data log interrupt enable bit

Bit 14 DLOGINT = 0 DLOGINT is disabled.

DLOGINT = 1 DLOGINT is enabled.

For bits INT1−INT14, the following general description applies:

INTx Interrupt x enable bit (x = 1, 2, 3, ..., or 14)

Bit (x−1) INTx = 0 INTx

INTx = 1 INTx

is disabled.

is enabled.

Figure 3−3 shows the DBGIER, which is used only when the CPU is halted in real-time emulation mode. An interrupt enabled in the DBGIER is defined as a time-critical interrupt. When the CPU is halted in real-time mode, the only in- terrupts that are serviced are time-critical interrupts that are also enabled in the IER. If the CPU is running in real-time emulation mode, the standard interrupt-handling process is used and the DBGIER is ignored.

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Maskable Interrupts: INT1−INT14, DLOGINT, and RTOSINT

As with the IER, you can read the DBGIER to identify enabled or disabled interrupts and write to the DBGIER to enable or disable interrupts. To enable an interrupt, set its corresponding bit to 1. To disable an interrupt, set its corresponding bit to 0. Use the PUSH DBGIER instruction to read from the DBGIER and the POP DBGIER instruction to write to the DBGIER. At reset, all the DBGIER bits are set to 0.

Figure 3−3. Debug Interrupt Enable Register (DBGIER)

RTOSINT

R/W−0

INT8

R/W−0

DLOGINT

ÁÁÁ

R/W−0

INT7

R/W−0

INT14

ÁÁ

R/W−0

INT6

R/W−0

INT13

ÁÁ

R/W−0

INT5

R/W−0

INT12

ÁÁÁ

R/W−0

INT4

R/W−0

INT11

ÁÁ

R/W−0

INT3

R/W−0

Note: R = Read access; W = Write access; value following dash (−) is value after reset.

Bits 15 and 14 of the DBGIER enable or disable the interrupts RTOSINT and DLOGINT:

RTOSINT Real-time operating system interrupt debug enable bit

Bit 15 RTOSINT = 0 RTOSINT is disabled.

RTOSINT = 1 RTOSINT is enabled.

DLOGINT Data log interrupt debug enable bit

Bit 14 DLOGINT = 0 DLOGINT is disabled.

DLOGINT = 1 DLOGINT is enabled.

For bits INT1−INT14, the following general description applies:

INT10

ÁÁ

R/W−0

INT2

R/W−0

INT9

ÁÁÁ

R/W−0

INT1

R/W−0

3-10

INTx Interrupt x debug enable bit (x = 1, 2, 3, ..., or 14)

Bit (x−1) INTx = 0 INTx

INTx = 1 INTx

is disabled.

is enabled.

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Standard Operation for Maskable Interrupts

3.4 Standard Operation for Maskable Interrupts

The flow chart in Figure 3−4 shows the standard process for handling interrupts. Section 7.4.2 on page 7-9 contains information on handling interrupts when the DSP is in real-time mode and the CPU is halted. When more than one interrupt is requested at the same time, the C28x services them one after another according to their set priority ranking. See the priorities in Table 3−1 on page 3-4.

Figure 3−4 is not meant to be an exact representation of how an interrupt is handled. It is a conceptual model of the important events.

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Standard Operation for Maskable Interrupts

Figure 3−4. Standard Operation for CPU Maskable Interrupts

Interrupt request sent to CPU

Set corresponding IFR flag bit.

Interrupt enabled in

IER?

Yes

Interrupt enabled by

INTM bit?

Yes

Clear corresponding IFR bit.

Empty pipeline.

Increment and temporarily store PC.

Fetch interrupt vector.

Increment SP by 1.

Perform automatic context save.

Clear corresponding IER bit.

This sequence

protected from interrupts

Set INTM and DBGM. Clear LOOP,

EALLOW, and IDLESTAT.

Load PC with fetched vector.

Execute interrupt service routine.

Program continues

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Standard Operation for Maskable Interrupts

What following list explains the steps shown in Figure 3−4:

1) Interrupt request sent to CPU. One of the following events occurs:

- One of the pins INT1−INT14 is driven low by an external event, periph-

eral or PIE interrupt request..

- The CPU emulation logic sends to the CPU a signal for DLOGINT or

RTOSINT.

- One of the interrupts INT1−INT14, DLOGINT, and RTOSINT is initi-

ated by way of the OR IFR instruction.

2) Set corresponding IFR flag bit. When the CPU detects a valid interrupt in step 1, it sets and latches the corresponding flag in the interrupt flag register (IFR). This flag stays latched even if the interrupt is not approved by the CPU in step 3. The IFR is explained in detail in section 3.3.1.

3) Is the interrupt enabled in IER? Is the interrupt enabled by INTM bit? The CPU approves the interrupt only if the following conditions are true:

- The corresponding bit in the IER is 1.

- The INTM bit in ST1 is 0.

Once an interrupt has been enabled and then approved by the CPU, no other interrupts can be serviced until the CPU has begun executing the interrupt service routine for the approved interrupt (step 13). The IER is described in section 3.3.2. ST1 is described in section 2.4 on page 2-34.

4) Clear corresponding IFR bit. Immediately after the interrupt is approved, its IFR bit is cleared. If the interrupt signal is kept low, the IFR register bit will be set again. However, the interrupt is not immediately serviced again. The CPU blocks new hardware interrupts until the interrupt service routine (ISR) begins. In addition, the IER bit is cleared (in step 10) before the ISR begins; therefore, an interrupt from the same source cannot disturb the ISR until the IER bit is set again by the ISR.

5) Empty the pipeline. The CPU completes any instructions that have reached or passed their decode 2 phase in the instruction pipeline. Any instructions that have not reached this phase are flushed from the pipeline.

6) Increment and temporarily store PC. The PC is incremented by 1 or 2, depending on the size of the current instruction. The result is the return address, which is temporarily saved in an internal hold register. During the automatic context save (step 9), the return address is pushed onto the stack.

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Standard Operation for Maskable Interrupts

Regist

7) Fetch interrupt vector. The PC is filled with the address of the appropri- ate interrupt vector, and the vector is fetched from that location. To determine which vector address has been assigned to each of the interrupts, see section 3.2, Interrupt Vectors, on page 3-4 or, if your device uses a PIE module, see the System and Interrupts Reference Guide for your specific device.

8) Increment SP by 1. The stack pointer (SP) is incremented by 1 in prepara- tion for the automatic context save (step 9). During the automatic context save, the CPU performs 32-bit accesses, and the CPU expects 32-bit accesses to be aligned to even addresses by the memory wrapper. Incrementing SP by 1 ensures that the first 32-bit access does not overwrite the previous stack value.

9) Perform automatic context save. A number of register values are saved automatically to the stack. These registers are saved in pairs; each pair is saved in a single 32-bit operation. At the end of each 32-bit save operation, the SP is incremented by 2. Table 3−3 shows the register pairs and the order in which they are saved. The CPU expects all 32-bit saves to be even-word aligned by the memory wrapper. As shown in the table, the SP is not affected by this alignment.

Table 3−3. Register Pairs Saved and SP Positions for Context Saves

ББББББББББББББББББББББББББББ

ave

Operation

†

Pairs

SP Starts at Odd Address

1 ← SP position before step 8

Bit 0 of Storage Address

SP Starts at Even Address

1st ST0 0 0 ← SP position before step 8

T 1 1

2nd

3rd PL

‡

0 0

PH 1 1

4th AR0 0 0

AR1 1 1

5th ST1 0 0

DP 1 1

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Page 95

Standard Operation for Maskable Interrupts

ББББББББББББББББББББ

ББББББББББ

Table 3−3. Register Pairs Saved and SP Positions for Context Saves (Continued)

Bit 0 of Storage Address

SP Starts at Even Address

БББББББББ

Save

Save Operation

Operation

6th

ÁÁÁÁБББББ

†

Pairs

IER

DBGSTAT

7th Return address

SP Starts at Odd Address

ББББББББ

0 0

(low half)

Return address

1 1

(high half)

0 ← SP position after save 0

1 1 ← SP position after save

†

All registers are saved as pairs, as shown.

‡

The P register is saved with 0 shift (CPU ignores current state of the product shift mode bits, PM, in status register 0).

The DBGSTAT register contains special emulation information.

10) Clear corresponding IER bit. After the IER register is saved on the stack in step 9, the CPU clears the IER bit that corresponds to the interrupt being handled. This prevents reentry into the same interrupt. If you want to nest occurrences of the interrupt, have the ISR set that IER bit again.

11) Set INTM and DBGM. Clear LOOP, EALLOW, and IDLESTAT. All these bits are in status register ST1. By setting INTM to 1, the CPU prevents maskable interrupts from disturbing the ISR. If you wish to nest interrupts, have the ISR clear the INTM bit. By setting DBGM to 1, the CPU prevents debug events from disturbing time-critical code in the ISR. If you do not want debug events blocked, have the ISR clear DBGM.

The CPU clears LOOP, EALLOW, and IDLESTAT so that the ISR operates within a new context.

12) Load PC with fetched vector. The PC is loaded with the interrupt vector that was fetched in step 7. The vector forces program control to the ISR.

13) Execute interrupt service routine. Here is where the CPU executes the program code you have prepared to handle the interrupt. A typical ISR is shown in Example 3−1.

Although a number of register values are saved automatically in step 10, if the ISR uses other registers, you may need to save the contents of these registers at the beginning of the ISR. These values must then be restored before the return from the ISR. The ISR in Example 3−1 saves and re- stores auxiliary registers AR1H:AR0H, XAR2−XAR7, and the temporary register XT.

3-15CPU Interrupts and Reset

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Standard Operation for Maskable Interrupts

If you want the ISR to inform a peripheral that the interrupt is being serviced, you can use the IACK instruction to send an interrupt acknowledge signal. The IACK instruction accepts a 16-bit constant as an operand. For a detailed description of the IACK instruction, see Chapter 6, C28x As- sembly Language Instructions.

14) Program continues. If the interrupt is not approved by the CPU, the inter- rupt is ignored, and the program continues uninterrupted. If the interrupt is approved, its interrupt service routine is executed and the program continues where it left off (at the return address).

Example 3−1. Typical ISR

C28x Full Context Save/Restore

INTX: .; 8 cycles

PUSH AR1H:AR0H ; 32-bit PUSH XAR2 ; 32-bit PUSH XAR3 ; 32-bit PUSH XAR4 ; 32-bit PUSH XAR5 ; 32-bit PUSH XAR6 ; 32-bit PUSH XAR7 ; 32-bit PUSH XT ; 32-bit ; +8 = 16 cycles . . . POP XT POP XAR7 POP XAR6 POP XAR5 POP XAR4 POP XAR3 POP XAR2 POP XAR1H;AR0H IRET ; 16 cycles

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3.5 Nonmaskable Interrupts

Nonmaskable interrupts cannot be blocked by any of the enable bits (the INTM bit, the DBGM bit, and enable bits in the IFR, IER, or DBGIER). The C28x immediately approves this type of interrupt and branches to the corresponding interrupt service routine. There is one exception to this rule: When the CPU is halted in stop mode (an emulation mode), no interrupts are serviced. Stop mode is described in section 7.4.1 on page 7-7.

The C28x nonmaskable interrupts include:

- Software interrupts (the INTR and TRAP instructions).

- Hardware interrupt NMI

- Illegal-instruction trap

- Hardware reset interrupt (RS)

Nonmaskable Interrupts

The software interrupt instructions and NMI illegal-instruction trap and reset are described in sections 3.6 and 3.7, respectively.

3.5.1 INTR Instruction

You can use the INTR instruction to initiate one of the following interrupts by name: INT1−INT14, DLOGINT, RTOSINT and NMI. For example, you can execute the interrupt service routine for INT1

INTR INT1

Once an interrupt is initiated by the INTR instruction, how it is handled depends on which interrupt is specified:

- INT1−INT14, DLOGINT, and RTOSINT. These maskable interrupts have

- NMI. Because this interrupt is nonmaskable, a hardware request at a pin

are described in this section. The

by using the following instruction:

corresponding flag bits in the IFR. When a request for one of these interrupts is received at an external pin, the corresponding IFR bit is set and the interrupt must be enabled to be serviced. In contrast, when one of these interrupts is initiated by the INTR instruction, the IFR flag is not set, and the interrupt is serviced regardless of the value of any enable bits. However, in other respects, the INTR instruction and the hardware request are the same. For example, both clear the IFR bit that corresponds to the requested interrupt. For more details, see section 3.4 on page 3-11.

and a software request with the INTR instruction lead to the same events. These events are identical to those that take place during a TRAP instruction (see section 3.5.2).

Chapter 6, C28x Assembly Language Instructions, contains a detailed de- scription of the INTR instruction.

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Nonmaskable Interrupts

3.5.2 TRAP Instruction

You can use the TRAP instruction to initiate any interrupt, including one of the user-defined software interrupts (see USER1−USER12 in Table 3−1 on page 3-4). The TRAP instruction refers to one of the 32 interrupts by a number from 0 to 31. For example, you can execute the interrupt service routine for INT1 by using the following instruction:

TRAP #1

Regardless of whether the interrupt has bits set in the IFR and IER, neither the IFR nor the IER is affected by this instruction. Figure 3−5 shows a functional flow chart for an interrupt initiated by the TRAP instruction. For more details about the TRAP instruction, see Chapter 6, C28x Assembly Language Instruc- tions.

Note:

The TRAP #0 instruction does not initiate a full reset. It only forces execution of the interrupt service routine that corresponds to the RESET interrupt vector.

Figure 3−5. Functional Flow Chart for an Interrupt Initiated by the TRAP Instruction

INTM bit, IFR,

IER, and DBGIER

ignored and not affected

TRAP instruction fetched

Empty the pipeline.

Increment and temporarily store PC.

Fetch interrupt vector.

Increment SP by 1.

Perform automatic context save.

Set INTM and DBGM. Clear LOOP,

EALLOW, and IDLESTAT.

Load PC with fetched vector.

Execute interrupt service routine.

Program continues

This sequence protected from

interrupts

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Nonmaskable Interrupts

The following lists explains the steps shown in Figure 3−5:

1) TRAP instruction fetched. The CPU fetches the TRAP instruction from program memory. The desired interrupt vector has been specified as an operand and is now encoded in the instruction word. At this stage, no other interrupts can be serviced until the CPU begins executing the interrupt service routine (step 9).

2) Empty the pipeline. The CPU completes any instructions that have reached or passed the decode 2 phase of the pipeline. Any instructions that have not reached this phase are flushed from the pipeline.

3) Increment and temporarily store PC. The PC is incremented by 1. This value is the return address, which is temporarily saved in an internal hold register. During the automatic context save (step 6), the return address is pushed onto the stack.

4) Fetch interrupt vector. The PC is set to point to the appropriate vector location (based on the VMAP bit and the interrupt), and the vector located at the PC address is loaded into the PC. (To determine which vector address has been assigned to each of the interrupts, see section 3.2, Inter- rupt Vectors, on page 3-4.)

5) Increment SP by 1. The stack pointer (SP) is incremented by 1 in prepara- tion for the automatic context save (step 6). During the automatic context save, the CPU performs 32-bit accesses, which are aligned to even addresses. Incrementing SP by 1 ensures that the first 32-bit access will not overwrite the previous stack value.

6) Perform automatic context save. A number of register values are saved automatically to the stack. These registers are saved in pairs; each pair is saved in a single 32-bit operation. At the end of each 32-bit operation, the SP is incremented by 2. Table 3−3 shows the register pairs and the order in which they are saved. All 32-bit saves are even-word aligned. As shown in the table, the SP is not affected by this alignment.

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Nonmaskable Interrupts

Regist

Table 3−4. Register Pairs Saved and SP Positions for Context Saves

ave

Operation

†

Pairs

SP Starts at Odd Address

1 ← SP position before step 5

Bit 0 of Storage Address

SP Starts at Even Address

1st ST0 0 0 ← SP position before step 5

T 1 1

2nd

ÁÁÁÁÁÁÁÁÁ

3rd PL

БББББББББ

‡

0 0

ББББББББ

PH 1 1

4th AR0 0 0

AR1 1 1

5th ST1 0 0

DP 1 1

6th

ÁÁÁÁÁÁÁÁÁ

7th Return address

IER

DBGSTAT

БББББББББ

ББББББББ

0 0

(low half)

Return address

1 1

(high half)

0 ← SP position after save 0

1 1 ← SP position after save

†

All registers are saved as pairs, as shown.

‡

The P register is saved with 0 shift (CPU ignores current state of the product shift mode bits, PM, in status register 0).

The DBGSTAT register contains special emulation information.

7) Set INTM and DBGM. Clear LOOP, EALLOW, and IDLESTAT. All these bits are in status register ST1 (described in section 2.4 on page 2-34). By setting INTM to 1, the CPU prevents maskable interrupts from disturbing the ISR. If you wish to nest interrupts, have the ISR clear the INTM bit. By setting DBGM to 1, the CPU prevents debug events from disturbing timecritical code in the ISR. If you do not want debug events blocked, have the ISR clear DBGM.

3-20