TEXAS INSTRUMENTS TMS27C128 Technical data

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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY

TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

This Data Sheet is Applicable to All TMS27C128s and TMS27PC128s Symbolized with Code “B” as Described on Page 12.

• Organization...16K × 8

• Single 5-V Power Supply

• Pin Compatible With Existing 128K MOS

ROMs, PROMs, and EPROMs

• All Inputs/Outputs Fully TTL Compatible

• Max Access/Min Cycle Times

± 10%

’27C128-12 120 ns ’27C/PC128-15 150 ns ’27C/PC128-20 200 ns ’27C/PC128-25 250 ns

• Power Saving CMOS Technology

• Very High-Speed SNAP! Pulse Programming

• 3-State Output Buffers

• 400-mV Minimum DC Noise Immunity With

Standard TTL Loads

• Latchup Immunity of 250 mA on All Input

and Output Lines

• Low Power Dissipation (V

= 5.25 V)

– Active...158 mW Worst Case – Standby...1.4 mW Worst Case

(CMOS Input Levels)

• PEP4 Version Available With 168-Hour

Burn-In and Choices of Operating T emperature Ranges

• 128K EPROM Available With MIL-STD-883C

Class B High-Reliability Processing (SMJ27C128)

description

The TMS27C128 series are 131 072-bit, ultraviolet-light erasable, electrically programmable read-only memories.

The TMS27PC128 series are 131 072-bit, one time electrically programmable read-only memories.

J AND N PACKAGES

(TOP VIEW)

A12

DQ0

DQ1

DQ2

GND

A6 A5 A4 A3 A2 A1 A0

DQ0

A0–A13 Address Inputs E G GND Ground NC No Connection NU Make No External Connection PGM DQ0–DQ7 Inputs (programming)/Outputs V

FM PACKAGE

(TOP VIEW)

A12VNUVPGM

3213231

430

5 6 7 8 9

11 12 13

15 16 17 18 19

DQ1

DQ2

PIN NOMENCLATURE

Chip Enable/Powerdown Output Enable

Program

5-V Power Supply 12-13 V Programming Power Supply

28 27 26 25 24 23 22 21 20 19 18 17 16 15

DQ3

PGM A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3

DQ4

A13

29 28 27 26 25 24 23 22 21

DQ5

A8 A9 A1 1 NC G A10 E DQ7 DQ6

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

These devices are fabricated using power-saving CMOS technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external resistors.

The data outputs are three-state for connecting multiple devices to a common bus. The TMS27C128 and the TMS27PC128 are pin compatible with 28-pin 128K MOS ROMs, PROMs, and EPROMs.

The TMS27C128 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C128 is offered with two operating temperature ranges of 0°C to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). The TMS27C128 is also offered with 168-hour burn-in temperature ranges (JL4 and JE4 suffixes). (See table below).

The TMS27PC128 PROM is offered in a dual-in-line plastic package (N suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The TMS27PC128 is also supplied in a 32-lead plastic leaded chip carrier package using 1,25-mm (50-mil) lead spacing (FM suffix). The TMS27PC128 is also offered with two operating temperature ranges of 0°C to 70°C (NL and FML suffixes) and –40°C to 85°C (NE and FME suffixes). The TMS27PC128 is also offered with 168 hour burn-in temperature ranges (NL4, FML4, NE4, and FME4 suffixes). (See table below).

All package styles conform to JEDEC standards.

EPROM

AND

PROM

TMS27C128-XXX JL JE JL4 JE4 TMS27PC128-XXX NL NE NL4 NE4 TMS27PC128-XXX FML FME FML4 FME4

SUFFIX FOR OPERATING TEMPERATURE RANGES WITHOUT PEP4 BURN-IN

0°C TO 70°C –40 °C TO 85°C 0°C TO 70°C –40 °C TO 85°C

SUFFIX FOR OPERATING

TEMPERATURE RANGES WITH

PEP4 168 HR. BURN-IN

These EPROMs and PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use in microprocessor-based systems. One other 12-13-V supply is needed for programming . All programming signals are TTL level. These devices are programmable by using the SNAP! Pulse programming algorithm.The SNAP! Pulse programming algorithm uses a V

of 13.0 V and a VCC of 6.5 V for a nominal programming time

of two seconds. For programming outside the system, existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random.

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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY

TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

operation

The seven modes of operation are listed in the following table. Read mode requires a single 5-V supply . All inputs are TTL level except for V mode.

FUNCTION

E V G V

PGM V

A9 X X X X X X V A0 X X X X X X V

DQ0–DQ7

†

X can be VIL or VIH. VH = 12 V ± 0.5 V.

READ

IL IL

Data Out

OUTPUT

DISABLE

V V V

HI-Z HI-Z

during programming (13 V for SNAP! Pulse), and 12 V on A9 for the signature

MODE

STANDBY PROGRAMMING VERIFY

IL IH IH

†

X V

Data In Data Out

PROGRAM

INHIBIT

IH X V X

HI-Z MFG DEVICE

SIGNATURE

H IL

97 83

MODE

V V V

CODE

IL IL

IH CC CC

‡

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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

read/output disable

When the outputs of two or more TMS27C128s or TMS27PC128s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of the other devices. To read the output of a single device, a low-level signal is applied to the E All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins. Output data is accessed at pins DQ0 through DQ7.

latchup immunity

Latchup immunity on the TMS27C128 and TMS27PC128 is a minimum of 250 mA on all inputs and outputs. This feature provides latchup immunity beyond any potential transients at the P .C. board level when the devices are interfaced to industry-standard TTL or MOS logic devices. Input/output layout approach controls latchup without compromising performance or packing density.

power down

Active ICC supply current can be reduced from 30 mA to 500 µA (TTL-level inputs) or 250 µA (CMOS-level inputs) by applying a high TTL or CMOS signal to the E

pin. In this mode all outputs are in the high-impedance state.

erasure (TMS27C128)

Before programming, the TMS27C128 EPROM is erased by exposing the chip through the transparent lid to a high intensity ultraviolet light (wavelength 2537 Å). EPROM erasure before programming is necessary to assure that all bits are at the logic high level. Logic lows are programmed into the desired locations. A programmed logic low can be erased only by ultraviolet light. The recommended minimum ultraviolet light

exposure dose (UV intensity × exposure time) is 15-W⋅s/cm

. A typical 12-mW/cm2, filterless UV lamp will erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C128, the window should be covered with an opaque label.

and G pins.

initializing (TMS27PC128)

The one-time programmable TMS27PC128 PROM is provided with all bits at the logic high level. The logic lows are programmed into the desired locations. Logic lows programmed into a PROM cannot be erased.

SNAP! Pulse programming

The 128K EPROM and PROM are programmed using the TI SNAP! Pulse programming algorithm, illustrated by the flowchart in Figure 1, which programs in a nominal time of two seconds. Actual programming time will vary as a function of the programmer used.

Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, PGM pulsed.

The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (µs) followed by a byte verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs pulses per byte are provided before a failure is recognized.

The programming mode is achieved when V

= 13 V, VCC = 6.5 V, G = VIH, and E = VIL. More than

one device can be programmed when the devices are connected in parallel. Locations can be programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with V

= VPP = 5 V.

program inhibit

Programming may be inhibited by maintaining a high level input on the E

or PGM pin.

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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY

program verify

TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

Programmed bits may be verified with V

= 13 V when G = VIL, E = VIL, and PGM = VIH.

signature mode

The signature mode provides access to a binary code identifying the manufacturer and type. This mode is activated when A9 is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by A0; i.e., A0 = V accesses the manufacturer code, which is output on DQ0–DQ7; A0 = VIH accesses the device code, which is output on DQ0–DQ7. All other addresses must be held at V

. The manufacturer code for these devices

is 97, and the device code is 83.

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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

Start

Address = First Location

VCC = 6.5 V ± 0.25 V, VPP = 13 V ± 0.25 V

Program One Pulse = tw = 100 µs

Last

Address?

Yes

Address = First Location

X = 0

Increment

Address

Verify

One Byte

Pass

Fail

Increment Address

Program One Pulse = tw = 100 µs

X = 10?X = X + 1

Program

Mode

Interactive

Mode

VCC = VPP = 5 V ± 0.5 V

Last

Address?

Yes Yes

Compare All Bytes

To Original

Data

Pass

Device Passed

Fail

Figure 1. SNAP! Pulse Programming Flowchart

Device Failed

Final

Verification

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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY

TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

logic symbol

A10

A11

A12

A13

••

PGM

†

EPROM 16 384 × 8

16 383

13 [PWR DWN]

PROM 16 384 × 8

A∇ A∇

A∇ A∇ A∇ A∇ A∇ A∇

12 13 15 16 17 18 19

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

A3 A4 A5

A6 A7 A8

A10 A11

A12 A13

PGM

6 5 4 3 25 24 21 23 2 26 20

16 383

13 [PWR DWN]

A∇ A∇

A∇ A∇ A∇ A∇ A∇ A∇

12 13 15 16 17 18 19

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

†

These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are J and N packages.

‡

+ 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V Supply voltage range, V Input voltage range (see Note 1), All inputs except A9 –0.6 V to V

(see Note 1) –0.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 1) –0.6 V to 14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A9 –0.6 V to 13.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range (see Note 1) –0.6 V to V

+ 1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range (’27C128-_ _JL and JL4, ’27PC128-_ _NL, and NL4

FML, and FML4) 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range (’27C128-_ _JE and JE4, ’27PC128-_ _NE, NE4,

FME, and FME4) –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Under absolute maximum ratings, voltage values are with respect to GND.

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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY

VCCSuppl

oltage

VPPSuppl

oltage

VIHHigh-level dc input voltage

VILLow-level dc input voltage

VOHHigh-level dc output voltage

VOLLow-level dc output voltage

pply current (standby)

TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

recommended operating conditions

MIN NOM MAX UNIT

y v

Operating free-air temperature

NOTES: 2. VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted

into or removed from the board when VPP or VCC is applied.

Read mode (see Note 2) 4.5 5 5.5 SNAP! Pulse programming algorithm 6.25 6.5 6.75 Read mode VCC– 0.6 VCC+ 0.6 SNAP! Pulse programming algorithm 12.75 13 13.25

TTL 2 VCC+1 CMOS VCC–0.2 VCC+1 TTL –0.5 0.8 V CMOS –0.5 0.2 V

’27C128-_ _JL,JL4

’27PC128_ _NL,NL4

FML, FML4

’27C128-_ _JE,JE4

’27PC128_ _NE,NE4

FME, FME4

0 70 °C

–40 70 °C

electrical characteristics over full ranges of operating conditions

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Input current (leakage) VI = 0 to 5.5 V ±1 µA

Output current (leakage) VO = 0 to V

PP1VPP

PP2VPP

CC1VCC

CC2VCC

†

Typical values are at TA = 25°C and nominal voltages.

supply current VPP = VCC = 5.5 V 1 10 µA supply current (during program pulse) VPP = 13 V 35 50 mA

supply current (active) t

TTL-input level VCC = 5.5 V, E = V CMOS-input level VCC = 5.5 V, E = V

IOH = –2.5 mA 3.5 V IOH = –20 µA VCC–0.1 V IOL = 2.1 mA 0.4 V IOL = 20 µA 0.1 V

IH CC

VCC = 5.5 V, E = VIL,

= minimum cycle time, 15 30 mA

cycle

outputs open

250 500 µA 100 250 µA

±1 µA

capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Input capacitance VI = 0, f = 1 MHz 6 10 pF

Output capacitance VO = 0, f = 1 MHz 10 14 pF

†

Typical values are at TA = 25°C and nominal voltages. Capacitance measurements are made on sample basis only.

‡

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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY

PARAMETER

TEST CONDITIONS

UNIT

100 F

In ut t

UNIT

100 F

In ut t

TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

switching characteristics over full ranges of recommended operating conditions (see Notes 3 and 4)

’27C128-12 ’27C/PC128-15

MIN MAX MIN MAX

120 150 ns

55 75 ns

0 45 0 60 ns 0 0 ns

a(A)

a(E)

en(G)

dis

v(A)

TEST CONDITIONS

(SEE NOTES 3 AND 4)

Access time from address 120 150 ns Access time from chip enable Output enable time from G

Output disable time from G or E, whichever occurs first Output data valid time after change of address,

, or G, whichever occurs first

†

1 Series 74 TTL Load,

†

Input tr ≤ 20 ns,

≤ 20

TEST CONDITIONS

(SEE NOTES 3 AND 4)

a(A)

a(E)

en(G)

dis

v(A)

†

Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.

Access time from address 200 250 ns Access time from chip enable Output enable time from G

Output disable time from Go r E, whichever occurs first Output data valid time after change of address, E, or G,

whichever occurs first

†

1 Series 74 TTL Load,

†

Input tr ≤ 20 ns,

≤ 20

’27C/PC128-20 ′27C/PC128-25

MIN MAX MIN MAX

200 250 ns

75 100 ns

0 60 0 60 ns 0 0 ns

switching characteristics for programming:VCC = 6.5 V and VPP = 13 V (SNAP! Pulse), TA = 25°C (see Note 3)

PARAMETER MIN NOM MAX UNIT

dis(G)

en(G)

recommended timing requirements for programming: VCC = 6.5 V and V Pulse), T

w(IPGM)

su(A)

su(E)

su(G)

su(D)

su(VPP)

su(VCC)

h(A)

h(D)

NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high

Output disable time from G 0 130 ns Output enable time from G 150 ns

=13 V (SNAP!

= 25°C (see Note 3)

Initial program pulse duration SNAP! Pulse programming algorithm 95 100 105 µs Address setup time 2 µs E setup time 2 µs G setup time 2 µs Data setup time 2 µs VPP setup time 2 µs VCC setup time 2 µs Address hold time 0 µs Data hold time 2 µs

and 0.8 V for logic low (reference page 10).

4. Common test conditions apply for t

except during programming.

dis

MIN NOM MAX UNIT

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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

PARAMETER MEASUREMENT INFORMATION

2.08 V

RL = 800 Ω

Output

Under Test

CL = 100 pF

Figure 2. AC Testing Output Load Circuit

AC testing input/output wave forms

2.4 V

0.4 V

2 V

0.8 V

2 V

0.8 V

AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs and outputs.

A0–A13

DQ0–DQ7

Addresses Valid

a(A)

a(E)

en(G)

HI-Z HI-ZOutput Valid

v(A)

dis

Figure 3. Read Cycle Timing

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A0–A13

DQ0–DQ7

PGM

TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY

TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

PARAMETER MEASUREMENT INFORMATION

Verify

Program

Address Stable

su(A)

Data In Stable

su(D)

su(VPP)

su(VCC)

su(E)

w(IPGM)

h(D)

su(G)

Data Out

Valid

en(G)

h(A)

dis(G)

†

Address

N + 1

†

‡

†

and t

dis(G)

13-V VPP and 6.5-V VCC for SNAP! Pulse programming.

are characteristics of the device but must be accommodated by the programmer.

en(G)

Figure 4. Program Cycle Timing

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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

device symbolization

This data sheet is applicable to all TI TMS27C128 CMOS EPROMs and TMS27PC128 PROMs with the data sheet revision code “B” as shown below.

TI FML

TMS27PC128

TMS 27C128

B L X P YY WW

Data Sheet Revision Code Wafer Fab Code Die Revision Code Assembly Site Code

Year of Manufacture Month of Manufacture

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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY

TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

TYPICAL TMS27C/PC128 CHARACTERISTICS

1.50

1.25

1.00

0.75

(Normalized)

—Standby Supply CurrentI

0.50

CC1

–75 –50 –25 0 25 50 75

1.50

1.25

STANDBY SUPPLY CURRENT

FREE-AIR TEMPERATURE

VCC = 5 V

— Free-Air Temperature — °C

ACTIVE SUPPLY CURRENT

FREE-AIR TEMPERATURE

VCC = 5 V

100 125

1.50

1.25

1.00

(Normalized)

0.75

—Standby Supply CurrentI

0.50

CC1

4.25 4.5 4.75 5 5.25

1.50

1.25

STANDBY SUPPLY CURRENT

SUPPLY VOLTAGE

TA = 25 °C

— Supply Voltage — V

ACTIVE SUPPLY CURRENT

SUPPLY VOLTAGE

TA = 25 °C

f = Max

5.5 5.75

1.00

0.75

(Normalized)

— Active Supply CurrentI

0.50

CC2

— Acctss TimeT

–75 –50 –25 0 25 50 75 100 125

1.50

1.25

1.00

0.75

(Normalized)

0.50 –75 –50 –25 0 25 50 75 100 125

— Free-Air Temperature — °C

ACCESS TIME

FREE-AIR TEMPERATURE

VCC = 5 V

1.00

(Normalized)

0.75

— Active Supply CurrentI

CC2

0.50

4.25 4.5 4.75 5 5.25 5.5 5.75

1.50

1.25

1.00

— Access TimeT

(Normalized)

0.75

0.50

4.25 4.5 4.75 5 5.25 5.5 5.75

— Supply Voltage — V

TA = 25 °C

ACCESS TIME

SUPPLY VOLTAGE

— Free-Air Temperature — °C

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— Supply Voltage — V

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

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TEXAS INSTRUMENTS TMS27C128 Technical data

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Frequently Asked Questions

User Manual