TEXAS INSTRUMENTS TMS27C128 Technical data

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TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY

TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

This Data Sheet is Applicable to All
TMS27C128s and TMS27PC128s Symbolized
with Code “B” as Described on Page 12.

• Organization...16K × 8

• Single 5-V Power Supply

• Pin Compatible With Existing 128K MOS

ROMs, PROMs, and EPROMs

• All Inputs/Outputs Fully TTL Compatible

• Max Access/Min Cycle Times

± 10%

V

CC

’27C128-12 120 ns
’27C/PC128-15 150 ns
’27C/PC128-20 200 ns
’27C/PC128-25 250 ns

• Power Saving CMOS Technology

• Very High-Speed SNAP! Pulse Programming

• 3-State Output Buffers

• 400-mV Minimum DC Noise Immunity With

Standard TTL Loads

• Latchup Immunity of 250 mA on All Input

and Output Lines

• Low Power Dissipation (V

= 5.25 V)

CC

– Active...158 mW Worst Case
– Standby...1.4 mW Worst Case

(CMOS Input Levels)

• PEP4 Version Available With 168-Hour

Burn-In and Choices of Operating
T emperature Ranges

• 128K EPROM Available With MIL-STD-883C

Class B High-Reliability Processing
(SMJ27C128)

description

The TMS27C128 series are 131 072-bit,
ultraviolet-light erasable, electrically
programmable read-only memories.

The TMS27PC128 series are 131 072-bit, one
time electrically programmable read-only
memories.

J AND N PACKAGES

(TOP VIEW)

V

1

PP

A12

2

A7

3

A6

4

A5

5

A4

6

A3

7

A2

8

A1

9

A0

10

DQ0

11

DQ1

12

DQ2

13

GND

A6
A5
A4
A3
A2
A1
A0

NC

DQ0

A0–A13 Address Inputs
E
G
GND Ground
NC No Connection
NU Make No External Connection
PGM
DQ0–DQ7 Inputs (programming)/Outputs
V

CC

V

PP

14

FM PACKAGE

(TOP VIEW)

PP

A7

A12VNUVPGM

3213231

430

5
6
7
8
9

10

11
12
13

14

15 16 17 18 19

SS

V

DQ1

DQ2

PIN NOMENCLATURE

Chip Enable/Powerdown
Output Enable

Program

5-V Power Supply
12-13 V Programming Power Supply

28
27
26
25
24
23
22
21
20
19
18
17
16
15

NU

CC

DQ3

V

CC

PGM
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3

20

DQ4

A13

29
28
27
26
25
24
23
22
21

DQ5

A8
A9
A1 1
NC
G
A10
E
DQ7
DQ6

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 1443 • HOUSTON, TEXAS

77251–1443

Copyright  1993, Texas Instruments Incorporated

1

TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.

The data outputs are three-state for connecting multiple devices to a common bus. The TMS27C128 and the
TMS27PC128 are pin compatible with 28-pin 128K MOS ROMs, PROMs, and EPROMs.

The TMS27C128 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C128 is offered with two operating temperature
ranges of 0°C to 70°C (JL suffix) and – 40°C to 85°C (JE suffix). The TMS27C128 is also offered with 168-hour
burn-in temperature ranges (JL4 and JE4 suffixes). (See table below).

The TMS27PC128 PROM is offered in a dual-in-line plastic package (N suffix) designed for insertion in mounting
hole rows on 15,2-mm (600-mil) centers. The TMS27PC128 is also supplied in a 32-lead plastic leaded chip
carrier package using 1,25-mm (50-mil) lead spacing (FM suffix). The TMS27PC128 is also offered with two
operating temperature ranges of 0°C to 70°C (NL and FML suffixes) and –40°C to 85°C (NE and FME suffixes).
The TMS27PC128 is also offered with 168 hour burn-in temperature ranges (NL4, FML4, NE4, and FME4
suffixes). (See table below).

All package styles conform to JEDEC standards.

EPROM

AND

PROM

TMS27C128-XXX JL JE JL4 JE4
TMS27PC128-XXX NL NE NL4 NE4
TMS27PC128-XXX FML FME FML4 FME4

SUFFIX FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN-IN

0°C TO 70°C –40 °C TO 85°C 0°C TO 70°C –40 °C TO 85°C

SUFFIX FOR OPERATING

TEMPERATURE RANGES WITH

PEP4 168 HR. BURN-IN

These EPROMs and PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use in
microprocessor-based systems. One other 12-13-V supply is needed for programming . All programming
signals are TTL level. These devices are programmable by using the SNAP! Pulse programming algorithm.The
SNAP! Pulse programming algorithm uses a V

of 13.0 V and a VCC of 6.5 V for a nominal programming time

PP

of two seconds. For programming outside the system, existing EPROM programmers can be used. Locations
may be programmed singly, in blocks, or at random.

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS

77251–1443

TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY

TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

operation

The seven modes of operation are listed in the following table. Read mode requires a single 5-V supply . All
inputs are TTL level except for V
mode.

FUNCTION

E V
G V

PGM V

V

PP

V

CC

A9 X X X X X X V
A0 X X X X X X V

DQ0–DQ7

†

X can be VIL or VIH.
VH = 12 V ± 0.5 V.

READ

IL
IL

IH

V

CC

V

CC

Data Out

OUTPUT

DISABLE

V
V
V

V

CC

V

CC

HI-Z HI-Z

during programming (13 V for SNAP! Pulse), and 12 V on A9 for the signature

PP

MODE

STANDBY PROGRAMMING VERIFY

IL
IH
IH

V

IH

†

X

X V

V

CC

V

CC

V

IL

V

IH

IL

V

PP

V

CC

Data In Data Out

V

IL

V

IL

V

IH

V

PP

V

CC

PROGRAM

INHIBIT

V

IH
X V
X

V

PP

V

CC

HI-Z MFG DEVICE

SIGNATURE

H
IL

97 83

MODE

V

V
V
V

CODE

IL
IL

IH
CC
CC

‡

V

H

V

IH

POST OFFICE BOX 1443 • HOUSTON, TEXAS

77251–1443

3

TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

read/output disable

When the outputs of two or more TMS27C128s or TMS27PC128s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E
All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins DQ0 through DQ7.

latchup immunity

Latchup immunity on the TMS27C128 and TMS27PC128 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P .C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input/output layout approach controls latchup
without compromising performance or packing density.

power down

Active ICC supply current can be reduced from 30 mA to 500 µA (TTL-level inputs) or 250 µA (CMOS-level inputs)
by applying a high TTL or CMOS signal to the E

pin. In this mode all outputs are in the high-impedance state.

erasure (TMS27C128)

Before programming, the TMS27C128 EPROM is erased by exposing the chip through the transparent lid to
a high intensity ultraviolet light (wavelength 2537 Å). EPROM erasure before programming is necessary to
assure that all bits are at the logic high level. Logic lows are programmed into the desired locations. A
programmed logic low can be erased only by ultraviolet light. The recommended minimum ultraviolet light

2

exposure dose (UV intensity × exposure time) is 15-W⋅s/cm

. A typical 12-mW/cm2, filterless UV lamp will
erase the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. It
should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when
using the TMS27C128, the window should be covered with an opaque label.

and G pins.

initializing (TMS27PC128)

The one-time programmable TMS27PC128 PROM is provided with all bits at the logic high level. The logic lows
are programmed into the desired locations. Logic lows programmed into a PROM cannot be erased.

SNAP! Pulse programming

The 128K EPROM and PROM are programmed using the TI SNAP! Pulse programming algorithm, illustrated
by the flowchart in Figure 1, which programs in a nominal time of two seconds. Actual programming time will
vary as a function of the programmer used.

Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, PGM
pulsed.

The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (µs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs
pulses per byte are provided before a failure is recognized.

The programming mode is achieved when V

= 13 V, VCC = 6.5 V, G = VIH, and E = VIL. More than

PP

one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified
with V

= VPP = 5 V.

CC

program inhibit

Programming may be inhibited by maintaining a high level input on the E

or PGM pin.

is

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS

77251–1443

TMS27C128 131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY

program verify

TMS27PC128 131 072-BIT PROGRAMMABLE READ-ONLY MEMORY

SMLS128E–OCTOBER 1984–REVISED JANUARY 1993

Programmed bits may be verified with V

= 13 V when G = VIL, E = VIL, and PGM = VIH.

PP

signature mode

The signature mode provides access to a binary code identifying the manufacturer and type. This mode
is activated when A9 is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by A0; i.e., A0 = V
accesses the manufacturer code, which is output on DQ0–DQ7; A0 = VIH accesses the device code, which
is output on DQ0–DQ7. All other addresses must be held at V

. The manufacturer code for these devices

IL

is 97, and the device code is 83.

IL

POST OFFICE BOX 1443 • HOUSTON, TEXAS

77251–1443

5