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TMP320C40KGDL60C
Datasheet
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Texas Instruments TMP320C40KGDL60C Datasheet

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TMP320C40KGDC, SMJ320C40KGDC, TMP320C40KGDCT, SMJ320C40KGDCT
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
KNOWN GOOD DIES
SGUS024B – MARCH 1997 – REVISED APRIL 2000
1
D
SMJ: QML Processing to MIL–PRF–38535
D
TMP: Commercial Level Processing
D
Operating Temperature Ranges: – Military (M) –55°C to 125°C
– Commercial (C) –25°C to 85°C – Commercial (L) 0°C to 70°C
D
Highest Performance Floating-Point Digital Signal Processor (DSP) – ’C40-50:
40-ns Instruction Cycle Time: 50 MFLOPS, 25 MIPS, 275 MOPS, 320 MBps
– ’C40-40:
50-ns Instruction Cycle Time: 40 MFLOPS, 20 MIPS, 220 MOPS, 256 MBps
D
Six Communications Ports
D
6-Channel Direct Memory Access (DMA) Coprocessor
D
Single-Cycle Conversion to and From IEEE-745 Floating-Point Format
D
Single Cycle 1/x, 1/
D
Source-Code Compatible With SMJ320C30
D
Validated Ada Compiler
D
Single-Cycle 40-Bit Floating-Point, 32-Bit Integer Multipliers
D
12 40-Bit Registers, 8 Auxiliary Registers, 14 Control Registers, and 2 Timers
D
IEEE Standard 1149.1† Test-Access Port (JTAG)
D
Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers: – High Port-Data Rate of 100 MBytes/s
(Each Bus)
– 16G-Byte Continuous
Program/Data/Peripheral Address Space
– Memory-Access Request for Fast,
Intelligent Bus Arbitration
– Separate Address-, Data-, and
Control-Enable Pins
– Four Sets of Memory-Control Signals
Support Different Speed Memories in Hardware
D
Fabricated Using 0.72-µm Enhanced Performance Implanted CMOS (EPIC) Technology by Texas Instruments (TI)
D
Separate Internal Program, Data, and DMA Coprocessor Buses for Support of Massive Concurrent Input/Output (I/O) of Program and Data Throughput, Maximizing Sustained Central Processing Unit (CPU) Performance
D
On-Chip Program Cache and Dual-Access/Single-Cycle RAM for Increased Memory-Access Performance – 512-Byte Instruction Cache – 8K Bytes of Single-Cycle Dual-Access
Program or Data RAM
– ROM-Based Bootloader Supports
Program Bootup Using 8-, 16-, or 32-Bit Memories Over Any One of the Communications Ports
description
The TMP/SMJ320C40KGD DSP is a 32-bit, floating-point processor manufactured in 0.72-µm, double-level metal CMOS technology . It is the fourth generation of DSPs from Texas Instruments, and it is the world’ s first DSP designed for parallel processing. The on-chip parallel processing capabilities of the ’C40 make the floating-point performance required by many applications achievable and cost-effective.
The TMP/SMJ320C40 is the first DSP with on-chip communication ports for processor-to-processor communication using simple communication software with no external hardware. This allows connectivity with no external glue logic. The communication ports remove I/O bottlenecks, and the independent smart-DMA coprocessor is able to handle the CPU I/O requirements.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2000, Texas Instruments Incorporated
†
IEEE Standard 1149.1–1990 Standard Test-Access Port and Boundary-Scan Architecture
EPIC and TI are trademarks of Texas Instruments Incorporated.
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
TMP320C40KGDC, SMJ320C40KGDC, TMP320C40KGDCT, SMJ320C40KGDCT FLOATING-POINT DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIES
SGUS024B – MARCH 1997 – REVISED APRIL 2000
2
description (continued)
The features of the communication ports are:
D
Six communication ports for direct interprocessor communication and processor I/O
D
20 MBps bidirectional interface on each communication port for high-speed and low-cost multiprocessor interface
D
Separate input and output first-in, first-out (FIFO) buffers for I/O and processor-to-processor communication
D
Automatic arbitration and handshaking for direct processor-to-processor connection
The DMA coprocessor allows concurrent I/O and CPU processing for superior sustained CPU performance. The key features of the DMA coprocessor:
D
Link pointers that allow DMA channels to auto-initialize
D
Parallel CPU operation and DMA transfers
D
Six DMA channels support communication-port-to-memory data transfers
The TMP/SMJ320C40KGD CPU is configured for high-speed internal parallel processing. The key features of the CPU are:
D
Eight operations/cycles – 40-/32-bit floating-point/integer multiply – 40-/32-bit floating-point/integer arithmetic and logic unit (ALU) operation – Two data accesses – Two address-register updates
D
IEEE floating-point conversion
D
Division and square-root support
D
’C30 assembly language compatibility
D
Byte and halfword accessibility
Key factors in a parallel-processing implementation are the development tools that are available. The ’C40 is supported by a host of parallel-processing development tools for developing and simulating code and for debugging parallel-processing systems. The code generation tools include:
D
Optimizing ANSI C compiler with a runtime library that supports use of communication ports and DMA
D
SPOX, by Spectron Microsystems Incorporated, which provides parallel processing support as well as DMA and communication port drivers
D
Assembler and linker with support for mapping program and data to parallel processors.
SPOX is a trademark of Spectron Microsystems, Inc.
TMP320C40KGDC, SMJ320C40KGDC, TMP320C40KGDCT, SMJ320C40KGDCT
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
KNOWN GOOD DIES
SGUS024B – MARCH 1997 – REVISED APRIL 2000
3
description (continued)
The simulation tools include:
D
Parallel DSP system-level simulation, by Logic Modeling Corporation (LMC), which includes a hardware verification (HV) model and a full functional (FF) model
D
TI software simulator with high-level language debugger interface for simulating a single processor
The hardware development and verification tools include:
D
Parallel processor in-circuit emulator and high-level language debugger: XDS510
D
Parallel processor development system with four TMS320C40s, local and global memory, and communication port connections
known good die technology
Known good die (KGD) options are offered for use in multichip modules and chip-on-board (COB) applications. There are currently two verification technologies used at TI to support KGD requirements for the TMP/SMJ320C40KGD: Removable Tab (R-Tab), and Temporary Wire Bond (TWB).
The availability of selected DSP products in a tape-automated bond (T AB) configuration has made possible the use of a removable T AB technique. The TAB leadframe is attached to a gold-bumped die using modified bonding parameters. This technique allows easy removal of the tape after all needed 100% screens and parametric tests have been performed. The tape is removed from the tested part and the die is shipped in a conventional die container. The gold bumps remain on the bond pads, which allow for subsequent attachment of gold-ball bonds.
Similarly , with KGD using the TWB technique, bond wires are attached to the bond pads using adjusted bonding parameters which allow for easy removal of the die after all needed 100% screens and parametric tests have been performed. The die is removed from the temporary package and the die is shipped in a conventional die container.
visual inspection of known good die (KGD) using temporary wire bond (TWB) process
QML KGD devices produced using the TWB technology do not optically meet MIL-STD-883E (Method 2010, paragraph 3.1.1.1.h) metal bond pad visual inspection criterion due to the bond pad marks formed during bonding removal process. However, these devices have been reliably bonded using normal wire bond precesses, and pass bond strength evaluations.
electrical specifications
For military electrical and timing specifications, please refer to the
SMJ320C40 Digital Signal Processor
data
sheet, literature number SGUS017. For commercial electrical and timing specifications, see the
TMS320C40
Digital Signal Processor Data Sheet
, literature number SPRS038.
XDS510 is a trademark of Texas Instruments Incorporated.
TMP320C40KGDC, SMJ320C40KGDC, TMP320C40KGDCT, SMJ320C40KGDCT FLOATING-POINT DIGITAL SIGNAL PROCESSOR KNOWN GOOD DIES
SGUS024B – MARCH 1997 – REVISED APRIL 2000
4
SMJ 320 C 40 MKGD 50
PREFIX
SMJ = MIL-PRF-38535 Processing TMP = Commercial Level
DEVICE FAMILY
320 = DSP Family
TECHNOLOGY
C = CMOS
DEVICE
40 = Floating-Point DSP
SPEED RANGE
40 = 40 MHz 50 = 50 MHz
PACKAGE TYPE
KGD = Known Good Die
TEMPERATURE RANGE
M (Military) = –55°C to 125°C L (Commercial) = 0°Cto70°C
C
DIE REVISION
C = Revision 5.2
T
KGD OPTION
T = TWB process
blank = R-T ab process
Figure 1. TMP/SMJ320C40KGD Device Nomenclature
JEDEC STANDARD
D
Die thickness is approximately 15 mils ± 1 mil.
D
Backside surface finish is silicon.
D
Maximum allowable die junction operating temperature is 175°C.
D
Glassivation material is compressive nitride.
D
Bond pad metal is composed of copper-doped aluminum.
D
Percent defective allowed for burned-in die is 5.
D
Life test data is available.
D
Configuration control notification.
D
Group A attribute summary is available (SMJ only).
D
Suggested die-attach material is silver glass (QMI 2569F).
D
Suggested bond wire size is 1.25 mil.
D
For gold bumped KGD die, suggested bonding method is gold-ball bonding.
D
ESD rating is Class II.
D
Maximum allowable peak process temperature for die-attach is 440°C ± 5°C (for QMS2569F)
D
Saw kerf is dependent on blade size used.
D
Die backside potential is left floating.
TMP320C40KGDC, SMJ320C40KGDC, TMP320C40KGDCT, SMJ320C40KGDCT
FLOATING-POINT DIGITAL SIGNAL PROCESSOR
KNOWN GOOD DIES
SGUS024B – MARCH 1997 – REVISED APRIL 2000
5
’320C40 (rev 5.2) known good die pad information
325 244Die Side Number 4
Pad Number One 1
•
•
•
Die Side Number 1
•
•
•
81
Zero-Zero
(origin)
82 162Die Side Number 2
243
•
•
•
Die Side Number 3
•
•
•
163
Die Designator
Figure 2. ’320C40 Die Numbering Format
(See Table 1)
Table 1 provides a reference for the following:
D
The ’C40 signal identities in relation to the pad numbers
D
The ’C40 X,Y coordinates, where bond pad 82 serves as the origin (0,0)
In addition, the following notes are significant:
A. X,Y coordinate data is in microns. B. The active silicon dimensions are 12424.86 µm × 12035.52 µm (489.16 mils × 473.83 mils). C. The die size is approximately 12598.40 µm × 12192.00 µm (496.00 mils × 480.00 mils). D. Bond pad dimensions are 108.00 µm × 108.00 µm (4.25 mils × 4.25 mils). E. Center of bond pad to edge of die min (without scribe) = 107.80 µm (4.24 mils). F. For R-Tab devices, gold bump dimensions are approximately 92 µm × 92 µm (3.62 mils × 3.62 mils). G. Coordinate origin is at (0,0) (center of bond pad 82).
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