查询TMP100NA/3K供应商
TMP100
TMP101
SBOS231C – JANUARY 2002 – REVISED JULY 2003
Digital Temperature Sensor
with I2C Interface
FEATURES
● DIGITAL OUTPUT: I2C Serial 2-Wire
● RESOLUTION: 9- to 12-Bits, User-Selectable
● ACCURACY: ±2.0°C from –25°C to +85°C (max)
±
3.0°C from –55°C to +125°C (max)
● LOW QUIESCENT CURRENT: 45µA, 0.1µA Standby
● WIDE SUPPLY RANGE: 2.7V to 5.5V
● TINY SOT23-6 PACKAGE
APPLICATIONS
● POWER-SUPPLY TEMPERATURE MONITORING
● COMPUTER PERIPHERAL THERMAL PROTECTION
● NOTEBOOK COMPUTERS
● CELL PHONES
● BATTERY MANAGEMENT
● OFFICE MACHINES
● THERMOSTAT CONTROLS
● ENVIRONMENTAL MONITORING and HVAC
● ELECTROMECHANICAL DEVICE TEMPERATURE
DESCRIPTION
The TMP100 and TMP101 are 2-wire, serial output temperature sensors available in SOT23-6 packages. Requiring no
external components, the TMP100 and TMP101 are capable
of reading temperatures with a resolution of 0.0625°C.
The TMP100 and TMP101 feature SMBus and I
face compatibility, with the TMP100 allowing up to eight
devices on one bus. The TMP101 offers SMBus alert function with up to three devices per bus.
The TMP100 and TMP101 are ideal for extended temperature measurement in a variety of communication, computer,
consumer, environmental, industrial, and instrumentation
applications.
The TMP100 and TMP101 are specified for operation over a
temperature range of –55°C to +125°C.
I2C is a registered trademark of Philips Incorporated.
2
C™ inter-
Temperature
Diode
1
2
3
Temp.
Sensor
∆Σ
A/D
Converter
OSC
TMP100
SCL
GND
ADD1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Control
Logic
Serial
Interface
Config
and T emp
Register
6
5
4
SDA
ADD0
V+
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Temperature
SCL
GND
ALERT
Diode
1
Temp.
Sensor
∆Σ
2
A/D
Converter
3
OSC
TMP101
Copyright © 2002-2003, Texas Instruments Incorporated
Control
Logic
Serial
Interface
Config
and T emp
Register
6
SDA
5
ADD0
4
V+
ABSOLUTE MAXIMUM RATINGS
SCL
GND
ALERT
SDA
ADD0
V+
1
2
3
6
5
4
T101
Power Supply, V+ ............................................................................... 7.5V
Input Voltage
Operating Temperature Range ......................................–55°C to +125°C
Storage Temperature Range ......................................... –60°C to +150°C
Junction Temperature (T
Lead Temperature (soldering)....................................................... +300°C
NOTES: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability. (2) Input voltage
rating applies to all TMP100 and TMP101 input voltages.
(2)
.................................................................... –0.5V to 7.5V
Max) .................................................... +150°C
J
(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT PACKAGE-LEAD DESIGNATOR
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
TMP100 SOT23-6 DBV –55°C to +125°C T100 TMP100NA/250 Tape and Reel, 250
(1)
"" "" "TMP100NA/3K Tape and Reel, 3000
TMP101 SOT23-6 DBV –55°C to +125°C T101 TMP101NA/250 Tape and Reel, 250
"" "" "TMP101NA/3K Tape and Reel, 3000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
SPECIFIED
RANGE MARKING NUMBER MEDIA, QUANTITY
PIN CONFIGURATIONS
Top View SOT23 Top View SOT23
T100
SCL
GND
ADD1
1
2
3
TMP100 TMP101
6
SDA
5
ADD0
4
V+
2
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TMP100, 101
SBOS231C
ELECTRICAL CHARACTERISTICS
At TA = –55°C to +125°C, and V+ = 2.7V to 5.5V, unless otherwise noted.
TMP100, TMP101
PARAMETER CONDITION MIN TYP MAX UNITS
TEMPERATURE INPUT
Range –55 +125 °C
Accuracy (Temperature Error) –25°C to +85°C ±0.5 ±2.0 °C
Resolution Selectable ±0.0625 °C
DIGITAL INPUT/OUTPUT
Input Logic Levels:
V
IH
V
IL
Input Current, I
Output Logic Levels:
V
SDA IOL = 3mA 0 0.15 0.4 V
OL
V
ALERT IOL = 4mA 0 0.15 0.4 V
OL
Resolution Selectable 9 to 12 Bits
Conversion Time 9-Bit 40 75 ms
Conversion Rate 9-Bit 25 s/s
POWER SUPPLY
Operating Range 2.7 5.5 V
Quiescent Current I
Shutdown Current I
TEMPERATURE RANGE
Specified Range –55 +125 °C
Storage Range –60 +150 °C
Thermal Resistance,
IN
Q
Serial Bus Active, SCL Freq = 400kHz 70 µA
Serial Bus Active, SCL Freq = 3.4MHz 150 µA
SD
Serial Bus Active, SCL Freq = 400kHz 20 µA
Serial Bus Active, SCL Freq = 3.4MHz 100 µA
θ
JA
–55°C to +125°C ±1.0 ±3.0 °C
0.7(V+) 6.0 V
–0.5 0.3(V+) V
0V ≤ VIN ≤ 6V 1 µA
10-Bit 80 150 ms
11-Bit 160 300 ms
12-Bit 320 600 ms
10-Bit 12 s/s
11-Bit 6 s/s
12-Bit 3 s/s
Serial Bus Inactive 45 75 µA
Serial Bus Inactive 0.1 1 µA
SOT23-6 Surface-Mount 150 °C/W
TMP100, 101
SBOS231C
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3
TYPICAL CHARACTERISTICS
At TA = +25°C, V+ = 5.0V, unless otherwise noted.
70
60
50
(µA)
Q
I
40
30
400
350
300
Conversion Time (ms)
250
QUIESCENT CURRENT vs TEMPERATURE
V+ = 5V
V+ = 2.7V
Serial Bus Inactive
–60 –40 –20 0 20 40 60 80 100 120 140
Temperature (°C)
CONVERSION TIME vs TEMPERATURE
V+ = 5V
V+ = 2.7V
NOTE: 12-bit resolution.
–60 –40 –20 0 20 40 60 80 100 120 140
Temperature (°C)
1.0
0.9
0.8
0.7
0.6
0.5
(µA)
0.4
SD
I
0.3
0.2
0.1
0.0
–0.1
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
Temperature Error (°C)
–1.5
–2.0
SHUTDOWN CURRENT vs TEMPERATURE
–60 –40 –20 0 20 40 60 80 100 120 140
Temperature (°C)
TEMPERATURE ACCURACY vs TEMPERATURE
3 Typical Units
–60 –40 –20 0 20 40 60 80 100 120 140
Temperature (°C)
NOTE: 12-bit resolution.
QUIESCENT CURRENT WITH
180
160
140
120
100
(µA)
Q
80
I
60
40
20
FAST MODE Hs MODE
0
10k 100k 1M 10M
4
BUS ACTIVITY vs TEMPERATURE
125°C
25°C
–55°C
SCL Frequency (Hz)
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125°C
25°C
–55°C
TMP100, 101
SBOS231C
APPLICATIONS INFORMATION
The TMP100 and TMP101 are digital temperature sensors
optimal for thermal management and thermal protection
applications. The TMP100 and TMP101 are I
interface compatible and are specified over a temperature
range of –55°C to +125°C.
The TMP100 and TMP101 require no external components
for operation except for pull-up resistors on SCL, SDA, and
ALERT, although a 0.1µF bypass capacitor is recommended,
as shown in Figure 1 and Figure 2.
V+
2
C and SMBus
POINTER REGISTER
Figure 3 shows the internal register structure of the TMP100
and TMP101. The 8-bit Pointer Register of the TMP100 and
TMP101 is used to address a given data register. The Pointer
Register uses the two LSBs to identify which of the data
registers should respond to a read or write command. Table
I identifies the bits of the Pointer Register byte. Table II
describes the pointer address of the registers available in the
TMP100 and TMP101. Power-up Reset value of P1/P0 is 00.
Pointer
Register
0.1µF
3
5
NOTE: (1) SCL, SDA and ALERT
require pull-up resistors for
2
I
C bus applications.
ALERT
(Output)
ADD0
(Input)
To I
Controller
4
SCL
SDA
1
6
TMP101
2
GND
2
C
FIGURE 1. Typical Connections of the TMP101.
V+
0.1µF
3
5
NOTE: (1) SCL and SDA
require pull-up resistors for
2
I
C bus applications.
ADD1
(Input)
ADD0
(Input)
To I
Controller
4
SCL
SDA
1
6
TMP100
2
GND
2
C
FIGURE 2. Typical Connections of the TMP100.
The die flag of the lead frame is connected to pin 2. The
sensing device of the TMP100 and TMP101 is the chip itself.
Thermal paths run through the package leads as well as the
plastic package. The lower thermal resistance of metal causes
the leads to provide the primary thermal path. The GND pin
of the TMP100 or TMP101 is directly connected to the metal
lead frame, and is the best choice for thermal input.
To maintain the accuracy in applications requiring air or
surface temperature measurement, care should be taken to
isolate the package and leads from ambient air temperature.
A thermally conductive adhesive will assist in achieving
accurate surface temperature measurement.
Temperature
Register
Configuration
Register
T
LOW
Register
T
HIGH
Register
I/O
Control
Interface
SCL
SDA
FIGURE 3. Internal Register Structure of TMP100 and TMP101.
P7 P6 P5 P4 P3 P2 P1 P0
0 0 0 0 0 0 Register Bits
TABLE I. Pointer Register Byte.
P1 P0 REGISTER
0 0 Temperature Register (READ Only)
0 1 Configuration Register (READ/WRITE)
10T
11T
Register (READ/WRITE)
LOW
Register (READ/WRITE)
HIGH
TABLE II. Pointer Addresses of the TMP100 and TMP101
Registers.
TEMPERATURE REGISTER
The Temperature Register of the TMP100 or TMP101 is a 12bit read-only register that stores the output of the most recent
conversion. Two bytes must be read to obtain data and are
described in Table III and Table IV. The first 12 bits are used
to indicate temperature with all remaining bits equal to zero.
Data format for temperature is summarized in Table V.
Following power-up or reset, the Temperature Register will
read 0°C until the first conversion is complete.
D7 D6 D5 D4 D3 D2 D1 D0
T11 T10 T9 T8 T7 T6 T5 T4
TABLE III. Byte 1 of Temperature Register.
D7 D6 D5 D4 D3 D2 D1 D0
T3 T2 T1 T0 0 0 0 0
TABLE IV. Byte 2 of Temperature Register.
TMP100, 101
SBOS231C
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5
TEMPERATURE DIGITAL OUTPUT
(
°C) (BINARY) HEX
128 0111 1111 1111 7FF
127.9375 0111 1111 1111 7FF
100 0110 0100 0000 640
80 0101 0000 0000 500
75 0100 1011 0000 4B0
50 0011 0010 0000 320
25 0001 1001 0000 190
0.25 0000 0000 0100 004
0.0 0000 0000 0000 000
–0.25 1111 1111 1100 FFC
–25 1110 0111 0000 E70
–55 1100 1001 0000 C90
–128 1000 0000 0000 800
TABLE V. Temperature Data Format.
The user can obtain 9, 10, 11, or 12 bits of resolution by
addressing the Configuration Register and setting the resolution bits accordingly.
For 9, 10, or 11 bit resolution, the most
significant bits in the Temperature Register are used with the
unused LSBs set to zero.
CONFIGURATION REGISTER
The Configuration Register is an 8-bit read/write register
used to store bits that control the operational modes of the
temperature sensor. Read/write operations are performed
MSB first. The format of the Configuration Register for the
TMP100 and TMP101 is shown in Table VI, followed by a
breakdown of the register bits. The power-up/reset value of
the Configuration Register is all bits equal to 0. The OS/
ALERT bit will read as 1 after power-up/reset.
Byte D7 D6 D5 D4 D3 D2 D1 D0
1
OS/ALERT
R1 R0 F1 F0 POL TM SD
TABLE VI. Configuration Register Format.
SHUTDOWN MODE (SD)
The Shutdown Mode of the TMP100 and TMP101 allows the
user to save maximum power by shutting down all device
circuitry other than the serial interface, which reduces current
consumption to less than 1µA. For the TMP100 and TMP101,
Shutdown Mode is enabled when the SD bit is 1. The device will
shutdown once the current conversion is completed. For SD
equal to 0, the device will maintain continuous conversion.
THERMOSTAT MODE (TM)
The Thermostat Mode bit of the TMP101 indicates to the device
whether to operate in Comparator Mode (TM = 0) or Interrupt
Mode (TM = 1). For more information on comparator and
interrupt modes, see text “HIGH and LOW Limit Registers.”
POLARITY (POL)
The Polarity Bit of the TMP101 allows the user to adjust the
polarity of the ALERT pin output. If POL = 0, the ALERT pin
will be active LOW, as shown in Figure 4. For POL = 1 the
ALERT Pin will be active HIGH, and the state of the ALERT
Pin is inverted.
T
Read
T
HIGH
LOW
Measured
Temperature
TMP101 ALERT PIN
(Comparator Mode)
POL = 0
TMP101 ALERT PIN
(Interrupt Mode)
POL = 0
TMP101 ALERT PIN
(Comparator Mode)
POL = 1
TMP101 ALERT PIN
(Interrupt Mode)
POL = 1
Read Read
Time
FIGURE 4. Output Transfer Function Diagrams.
FAULT QUEUE (F1/F0)
A fault condition occurs when the measured temperature
exceeds the limits set in the T
HIGH
and T
Registers. The
LOW
Fault Queue is provided to prevent a false alert due to
environmental noise and requires consecutive fault measurements to trigger the alert function of the TMP101. Table
VII defines the number of measured faults that may be
programmed to trigger an alert condition.
F1 F0 CONSECUTIVE FAULTS
00 1
01 2
10 4
11 6
TABLE VII. Fault Settings of the TMP100 and TMP101.
CONVERTER RESOLUTION (R1/R0)
The Converter Resolution Bits control the resolution of the
internal Analog-to-Digital (A/D) converter. This allows the
user to maximize efficiency by programming for higher resolution or faster conversion time. Table VIII identifies the
Resolution Bits and relationship between resolution and conversion time.
R1 R0 RESOLUTION (typical)
0 0 9 Bits (0.5°C) 40ms
0 1 10 Bits (0.25°C) 80ms
1 0 11 Bits (0.125°C) 160ms
1 1 12 Bits (0.0625°C) 320ms
TABLE VIII. Resolution of the TMP100 and TMP101.
CONVERSION TIME
6
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TMP100, 101
SBOS231C
OS/ALERT (OS)
The TMP100 and TMP101 feature a One-Shot Temperature
Measurement Mode. When the device is in Shutdown Mode,
writing a 1 to the OS/ALERT bit will start a single temperature
conversion. The device will return to the shutdown state at
the completion of the single conversion. This is useful to
reduce power consumption in the TMP100 and TMP101
when continuous monitoring of temperature is not required.
Reading the OS/ALERT bit will provide information about the
Comparator Mode status. The state of the POL bit will invert the
polarity of data returned from the OS/ALERT bit. For POL = 0,
the OS/ALERT will read as 0 until the temperature equals or
exceeds T
for the programmed number of consecutive
HIGH
faults, causing the OS/ALERT bit to read as 1. The OS/ALERT
bit will continue to read as 1 until the temperature falls below
T
for the programmed number of consecutive faults when it
LOW
will again read as 0. The status of the TM bit does not affect the
status of the OS/ALERT bit.
HIGH AND LOW LIMIT REGISTERS
In Comparator Mode (TM = 0), the ALERT Pin of the TMP101
becomes active when the temperature equals or exceeds the
value in T
according to fault bits F1 and F0. The ALERT pin will remain
active until the temperature falls below the indicated T
value for the same number of faults.
In Interrupt Mode (TM = 1) the ALERT Pin becomes active
when the temperature equals or exceeds T
secutive number of fault conditions. The ALERT pin remains
active until a read operation of any register occurs or the
device successfully responds to the SMBus Alert Response
Address. The ALERT pin will also be cleared if the device is
placed in Shutdown Mode. Once the ALERT pin is cleared,
it will only become active again by the temperature falling
below T
ALERT pin will become active and remain active until cleared
by a read operation of any register or a successful response
to the SMBus Alert Response Address. Once the ALERT pin
is cleared, the above cycle will repeat with the ALERT pin
becoming active when the temperature equals or exceeds
T
. The ALERT pin can also be cleared by resetting the
HIGH
device with the General Call Reset command. This will also
clear the state of the internal registers in the device returning
the device to Comparator Mode (TM = 0).
Both operational modes are represented in the Figure 4. Tables
IX and X describe the format for the T
Power-up Reset values for T
and T
LOW
is the same as for the Temperature Register.
All 12 bits for the Temperature, T
used in the comparisons for the ALERT function for all converter resolutions. The three LSBs in T
affect the ALERT output even if the converter is configured for
9-bit resolution.
and generates a consecutive number of faults
HIGH
HIGH
. When the temperature falls below T
LOW
and T
HIGH
and T
HIGH
= 75°C. The format of the data for T
HIGH
LOW
, and T
HIGH
are: T
HIGH
LOW
and T
LOW
for a con-
, the
LOW
registers.
LOW
= 80°C
HIGH
and T
LOW
registers are
can
LOW
ByteD7D6D5D4D3D2D1D0
1 H11 H10 H9 H8 H7 H6 H5 H4
ByteD7D6D5D4D3D2D1D0
2H3H2H1H0 0 0 0 0
TABLE IX. Bytes 1 and 2 of T
ByteD7D6D5D4D3D2D1D0
1 L11 L10 L9 L8 L7 L6 L5 L4
ByteD7D6D5D4D3D2D1D0
2L3L2L1L00 0 0 0
TABLE X. Bytes 1 and 2 of T
HIGH
Register.
LOW
Register.
SERIAL INTERFACE
The TMP100 and TMP101 operate only as slave devices on
2
the I
C bus and SMBus. Connections to the bus are made via
the open-drain I/O lines SDA and SCL. The TMP100 and
TMP101 support the transmission protocol for fast (up to
400kHz) and high-speed (up to 3.4MHz) modes. All data
bytes are transmitted most significant bit first.
SERIAL BUS ADDRESS
To program the TMP100 and TMP101, the master must first
address slave devices via a slave address byte. The slave
address byte consists of seven address bits, and a direction
bit indicating the intent of executing a read or write operation.
The TMP100 features two address pins to allow up to eight
devices to be addressed on a single I
describes the pin logic levels used to properly connect up to eight
devices. ‘Float’ indicates the pin is left unconnected. The state of
pins ADD0 and ADD1 is sampled on the first I
cation and should be set prior to any activity on the interface.
ADD1 ADD0 SLAVE ADDRESS
0 0 1001000
0 Float 1001001
0 1 1001010
1 0 1001100
1 Float 1001101
1 1 1001110
Float 0 1001011
Float 1 1001111
TABLE XI. Address Pins and Slave Addresses for TMP100.
The TMP101 features one address pin and an ALERT pin,
allowing up to three devices to be connected per bus. Pin logic
levels are described in Table XII. The address pins of the
TMP100 and TMP101 are read after reset or in response to an
2
I
C address acquire request. Following reading, the state of
the address pins is latched to minimize power dissipation
associated with detection.
ADD0 SLAVE ADDRESS
0 1001000
Float 1001001
1 1001010
TABLE XII. Address Pins and Slave Address for TMP101.
2
C interface. Table XI
2
C bus communi-
TMP100, 101
SBOS231C
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7
BUS OVERVIEW
The device that initiates the transfer is called a “master,” and
the devices controlled by the master are “slaves.” The bus
must be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and generates
the START and STOP conditions.
To address a specific device, a START condition is initiated,
indicated by pulling the data-line (SDA) from a HIGH to LOW
logic level while SCL is HIGH. All slaves on the bus shift in the
slave address byte, with the last bit indicating whether a read
or write operation is intended. During the ninth clock pulse,
the slave being addressed responds to the master by generating an Acknowledge and pulling SDA LOW.
Data transfer is then initiated and sent over eight clock pulses
followed by an Acknowledge Bit. During data transfer SDA
must remain stable while SCL is HIGH, as any change in SDA
while SCL is HIGH will be interpreted as a control signal.
Once all data has been transferred, the master generates a
STOP condition indicated by pulling SDA from LOW to HIGH,
while SCL is HIGH.
WRITING/READING TO THE TMP100 AND TMP101
Accessing a particular register on the TMP100 and TMP101
is accomplished by writing the appropriate value to the
Pointer Register. The value for the Pointer Register is the
first byte transferred after the I
R/W
bit LOW. Every write operation to the TMP100 and
TMP101 requires a value for the Pointer Register. (Refer to
Figure 6.)
When reading from the TMP100 and TMP101, the last value
stored in the Pointer Register by a write operation is used to
determine which register is read by a read operation. To
change the register pointer for a read operation, a new value
must be written to the Pointer Register. This is accomplished
by issuing an I
2
C slave address byte with the R/W bit LOW,
followed by the Pointer Register Byte. No additional data is
required. The master can then generate a START condition
and send the I
2
C slave address byte with the R/W bit HIGH
to initiatnlthe read command. See Figure 7 for details of this
sequence. If repeated reads from the same register are
desired, it is not necessary to continually send the Pointer
Register bytes as the TMP100 and TMP101 will remember
the Pointer Register value until it is changed by the next write
operation.
2
C slave address byte with the
byte or bytes are written to the register addressed by the Pointer
register. The TMP100 and TMP101 will acknowledge reception of each data byte.
The master may terminate data
transfer by generating a START or STOP condition.
Slave Transmitter Mode:
The first byte is transmitted by the master and is the slave
address, with the R/W
bit HIGH. The slave acknowledges
reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of the
register indicated by the Pointer Register. The master acknowledges reception of the data byte. The next byte transmitted by the slave is the least significant byte. The master
acknowledges reception of the data byte. The master may
terminate data transfer by generating a Not-Acknowledge on
reception of any data byte, or generating a START or STOP
condition.
SMBus ALERT FUNCTION
The TMP101 supports the SMBus Alert function. When the
TMP101 is operating in Interrupt Mode (TM = 1), the ALERT
pin of the TMP101 may be connected as an SMBus Alert
signal. When a master senses that an ALERT condition is
present on the ALERT line, the master sends an SMBus Alert
command (00011001) on the bus. If the ALERT pin of the
TMP101 is active, the TMP101 will acknowledge the SMBus
Alert command and respond by returning its slave address
on the SDA line. The eighth bit (LSB) of the slave address
byte will indicate if the temperature exceeding T
below T
caused the ALERT condition. This bit will be
LOW
HIGH if the temperature is greater than or equal to T
This bit will be LOW if the temperature is less than T
Refer to Figure 8 for details of this sequence.
If multiple devices on the bus respond to the SMBus Alert
command, arbitration during the slave address portion of the
SMBus alert command will determine which device will clear
its ALERT status. If the TMP101 wins the arbitration, its
ALERT pin will become inactive at the completion of the
SMBus Alert command. If the TMP101 loses the arbitration,
its ALERT pin will remain active.
The TMP100 will also respond to the SMBus ALERT command if its TM bit is set to 1. Since it does not have an ALERT
pin, the master needs to periodically poll the device by
issuing an SMBus Alert command. If the TMP100 has generated an ALERT, it will acknowledge the SMBus Alert
command and return its slave address in the next byte.
HIGH
or falling
HIGH
LOW
.
.
SLAVE MODE OPERATIONS
The TMP100 and TMP101 can operate as slave receivers or
slave transmitters.
Slave Receiver Mode:
The first byte transmitted by the master is the slave address, with
the
R/W
bit LOW. The TMP100 or TMP101 then acknowledges
reception of a valid address. The next byte transmitted by the
master is the Pointer Register. The TMP100 or TMP101 then
acknowledges reception of the Pointer Register byte. The next
8
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GENERAL CALL
The TMP100 and TMP101 respond to the I2C General Call
address (0000000) if the eighth bit is 0. The device will
acknowledge the General Call address and respond to commands in the second byte. If the second byte is 00000100,
the TMP100 and TMP101 will latch the status of their
address pins, but will not reset. If the second byte is 00000110,
the TMP100 and TMP101 will latch the status of their
address pins and reset their internal registers.
TMP100, 101
SBOS231C
HIGH-SPEED MODE
In order for the I2C bus to operate at frequencies above
400kHz, the master device must issue an Hs-mode master
code (00001XXX) as the first byte after a START condition to
switch the bus to high-speed operation. The TMP100 and
TMP101 will not acknowledge this byte as required by the I
2
specification, but will switch their input filters on SDA and
SCL and their output filters on SDA to operate in Hs-mode,
allowing transfers at up to 3.4MHz. After the Hs-mode master
code has been issued, the master will transmit an I
2
C slave
address to initiate a data transfer operation. The bus will
continue to operate in Hs-mode until a STOP condition
occurs on the bus. Upon receiving the STOP condition, the
TMP100 and TMP101 will switch their input and output filters
back to fast-mode operation.
TIMING DIAGRAMS
The TMP100 and TMP101 are I2C and SMBus compatible.
Figures 5 to 8 describe the various operations on the TMP100
and TMP101. Bus definitions are given below. Parameters
for Figure 5 are defined in Table XIII.
Bus Idle: Both SDA and SCL lines remain HIGH.
Start Data Transfer: A change in the state of the SDA line,
from HIGH to LOW, while the SCL line is HIGH, defines a
START condition. Each data transfer is initiated with a
START condition.
Stop Data Transfer: A change in the state of the SDA line
C
from LOW to HIGH while the SCL line is HIGH defines a
STOP condition. Each data transfer is terminated with a
repeated START or STOP condition.
Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is
determined by the master device. The receiver acknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is
obliged to generate an Acknowledge bit. A device that
acknowledges must pull down the SDA line during the
Acknowledge clock pulse in such a way that the SDA line is
stable LOW during the HIGH period of the Acknowledge
clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data
transfer can be signaled by the master generating a NotAcknowledge on the last byte that has been transmitted by
the slave.
FAST MODE HIGH-SPEED MODE
PARAMETER MIN MAX MIN MAX UNITS
SCLK Operating Frequency f
Bus Free Time Between STOP and START Condition t
Hold Time After Repeated START Condition. t
After this period, the first clock is generated.
Repeated START Condition Setup Time t
STOP Condition Setup Time t
Data Hold Time t
Data Setup Time t
SCLK Clock LOW Period t
SCLK Clock HIGH Period t
Clock/Data Fall Time t
Clock/Data Rise Time t
(SCLK)
(BUF)
(HDSTA)
(SUSTA)
(SUSTO)
(HDDAT)
(SUDAT)
(LOW)
(HIGH)
600 160 ns
600 160 ns
600 160 ns
600 160 ns
00ns
100 10 ns
1300 160 ns
600 60 ns
F
R
0.4 3.4 MHz
300 160 ns
300 160 ns
TABLE XIII. Timing Diagram Definitions.
TMP100, 101
SBOS231C
www.ti.com
9
I2C TIMING DIAGRAMS
t
SCL
SDA
t
(BUF)
PS S P
FIGURE 5. I2C Timing Diagram.
(LOW)
t
(HDSTA)
(HDDAT)
t
F
t
(HIGH)
t
(SUSTA)
t
(SUDAT)
t
(HDSTA)
t
(SUSTO)
t
R
t
191
SCL
SDA
Start By
Master
SCL
(Continued)
SDA
(Continued)
0 0 1 A2 A1 A0 R/W 0 0 0 0 0 0 P1 P0
1
TMP100 or TMP101
Frame 1 I2C Slave Address Byte Frame 2 Pointer Register Byte
1
D7
D6 D5 D4 D3 D2 D1 D0
TMP100 or TMP101
Frame 3 Data Byte 1
FIGURE 6. I2C Timing Diagram for Write Word Format.
ACK By
ACK By
9
…
…
ACK By
TMP100 or TMP101
9
1
D7 D6 D5 D4 D3 D2 D1 D0
TMP100 or TMP101
Frame 4 Data Byte 2
9
ACK By
Stop By
Master
10
www.ti.com
TMP100, 101
SBOS231C
SCL
191
9
…
SDA
SCL
(Continued)
SDA
(Continued)
SCL
(Continued)
SDA
(Continued)
0 0 1 A2 A1 A0 R/W 0 0 0 0 0 0 P1 P0
1
Start By
Master
Frame 1 I2C Slave Address Byte Frame 2 Pointer Register Byte
191
1 0 0 1 A2 A1 A0 R/W
Start By
Master
Frame 3 I2C Slave Address Byte Frame 4 Data Byte 1 Read Register
1
D7 D6 D5 D4 D3 D2 D1 D0
From
TMP100 or TMP101
Frame 5 Data Byte 2 Read Register
ACK By
TMP100 or TMP101
ACK By
TMP100 or TMP101
9
ACK By
Master
Stop By
Master
TMP100 or TMP101
D7 D6 D5 D4 D3 D2 D1 D0
From
TMP100 or TMP101
…
ACK By
9
…
…
ACK By
Master
FIGURE 7. I2C Timing Diagram for Read Word Format.
ALERT
191
SCL
SDA
Start By
Master
0 0 0 1 1 0 0 R/W 1 0 0 1 A2 A1 A0
Frame 1 SMBus ALERT Response Address Byte Frame 2 Slave Address From TMP100
FIGURE 8. Timing Diagram for SMBus ALERT.
ACK By
TMP100 or TMP101
From
TMP100 or TMP101
Status
NACK By
9
Master
Stop By
Master
TMP100, 101
SBOS231C
www.ti.com
11
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY
TMP100NA/250 ACTIVE SOP DBV 6 250
TMP100NA/3K ACTIVE SOP DBV 6 3000
TMP101NA/250 ACTIVE SOP DBV 6 250
TMP101NA/3K ACTIVE SOP DBV 6 3000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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