Texas Instruments TLV62595 Datasheet
R1
200 k
R2
100 k
SW
GND FB
EN
PG
VIN
C2
3x10 µF
R3
100 k
C1
4.7 µF
V
IN
2.5 V to 5.5 V
V
PG
V
OUT
1.8 V
L1
0.47 µH
TLV62595
C3
120 pF
Load (A)
Efficiency (%)
50
55
60
65
70
75
80
85
90
95
100
100P 1m 10m 100m 1 4
D007
V
OUT
= 0.6V
V
OUT
= 1.2V
V
OUT
= 1.8V
V
OUT
= 2.5V
V
OUT
= 3.3V
TLV62595
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SLUSDR2 – DECEMBER 2020
SLUSDR2 – DECEMBER 2020
TLV62595
TLV62595, 2.5-V to 5.5-V Input, 4-A Step-Down Converter with 1% Output Accuracy in
1.5-mm × 1.5-mm QFN Package
1 Features
• Up to 97% efficiency
• Low R
power switches 26 mΩ / 25 mΩ
DS(ON)
• 2.5-V to 5.5-V input voltage range
• Adjustable output voltage from 0.6 V to 4 V
• 1% feedback voltage accuracy (full temperature
range)
• DCS-control topology
• Power save mode for light load efficiency
• 100% duty cycle for lowest dropout
• 10-μA operating quiescent current
• 2.2-MHz typical switching frequency
• Short circuit protection (HICCUP)
• Active output discharge
• Power good output
• Thermal shutdown protection
• Create a custom design using the TLV62595 with
the WEBENCH® Power Designer
2 Applications
• Solid state drive
• Portable electronics
• IP network camera
• Industrial PC
• Multifunction printers
3 Description
The TLV62595 is a high-frequency synchronous stepdown converter optimized for compact solution size
and high efficiency. The device integrates switches
capable of delivering an output current up to 4 A. At
medium to heavy loads, the converter operates in
pulse width modulation (PWM) mode with typical 2.2MHz switching frequency. At light load, the device
automatically enters Power Save Mode (PSM) to
maintain high efficiency over the entire load current
range with a quiescent current as low as 10-µA.
Based on the DCS Control topology, it provides a fast
transient response. The internal reference regulates
the output voltage down to 0.6 V with a high feedback
voltage accuracy of 1% over the junction temperature
range of –40°C to 125°C. The entire solution requires
a small 470-nH inductor, a single 4.7-μF input
capacitor and three 10-μF or single 47-μF output
capacitor.
The device is available in a 6-pin 1.5-mm x 1.5-mm
QFN package, offering a high power density solution.
Device Information
PART NUMBER PACKAGE
TLV62595 6-Pin VSON-HR 1.5 mm x 1.5 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(1)
BODY SIZE (NOM)
Typical Application Schematic
Copyright © 2020 Texas Instruments Incorporated
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Efficiency at VIN = 5 V
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Typical Characteristics................................................6
7 Detailed Description........................................................7
7.1 Overview.....................................................................7
7.2 Functional Block Diagram...........................................7
7.3 Feature Description.....................................................8
7.4 Device Functional Modes............................................9
4 Revision History
DATE REVISION NOTES
December 2020 * Initial release
8 Application and Implementation..................................10
8.1 Application Information............................................. 10
8.2 Typical Application....................................................10
9 Power Supply Recommendations................................18
10 Layout...........................................................................19
10.1 Layout Guidelines................................................... 19
10.2 Layout Example...................................................... 19
11 Device and Documentation Support..........................20
11.1 Device Support........................................................20
11.2 Documentation Support.......................................... 20
11.3 Receiving Notification of Documentation Updates..20
11.4 Support Resources................................................. 20
11.5 Trademarks............................................................. 20
11.6 Electrostatic Discharge Caution..............................21
11.7 Glossary..................................................................21
12 Mechanical, Packaging, and Orderable
Information.................................................................... 21
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SW
VIN
GND
PG
EN
FB
1
2
3
6
5
4
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5 Pin Configuration and Functions
Figure 5-1. 6-Pin VSON-HR DMQ Package (Bottom View)
Table 5-1. Pin Functions
PIN
NAME NO.
EN 1 I
PG 2 O
FB 3 I
GND 4 Ground pin
SW 5 PWR Switch pin of the power stage
VIN 6 PWR Input voltage pin
I/O DESCRIPTION
Device enable pin. To enable the device, this pin needs to be pulled high. Pulling this pin low
disables the device. Do not leave floating.
Power-good open-drain output pin. The pullup resistor can be connected to voltages up to
5.5 V. If unused, leave it floating.
Feedback pin. For the fixed output voltage versions, this pin must be connected to the
output.
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TLV62595
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6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Temperature Operating Junction, T
Temperature Storage, T
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
(2) All voltage values are with respect to the network ground terminal
(3) While switching
(2)
(2)
(2)
(2)
VIN, FB, EN, PG – 0.3 6 V
SW (DC) – 0.3 VIN + 0.3 V
SW (DC, in current limit) – 1 VIN + 0.3
SW (AC, less than 10ns)
STG
(3)
J
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC
(1)
V
(ESD)
Electrostatic discharge
JS-001
Charged device model (CDM), per JEDEC
specificationJESD22-C101
(1)
MIN MAX UNIT
– 2.5 10 V
–40 150 °C
–65 150 °C
VALUE UNIT
±2000
V
(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V
IN
V
OUT
I
OUT
V
PG
I
SINK_PG
T
J
Input voltage range 2.5 5.5 V
Output voltage range 0.6 4.0 V
Output curent range 0 4 A
Pull-up resistor voltage 5.5 V
Sink current at PG pin 1 mA
Operating junction temperature –40 125 °C
6.4 Thermal Information
TLV62595 TLV62595EVM-794
(1)
6 PINS 6 PINS
R
θJA
R
θJC(top)
R
θJB
Ψ
JT
Y
JB
THERMAL METRIC
Junction-to-ambient thermal resistance 129.5 71.4 °C/W
Junction-to-case (top) thermal resistance 103.9 n/a °C/W
Junction-to-board thermal resistance 33.1 n/a °C/W
Junction-to-top characterization parameter 3.8 3.9 °C/W
Junction-to-board characterization parameter 33.1 38.6 °C/W
UNITDMQ (JEDEC) DMQ (EVM)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
TJ = 25 °C and VIN = 5 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
I
Q
I
SD
V
UVLO
T
JSD
LOGIC INTERFACE EN
V
IH
V
IL
SOFT START, POWER GOOD
t
SS
V
PG
V
PG,OL
I
PG,LKG
t
PG,DLY
OUTPUT
V
FB
I
FB,LKG
I
DIS
POWER SWITCH
R
DS(on)
I
LIM
f
SW
Quiescent current EN = High, no load, device not switching 10 µA
Shutdown current EN = Low, TJ = -40℃ to 85℃ 0.05 µA
Undervoltage lock out threshold VIN falling 2.1 2.2 2.3 V
Undervoltage lock out hysteresis VIN rising 160 mV
Thermal shutdown threshold TJ rising 150 °C
Thermal shutdown hysteresis TJ falling 20 °C
High-level threshold voltage VIN = 2.5 V to 5.5 V 1.0 V
Low-level threshold voltage VIN = 2.5 V to 5.5 V 0.4 V
Soft start time Time from EN high to 95% of V
Power good lower threshold
Power good upper threshold
Low-level output voltage I
Input leakage current into PG pin VPG = 5.0 V 0.01 µA
Power good deglitch delay
Feedback regulation voltage
Feedback input leakage current for
adjustable output voltage
Output discharge current VSW = 0.4V; EN = LOW 400 mA
Load regulation I
High-side FET on-resistance 26 mΩ
Low-side FET on-resistance 25 mΩ
High-side FET switch current limit, DC 4.8 5.6 A
PWM switching frequency I
SLUSDR2 – DECEMBER 2020
TLV62595
nominal 1.75 ms
OUT
VPG rising, VFB referenced to VFB nominal 96 %
VPG falling, VFB referenced to VFB nominal 92 %
VPG rising, VFB referenced to VFB nominal 105 %
VPG falling, VFB referenced to VFB nominal 110 %
= 1 mA 0.4 V
sink
PG rising edge 100
PG falling edge 20
PWM mode, 2.5 V ≤ VIN ≤ 5.5 V, TJ = -40°C to
125°C
594 600 606 mV
VFB = 0.6 V 0.01 µA
= 0.5 A to 3 A, V
OUT
= 1 A, V
OUT
OUT
= 1.8 V 0.1 %/A
OUT
= 1.8 V 2.2 MHz
µs
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Input Voltage (V)
R
DS(on)
(mOhm)
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
D010
TJ = 0 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
Input Voltage (V)
R
DS(on)
(mOhm)
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0
10.0
20.0
30.0
40.0
50.0
60.0
70.0
D011
TJ = 0 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
Input Voltage (V)
6KXWGRZQ&XUUHQW$
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0
0.1
0.2
0.3
0.4
0.5
D000
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
Input Voltage (V)
4XLHVFHQW&XUUHQW$
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.0
2.0
4.0
6.0
8.0
D001
TJ = -40 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
Input Voltage (V)
Output Discharge Current (mA)
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0
50
100
150
200
250
300
350
400
450
500
D012
TJ = 0 °C
TJ = 25 °C
TJ = 85 °C
TJ = 125 °C
TLV62595
SLUSDR2 – DECEMBER 2020
6.6 Typical Characteristics
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Figure 6-1. High-Side FET On-Resistance
Figure 6-3. Shutdown Current
Figure 6-2. Low-Side FET On-Resistance
Figure 6-4. Quiescent Current
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Figure 6-5. Output Discharge Current
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UVLO
Control Logic
Soft-Start
Thermal
Shutdown
Gate Drive
Peak Current Detect
Zero Current Detect
HICCUP
Modulator
Ton
Ramp
EA
V
SW
V
SW
V
REF
V
FB
V
REF
V
IN
V
SW
V
FB
V
REF
Comp
V
IN
FB
EN
0.6 V
Or
Fixed Output Voltages
PG
VIN
SW
GND
Output
Discharge
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SLUSDR2 – DECEMBER 2020
7 Detailed Description
7.1 Overview
The TLV62595 are synchronous step-down converters based on the DCS-Control topology with an adaptive
constant on-time control and a stabilized switching frequency. It operates in PWM (pulse width modulation) mode
for medium to heavy loads and in PSM (power save mode) at light load conditions, keeping the output voltage
ripple small. The nominal switching frequency is about 2.2 MHz with a small and controlled variation over the
input voltage range. As the load current decreases, the converter enters PSM, reducing the switching frequency
to keep efficiency high over the entire load current range. Since combining both PWM and PSM within a single
building block, the transition between modes is seamless and without effect on the output voltage. The devices
offer both excellent dc voltage and fast load transient regulation, combined with a very low output voltage ripple.
7.2 Functional Block Diagram
TLV62595
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7
ns
V
V
OUT
ON
450×=
×
=
-
é ù
×
ê ú
ë û
2
2
OUT
PSM
IN OUT
IN
ON
OUT
I
f
V V
V
T
V L
IN,MIN OUT OUT,MAX DS(on) L
V V I (R + R )= + ´
TLV62595
SLUSDR2 – DECEMBER 2020
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7.3 Feature Description
7.3.1 Pulse Width Modulation (PWM) Operation
At load currents larger than half the inductor ripple current, the device operates in pulse width modulation in
continuous conduction mode (CCM). The PWM operation is based on an adaptive constant on-time control with
stabilized switching frequency. To achieve a stable switching frequency in a steady state condition, the on-time is
calculated as:
(1)
7.3.2 Power Save Mode (PSM) Operation
To maintain high efficiency at light loads, the device enters power save mode (PSM) at the boundary to
discontinuous conduction mode (DCM). This happens when the output current becomes smaller than half of the
ripple current of the inductor. The device operates now with a fixed on-time and the switching frequency further
decreases proportionally to the load current. It can be calculated as:
(2)
In PSM, the output voltage rises slightly above the nominal target, which can be minimized using larger output
capacitance. At duty cycles larger than 90%, the device may not enter PSM. The device maintains output
regulation in PWM mode.
7.3.3 Minimum Duty Cycle and 100% Mode Operation
There is no limitation for small duty cycles, since even at very low duty cycles, the switching frequency is
reduced as needed to always ensure a proper regulation.
If the output voltage level comes close to the input voltage, the device enters 100% mode. While the high-side
switch is constantly turned on, the low-side switch is switched off. The difference between VIN and VOUT is
determined by the voltage drop across the high-side FET and the dc resistance of the inductor. The minimum
VIN that is needed to maintain a specific VOUT value is estimated as:
(3)
where
• V
• I
• R
= Minimum input voltage to maintain an output voltage
IN,MIN
OUT,MAX
= Maximum output current
= High-side FET ON-resistance
DS(on)
• RL = Inductor ohmic resistance (DCR)
7.3.4 Soft Start
About 250 μs after EN goes high, the internal soft-start circuitry controls the output voltage during start-up. This
avoids excessive inrush current and ensures a controlled output voltage ramp. It also prevents unwanted voltage
drops from high-impedance power sources or batteries. The TLV62595 can start into a pre-biased output.
7.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
The switch current limit prevents the device from drawing excessive current in case of externally-caused
overcurrent or short circuit condition. Due to an internal propagation delay (typically 60 ns), the actual ac peak
current can exceed the static current limit during that time.
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TLV62595
If the current limit threshold is reached, the device delivers its maximum output current. Detecting this condition
for 32 switching cycles (about 13 μs), the device turns off the high-side MOSFET for about 100 μs which allows
the inductor current to decrease through the low-side MOSFET's body diode and then restart again with a soft
start cycle. As long as the overload condition is present, the device hiccups that way, limiting the output power.
7.3.6 Undervoltage Lockout
The undervoltage lockout (UVLO) function prevents misoperation of the device, if the input voltage drops below
the UVLO threshold. It is set to about 2.2 V with a hysteresis of typically 160 mV.
7.3.7 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 150°C
(typ.), the device goes in thermal shutdown with a hysteresis of typically 20°C. Once the TJ has decreased
enough, the device resumes normal operation.
7.4 Device Functional Modes
7.4.1 Enable, Disable and Output Discharge
The device starts operation, when Enable (EN) is set High. The input threshold levels are typically 0.9 V for
rising and 0.7 V for falling signals. Do not leave EN floating. Shutdown is forced if EN is pulled low with a
shutdown current of typically 50 nA. During shutdown, the internal power MOSFETs as well as the entire control
circuitry, are turned off and the output voltage is actively discharged through the SW pin by a current sink.
Therefore VIN must remain present for the discharge to function.
7.4.2 Power Good
The TLV62595 has a built-in power good (PG) function. The PG pin goes high impedance, when the output
voltage has reached its nominal value. Otherwise, including when disabled, in UVLO or in thermal shutdown, PG
is low (see Table 7-1). The PG function is formed with a window comparator, which has an upper and lower
voltage threshold. The PG pin is an open-drain output and is specified to sink up to 1 mA. The power good
output requires a pullup resistor connecting to any voltage rail less than 5.5 V.
The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters.
Leave the PG pin unconnected when not used. The PG rising edge has a 100-µs blanking time and the PG
falling edge has a deglitch delay of 20 µs.
Table 7-1. PG Pin Logic
DEVICE CONDITIONS
EN = High, VFB ≥ 0.576 V √
Enable
Shutdown EN = Low √
Thermal Shutdown TJ > T
UVLO 0.7 V < VIN < V
Power Supply Removal VIN < 0.7 V √
EN = High, VFB ≤ 0.552 V √
EN = High, VFB ≤ 0.63 V √
EN = High, VFB ≥ 0.66 V √
JSD
UVLO
HIGH Z LOW
LOGIC STATUS
√
√
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