TEXAS INSTRUMENTS TLV5637 Technical data
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1
2
3
4
8
7
6
5
DIN
SCLK
CS
OUTA
V
DD
OUTB
REF
AGND
D PACKAGE
(TOP VIEW)
SLAS224B – JUNE 1999 – REVISED JANUARY 2004
2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTER WITH
INTERNAL REFERENCE AND POWER DOWN
TLV5637
FEATURES
• Dual 10-Bit Voltage Output DAC
• Programmable Internal Reference
• Programmable Settling Time:
– 0.8 µs in Fast Mode
– 2.8 µs in Slow Mode
• Compatible With TMS320 and SPI™ Serial
Ports
• Differential Nonlinearity <0.1 LSB Typ
• Monotonic Over Temperature
APPLICATIONS
• Digital Servo Control Loops
• Digital Offset and Gain Adjustment
• Industrial Process Control
• Machine and Motion Control Devices
• Mass Storage Devices
DESCRIPTION
The TLV5637 is a dual 10-bit voltage output DAC
with a flexible 3-wire serial interface. The serial
interface allows glueless interface to TMS320 and
SPI™, QSPI™, and Microwire™ serial ports. It is
programmed with a 16-bit serial string containing 2
control and 10 data bits.
The resistor string output voltage is buffered by a x2
gain rail-to-rail output buffer. The buffer features a
Class AB output stage to improve stability and reduce
settling time. The programmable settling time of the
DAC allows the designer to optimize speed versus
power dissipation. With its on-chip programmable
precision voltage reference, the TLV5637 simplifies
overall system design.
Because of its ability to source up to 1 mA, the
reference can also be used as a system reference.
Implemented with a CMOS process, the device is
designed for single supply operation from 2.7 V to 5.5
V. It is available in an 8-pin SOIC package to reduce
board space in standard commercial and industrial
temperature ranges.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
AVAILABLE OPTIONS
T
A
0°C to 70°C TLV5637CD
40°C to 85°C TLV5637ID
PACKAGE
SOIC (D)
Copyright © 1999–2004, Texas Instruments Incorporated
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Serial
Interface
and
Control
10-Bit
DAC B
Latch
SCLK
DIN
CS
OUTA
Power-On
Reset
x2
10
2-Bit
Control
Latch
Power
and Speed
Control
2
Voltage
Bandgap
PGA With
Output Enable
10-Bit
DAC A
Latch
10
REF AGND V
DD
2
10 10
OUTB
x2
Buffer
10
TLV5637
SLAS224B – JUNE 1999 – REVISED JANUARY 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
Terminal Functions
TERMINAL
NAME NO.
AGND 5 P Ground
CS 3 I Chip select. Digital input active low, used to enable/disable inputs
DIN 1 I Digital serial data input
OUTA 4 I DAC A analog voltage output
OUTB 7 O DAC B analog voltage output
REF 6 I/O Analog reference voltage input/output
SCLK 2 I Digital serial clock input
V
DD
2
I/O/P DESCRIPTION
8 P Positive power supply
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TLV5637
SLAS224B – JUNE 1999 – REVISED JANUARY 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply voltage (V
Reference input voltage range - 0.3 V to V
Digital input voltage range - 0.3 V to V
Operating free-air temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under, , absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under, , recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
to AGND) 7 V
DD
TLV5637C 0°C to 70°C
A
TLV5637I -40°C to 85°C
stg
(1)
UNIT
+ 0.3 V
DD
+ 0.3 V
DD
-65°C to 150°C
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
V
= 5 V 4.5 5 5.5 V
Supply voltage, V
DD
Power on threshold voltage, POR 0.55 2 V
High-level digital input voltage, V
Low-level digital input voltage, V
Reference voltage, V
Reference voltage, V
Load resistance, R
Load capacitance, C
Clock frequency, f
to REF terminal V
ref
to REF terminal V
ref
L
L
CLK
Operating free-air temperature, T
IH
IL
A
(1) Due to the x2 output buffer, a reference input voltage ≥ (V
internal reference must be disabled, if an external reference is used.
DD
V
= 3 V 2.7 3 3.3 V
DD
DV
= 2.7 V 2
DD
DV
= 5.5 V 2.4
DD
DV
= 2.7 V 0.6
DD
DV
= 5.5 V 1
DD
= 5 V (see
DD
= 3 V (see
DD
(1)
) AGND 2.048 VDD-1.5 V
(1)
) AGND 1.024 VDD-1.5 V
2 kΩ
TLV5637C 0 70
TLV5637I 40 85
- 0.4 V)/2 causes clipping of the transfer function. The output buffer of the
DD
100 pF
20 MHz
V
V
°C
3
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TLV5637
SLAS224B – JUNE 1999 – REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
POWER SUPPLY
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
= 5 V, Int. ref.
DD
V
= 3 V, Int. ref.
V
V
DD
DD
DD
= 5 V, Ext. ref.
= 3 V, Ext. ref.
I
DD
Power supply current
No load, All inputs = AGND or
VDD, DAC latch = 0x800
Power-down supply current 0.01 10 µA
PSRR Power supply rejection ratio dB
Zero scale, See
Full scale, See
(1) Power supply rejection ratio at zero scale is measured by varying V
EZS(V
min))/V
(2) Power supply rejection ratio at full scale is measured by varying V
DD
EG(V
min))/V
DD
max]
DD
max]
DD
(1)
(2)
and is given by: PSRR = 20 log [(E
DD
and is given by: PSRR = 20 log [(E
DD
STATIC DAC SPECIFICATIONS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 10 bits
INL Integral nonlinearity, end point adjusted See
DNL Differential nonlinearity See
E
Zero-scale error (offset error at zero scale) See
ZS
EZSTC Zero-scale-error temperature coefficient See
E
EGT
Gain error See
G
Gain error temperature coefficient See
C
(1)
(2)
(3)
(4)
(5)
(6)
OUTPUT SPECIFICATIONS
V
Output voltage RL= 10 kΩ 0 V
O
Output load regulation accuracy VO= 4.096 V, 2.048 V, RL= 2 kΩ ±0.25
(1) The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from
the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 32 to 4095.
(2) The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB
amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant)
as a change in the digital input code.
(3) Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
(4) Zero-scale-error temperature coefficient is given by: E
(5) Gain error is the deviation from the ideal output (2V
(6) Gain temperature coefficient is given by: EGTC = [EG(T
TC = [E
ZS
- 1 LSB) with an output load of 10 k excluding the effects of the zero-error.
ref
) - EG(T
max
(T
) - E
(T
ZS
max
)]/V
× 10
min
ref
)]/V
ZS
min
ref
6
/(T
- T
max
Fast 4.2 7 mA
Slow 2 3.6 mA
Fast 3.7 6.3 mA
Slow 1.7 3.0 mA
Fast 3.8 6.3 mA
Slow 1.7 3.0 mA
Fast 3.4 5.7 mA
Slow 1.4 2.6 mA
(V
ZS
G(VDD
6
× 10
/(T
- T
max
).
min
).
min
65
65
max) -
DD
max) -
±0.4 ±1 LSB
±0.1 ±0.5 LSB
±24 mV
10 ppm/°C
±0.6
10 ppm/°C
VDD-
0.4
% full
scale V
% full
scale V
4
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TLV5637
SLAS224B – JUNE 1999 – REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS (CONTINUED)
over recommended operating conditions (unless otherwise noted)
REFERENCE PIN CONFIGURED AS OUTPUT (REF)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
ref(OUTL)
V
ref(OUTH)
I
ref(source)
I
ref(sink)
PSRR Power supply rejection ratio 65 dB
REFERENCE PIN CONFIGURED AS INPUT (REF)
V
Input voltage 0 V
I
R
Input resistance 10 MΩ
I
C
Input capacitance 5 pF
I
Reference input bandwidth REF = 0.2 Vpp+ 1.024 V dc
Reference feedthrough REF = 1 Vppat 1 kHz + 1.024 V dc, See
(1) Reference feedthrough is measured at the DAC output with an input code = 0x000.
DIGITAL INPUTS
I
IH
I
IL
C
i
Low reference voltage 1.003 1.024 1.045 V
High reference voltage V
> 4.75 V 2.027 2.048 2.069 V
DD
Output source current 1 mA
Output sink current 1 mA
Load capacitance 100 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DD-1.5
Fast 1.3 MHz
Slow 525 kHz
(1)
80 dB
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-level digital input current VI= V
DD
Low-level digital input current VI= 0 V 1 µA
Input capacitance 8 pF
V
1 µA
5
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t
wL
SCLK
CS
DIN
D15 D14 D13 D12 D1 D0 XX
1
X
2 3 4 5 15 16
X
t
wH
t
su(D)th(D)
t
su(CS-CK)
t
su(C16-CS)
TLV5637
SLAS224B – JUNE 1999 – REVISED JANUARY 2004
ELECTRICAL CHARACTAERISTICS (CONTINUED)
over recommended operating conditions (unless otherwise noted)
ANALOG OUTPUT DYNAMIC PERFORMANCE
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
t
Output settling time, full scale RL= 10 kΩ, CL= 100 pF, See
s(FS)
Output settling time, code to code RL= 10 kΩ, CL= 100 pF, See
s(CC)
SR Slew rate RL= 10 kΩ, CL= 100 pF, See
Glitch energy DIN = 0 to 1, f
= 100 kHz, CS = V
CLK
(1)
(2)
(3)
SNR Signal-to-noise ratio 53 56
S/(N+
D)
Signal-to-noise + distortion 50 54
fs= 480 kSPS, f
= 1 kHz, RL= 10 kΩ, CL= 100 pF dB
out
THD Total harmonic distortion 61 50
SFDR Spurious free dynamic range 51 62
(1) Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of
0x020 to 0xFDF or 0xFDF to 0x020 respectively. Not tested, assured by design.
(2) Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of
one count. Not tested, assured by design.
(3) Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
Fast 0.8 2.4
Slow 2.8 5.5
Fast 0.4 1.2
Slow 0.8 1.6
Fast 12
Slow 1.8
DD
5 nV-S
µs
µs
V/µs
DIGITAL INPUT TIMING REQUIREMENTS
t
su(CS-CK)
t
su(C16-CS)
t
wH
t
wL
t
su(D)
t
h(D)
MIN NOM MAX UNIT
Setup time, CS low before first negative SCLK edge 10 ns
Setup time, 16
th
negative SCLK edge (when D0 is sampled) before CS rising edge 10 ns
SCLK pulse width high 25 ns
SCLK pulse width low 25 ns
Setup time, data ready before SCLK falling edge 10 ns
Hold time, data held valid after SCLK falling edge 5 ns
PARAMETER MEASUREMENT INFORMATION
6
Figure 1. Timing Diagram
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