Datasheet TLV5623IDR, TLV5623IDGKR, TLV5623ID, TLV5623IDGK, TLV5623CDR Datasheet (Texas Instruments)

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

8-Bit Voltage Output DAC

D

Programmable Settling Time vs Power
Consumption

3 µs in Fast Mode
9 µs in Slow Mode

D

Ultra Low Power Consumption:

900 µW Typ in Slow Mode at 3 V

2.1 mW Typ in Fast Mode at 3 V

D

Differential Nonlinearity...<0.2 LSB Typ

D

Compatible With TMS320 and SPI Serial
Ports

D

Power-Down Mode

D

Buffered High-Impedance Reference Input

D

Monotonic Over Temperature

D

Available in MSOP Package

applications

D

Digital Servo Control Loops

D

Digital Offset and Gain Adjustment

D

Industrial Process Control

D

Machine and Motion Control Devices

D

Mass Storage Devices

description

The TLV5623 is a 8-bit voltage output digital-to­analog converter (DAC) with a flexible 4-wire
serial interface. The 4-wire serial interface allows
glueless interface to TMS320, SPI, QSPI, and
Microwire serial ports. The TLV5623 is pro­grammed with a 16-bit serial string containing 4
control and 12 data bits. Developed for a wide
range of supply voltages, the TLV5623 can
operate from 2.7 V to 5.5 V.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer . The buffer features a Class AB
output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow
the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within
the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need
for a low source impedance drive to the terminal.

Implemented with a CMOS process, the TL V5623 is designed for single supply operation from 2.7 V to 5.5 V.
The device is available in an 8-terminal SOIC package. The TL V5623C is characterized for operation from 0°C
to 70°C. The TLV5623I is characterized for operation from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

T

A

SMALL OUTLINE

†

(D)

MSOP
(DGK)

0°C to 70°C TLV5623CD TLV5623CDGK

–40°C to 85°C TLV5623ID TLV5623IDGK

†

Available in tape and reel as the TL V5623CDR and the TLV5623IDR

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4

8
7
6
5

DIN

SCLK

CS

FS

V

DD

OUT
REFIN
AGND

D OR DGK PACKAGE

(TOP VIEW)

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Serial Input

Register

16 Cycle

Timer

REFIN

CS

SCLK

FS

OUT

_
+

Power-On

Reset

DIN

8-Bit
Data

Latch

Speed/Power-Down

Logic

2

8

Update

6

1

2
3
4

7

x2

10

8

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AGND 5 Analog ground
CS 3 I Chip select. Digital input used to enable and disable inputs, active low.
DIN 1 I Serial digital data input
FS 4 I Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface.
OUT 7 O DAC analog output
REFIN 6 I Reference analog input voltage
SCLK 2 I Serial digital clock input
V

DD

8 Positive power supply

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (V

DD

to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range – 0.3 V to V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

: TLV5623C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5623I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

pp

VDD = 5 V 4.5 5 5.5 V

Suppl

y v

oltage, V

DD

VDD = 3 V 2.7 3 3.3 V

High-level digital input voltage, V

IH

VDD = 2.7 V to 5.5 V 2 V

Low-level digital input voltage, V

IL

VDD = 2.7 V to 5.5 V 0.8 V

Reference voltage, V

ref

to REFIN terminal VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 V

Reference voltage, V

ref

to REFIN terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V

Load resistance, R

L

2 10 kΩ

Load capacitance, C

L

100 pF

Clock frequency, f

CLK

20 MHz

p

p

TLV5623C 0 70 °C

Operating free-air temperature, T

A

TLV5623I –40 85 °C

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ V

DD/2

causes clipping of the transfer function.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

UNIT

VDD = 5 V, VREF = 2.048 V,
No load,

Fast 0.9 1.35 mA

pp

All inputs = AGND or VDD,
DAC latch = 0x800

Slow 0.4 0.6 mA

IDDPower supply current

VDD = 3 V, VREF = 1.024 V
No load,

Fast 0.7 1.1 mA

All inputs = AGND or VDD,
DAC latch = 0x800

Slow 0.3 0.45 mA

Power down supply current (see Figure 12) 1 µA

pp

Zero scale See Note 2 –68

PSRR

Power supply rejection ratio

Full scale See Note 3 –68

dB

Power on threshold voltage, POR 2 V

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax]

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)

static DAC specifications RL = 10 kΩ, CL = 100 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 8 bits
INL Integral nonlinearity See Note 4 ± 0.3 ±0.5 LSB
DNL Dif ferential nonlinearity See Note 5 ± 0.07 ± 0.2 LSB
E

ZS

Zero-scale error (offset error at zero scale) See Note 6 ±10 mV
EZS

TC

Zero-scale-error temperature coefficient See Note 7 10 ppm/°C

E

G

Gain error See Note 8 ±0.6

% of

FS

voltage

Gain-error temperature coefficient See Note 9 10 ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error , is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale-error temperature coef ficient is given by: EZSTC = [EZS(T

max

) – EZS(T

min

)]/V

ref

× 106/(T

max

– T

min

).

8. Gain error is the deviation from the ideal output (2V

ref

– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error .

9. Gain temperature coefficient is given by: EGTC = [EG(T

max

) – EG (T

min

)]/V

ref

× 106/(T

max

– T

min

).

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Voltage output range RL = 10 kΩ 0 VDD–0.1 V
Output load regulation accuracy RL = 2 kΩ, vs 10 kΩ ±0.1 ±0.25

% of FS

voltage

reference input (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

I

Input voltage range 0 VDD–1.5 V

R

I

Input resistance 10 MΩ

C

I

Input capacitance 5 pF

p

Slow 525 kHz

Reference input bandwidth

REFIN

= 0.2

V

pp

+

1.024 V dc

Fast 1.3 MHz

Reference feed through

REFIN = 1 Vpp at 1 kHz + 1.024 V dc
(see Note 10)

–75 dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

IH

High-level digital input current VI = V

DD

±1 µA

I

IL

Low-level digital input current VI = 0 V ±1 µA

C

I

Input capacitance 3 pF

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics over recommended operating free-air temperature range (unless
otherwise noted)

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

R

= 10 kΩ,

CL = 100 pF,

Fast 3 5.5

t

s(FS)

Output settling time, full scale

L

,

See Note 11

Slow 9 20

µ

s

p

R

= 10 kΩ,

CL = 100 pF,

Fast 1 µs

t

s(CC)

Output settling time, code to code

L

,

See Note 12

Slow 2 µs

R

= 10 kΩ, C

= 100 pF,

Fast 3.6

SR

Slew rate

L

,

See Note 13

L

,

Slow 0.9

V/µs

Glitch energy Code transition from 0x7F0 to 0x800 10 nV–s
S/N Signal to noise 57 dB
S/(N+D) Signal to noise + distortion

fs = 400 KSPS fout = 1.1 kHz,

p

49 dB

THD Total harmonic distortion

R

L

=

10 kΩ,C

L

=

100 pF

,

BW = 2

0

kHz

–50 dB

Spurious free dynamic range

BW = 20 kHz

60 dB

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFF0 or 0xFF0 to 0x020. Not tested, ensured by design.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, ensured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

digital input timing requirements

MIN NOM MAX UNIT

t

su(CS–FS)

Setup time, CS low before FS↓ 10 ns

t

su(FS–CK)

Setup time, FS low before first negative SCLK edge 8 ns

t

su(C16–FS)

Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising
edge of FS

10 ns

t

su(C16–CS)

Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS

rising edge.

10 ns

t

wH

Pulse duration, SCLK high 25 ns

t

wL

Pulse duration, SCLK low 25 ns

t

su(D)

Setup time, data ready before SCLK falling edge 8 ns

t

h(D)

Hold time, data held valid after SCLK falling edge 5 ns

t

wH(FS)

Pulse duration, FS high 20 ns

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

123451516

D15 D14 D13 D12 D1 D0

t

su(FS-CK)

t

su(CS-FS)

t

wH(FS)

t

h(D)

t

su(D)

t

wH

t

wL

t

su(C16-CS)

t

su(C16-FS)

SCLK

DIN

CS

FS

Figure 1. Timing Diagram

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 2

1.998

1.996

1.994

1.990
0 0.01 0.02 0.05 0.1 0.2 0.5

– Output Voltage – V

2

2.002

Load Current – mA

OUTPUT VOLTAGE

vs

LOAD CURRENT

2.004

12

3 V Slow Mode, SOURCE

3 V Fast Mode, SOURCE

1.992

V

O

VDD = 3 V,
V

ref

= 1 V,

Full Scale

Figure 3

3.995

3.99

3.985

3.975
0 0.02 0.04 0.1 0.2 0.4 1

4

4.005

OUTPUT VOLTAGE

vs

LOAD CURRENT

4.01

24

3.98

– Output Voltage – V

Load Current – mA

5 V Slow Mode, SOURCE

5 V Fast Mode, SOURCE

V

O

VDD = 5 V,
V

ref

= 2 V,

Full Scale

Figure 4

0.1

0.08

0.04

0

0 0.01 0.02 0.05 0.1 0.2 0.5

0.16

0.18

OUTPUT VOLTAGE

vs

LOAD CURRENT

0.2

12

0.14

0.12

0.06

0.02

– Output Voltage – V

Load Current – mA

3 V Slow Mode, SINK

3 V Fast Mode, SINK

V

O

VDD = 3 V,
V

ref

= 1 V,

Zero Code

Figure 5

0.2

0.15

0.1

0

0 0.02 0.04 0.1 0.2 0.4 1

0.25

0.3

OUTPUT VOLTAGE

vs

LOAD CURRENT

0.35

24

0.05

– Output Voltage – V

Load Current – mA

5 V Slow Mode, SINK

5 V Fast Mode, SINK

V

O

VDD = 5 V,
V

ref

= 2 V,

Zero Code

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 6

0.6

0.4

0.2
–55 –40 –25 0 25 40 70

– Supply Current – mA

0.8

SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

1

85 125

I

DD

VDD = 3 V,
V

ref

= 1 V,

Full Scale

TA – Free-Air Temperature – C°

Fast Mode

Slow Mode

Figure 7

SUPPLY CURRENT

vs

FREE-AIR TEMPERATURE

0.6

0.4

0.2
–55 –40 –25 0 25 40 70

– Supply Current – mA

0.8

1

85 125

I

DD

VDD = 5 V,
V

ref

= 2 V,

Full Scale

TA – Free-Air Temperature – C°

Fast Mode

Slow Mode

Figure 8

––40

–50

–70

–80

0 5 10 20

THD – Total Harmonic Distortion – dB

–30

–10

f – Frequency – kHz

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

0

30 50 100

–20

–60

V

ref

= 1 V dc + 1 V p/p Sinewave,

Output Full Scale

Fast Mode

Figure 9

––40

–50

–70

–80

0 5 10 20

THD – Total Harmonic Distortion – dB

–30

–10

f – Frequency – kHz

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

0

30 50 100

–20

–60

V

ref

= 1 V dc + 1 V p/p Sinewave,

Output Full Scale

Slow Mode

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 10

––40

–50

–70

–80

0 5 10 20

THD – Total Harmonic Distortion And Noise – dB

–30

–10

f – Frequency – kHz

TOTAL HARMONIC DISTORTION AND NOISE

vs

FREQUENCY

0

30 50 100

–20

–60

V

ref

= 1 V dc + 1 V p/p Sinewave,

Output Full Scale

Fast Mode

Figure 11

––40

–50

–70

–80

0 5 10 20

–30

–10

f – Frequency – kHz

TOTAL HARMONIC DISTORTION AND NOISE

vs

FREQUENCY

0

30 50 100

–20

–60

V

ref

= 1 V dc + 1 V p/p Sinewave,

Output Full Scale

THD – Total Harmonic Distortion And Noise – dB

Slow Mode

Figure 12

400

300

100

0

0 100 200 300 400 500 600

– Supply Current –

600

800

T – Time – ns

SUPPLY CURRENT

vs

TIME (WHEN ENTERING POWER-DOWN MODE)

900

700 800 900 1000

700

500

200

I

DD

µ A

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 13

–0.10

–0.08

–0.06

–0.04

–0.02

0.00

0.02

0.04

0.06

0.08

0.10

0 255

DNL – Differential Nonlinearity – LSB

Digital Output Code

DIFFERENTIAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

12864 192

Figure 14

–0.5

–0.4

–0.3

–0.2

–0.1

–0.0

0.1

0.2

0.3

0.4

0.5

0 255

INL – Integral Nonlinearity – LSB

Digital Output Code

INTEGRAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

64 128 192

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

general function

The TL V5623 is an 8-bit single supply DAC based on a resistor string architecture. The device consists of a serial
interface, speed and power-down control logic, a reference input buffer , a resistor string, and a rail-to-rail output
buffer .

The output voltage (full scale determined by external reference) is given by:

2REF

CODE

0x1000

[V]

Where REF is the reference voltage and CODE is the digital input value within the range of 0x000 to 0xFF0.
Bits 3 to 0 must be set to zero. A power-on reset initially resets the internal latches to a defined state (all bits
zero).

serial interface

The device has to be enabled with CS set to low. A falling edge of FS starts shifting the data bit-per-bit (starting
with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or FS
rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new
level.

The serial interface of the TLV5623 can be used in two basic modes:

D

Four wire (with chip select)

D

Three wire (without chip select)

Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of
the data source (DSP or microcontroller). The interface is compatible with the TMS320 family . Figure 15 shows
an example with two TLV5623s connected directly to a TMS320 DSP.

TMS320

DSP

XF0
XF1

FSX

DX

CLKX

TLV5623

CS

FS DIN SCLK

TLV5623

CS

FS DIN SCLK

Figure 15. TMS320 Interface

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

serial interface (continued)

If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows
an example of how to connect the TLV5623 to a TMS320, SPI, or Microwire port using only three pins.

TMS320

DSP

FSX

DX

CLKX

TLV5623

FS
DIN
SCLK

CS

SPI

SS

MOSI

SCLK

TLV5623

FS
DIN
SCLK

CS

Microwire

I/O

SO

SK

TLV5623

FS
DIN
SCLK

CS

Figure 16. Three-Wire Interface

Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must
be performed to program the TLV5623. After the write operation(s), the DAC output is updated automatically
on the sixteenth positive clock edge.

serial clock frequency and update rate

The maximum serial clock frequency is given by:

f

SCLKmax

+

1

t

wH(min)

)

t

wL(min)

+

20 MHz

The maximum update rate is:

f

UPDATEmax

+

1

16

ǒ

t

wH(min)

)

t

wL(min)

Ǔ

+

1.25 MHz

The maximum update rate is a theoretical value for the serial interface, since the settling time of the TL V5623
has to be considered also.

data format

The 16-bit data word for the TLV5623 consists of two parts:

D

Control bits (D15 . . . D12)

D

New DAC value (D11 ...D0)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X SPD PWR X New DAC value (8 bits) 0 0 0 0

X: don’t care
SPD: Speed control bit. 1 → fast mode 0 → slow mode
PWR: Power control bit. 1 → power down 0 → normal operation

In power-down mode, all amplifiers within the TLV5623 are disabled.

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

TLV5623 interfaced to TMS320C203 DSP

hardware interfacing

Figure 17 shows an example how to connect the TL V5623 to a TMS320C203 DSP. The serial interface of the
TLV5623 is ideally suited to this configuration, using a maximum of four wires to make the necessary
connections. In applications where only one synchronous serial peripheral is used, the interface can be
simplified even further by pulling CS

low all the time as shown in the figure.

FS
DIN
SCLK

OUT

REFIN

CS

AGND

V

DD

REF

FS

DX

CLKX

TMS320C203 TLV5623

R

LOAD

Figure 17. TLV5623 to DSP Interface

TLV5623 interfaced to MCS51 microcontroller

hardware interfacing

Figure 18 shows an example of how to connect the TL V5623 to an MCS51 compatible microcontroller. The
serial DAC input data and external control signals are sent via I/O port 3 of the controller. The serial data is sent
on the RxD line, with the serial clock output on the TxD line. P3.4 and P3.5 are configured as outputs to provide
the chip select and frame sync signals for the TLV5623.

SDIN
SCLK
CS

OUT

REFIN

AGND

REF

RxD

TxD

P3.4

MCS51



Controller TLV5623

FS

P3.5

V

DD

R

LOAD

Figure 18. TL V5623 to MCS51 Controller Interface

MCS is a registered trademark of Intel Corporation

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

linearity, offset, and gain error using single ended supplies

When an amplifier is operated from a single supply , the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage
may not change with the first code, depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 19.

DAC Code

Output

Voltage

0 V

Negative

Offset

Figure 19. Effect of Negative Offset (single supply)

This offset error , not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.

For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way . However , single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage.

power-supply bypassing and ground management

Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground
currents are well managed and there are negligible voltage drops across the ground plane.

A 0.1-µF ceramic-capacitor bypass should be connected between V

DD

and AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the
digital power supply.

Figure 20 shows the ground plane layout and bypassing technique.

0.1 µF

Analog Ground Plane

1
2
3
4

8
7
6
5

Figure 20. Power-Supply Bypassing

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

definitions of specifications and terminology

integral nonlinearity (INL)

The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale
errors.

differential nonlinearity (DNL)

The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.

zero-scale error (E

ZS

)

Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.

gain error (E

G

)

Gain error is the error in slope of the DAC transfer function.

signal-to-noise ratio + distortion (S/N+D)

S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.

spurious free dynamic range (SFDR)

SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious
signal within a specified bandwidth. The value for SFDR is expressed in decibels.

total harmonic distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal
and is expressed in decibels.

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047/D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394

(10,00)

0.386

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN

SLAS231 – JUNE 1999

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE

0,69

0,41

0,25

0,15 NOM

Gage Plane

4073329/B 04/98

4,98

0,25

5

3,05

4,78

2,95

8

4

3,05
2,95

1

0,38

1,07 MAX

Seating Plane

0,65

M

0,25

0°–6°

0,10

0,15
0,05

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated