Texas Instruments TLV5619QDWR, TLV5619QDW, TLV5619IPWR, TLV5619IPW, TLV5619IDWR Datasheet

TLV5619

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN

SLAS172C – DECEMBER 1997 – REVISED APRIL 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Single Supply 2.7-V to 5.5-V Operation

D

±0.4 LSB Differential Nonlinearity (DNL),
±1.5 LSB Integral Nonlinearity (INL)

D

12-Bit Parallel Interface

D

Compatible With TMS320 DSP

D

Internal Power On Reset

D

Settling Time 1 µs Typ

D

Low Power Consumption:
– 8 mW for 5-V Supply
– 4.3 mW for 3-V Supply

D

Reference Input Buffers

D

Voltage Output

D

Monotonic Over Temperature

D

Asynchronous Update

applications

D

Battery Powered Test Instruments

D

Digital Offset and Gain Adjustment

D

Battery Operated/Remote Industrial
Controls

D

Machine and Motion Control Devices

D

Cordless and Wireless Telephones

D

Speech Synthesis

D

Communication Modulators

D

Arbitrary Waveform Generation

description

The TL V5619 is a 12-bit voltage output DAC with
a microprocessor and TMS320 compatible
parallel interface. The 12 data bits are double
buffered so that the output can be updated
asynchronously using the LDAC

pin. During
normal operation, the device dissipates 8 mW at
a 5-V supply and 4.3 mW at a 3-V supply. The
power consumption can be lowered to 50 nW by
setting the DAC to power-down mode.

The output voltage is buffered by a ×2 gain
rail-to-rail amplifier, which features a Class A
output stage to improve stability and reduce
settling time.

AVAILABLE OPTIONS

PACKAGE

T

A

SMALL OUTLINE

(DW)

TSSOP

(PW)

0°C to 70°C TLV5619CDW TLV5619CPW

–40°C to 85°C TLV5619IDW TLV5619IPW

–40°C to 125°C TLV5619QDW —

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

D2
D3
D4
D5
D6
D7
D8

D9
D10
D11

D1
D0
CS
WE
LDAC
PD
GND
OUT
REFIN
V

DD

DW OR PW PACKAGE

(TOP VIEW)

TLV5619

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN

SLAS172C – DECEMBER 1997 – REVISED APRIL 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

_

+

REFIN

12

19
20

1
2

3
4
5
6

18
17

D0
D1
D2
D3
D4
D5
D6
D7

CS

WE

Power-On

Reset

12

12

x2

LDAC

16

13

OUT

12-Bit

Input

Register

Select

and

Control

Logic

12-Bit

DAC

Latch

7

D8

8

D9

9

D10

10

D11

PD

15

Resistor

String DAC

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

CS 18 I Chip select
D0 (LSB)–D11 (MSB)

19, 20,

1 – 10

I Parallel data input

GND 14 Ground
LDAC 16 I Load DAC
OUT 13 O Analog output

PD 15 I When low, disables all buffer amplifier voltages to reduce supply current
REFIN 12 I Voltage reference input
V

DD

11 Positive power supply

WE 17 I Write enable

TLV5619

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN

SLAS172C – DECEMBER 1997 – REVISED APRIL 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (VDD to GND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range to GND – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLV5619C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5619I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5619Q –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, VDD (5-V Supply) 4.5 5 5.5 V
Supply voltage, VDD (3-V Supply) 2.7 3 3.3 V
High-level digital input voltage, V

IH

V

DD

2 V

Low-level digital input voltage, V

IL

V

DD

0.8 V

Reference voltage, V

ref

to REFIN terminal (5-V Supply) 0 2.048 VDD–1.5 V

Reference voltage, V

ref

to REFIN terminal (3-V Supply) 0 1.024 VDD–1.5 V

Load resistance, R

L

2 10 kΩ

Load capacitance, C

L

100 pF

TLV5619C 0 70

Operating free-air temperature, T

A

TLV5619I –40 85

°C

TLV5619Q –40 125

NOTES: 1. The recommended operating levels for both VIH and VIL apply to all valid values of VDD.

2. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.

TLV5619

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN

SLAS172C – DECEMBER 1997 – REVISED APRIL 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution

V

ref(REFIN)

= 2.048 V at 5 V ,

1.024 V at 3 V

12 bits

Integral nonlinearity (INL)

V

ref(REFIN)

= 2.048 V at 5 V ,

1.024 V at 3 V ,

See Note 3 ±1.5 ±4 LSB

Differential nonlinearity (DNL)

V

ref(REFIN)

= 2.048 V at 5 V ,

1.024 V at 3 V ,

See Note 4 ± 0.4 ± 1 LSB

E

ZS

Zero-scale error (offset error at zero scale)

V

ref(REFIN)

= 2.048 V at 5 V ,

1.024 V at 3 V ,

See Note 5 ±3 ±20 mV

Zero-scale-error temperature coefficient

V

ref(REFIN)

= 2.048 V at 5 V ,

1.024 V at 3 V ,

See Note 6 3 ppm/°C

E

G

Gain error

V

ref(REFIN)

= 2.048 V at 5 V ,

1.024 V at 3 V ,

See Note 7 ±0.25 ±0.5

% of FS

voltage

Gain error temperature coefficient

V

ref(REFIN)

= 2.048 V at 5 V ,

1.024 V at 3 V ,

See Note 8 1 ppm/°C

pp

Zero scale

65

PSRR

Power-supply rejection ratio

Gain

See Notes 9 and 10

65

dB

NOTES: 3. The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

4. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.

5. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

6. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(T

max

) – EZS(T

min

)]/V

ref

× 106/(T

max

– T

min

).

7. Gain error is the deviation from the ideal output (2 × V

ref

– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.

8. Gain temperature coefficient is given by: EGTC = [EG(T

max

) – EG (T

min

)]/V

ref

× 106/(T

max

– T

min

).

9. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage.

10. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero scale change.

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Voltage output range RL = 10 kΩ 0 VDD–0.4 V
Output load regulation accuracy

V

O(OUT)

= 4.096 V,

2.048 V

RL = 2 kΩ 0.1 0.29

% of FS

voltage

p

V

O(OUT

)

= 0 V,

5-V Supply 100

I

OSC(

source

)

Out ut short circuit source current

O(OUT)

Full scale code

3-V Supply 25

mA

p

5-V Supply 10

I

O(

source

)

Out ut source current

R

L

=

100 Ω

3-V Supply 10

mA

TLV5619

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN

SLAS172C – DECEMBER 1997 – REVISED APRIL 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)

reference input (REFIN)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

ref

Reference input voltage See Note 11 0 VDD–1.5 V
RiReference input resistance 10 MΩ
CiReference input capacitance 5 pF

Reference feed through REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 12) –60 dB

Reference input bandwidth REFIN = 0.2 Vpp + 1.024 V dc at –3 dB 1.4 MHz

NOTES: 11. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.

12. Reference feedthrough is measured at the DAC output with an input code = 0x000 and a V

ref(REFIN)

input = 1.024 V dc + 1 Vpp at

1 kHz.

digital inputs (D0 – D11, CS, WE, LDAC, PD)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

IH

High-level digital input current VI = V

DD

1 µA

I

IL

Low-level digital input current VI = 0 V –1 µA

C

i

Input capacitance 8 pF

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

UNIT

pp

p

5-V Supply 1.6 3

IDDPower supply current

No load

,

All inputs 0 V or V

DD

3-V Supply 1.44 2.7

mA

Power down supply current 0.01 10 µA

TLV5619

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER
WITH POWER DOWN

SLAS172C – DECEMBER 1997 – REVISED APRIL 2000

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CL = 100 pF,
R

= 10 kΩ,

V

ref(REFIN)

= 2.048 V,

1.024 V,

5-V

Supply

8 12 V/µs

SR

Slew rate

L

,

Code 32 to code 4095,
Code 4095 to code 32,

,

VO from 10% to 90%

90% to 10%

3-V

Supply

6 9 V/µs

t

s

Output settling time (full scale)

To ±0.5 LSB,
RL = 10 kΩ,

CL = 100 pF,
See Note 13

1 3 µs

Glitch energy DIN = all 0s to all 1s 5 nV–s

S/N Signal to noise

fs = 480 kSPS,
BW = 20 kHz,
CL = 100 pF,

f

OUT

= 1 kHz,
RL = 10 kΩ
TA = 25°C, See Note 14

5-V

Supply

65 78

fs = 480 kSPS,

f

OUT

= 1 kHz,

5-V

Supply

58 67

S/(N+D)

Signal to noise + distortion

BW

= 20

kHz

,

CL = 100 pF,

R

L

= 10 kΩ,

TA = 25°C, See Note 14

3-V

Supply

58 69

dB

Total harmonic distortion

fs = 480 kSPS,
BW = 20 kHz,
CL = 100 pF,

f

OUT

= 1 kHz,
RL = 10 kΩ,
TA = 25°C, See Note 14

–68 –60

Spurious free dynamic range

fs = 480 kSPS,
BW = 20 kHz,
CL = 100 pF,

f

OUT

= 1 kHz,
RL = 10 kΩ,
TA = 25°C, See Note 14

60 72

NOTES: 13. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0x3DF or 0x3DF to 0x020. Limits are ensured by design and characterization, but are not production tested.

14. 1 kHz sinewave generated by DAC, reference voltage = 1.024 V at 3 V and 2.048 V at 5 V.