Datasheet TLV5616IDGKR, TLV5616IDR, TLV5616IDGK, TLV5616ID, TLV5616CP Datasheet (Texas Instruments)

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TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12-Bit Voltage Output DAC

Programmable Settling Time vs Power Consumption

3 µs in Fast Mode 9 µs in Slow Mode

Ultra Low Power Consumption:

900 µW Typ in Slow Mode at 3 V

2.1 mW Typ in Fast Mode at 3 V

Differential Nonlinearity . . . <0.5 LSB Typ

Compatible With TMS320 and SPI Serial Ports

Power-Down Mode (10 nA)

Buffered High-Impedance Reference Input

Voltage Output Range ... 2 Times the Reference Input Voltage

Monotonic Over Temperature

Available in MSOP Package

applications

Digital Servo Control Loops

Digital Offset and Gain Adjustment

Industrial Process Control

Machine and Motion Control Devices

Mass Storage Devices

description

The TLV5616 is a 12-bit voltage output digital-to-analog converter (DAC) with a flexible 4-wire serial interface. The 4-wire serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports. The TLV5616 is programmed with a 16-bit serial string containing 4 control and 12 data bits. Developed for a wide range of supply voltages, the TLV5616 can operate from 2.7 V to 5.5 V.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer . The buffer features a Class AB output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need for a low source impedance drive to the terminal.

Implemented with a CMOS process, the TL V5616 is designed for single supply operation from 2.7 V to 5.5 V. The device is available in an 8-terminal SOIC package. The TL V5616C is characterized for operation from 0°C to 70°C. The TLV5616I is characterized for operation from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

SMALL OUTLINE

†

(D)

MSOP (DGK)

PLASTIC DIP

(P)

0°C to 70°C TLV5616CD TLV5616CDGK TLV5616CP

–40°C to 85°C TLV5616ID TLV5616IDGK TLV5616IP

†

Available in tape and reel as the TL V5616CDR and the TLV5616IDR

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

1 2 3 4

8 7 6 5

DIN

SCLK

OUT REFIN AGND

D, DGK, OR P PACKAGE

(TOP VIEW)

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Serial Input

16 Cycle

Timer

REFIN

SCLK

OUT

_ +

Power-On

Reset

DIN

12-Bit

Data

Latch

Speed/Power-Down

Logic

Update

2 3 4

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AGND 5 Analog ground CS 3 I Chip select. Digital input used to enable and disable inputs, active low. DIN 1 I Serial digital data input FS 4 I Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface. OUT 7 O DAC analog output REFIN 6 I Reference analog input voltage SCLK 2 I Serial digital clock input V

8 Positive power supply

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (V

to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLV5616C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5616I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

VDD = 5 V 4.5 5 5.5 V

Suppl

y v

oltage, V

VDD = 3 V 2.7 3 3.3 V

High-level digital input voltage, V

VDD = 2.7 V to 5.5 V 2 V

Low-level digital input voltage, V

VDD = 2.7 V to 5.5 V 0.8 V

Reference voltage, V

ref

to REFIN terminal VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 V

Reference voltage, V

ref

to REFIN terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V

Load resistance, R

2 10 kΩ

Load capacitance, C

100 pF

Clock frequency, f

CLK

20 MHz

TLV5616C 0 70 °C

Operating free-air temperature, T

TLV5616I –40 85 °C

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ V

DD/2

causes clipping of the transfer function.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

UNIT

VDD = 5 V, VREF = 2.048 V, No load,

Fast 0.9 1.35 mA

All inputs = AGND or VDD, DAC latch = 0x800

Slow 0.4 0.6 mA

IDDPower supply current

VDD = 3 V, VREF = 1.024 V No load,

Fast 0.7 1.1 mA

All inputs = AGND or VDD, DAC latch = 0x800

Slow 0.3 0.45 mA

Power down supply current (see Figure 12) 10 nA

Zero scale See Note 2 –80

PSRR

Power supply rejection ratio

Full scale See Note 3 –80

Power on threshold voltage, POR 2 V

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax]

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)

static DAC specifications RL = 10 kΩ, CL = 100 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 12 12 bits INL Integral nonlinearity See Note 4 ± 1.9 ±4 LSB DNL Differential nonlinearity See Note 5 ± 0.5 ± 1 LSB E

Zero-scale error (offset error at zero scale) See Note 6 ±10 mV

Zero-scale-error temperature coefficient See Note 7 10 ppm/°C

Gain error See Note 8 ±0.6

% of

voltage

Gain-error temperature coefficient See Note 9 10 ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error , is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale-error temperature coef ficient is given by: EZSTC = [EZS(T

max

) – EZS(T

min

)]/V

ref

× 106/(T

max

– T

min

8. Gain error is the deviation from the ideal output (2V

ref

– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error .

9. Gain temperature coefficient is given by: EGTC = [EG(T

max

) – EG (T

min

)]/V

ref

× 106/(T

max

– T

min

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Voltage output range RL = 10 kΩ 0 AVDD–0.1 V Output load regulation accuracy RL = 2 kΩ, vs 10 kΩ 0.1 ±0.25

% of FS

voltage

reference input (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input voltage range 0 VDD–1.5 V

Input resistance 10 MΩ

Input capacitance 5 pF

Slow 525 kHz

Reference input bandwidth

REFIN

= 0.2

+ 1.

024 V dc

Fast 1.3 MHz

Reference feed through

REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10)

–75 dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level digital input current VI = V

±1 µA

Low-level digital input current VI = 0 V ±1 µA

Input capacitance 3 pF

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics over recommended operating free-air temperature range (unless otherwise noted)

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

= 10 kΩ,

CL = 100 pF,

Fast 3 5.5

s(FS)

Output settling time, full scale

See Note 11

Slow 9 20

= 10 kΩ,

CL = 100 pF,

Fast 1 µs

s(CC)

Output settling time, code to code

See Note 12

Slow 2 µs

= 10 kΩ, C

= 100 pF,

Fast 3.6

Slew rate

See Note 13

Slow 0.9

V/µs

Glitch energy Code transition from 0x7FF to 0x800 10 nV–s S/N Signal to noise 74 dB S/(N+D) Signal to noise + distortion

fs = 400 KSPS fout = 1.1 kHz,

66 dB

THD Total harmonic distortion

= 10 kΩ,

100 pF

BW = 2

kHz

–68 dB

Spurious free dynamic range

BW = 20 kHz

70 dB

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 0x080 to 0x3FF or 0x3FF to 0x080. Not tested, ensured by design.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Code change from 0x1FF to 0x200. Not tested, ensured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

digital input timing requirements

MIN NOM MAX UNIT

su(CS–FS)

Setup time, CS low before FS↓ 10 ns

su(FS–CK)

Setup time, FS low before first negative SCLK edge 8 ns

su(C16–FS)

Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising edge of FS

10 ns

su(C16–CS)

Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup time is between the FS rising edge and CS

rising edge.

10 ns

Pulse duration, SCLK high 25 ns

Pulse duration, SCLK low 25 ns

su(D)

Setup time, data ready before SCLK falling edge 8 ns

h(D)

Hold time, data held valid after SCLK falling edge 5 ns

wH(FS)

Pulse duration, FS high 20 ns

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

123451516

D15 D14 D13 D12 D1 D0

su(FS-CK)

su(CS-FS)

wH(FS)

h(D)

su(D)

su(C16-CS)

su(C16-FS)

SCLK

DIN

Figure 1. Timing Diagram

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 2

1.998

1.996

1.994

1.990 0 0.01 0.02 0.05 0.1 0.2 0.5

– Output Voltage – V

2.002

Load Current – mA

OUTPUT VOLTAGE

LOAD CURRENT

2.004

3 V Slow Mode, SOURCE

3 V Fast Mode, SOURCE

1.992

VDD = 3 V, V

ref

= 1 V,

Full Scale

Figure 3

3.995

3.99

3.985

3.975 0 0.02 0.04 0.1 0.2 0.4 1

4.005

OUTPUT VOLTAGE

LOAD CURRENT

4.01

3.98

– Output Voltage – V

Load Current – mA

5 V Slow Mode, SOURCE

5 V Fast Mode, SOURCE

VDD = 5 V, V

ref

= 2 V,

Full Scale

Figure 4

0.1

0.08

0.04

0 0.01 0.02 0.05 0.1 0.2 0.5

0.16

0.18

OUTPUT VOLTAGE

LOAD CURRENT

0.2

0.14

0.12

0.06

0.02

– Output Voltage – V

Load Current – mA

3 V Slow Mode, SINK

3 V Fast Mode, SINK

VDD = 3 V, V

ref

= 1 V,

Zero Code

Figure 5

0.2

0.15

0.1

0 0.02 0.04 0.1 0.2 0.4 1

0.25

0.3

OUTPUT VOLTAGE

LOAD CURRENT

0.35

0.05

– Output Voltage – V

Load Current – mA

5 V Slow Mode, SINK

5 V Fast Mode, SINK

VDD = 5 V, V

ref

= 2 V,

Zero Code

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 6

0.6

0.4

0.2 –55 –40 –25 0 25 40 70

– Supply Current – mA

0.8

SUPPLY CURRENT

FREE-AIR TEMPERATURE

85 125

VDD = 3 V, V

ref

= 1 V,

Full Scale

TA – Free-Air Temperature – C°

Fast Mode

Slow Mode

Figure 7

SUPPLY CURRENT

FREE-AIR TEMPERATURE

0.6

0.4

0.2 –55 –40 –25 0 25 40 70

– Supply Current – mA

0.8

85 125

VDD = 5 V, V

ref

= 2 V,

Full Scale

TA – Free-Air Temperature – C°

Fast Mode

Slow Mode

Figure 8

––40

–50

–70

–80

0 5 10 20

THD – Total Harmonic Distortion – dB

–30

–10

f – Frequency – kHz

TOTAL HARMONIC DISTORTION

FREQUENCY

30 50 100

–20

–60

ref

= 1 V dc + 1 V p/p Sinewave,

Output Full Scale

Fast Mode

Figure 9

––40

–50

–70

–80

0 5 10 20

THD – Total Harmonic Distortion – dB

–30

–10

f – Frequency – kHz

TOTAL HARMONIC DISTORTION

FREQUENCY

30 50 100

–20

–60

ref

= 1 V dc + 1 V p/p Sinewave,

Output Full Scale

Slow Mode

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 10

––40

–50

–70

–80

0 5 10 20

THD – Total Harmonic Distortion And Noise – dB

–30

–10

f – Frequency – kHz

TOTAL HARMONIC DISTORTION AND NOISE

FREQUENCY

30 50 100

–20

–60

ref

= 1 V dc + 1 V p/p Sinewave,

Output Full Scale

Fast Mode

Figure 11

––40

–50

–70

–80

0 5 10 20

–30

–10

f – Frequency – kHz

TOTAL HARMONIC DISTORTION AND NOISE

FREQUENCY

30 50 100

–20

–60

ref

= 1 V dc + 1 V p/p Sinewave,

Output Full Scale

THD – Total Harmonic Distortion And Noise – dB

Slow Mode

Figure 12

400

300

100

0 100 200 300 400 500 600

– Supply Current –

600

800

T – Time – ns

SUPPLY CURRENT

TIME (WHEN ENTERING POWER-DOWN MODE)

900

700 800 900 1000

700

500

200

µ A

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

–2

–3.5

0 256 768 1280 1536 1792 2304

–1

0.5

INTEGRAL NONLINEARITY ERROR

2816 3328 3584

1.5 1

–0.5

–1.5

–2.5

–3

Digital Code

INL – Integral Nonlinearity Error – LSB

515

1024

2048

2560 3072

3840

Figure 13

0 256 512 768 1536 2048 2304

DNL – Differential Nonlinearity Error – LSB

0.1

Digital Code

DIFFERENTIAL NONLINEARITY ERROR

0.3

2560 3328 3584 3840

0.25

0.2

0.15

0.05 0

–0.05

–0.1

–0.15

–0.2

–0.25

–0.3

–0.35

–0.4

–0.45

–0.5

1024 1280 1792 2816 3072

Figure 14

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

general function

The TLV5616 is a 12-bit single supply DAC based on a resistor string architecture. The device consists of a serial interface, speed and power-down control logic, a reference input buffer , a resistor string, and a rail-to-rail output buffer .

The output voltage (full scale determined by external reference) is given by:

2REF

CODE

0x1000

[V]

Where REF is the reference voltage and CODE is the digital input value within the range of 0x000 to 0xFFF. A power-on reset initially resets the internal latches to a defined state (all bits zero).

serial interface

Explanation of data transfer: First, the device has to be enabled with CS set to low. Then, a falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch which updates the voltage output to the new level.

The serial interface of the TLV5616 can be used in two basic modes:

Four wire (with chip select)

Three wire (without chip select)

Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). The interface is compatible with the TMS320 family . Figure 15 shows an example with two TLV5616s connected directly to a TMS320 DSP.

TMS320

DSP

XF0 XF1

FSX

CLKX

TLV5616

FS DIN SCLK

TLV5616

FS DIN SCLK

Figure 15. TMS320 Interface

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

serial interface (continued)

If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows an example of how to connect the TLV5616 to a TMS320, SPI, or Microwire port using only three pins.

TMS320

DSP

FSX

CLKX

TLV5616

FS DIN SCLK

SPI

MOSI

SCLK

TLV5616

FS DIN SCLK

Microwire

I/O

TLV5616

FS DIN SCLK

Figure 16. Three-Wire Interface

Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5616. After the write operation(s), the DAC output is updated automatically on the sixteenth positive clock edge.

serial clock frequency and update rate

The maximum serial clock frequency is given by:

SCLKmax

wH(min)

)

wL(min)

20 MHz

The maximum update rate is:

UPDATEmax

wH(min)

)

wL(min)

1.25 MHz

The maximum update rate is a theoretical value for the serial interface, since the settling time of the TL V5616 has to be considered also.

data format

The 16-bit data word for the TLV5616 consists of two parts:

Control bits (D15 . . . D12)

New DAC value (D11 ...D0)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X SPD PWR X New DAC value (12 bits)

X: don’t care SPD: Speed control bit. 1 → fast mode 0 → slow mode PWR: Power control bit. 1 → power down 0 → normal operation

In power-down mode, all amplifiers within the TLV5616 are disabled.

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

TLV5616 interfaced to TMS320C203 DSP

hardware interfacing

Figure 17 shows an example how to connect the TL V5616 to a TMS320C203 DSP. The serial interface of the TLV5616 is ideally suited to this configuration, using a maximum of four wires to make the necessary connections. In applications where only one synchronous serial peripheral is used, the interface can be simplified even further by pulling CS low all the time as shown in the figure.

FS DIN SCLK

OUT

REFIN

AGND

REF

CLKX

TMS320C203 TLV5616

LOAD

Figure 17. TLV5616 to DSP Interface

software

No setup procedure is needed to access the TLV5616. The output voltage can be set using just a single command.

out data_addr, SDTR

Where data_addr points to an address location holding the control bits and the 12 data bits providing the output voltage data. SDTR is the address of the transmit FIFO of the synchronous serial port.

The following code shows how to use the timer of the TMS320C203 as a time base to generate a voltage ramp with the TLV5616.

A timer interrupt is generated every 205 µs. The corresponding interrupt service routine increments the output code (stored at 0x0064) for the DAC, adds the DAC control bits to the four most significant bits, and writes the new code to the TLV5616. The resulting period of the saw waveform is:

π = 4096 × 205 E-6 s = 0.84 s

;*************************************************************************************** ;* Title : Ramp generation with TLV5616 * ;* Version : 1.0 * ;* DSP : TI TMS320C203 * ;*  (1998) Texas Instruments Incorporated * ;***************************************************************************************

;––––––––––– I/O and memory mapped regs ––––––––––––

.include ”regs.asm”

;––––––––––– vectors –––––––––––––––––––––––––––––––

.ps 0h b start b INT1 b INT23 b TIM_ISR

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

;*************************************************************************************** ;* Main Program ;***************************************************************************************

.ps 1000h

.entry start: ; disable interrupts

setc INTM ; disable maskable interrupts

splk #0ffffh, IFR

splk #0004h, IMR ; set up the timer to interrupt ever 205uS

splk #0000h, 60h

splk #00FFh, 61h

out 61h, PRD

out 60h, TIM

splk #0c2fh, 62h

out 62h, TCR ; Configure SSP to use internal clock, internal frame sync and burst mode

splk #0CC0Eh, 63h

out 63h, SSPCR

splk #0CC3Eh, 63h

out 63h, SSPCR

splk #0000h, 64h ; set initial DAC value ; enable interrupts

clrc INTM ; enable maskable interrupts ; loop forever!

next: idle ;wait for interrupt

b next

; all else fails stop here done: b done ;hang there

;*************************************************************************************** ;* Interrupt Service Routines ;*************************************************************************************** INT1: ret ;do nothing and return

INT23: ret ;do nothing and return TIM_ISR:

lacl 64h ; restore counter value to ACC add #1h ; increment DAC value and #0FFFh ; mask 4 MSBs sacl 64h ; store 12 bit counter value or #4000h ; set DAC control bits sacl 65h ; store DAC value out 65h, SDTR ; send data

clrc intm ; re-enable interrupts ret

.END

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

TLV5616 interfaced to MCS51



microcontroller

hardware interfacing

Figure 18 shows an example of how to connect the TL V5616 to an MCS51 compatible microcontroller. The serial DAC input data and external control signals are sent via I/O port 3 of the controller. The serial data is sent on the RxD line, with the serial clock output on the TxD line. P3.4 and P3.5 are configured as outputs to provide the chip select and frame sync signals for the TLV5616.

SDIN SCLK CS

OUT

REFIN

AGND

REF

RxD TxD

P3.4

MCS51



Controller TLV5616

P3.5

LOAD

Figure 18. TLV5616 to MCS51 Controller Interface

software

The example program puts out a sine wave on the OUT pin. The on-chip timer is used to generate interrupts at a fixed frequency . The related interrupt service routine fetches

and writes the next sample to the DAC. The samples are stored in a lookup table, which describes one full period of a sine wave.

The serial port of the controller is used in mode 0, which transmits 8 bits of data on RxD, accompanied by a synchronous clock on TxD. Two writes concatenated together are required to write a complete word to the TL V5616. The CS and FS signals are provided in the required fashion through control of I/O port 3, which has bit addressable outputs.

;*************************************************************************************** ;* Title : Ramp generation with TLV5616 * ;* Version : 1.0 * ;* MCU : INTEL MCS51



;*  (1998) Texas Instruments Incorporated * ;***************************************************************************************

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Program function declaration ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

NAME GENSINE MAIN SEGMENT CODE

ISR SEGMENT CODE SINTBL SEGMENT CODE VAR1 SEGMENT DATA STACK SEGMENT IDATA

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Code start at address 0, jump to start ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

CSEG AT 0

MCS is a registered trademark of Intel Corporation

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

LJMP start ; Execution starts at address 0 on power–up.

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Code in the timer0 interrupt vector ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

CSEG AT 0BH LJMP timer0isr ; Jump vector for timer 0 interrupt is 000Bh

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Define program variables ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

RSEG VAR1

rolling_ptr: DS 1 ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

; Interrupt service routine for timer 0 interrupts ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

RSEG ISR

timer0isr:

PUSH PSW PUSH ACC

CLR T0 ; set CSB low CLR T1 ; set FS low

; The signal to be output on the dac is a sine function. One cycle of a sine wave is ; held in a table @ sinevals as 32 samples of msb, lsb pairs (64 bytes). The pointer, ; rolling_ptr, rolls round the table of samples incrementing by 2 bytes (1 sample) on ; each interrupt (at the end of this routine).

MOV DPTR,#sinevals ; set DPTR to the start of the table of sine signal values MOV A,rolling_ptr ; ACC loaded with the pointer into the sine table

MOVC A,@A+DPTR ; get msb from the table ORL A, #00H ; set control bits MOV SBUF,A ; send out msb of data word

MOV A,rolling_ptr; move rolling pointer in to ACC INC A ; increment ACC holding the rolling pointer MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC

MSB_TX:

JNB TI, MSB_TX ; wait for transmit to complete CLR TI ; clear for new transmit MOV SBUF,A ; and send out the lsb

LSB_TX:

JNB TI, LSB_TX ; wait for lsb transmit to complete SETB T1 ; set FS = 1 CLR TI ; clear for new transmit

MOV A,rolling_ptr ; load ACC with rolling pointer INC A ; increment the ACC twice, to get next sample INC A ANL A,#03FH ; wrap back round to 0 if >64 MOV rolling_ptr,A ; move value held in ACC back to the rolling pointer

SETB T0 ; CSB high POP ACC

POP PSW RETI

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Set up stack ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

RSEG STACK DS 10h ; 16 Byte Stack!

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Main Program ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

RSEG MAIN

start:

MOV SP,#STACK–1 ; first set Stack Pointer CLR A

MOV SCON,A ; set serial port 0 to mode 0 MOV TMOD,#02H ; set timer 0 to mode 2 – auto–reload MOV TH0,#0C8H ; set TH0 for 16.67 kHs interrupts

SETB T1 ; set FS = 1 SETB T0 ; set CSB = 1

SETB ET0 ; enable timer 0 interrupts SETB EA ; enable all interrupts

MOV rolling_ptr,A ; set rolling pointer to 0 SETB TR0 ; start timer 0

always:

SJMP always ; while(1) ! RET

;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Table of 32 sine wave samples used as DAC data ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––

RSEG SINTBL

sinevals:

DW 01000H DW 0903EH DW 05097H DW 0305CH DW 0B086H DW 070CAH DW 0F0E0H DW 0F06EH DW 0F039H DW 0F06EH DW 0F0E0H DW 070CAH DW 0B086H DW 0305CH DW 05097H DW 0903EH DW 01000H DW 06021H DW 0A0E8H DW 0C063H DW 040F9H DW 080B5H DW 0009FH DW 00051H DW 00026H DW 00051H DW 0009FH DW 080B5H DW 040F9H DW 0C063H DW 0A0E8H DW 06021H

END

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

linearity, offset, and gain error using single ended supplies

When an amplifier is operated from a single supply , the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 19.

DAC Code

Output

Voltage

0 V

Negative

Offset

Figure 19. Effect of Negative Offset (Single Supply)

This offset error, not the linearity error , produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail.

For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way . However , single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage.

power-supply bypassing and ground management

Printed-circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane.

A 0.1-µF ceramic-capacitor bypass should be connected between V

and AGND and mounted with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digital power supply.

Figure 20 shows the ground plane layout and bypassing technique.

0.1 µF

Analog Ground Plane

1 2 3 4

8 7 6 5

Figure 20. Power-Supply Bypassing

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

definitions of specifications and terminology

integral nonlinearity (INL)

The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.

differential nonlinearity (DNL)

The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

zero-scale error (E

)

Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.

gain error (EG)

Gain error is the error in slope of the DAC transfer function.

signal-to-noise ratio + distortion (S/N+D)

S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.

spurious free dynamic range (SFDR)

SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels.

total harmonic distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels.

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047/D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

0.014 (0,35)

0.020 (0,51)

0.157 (4,00)

0.150 (3,81)

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

(8,55)

(8,75)

0.337

0.344

(9,80)

0.394

(10,00)

0.386

0.004 (0,10)

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE

0,69

0,41

0,25

0,15 NOM

Gage Plane

4073329/B 04/98

4,98

0,25

3,05

4,78

2,95

3,05 2,95

0,38

1,07 MAX

Seating Plane

0,65

0,25

0°–6°

0,10

0,15 0,05

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. Falls within JEDEC MO-187

TLV5616C, TLV5616I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS152B – DECEMBER 1997 – REVISED MARCH 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE

4040082/B 03/95

0.310 (7,87)

0.290 (7,37)

0.010 (0,25) NOM

0.400 (10,60)

0.355 (9,02)

0.020 (0,51) MIN

0.070 (1,78) MAX

0.240 (6,10)

0.260 (6,60)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.015 (0,38)

0.021 (0,53)

Seating Plane

0.010 (0,25)

0.100 (2,54)

0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

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Datasheet TLV5616IDGKR, TLV5616IDR, TLV5616IDGK, TLV5616ID, TLV5616CP Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual