Datasheet TLV5604IDR, TLV5604ID, TLV5604CPWR, TLV5604CDR, TLV5604CPW Datasheet (Texas Instruments)

...
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
D
D
Programmable Settling Time of 3 µs or 9 µs Typ
D
TMS320, (Q)SPI, and Microwire Compatible Serial Interface
D
Internal Power-On Reset
D
Low Power Consumption:
5.5 mW, Slow Mode – 5-V Supply
3.3 mW, Slow Mode – 3-V Supply
D
Reference Input Buffers
D
Voltage Output Range...2× the Reference Input Voltage
D
Monotonic Over Temperature
D
Dual 2.7-V to 5.5-V Supply (Separate Digital and Analog Supplies)
description
The TL V5604 is a quadruple 10-bit voltage output digital-to-analog converter (DAC) with a flexible 4-wire serial interface. The 4-wire serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports. The TLV5604 is programmed with a 16-bit serial word comprised of a DAC address, individual DAC control bits, and a 10-bit DAC value.
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
WITH POWER DOWN
D
Hardware Power Down (10 nA)
D
Software Power Down (10 nA)
D
Simultaneous Update
applications
D
Battery Powered Test Instruments
D
Digital Offset and Gain Adjustment
D
Industrial Process Controls
D
Machine and Motion Control Devices
D
Communications
D
Arbitrary Waveform Generation
D OR PW PACKAGE
(TOP VIEW)
DV
LDAC
SCLK
DGND
DD
PD
DIN
CS
FS
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
AV
DD
REFINAB OUTA OUTB OUTC OUTD REFINCD AGND
TLV5604
The device has provision for two supplies: one digital supply for the serial interface (via pins DV and one for the DACs, reference buffers and output buffers (via pins AV
and AGND). Each supply is
DD
and DGND),
DD
independent of the other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the DAC will be controlled via a microprocessor operating on a 3-V supply (also used on pins DV
and DGND), with the DACs operating on a 5-V supply . Of course, the digital and analog supplies can be
DD
tied together. The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer . The buffer features a Class AB
output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow DACs A and B to have a different reference voltage then DACs C and D.
The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The TL V5604C is characterized for operation from 0°C to 70°C. The TLV5604I is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
AVAILABLE OPTIONS
PACKAGE
functional block diagram
T
A
0°C to 70°C TLV5604CD TLV5604CPW
–40°C to 85°C TLV5604ID TLV5604IPW
SOIC
(D)
TSSOP
(PW)
REFINAB
SCLK
AV
DD
15 16 1
DAC A
+ _
10-Bit
DAC
Latch
2-Bit
Control
Data
Latch
DAC B
DIN
FS
CS
4
7 5
6
Power-On
Reset
Serial
Input
Register
2
DAC
Select/
Control
Logic
14
14-Bit
Data
and
Control
Register
10
2
DV
DD
10
2
Power Down/
Speed Control
x2
13
14
OUTA
OUTB
REFINCD
2
9
AGND
8
DGND
32
LDAC
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DAC C
DAC D
PD
12
11
OUTC
OUTD
I/O
DESCRIPTION
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
Terminal Functions
TERMINAL
NAME NO.
AGND 9 Analog ground AV
DD
CS 6 I Chip select. This terminal is active low. DGND 8 Digital ground DIN 4 I Serial data input DV
DD
FS 7 I Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out
PD 2 I Power-down pin. Powers down all DACs (overriding their individual power down settings), and all output stages.
LDAC 3 I Load DAC. When the LDAC signal is high, no DAC output updates occur when the input digital data is read into
REFINAB 15 I Voltage reference input for DACs A and B. REFINCD 10 I Voltage reference input for DACs C and D. SCLK 5 I Serial Clock input OUTA 14 O DAC A output OUTB 13 O DAC B output OUTC 12 O DAC C output OUTD 11 O DAC D output
16 Analog supply
1 Digital supply
to the TLV5604.
This terminal is active low.
the serial interface. The DAC outputs are only updated when LDAC
is low.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, (DV Supply voltage difference, (AV Digital input voltage range –0.3 V to DV Reference input voltage range –0.3 V to AV Operating free-air temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
, AVDD to GND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
to DVDD) –2.8 V to 2.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
: TLV5604C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
TLV5604I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
DD DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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3
TLV5604
Suppl
oltage, AV
DV
V
Reference voltage, V
to REFINAB, REFINCD terminal
V
Operating free-air temperature
°C
PSRR
Power supply rejection ratio
See Notes 8 and 9
dB
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
recommended operating conditions
MIN NOM MAX UNIT
pp
y v
High-level digital input, V Low-level digital input, V
Load resistance, R Load capacitance, C Serial clock rate, SCLK 20 MHz
p
NOTE 1: Voltages greater than AVDD/2 will cause output saturation for large DAC codes.
DD
L
L
ref
,
DD
IH
IL
p
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
5-V supply 4.5 5 5.5 3-V supply 2.7 3 3.3 DVDD = 2.7 V to 5.5 V 2 V DVDD = 2.7 V to 5.5 V 0.8 V 5-V supply (see Note 1) 0 2.048 AVDD–1.5 3-V supply (see Note 1) 0 1.024 AVDD–1.5
2 10 k
100 pF
TLV5604C 0 70 TLV5604I –40 85
°
static DAC specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 10 bits Integral nonlinearity (INL), end point adjusted See Note 2 ±1 LSB Differential nonlinearity (DNL) See Note 3 ±0.1 ±1 LSB
E
ZS
E
G
NOTES: 2. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error , is the maximum deviation of the output
Zero scale error (offset error at zero scale) See Note 4 ±12 mV Zero scale error temperature coefficient See Note 5 10 ppm/°C
min
).
%of FS voltage
Gain error See Note 6 ±0.6 Gain error temperature coefficient See Note 7 10 ppm/°C
pp
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
3. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
4. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
5. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (T
6. Gain error is the deviation from the ideal output (2V
7. Gain temperature coef ficient is given by: EG TC = [EG(T
8. Zero-scale-error rejection ratio (EZS–RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.5 V dc, and measuring the proportion of this signal imposed on the zero-code output voltage.
9. Gain-error rejection ratio (EG-RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.5 V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero scale change.
Zero scale gain Gain
) – EZS (T
– 1 LSB) with an output load of 10 k excluding the effects of the zero-error.
ref
max
) – EG (T
max
min
)]/V
× 106/(T
ref
min
)]/V
max
ref
– T
× 106/(T
).
min
–80 –80
max
– T
4
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Reference input bandwidth
REFIN
V
024 V dc
MH
5-V suppl
load, Clock running
mA
IDDPower supply current
3-V suppl
load, Clock running
mA
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)
individual DAC output specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
O
reference input (REFINAB, REFINCD)
V
I
R
I
C
I
NOTES: 10. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.
Voltage output RL = 10 k 0 AVDD–0.1 V Output load regulation accuracy RL = 2 k vs 10 k 0.1 0.25
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range See Note 10 0 AVDD–1.5 V Input resistance 10 M Input capacitance 5 pF
Reference feed through
p
11. Reference feedthrough is measured at the DAC output with an input code = 000 hex and a V input = 1.024 Vdc + 1 Vpp at 1 kHz.
REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 11)
= 0.2
pp
+ 1.
–75 dB
Slow 0.5 Fast 1
ref(REFINAB or REFINCD)
TLV5604
% of FS
voltage
z
digital inputs (D0–D11, CS, WEB, LDAC, PD)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
IH
I
IL
C
I
High-level digital input current VI = DV Low-level digital input current VI = 0 V ±1 µA Input capacitance 3 pF
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
pp
Power down supply current, See Figure 12
pp
pp
y, No
y, No
DD
Slow 1.4 2.2 Fast 3.5 5.5 Slow 1 1.5 Fast 3 4.5
±1 µA
10 nA
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
5
TLV5604
SR
Output slew rate
V
10% to 90%
tsOutput settling time
,
L
,
s
t
Output settling time, code to code
,
L
,
s
S,
f
s
400 KSPS
C
L
100 pF
R
L
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
p
p
s(c)
SNR Signal-to-noise ratio S/(N+D) Signal to noise + distortion THD Total harmonic Distortion
SFDR Spurious free dynamic range
NOTES: 12. Settling time is the time for the output signal to remain within ± 0.5LSB of the final measured value for a digital input code change
p
Glitch energy Code transition from 7FF to 800 10 nV-sec
of 020 hex to 3FF hex or 3FF hex to 020 hex.
13. Settling time is the time for the output signal to remain within ± 0.5LSB of the final measured value for a digital input code change of one count, 1FF hex to 200 hex.
14. Limits are ensured by design and characterization, but are not production tested.
CL = 100 pF, RL = 10 k,
=
O
V
= 2.048 V , 1024 V
ref
To ± 0.5 LSB, C RL = 10 k, See Notes 12 and 14
To ± 0.5 LSB, C RL = 10 k, See Note 13
Sinewave generated by DAC, Reference voltage = 1.024 at 3 V and 2.048 at 5 V , f
= 400 KSP
=
f
= 1.1 kHz sinewave,
OUT
=
BW = 20 kHz
p
,
,
,
= 100 pF,
= 100 pF,
= 10 k,
Fast 5 V/µs
Slow 1 V/µs
Fast 2.5 4
Slow 8.5 18
Fast 1
Slow 2
68 65
–68
70
µ
µ
dB
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)
digital input timing requirements
MIN NOM MAX UNIT
t
su(CS–FS)
t
su(FS–CK)
t
su(C16–FS)
t
su(C16–CS)
t
wH
t
wL
t
su(D)
t
h(D)
t
wH(FS)
Setup time, CS low before FS 10 ns Setup time, FS low before first negative SCLK edge 8 ns Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising
edge of FS Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup time is between the FS rising edge and CS
Pulse duration, SCLK high 25 ns Pulse duration, SCLK low 25 ns Setup time, data ready before SCLK falling edge 8 ns
Hold time, data held valid after SCLK falling edge 5 ns Pulse duration, FS high 20 ns
rising edge.
10 ns
10 ns
TLV5604
SCLK
DIN
CS
FS
t
su(D)
PARAMETER MEASUREMENT INFORMATION
t
wL
123451516
t
h(D)
D15 D14 D13 D12 D1 D0
t
su(FS-CK)
t
su(CS-FS)
t
wH(FS)
Figure 1. Timing Diagram
t
wH
t
t
su(C16-FS)
su(C16-CS)
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7
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
TYPICAL CHARACTERISTICS
0.35
0.30
0.25
0.20
0.15
– Output Voltage – V
0.10
O
V
0.05
0
4.002
LOAD REGULATION
VDD = 5 V, V
= 2 V,
REF
VO = Full Scale
5 V Slow Mode, Sink
5 V Fast Mode, Sink
0 0.02 0.04 0.1 0.2 0.4 1
Load Current – mA
Figure 2
LOAD REGULATION
24
0.20
0.18
0.16
0.14
0.12
0.10
0.08
– Output Voltage – V
0.06
O
V
0.04
0.02 0
2.003
LOAD REGULATION
VDD = 3 V, V
= 1 V,
REF
VO = Full Scale
3 V Slow Mode, Sink
3 V Fast Mode, Sink
0 0.01 0.02 0.05 0.1 0.2 0.5
Load Current – mA
Figure 3
LOAD REGULATION
12
4.00
3.998
3.996
3.994
3.992
– Output Voltage – V
3.99
O
V
3.988
3.986
3.984
5 V Slow Mode, Source
5 V Fast Mode, Source
VDD = 5 V, V
REF
VO = Full Scale
0 0.02 0.04 0.1 0.2 0.4 1
Load Current – mA
Figure 4
= 2 V,
24
2.002
2.002
2.001
2.001
2
– Output Voltage – V
O
V
2
1.999
1.999
3 V Fast Mode, Source
3 V Slow Mode, Source
VDD = 3 V, V
REF
VO = Full Scale
0 0.01 0.02 0.05 0.1 0.2 0.5
Load Current – mA
Figure 5
= 1 V,
12
8
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TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
TYPICAL CHARACTERISTICS
4
VDD = 3 V, V
= 1.024 V,
REF
3.5
VO = Full Scale
3
2.5
2
– Supply Current – mA
1.5
DD
I
1
0.5 –55 –40 –25 0 25 40 70
TOTAL HARMONIC DISTORTION
0
V
= 1 V dc + 1 V p/p Sinewave,
–10
ref
Output Full Scale
SUPPLY CURRENT
vs
TEMPERATURE
Fast Mode
Slow Mode
T – Temperature – °C
Figure 6
vs
FREQUENCY
85 125
4
3.5
3
2.5
2
– Supply Current – mA
1.5
DD
I
VDD = 5 V,
1
V
= 1.024 V,
REF
VO = Full Scale
0.5 –55 –40 –25 0 25 40 70
TOTAL HARMONIC DISTORTION
0
V
= 1 V dc + 1 V p/p Sinewave,
–10
ref
Output Full Scale
SUPPLY CURRENT
vs
TEMPERATURE
Fast Mode
Slow Mode
85 125
T – Temperature – °C
Figure 7
vs
FREQUENCY
–20
–30
––40
–50
–60
THD – Total Harmonic Distortion – dB
–70
–80
0 5 10 20
f – Frequency – kHz
Figure 8
Fast Mode
–20
–30
––40
–50
–60
THD – Total Harmonic Distortion – dB
–70
30 50 100
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
–80
0 5 10 20
Slow Mode
30 50 100
f – Frequency – kHz
Figure 9
9
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
0
V
= 1 V dc + 1 V p/p Sinewave,
–10
–20
–30
––40
–50
–60
–70
THD – Total Harmonic Distortion And Noise – dB
–80
ref
Output Full Scale
Fast Mode
0 5 10 20
f – Frequency – kHz
30 50 100
Figure 10
(WHEN ENTERING POWER-DOWN MODE)
4000
–10
–20
–30
––40
–50
–60
–70
THD – Total Harmonic Distortion And Noise – dB
–80
SUPPLY CURRENT
vs
TIME
TOTAL HARMONIC DISTORTION AND NOISE
vs
FREQUENCY
0
V
= 1 V dc + 1 V p/p Sinewave,
ref
Output Full Scale
Slow Mode
0 5 10 20
f – Frequency – kHz
30 50 100
Figure 11
3500
3000
Aµ
2500
2000
1500
– Supply Current –
DD
1000
I
500
0
0 200 400 600
800 1000
t – Time – ns
Figure 12
10
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TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
TYPICAL CHARACTERISTICS
0.2
0
–0.2
–0.4
INL – Integral Nonlinearity – LSB
–0.6
0 64 128 192 256 320 384
0.15
0.1
0.05
VDD = 5 V, V CLK = 1 MHz
0
ref
= 2 V,
INTEGRAL NONLINEARITY
VDD = 5 V, Vref = 2 V, CLK = 1 MHz
448 512 704
Digital Code
576 640 768 832
Figure 13
DIFFERENTIAL NONLINEARITY
896 960
–0.05
–0.1
DNL – Differential Nonlinearity – LSB
0 64 128 192 256 384 512
320 448 832
Digital Code
Figure 14
576 640 704 768
896 960
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11
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
APPLICATION INFORMATION
general function
The TL V5604 is a 10-bit single supply DAC based on a resistor string architecture. The device consists of a serial interface, speed and power-down control logic, a reference input buffer , a resistor string, and a rail-to-rail output buffer .
The output voltage (full scale determined by external reference) is given by:
2REF
CODE
0x1000
[V]
Where REF is the reference voltage and CODE is the digital input value within the range of 0x000 to 0xFFF. A power-on reset initially resets the internal latches to a defined state (all bits zero).
serial interface
Explanation of data transfer: First, the device has to be enabled with CS set to low. Then, a falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new level.
The serial interface of the TLV5604 can be used in two basic modes:
D
Four wire (with chip select)
D
Three wire (without chip select)
Using chip select (four wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). The interface is compatible with the TMS320 family . Figure 15 shows an example with two TLV5604s connected directly to a TMS320 DSP.
TLV5604
CS
FS DIN SCLK
TLV5604
CS
FS DIN SCLK
12
TMS320
DSP
XF0 XF1
FSX
DX
CLKX
Figure 15. TMS320 Interface
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2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
APPLICATION INFORMATION
serial interface (continued)
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows an example of how to connect the TLV5604 to a TMS320, SPI, or Microwire port using only three pins.
TLV5604
TMS320
DSP
FSX
DX
CLKX
TLV5604
FS DIN SCLK
CS
SPI
SS MOSI SCLK
TLV5604
FS DIN SCLK
CS
Microwire
I/O
SO
SK
TLV5604
FS DIN SCLK
CS
Figure 16. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5604. After the write operation(s), the DAC output is updated automatically on the sixteenth positive clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
f
SCLKmax
+
t
wH(min)
The maximum update rate is:
f
UPDATEmax
+
16
1
)
ǒ
t
wH(min)
t
wL(min)
1
)
+
t
20 MHz
wL(min)
+
Ǔ
1.25 MHz
Note that the maximum update rate is a theoretical value for the serial interface since the settling time of the TLV5604 has to be considered also.
data format
The 16-bit data word for the TLV5604 consists of two parts:
D
Control bits (D15 . . . D12)
D
New DAC value (D11 ...D0)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A1 A0 PWR SPD New DAC value (12 bits) X X
X: don’t care SPD: Speed control bit. 1 fast mode 0 slow mode PWR: Power control bit. 1 power down 0 normal operation
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
13
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
APPLICATION INFORMATION
In power down mode, all amplifiers within the TLV5604 are disabled. A particular DAC (A, B, C, D) of the TLV5604 is selected by A1 and A0 within the input word.
A1 A0 DAC
0 0 A 0 1 B 1 0 C 1 1 D
TLV5604 interfaced to TMS320C203 DSP
Hardware interfacing
Figure 17 shows an example of how to connect the TLV5604 to a TMS320C203 DSP. The serial port is configured in burst mode, with FSX generated by the TMS320C203 to provide the Frame Sync (FS) input to the TLV5604. Data is transmitted on the DX line, with the serial clock input on the CLKX line. The general-purpose input/output port bits IO0 and IO1 are used to generate the Chip Select (CS Update (LDAC
) inputs to the TL V5604. The active low Power Down (PD) is pulled high all the time to ensure
the DACs are enabled.
TMS320C203
TLV5604
) and DAC Latch
DX
CLKX
FSX I/O 0 I/O 1
REF
SDIN SCLK FS CS LDAC
REFINAB REFINCD
V
DD PD
VOUTA VOUTB VOUTC VOUTD
V
SS
Figure 17. TLV5604 Interfaced with TMS320C203
Software
The application example generates a differential in-phase (sine) signal between the VOUT A and VOUTB pins, and it is quadrature (cosine) signal as the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency . The related interrupt service routine pulses LDAC low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The samples are stored in a look-up table, which describes two full periods of a sine wave.
The synchronous serial port of the DSP is used in burst mode. In this mode, the processor generates an FS pulse preceding the MSB of every data word. If multiple, contiguous words are transmitted, a violation of the tsu(C16-FS) timing requirement will occur. T o avoid this, the program waits until the transmission of the previous word has been completed.
14
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
APPLICATION INFORMATION
;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––;
; Processor: TMS320C203 runnning at 40 MHz; ; Description: ; ; This program generates a differential in-phase (sine) on (OUTA–OUTB) and it’s ; quadrature (cosine) as a differential signal on (OUTC–OUTD). ; ; The DAC codes for the signal samples are stored as a table of 64 12–bit values, ; describing 2 periods of a sine function. A rolling pointer is used to address the ; table location in the first period of this waveform, from which the DAC A samples are ; read. The samples for the other 3 DACs are read at an offset to this rolling pointer: ; DAC Function Offset from rolling pointer; ; A sine 0 ; B inverse sine 16 ; C cosine 8 ; D inverse cosine 24 ; ; The on-chip timer is used to generate interrupts at a fixed rate. The interrupt ; service routine first pulses LDAC low to update all DACs simultaneously with the ; values which were written to them in the previous interrupt. Then all 4 DAC values are ; fetched and written out through the synchronous serial interface. Finally, the ; rolling pointer is incremented to address the next sample, ready for the next ; interrupt. ; ; 1998, Texas Instruments Incorporated ;
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––;
; ––––––––––I/O and memory mapped regs –––––––––––– ; ––––––––––––––jump vectors––––––––––––––––––––––––––––––––––––––––––––––––––––––
;–––––––––––––––––––––– variables ––––––––––––––––––––––––––––– temp .equ 0060h r_ptr .equ 0061 iosr_stat .equ 0062h DACa_ptr .equ 0063h DACb_ptr .equ 0064h DACc_ptr .equ 0065h DACd_ptr .equ 0066h
;––––––––– constants ––––––––––––––––––––––– ; DAC control bits to be OR’ed onto data ; all fast mode DACa_control .equ 01000h DACb_control .equ 05000h DACc_control .equ 09000h DACd_control .equ 0d000h ;––––––––––– tables ––––––––––––––––––––––––––––––––
sinevals
.include ”regs.asm”
.ps 0h b start b int1 b int23 b timer_isr
––––––––––––––––––––––––––––––––––––––––
.ds 02000h .word 00800h
.word 0097Ch .word 00AE9h .word 00C3Ah .word 00D61h .word 00E53h .word 00F07h .word 00F76h .word 00F9Ch .word 00F76h .word 00F07h .word 00E53h .word 00D61h .word 00C3Ah
–––––––––––––––––––––––––––––––
–––––––––––––––––––
–––––––––––––––––––––––––––––––
TLV5604
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
15
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
APPLICATION INFORMATION
.word 00AE9h .word 0097Ch .word 00800h .word 00684h .word 00517h .word 003C6h .word 0029Fh .word 001ADh .word 000F9h .word 0008Ah .word 00064h .word 0008Ah .word 000F9h .word 001ADh .word 0029Fh .word 003C6h .word 00517h .word 00684h .word 00800h .word 0097Ch .word 00AE9h .word 00C3Ah .word 00D61h .word 00E53h .word 00F07h .word 00F76h .word 00F9Ch .word 00F76h .word 00F07h .word 00E53h .word 00D61h .word 00C3Ah .word 00AE9h .word 0097Ch .word 00800h .word 00684h .word 00517h .word 003C6h .word 0029Fh .word 001ADh .word 000F9h .word 0008Ah .word 00064h .word 0008Ah .word 000F9h .word 001ADh .word 0029Fh .word 003C6h .word 00517h
;––––––––––––––––––––––––––––––––––––––––––––––––––– ; Main Program ;––––––––––––––––––––––––––––––––––––––––––––
start ;––––––––––––––––––––––––––––––––––––––––––––––––––– ; disable interrupts ;–––––––––––––––––––––––––––––––––––––––––––––––––––
.word 00684h
––––––––––––––––––––––––––––––––––––––
–––––––––––––––––––––––––––––––––––––––––––––
.ps 1000h .entry
––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
setc INTM ; disable maskable interrupts splk #0ffffh, IFR ; clear all interrupts splk #0004h, IMR ; timer interrupts unmasked
16
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
APPLICATION INFORMATION
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; set up the timer ; timer period set by values in PRD and TDDR ; period = (CLKOUT1 period) × (1+PRD) × (1+TDDR) ; examples for TMS320C203 with 40 MHz main clock ; Timer rate TDDR PRD ; 80 kHz 9 24 (18h) ; 50 kHz 9 39 (27h) ;–––––––––––––––––––––––––––––––––––––––––––––––––––
prd_val.equ 0018h tcr_val.equ 0029h
splk #0000h, temp ; clear timer out temp, TIM splk #prd_val, temp ; set PRD out temp, PRD splk #tcr_val, temp ; set TDDR, and TRB=1 for auto-reload
out temp, TCR ;––––––––––––––––––––––––––––––––––––––––––––––––––– ; Configure IO0/1 as outputs to be : ; IO0 CS – and set high ; IO1 LDAC – and set high ;–––––––––––––––––––––––––––––––––––––––––––––––––––
in temp, ASPCR ; configure as output
lacl temp
or #0003h
sacl temp
out temp, ASPCR
in temp, IOSR ; set them high
lacl temp
or #0003h
sacl temp
out temp, IOSR ;––––––––––––––––––––––––––––––––––––––––––––––––––– ; set up serial port for ; SSPCR.TXM=1 Transmit mode – generate FSX ; SSPCR.MCM=1 Clock mode – internal clock source ; SSPCR.FSM=1 Burst mode ;–––––––––––––––––––––––––––––––––––––––––––––––––––
splk #0000Eh, temp
out temp, SSPCR ; reset transmitter
splk #0002Eh, temp
out temp, SSPCR ;––––––––––––––––––––––––––––––––––––––––––––––––––– ; reset the rolling pointer ;–––––––––––––––––––––––––––––––––––––––––––––––––––
lacl #000h sacl r_ptr ;––––––––––––––––––––––––––––––––––––––––––––––––––– ; enable interrupts ;–––––––––––––––––––––––––––––––––––––––––––––––––––
clrc INTM ; enable maskable interrupts ;––––––––––––––––––––––––––––––––––––––––––––––––––– ; loop forever! ;––––––––––––––––––––––––––––––––––––––––––––––––––– next idle ;wait for interrupt
b next ;––––––––––––––––––––––––––––––––––––––––––––––––––– ; all else fails stop here ;––––––––––––––––––––––––––––––––––––––––––––––––––– done b done ;hang there
––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
TLV5604
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
17
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
APPLICATION INFORMATION
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Interrupt Service Routines ;––––––––––––––––––––––––––––––––––––––––––––––––––– int1 ret ; do nothing and return int23 ret ; do nothing and return timer_isr:
in iosr_stat, IOSR ; store IOSR value into variable space lacl iosr_stat ; load acc with iosr status and #0FFFDh ; reset IO1 – LDAC low sacl temp ; out temp, IOSR ;
or #0002h ; set IO1 – LDAC high sacl temp ; out temp, IOSR ; and #0FFFEh ; reset IO0 – CS low sacl temp ; out temp, IOSR ; lacl r_ptr ; load rolling pointer to accumulator add #sinevals ; add pointer to table start sacl DACa_ptr ; to get a pointer for next DAC a sample add #08h ; add 8 to get to DAC C pointer sacl DACc_ptr add #08h ; add 8 to get to DAC B pointer sacl DACb_ptr add #08h ; add 8 to get to DAC D pointer sacl DACd_ptr mar *,ar0 ; set ar0 as current AR
––––––––––––––––––––––––––––––––––––––
; DAC A lar ar0, DACa_ptr ; ar0 points to DAC a sample lacl * ; get DAC a sample into accumulator or #DACa_control; OR in DAC A control bits sacl temp ;
out temp, SDTR ; send data ;––––––––––––––––––––––––––––––––––––––––––––––––––– ; We must wait for transmission to complete before writing next word to the SDTR. ; TLV5604 interface does not allow the use of burst mode with the full packet rate, as ; we need a CLKX –ve edge to clock in last bit before FS goes high again, to allow SPI ; compatibility. ;–––––––––––––––––––––––––––––––––––––––––––––––––––
rpt #016h ; wait long enough for this configuration
nop ; of MCLK/CLKOUT1 rate
; DAC B
lar ar0, DACb_ptr ; ar0 points to DAC a sample
lacl * ; get DAC a sample into accumulator
or #DACb_control; OR in DAC B control bits
sacl temp ;
out temp, SDTR ; send data
rpt #016h ; wait long enough for this configuration
nop ; of MCLK/CLKOUT1 rate
––––––––––––––––––––––––––––––––––––––
––––––––––––––––––––––––––––––––––––––
18
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
APPLICATION INFORMATION
; DAC C lar ar0, DACc_ptr ; ar0 points to DAC a sample lacl * ; get DAC a sample into accumulator or #DACc_control; OR in DAC C control bits sacl temp ; out temp, SDTR ; send data rpt #016h ; wait long enough for this configuration nop ; of MCLK/CLKOUT1 rate
; DAC D lar ar0, DACd_ptr; ar0 points to DAC a sample lacl * ; get DAC a sample into accumulator or #DACd_control; OR in DAC D control bits sacl temp ; out temp, SDTR ; send data lacl r_ptr ; load rolling pointer to accumulator add #1h ; increment rolling pointer and #001Fh ; count 0–31 then wrap back round sacl r_ptr ; store rolling pointer rpt #016h ; wait long enough for this configuration nop ; of MCLK/CLKOUT1 rate ; now take CS high again lacl iosr_stat ; load acc with iosr status or #0001h ; set IO0 – CS high sacl temp ; out temp, IOSR ; clrc intm ; re-enable interrupts ret ; return from interrupt
.end
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
19
TLV5604
®
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
APPLICATION INFORMATION
TLV5604 interfaced to MCS
51 microcontroller
hardware interfacing
Figure 18 shows an example of how to connect the TLV5604 to an MCS
51 Microcontroller. The serial DAC input data and external control signals are sent via I/O Port 3 of the controller. The serial data is sent on the RxD line, with the serial clock output on the TxD line. Port 3 bits 3, 4, and 5 are configured as outputs to provide the DAC latch update (LDAC down pin (PD
) of the TLV5604 is pulled high to ensure that the DACs are enabled.
), chip select (CS) and frame sync (FS) signals for the TL V5604. The active low power
MCS
51
RxD
TxD P3.3 P3.4
P3.4
REF
TLV5604
SDIN SCLK LDAC CS
FS
REFINAB REFINCD
V
DD PD
VOUTA VOUTB VOUTC VOUTD
V
SS
Figure 18. TLV5604 Interfaced with MCS51
software
The example is the same as for the TMS320C203 in this datasheet, but adapted for a MCS51 controller. It generates a differential in-phase (sine) signal between the VOUTA and VOUTB pins, and it’s quadrature (cosine) signal as the differential signal between VOUTC and VOUTD.
The on-chip timer is used to generate interrupts at a fixed frequency . The related interrupt service routine pulses LDAC
low to update all 4 DACs simultaneously, then fetches and writes the next sample to all 4 DACs. The
samples are stored as a look-up table, which describes one full period of a sine wave. The serial port of the controller is used in Mode 0, which transmits 8 bits of data on RxD, accompanied by a
synchronous clock on TxD. Two writes concatenated together are required to write a complete word to the TL V5604. The CS
and FS signals are provided in the required fashion through control of IO port 3, which has
bit addressable outputs.
MCS is a registered trademark of Intel Corporation.
20
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
APPLICATION INFORMATION
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
; Processor: 80C51 ; ; Description: ; ; This program generates a differential in–phase (sine) on (OUTA–OUTB) and it’s ; quadrature (cosine) as a differential signal on (OUTC–OUTD). ; 1998, Texas Instruments Incorporated ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
NAME GENIQ MAIN SEGMENT CODE ISR SEGMENT CODE SINTBL SEGMENT CODE VAR1 SEGMENT DATA
STACK SEGMENT IDATA ;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Code start at address 0, jump to start ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CSEG AT 0
LJMP start ; Execution starts at address 0 on power–up. ;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Code in the timer0 interrupt vector ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
CSEG AT 0BH
LJMP timer0isr ; Jump vector for timer 0 interrupt is 000Bh ;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Global variables need space allocated ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG VAR1 Temp_ptr: DS 1 rolling_ptr: DS 1 ;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Interrupt service routine for timer 0 interrupts ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG ISR timer0isr:
PUSH PSW
PUSH ACC
TLV5604
–––––––––
––––––
––––––
––––––
––––––
––––––
––––––
––––––
––––––
CLR INT1 ; pulse LDAC low
SETB INT1 ; to latch all 4 previous values at the same time
CLR T0 ; set CS low
; The signal to be output on each DAC is a sine function. ; One cycle of a sine wave is held in a table @ sinevals as 32 samples of msb, ; lsb pairs (64 bytes). We have one pointer which rolls round this table, ; rolling_ptr, incrementing by 2 bytes (1 sample) on each interrupt (at the end of ; this routine).
; The DAC samples are read at an offset to this rolling pointer: ; DAC Function Offset from rolling_ptr ; A sine 0 ; B inverse sine 32 ; C cosine 16 ; D inverse cosine 48 MOV DPTR,#sinevals ; set DPTR to the start of the table of sine signal values MOV R7,rolling_ptr ; R7 holds the pointer into the sine table MOV A,R7 ; get DAC A msb MOVC A,@A+DPTR ; msb of DAC A is in the ACC CLR T1 ; transmit it – set FS low MOV SBUF,A ; send it out the serial port INC R7 ; increment the pointer in R7 MOV A,R7 ; to get the next byte from the table MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
; 1st thing done in timer isr => fixed period
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
21
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
APPLICATION INFORMATION
A_MSB_TX:
JNB TI,A_MSB_TX ; wait for transmit to complete CLR TI ; clear for new transmit MOV SBUF,A ; and send out the lsb of DAC A
; DAC C next ; DAC C codes should be taken from 16 bytes (8 samples) further on in the sine table ; – this gives a cosine function MOV A,R7 ; pointer in R7 ADD A,#0FH ; add 15 – already done one INC ANL A,#03FH ; wrap back round to 0 if > 64 MOV R7,A ; pointer back in R7
MOVC A,@A+DPTR ; get DAC C msb from the table ORL A,#01H ; set control bits to DAC C address
A_LSB_TX:
JNB TI,A_LSB_TX ; wait for DAC A lsb transmit to complete SETB T1 ; toggle FS CLR T1 CLR TI ; clear for new transmit MOV SBUF,A ; and send out the msb of DAC C
INC R7 ; increment the pointer in R7 MOV A,R7 ; to get the next byte from the table MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
C_MSB_TX:
JNB TI,C_MSB_TX ; wait for transmit to complete CLR TI ; clear for new transmit MOV SBUF,A ; and send out the lsb of DAC C
; DAC B next ; DAC B codes should be taken from 16 bytes (8 samples) further on ; in the sine table – this gives an inverted sine function MOV A,R7 ; pointer in R7 ADD A,#0FH ; add 15 – already done one INC ANL A,#03FH ; wrap back round to 0 if > 64 MOV R7,A ; pointer back in R7
MOVC A,@A+DPTR ; get DAC B msb from the table ORL A,#02H ; set control bits to DAC B address
C_LSB_TX:
JNB TI,C_LSB_TX ; wait for DAC C lsb transmit to complete SETB T1 ; toggle FS CLR T1 CLR TI ; clear for new transmit MOV SBUF,A ; and send out the msb of DAC B
; get DAC B LSB INC R7 ; increment the pointer in R7 MOV A,R7 ; to get the next byte from the table MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
B_MSB_TX:
JNB TI,B_MSB_TX ; wait for transmit to complete CLR TI ; clear for new transmit MOV SBUF,A ; and send out the lsb of DAC B
22
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
APPLICATION INFORMATION
; DAC D next ; DAC D codes should be taken from 16 bytes (8 samples) further on in the sine table ; – this gives an inverted cosine function MOV A,R7 ; pointer in R7 ADD A,#0FH ; add 15 – already done one INC ANL A,#03FH ; wrap back round to 0 if > 64 MOV R7,A ; pointer back in R7
MOVC A,@A+DPTR ; get DAC D msb from the table ORL A,#03H ; set control bits to DAC D address
B_LSB_TX:
JNB TI,B_LSB_TX ; wait for DAC B lsb transmit to complete SETB T1 ; toggle FS CLR T1 CLR TI ; clear for new transmit MOV SBUF,A ; and send out the msb of DAC D
INC R7 ; increment the pointer in R7 MOV A,R7 ; to get the next byte from the table MOVC A,@A+DPTR ; which is the lsb of this sample, now in ACC
D_MSB_TX:
JNB TI,D_MSB_TX ; wait for transmit to complete CLR TI ; clear for new transmit MOV SBUF,A ; and send out the lsb of DAC D
; increment the rolling pointer to point to the next sample ; ready for the next interrupt MOV A,rolling_ptr ADD A,#02H ; add 2 to the rolling pointer ANL A,#03FH ; wrap back round to 0 if > 64 MOV rolling_ptr,A ; store in memory again
D_LSB_TX:
JNB TI,D_LSB_TX ; wait for DAC D lsb transmit to complete CLR TI ; clear for next transmit
SETB T1 ; FS high SETB T0 ; CS high POP ACC POP PSW
RETI ;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Stack needs definition ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG STACK DS 10h ; 16 Byte Stack!
––––––
––––––
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
23
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
APPLICATION INFORMATION
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Main program code ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG MAIN
start:
MOV SP,#STACK–1 ; first set Stack Pointer
CLR A MOV SCON,A ; set serial port 0 to mode 0 MOV TMOD,#02H ; set timer 0 to mode 2 – auto-reload MOV TH0,#038H ; set TH0 for 5 kHs interrupts
SETB INT1 ; set LDAC = 1 SETB T1 ; set FS = 1 SETB T0 ; set CS = 1
SETB ET0 ; enable timer 0 interrupts SETB EA ; enable all interrupts
MOV rolling_ptr,A ; set rolling pointer to 0 SETB TR0 ; start timer 0
––––––
always:
JMP always ; while(1) ! RET
;––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ; Table of 32 sine wave samples used as DAC data ;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
RSEG SINTBL
sinevals:
DW 01000H DW 0903EH DW 05097H DW 0305CH DW 0B086H DW 070CAH DW 0F0E0H DW 0F06EH DW 0F039H DW 0F06EH DW 0F0E0H DW 070CAH DW 0B086H DW 0305CH DW 05097H DW 0903EH DW 01000H DW 06021H DW 0A0E8H DW 0C063H DW 040F9H DW 080B5H DW 0009FH DW 00051H DW 00026H DW 00051H DW 0009FH DW 080B5H DW 040F9H DW 0C063H DW 0A0E8H DW 06021H
END
––––––
––––––
24
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
14
1
0.069 (1,75) MAX
0.020 (0,51)
0.014 (0,35) 8
7
A
0.010 (0,25)
0.004 (0,10)
DIM
0.157 (4,00)
0.150 (3,81)
PINS **
0.010 (0,25)
0.244 (6,20)
0.228 (5,80)
8
M
Seating Plane
0.004 (0,10)
14
0.008 (0,20) NOM
0°–8°
16
Gage Plane
0.010 (0,25)
0.044 (1,12)
0.016 (0,40)
A MAX
A MIN
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
0.197
(5,00)
0.189
(4,80)
0.344
(8,75)
0.337
(8,55)
0.394
(10,00)
0.386
(9,80)
4040047/D 10/96
25
TLV5604
2.7-V TO 5.5-V 10-BIT 3-µS QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN
SLAS176A – DECEMBER 1997 – REVISED SEPTEMBER 1998
MECHANICAL DATA
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,65
14
1
1,20 MAX
0,30 0,19
8
6,60
4,50 4,30
6,20
7
A
0,15 0,05
M
0,10
Seating Plane
0,10
0,15 NOM
Gage Plane
0,25
0°–8°
0,75 0,50
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153
8
3,10
2,90
14
5,10
4,90
16
5,10
20
6,60
6,404,90
24
7,90
7,70
28
9,80
9,60
4040064/E 08/96
26
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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