Texas Instruments TLV5580IPWR, TLV5580IPW, TLV5580IDW, TLV5580IDWR, TLV5580EVM Datasheet

TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

8-Bit Resolution 80 MSPS Sampling
Analog-to-Digital Converter (ADC)

D

Low Power Consumption: 165 mW Typ
Using External references

D

Wide Analog Input Bandwidth: 700 MHz Typ

D

3.3 V Single-Supply Operation

D

3.3 V TTL/CMOS-Compatible Digital I/O

D

Internal Bottom and Top Reference
Voltages

D

Adjustable Reference Input Range

D

Power Down (Standby) Mode

D

Separate Power Down for Internal Voltage
References

D

Three-State Outputs

D

28-Pin Small Outline IC (SOIC) and Thin
Shrink SOP (TSSOP) Packages

D

Applications
– Digital Communications (IF Sampling)
– Flat Panel Displays
– High-Speed DSP Front-End

(TMS320C6000)
– Medical Imaging
– Graphics Processing (Scan Rate/Format

Conversion)
– DVD Read Channel Digitization

description

The TLV5580 is an 8-bit 80 MSPS high-speed A/D converter. It converts the analog input signal into 8-bit
binary-coded digital words up to a sampling rate of 80 MHz. All digital inputs and outputs are 3.3 V
TTL/CMOS-compatible.

The device consumes very little power due to the 3.3 V supply and an innovative single-pipeline architecture
implemented in a CMOS process. The user obtains maximum flexibility by setting both bottom and top voltage
references from user-supplied voltages. If no external references are available, on-chip references are
available for internal and external use. The full-scale range is 1 Vpp up to 1.6 Vpp, depending on the analog
supply voltage. If external references are available, the internal references can be disabled independently from
the rest of the chip, resulting in an even greater power saving.

While usable in a wide variety of applications, the device is specifically suited for the digitizing of high-speed
graphics and for interfacing to LCD panels or LCD/DMD projection modules . Other applications include DVD
read channel digitization, medical imaging and communications. This device is suitable for IF sampling of
communication systems using sub-Nyquist sampling methods because of its high analog input bandwidth.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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28
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16
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DRV

DD

D0
D1
D2
D3
D4
D5
D6
D7

DRV

SS

DV

SS

CLK

OE

DV

DD

AV

SS

AV

DD

AIN
CML
PWDN_REF
AV

SS

REFBO
REFBI
REFTI
REFTO
AV

SS

BG
AV

DD

STBY

DW OR PW PACKAGE

(TOP VIEW)

Copyright  1999, Texas Instruments Incorporated

TLV5580
8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

SOIC-28 TSSOP-28

0°C to 70°C TLV5580CDW TLV5580CPW

–40°C to 85°C TLV5580IDW TLV5580IPW

functional block diagram

SHA

DACADC

+

–

ADC

Correction Logic

Output Buffers

22222

D0(LSB)–D7(MSB)

2

2

SHA SHA SHA SHA SHA

The single-pipeline architecture uses 6 ADC/DAC stages and one final flash ADC. Each stage produces a
resolution of 2 bits. The correction logic generates its result using the 2-bit result from the first stage, 1 bit from
each of the 5 succeeding stages, and 1 bit from the final stage in order to arrive at an 8-bit result. The correction
logic guarantees no missing codes over the full operating temperature range.

TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

circuit diagrams of inputs and outputs

DV

DD

AV

DD

AV

DD

0.5 pF

Internal
Reference
Generator

REFTO
or
REFBO

AV

DD

REFBI

or

REFTI

OE

ALL DIGITAL INPUT CIRCUITS AIN INPUT CIRCUIT

REFERENCE INPUT CIRCUIT D0–D7 OUTPUT CIRCUIT

DRV

DD

DRV

SS

D_Out

D

TLV5580
8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AIN 26 I Analog input
AV

DD

16, 27 I Analog supply voltage

AV

SS

18, 23, 28 I Analog ground

BG 17 O Band gap reference voltage. A 1 µF capacitor (with an optional 0.1 µF capacitor in parallel) should be

connected between this terminal and A VSS for external filtering.
CLK 12 I Clock input. The input is sampled on each rising edge of CLK.
CML 25 O Common mode level. This voltage is equal to (A VDD – AVSS) ÷ 2. An external 0.1 µF capacitor should be

connected between this terminal and A VSS.
D0 – D7 2 – 9 O Data outputs. D7 is the MSB
DRV

DD

1 I Supply voltage for digital output drivers

DRV

SS

10 I Ground for digital output drivers

DV

DD

14 I Digital supply voltage
OE 13 I Output enable. When high the D0 – D7 outputs go in high-impedance mode.
DV

SS

11 I Digital ground
PWDN_REF 24 I Power down for internal reference voltages. A high on this terminal will disable the internal reference

circuit.

REFBI 21 I Reference voltage bottom input. The voltage at this terminal defines the bottom reference voltage for the

ADC. It can be connected to REFBO or to an externally generated reference level. Sufficient filtering
should be applied to this input. The use a 0.1 µF capacitor connected between REFBI and AVSS is
recommended. Additionaly, a 0.1 µF capacitor can be connected between REFTI and REFBI.

REFBO 22 O Reference voltage bottom output. An internally generated reference is available at this terminal. It can be

connected to REFBI or left unconnected. A 1 µF capacitor between REFBO and AVSS will provide
sufficient decoupling required for this output.

REFTI 20 I Reference voltage top input. The voltage at this terminal defines the top reference voltage for the ADC.

It can be connected to REFTO or to an externally generated reference level. Sufficient filtering should be
applied to this input. The use of a 0.1 µF capacitor between REFTI and A VSS is recommended. Additionaly,
a 0.1 µF capacitor can be connected between REFTI and REFBI.

REFTO 19 O Reference voltage top output. An internally generated reference is available at this terminal. It can be

connected to REFTI or left unconnected. A 1 µF capacitor between REFTO and A VSS will provide sufficient
decoupling required for this output.

STBY 15 I Standby input. A high level on this input enables a powerdown mode.

TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage: AV

DD

to AGND, DVDD to DGND –0.5 V to 4.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage: AV

DD

to DVDD, AGND to DGND –0.5 V to 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range to DGND –0.5 V to DV

DD

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range to AGND –0.5 V to AV

DD

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital output voltage applied from external source to DGND –0.5 V to DV

DD

+ 0.5 V. . . . . . . . . . . . . . . . . . .

Reference voltage input range to AGND: V

(REFTI)

, V

(REFTO)

, V

(REFBI)

, V

(REFBO)

–0.5 V to AVDD + 0.5 V

Operating free-air temperature range, T

A

: TLV5580C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5580I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–55°C to 150° C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions over operating free-temperature range

power supply

MIN NOM MAX UNIT

AV

DD

Supply voltage

DV

DD

3 3.3 3.6 V

DRV

DD

analog and reference inputs

MIN NOM MAX UNIT

Reference input voltage (top), V

(REFTI)

(NOM) – 0.2 2 + (AVDD – 3) (NOM) + 0.2 V

Reference input voltage (bottom), V

(REFBI)

0.8 1 1.2 V

Reference voltage differential, V

(REFTI)

– V

(REFBI)

1 + (AVDD – 3) V

Analog input voltage, V

(AIN)

V

(REFBI)

V

(REFTI)

V

digital inputs

MIN NOM MAX UNIT

High-level input voltage, V

IH

2.0 DV

DD

V

Low-level input voltage, V

IL

DGND 0.2xDV

DD

V

Clock period, t

c

12.5 ns

Pulse duration, clock high, t

w(CLKH)

5.25 ns

Pulse duration, clock low, t

w(CLKL)

5.25 ns

TLV5580
8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions with f

CLK

= 80 MSPS and use

of external voltage references (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AV

DD

57 71

I

DD

Operating supply current

DV

DD

AVDD = DVDD = 3.3 V, DRVDD = 3 V,

p

–

3 3.6

mA

DRV

DD

C

L

= 15 F,

V

I

= 1

MHz

, –1

dBFS

5 7.5

p

PWDN_REF = L 213 270

PDPower dissipation

PWDN_REF = H 165 210

mW

P

D(STBY)

Standby power STBY = H, CLK held high or low 11 15

digital logic inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

IH

High-level input current on CLK

†

AVDD = DVDD = DRVDD = CLK = 3.6 V 10 µA

I

IL

Low-level input current on digital inputs
(OE

, STDBY, PWDN_REF, CLK)

AVDD = DVDD = DRVDD = 3.6 V,
Digital inputs at 0 V

10 µA

CIInput capacitance 5 pF

†

IIH leakage current on other digital inputs (OE

, STDBY , PWDN_REF) is not measured since these inputs have an internal pull-down resistor of

4 KΩ to DGND.

logic outputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

High-level output voltage

AVDD = DVDD = DRVDD = 3 V at IOH = 50 µA,
Digital output forced high

2.8 V

V

OL

Low-level output voltage

AVDD = DVDD = DRVDD = 3.6 V at IOL = 50 µA,
Digital output forced low

0.1 V

C

O

Output capacitance 5 pF

I

OZH

High-impedance state output current to
high level

10 µA

I

OZL

High-impedance state output current to
low level

AV

DD

=

DV

DD

=

DRV

DD

= 3.6

V

10 µA

TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions with f

CLK

= 80 MSPS and use

of external voltage references (unless otherwise noted)

dc accuracy

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TA = 25°C –2 ±1 2 LSB

Integral nonlinearity (INL), best-fit

Internal references (see Note 1)

TA = –40°C to 85°C –2.4 ±1 2.4 LSB
Differential nonlinearity (DNL) Internal references (see Note 2), TA = –40°C to 85°C –1 ±0.6 1.3 LSB
Zero error

5 %FS

Full scale error

AV

DD

=

DV

DD

=

3.3 V, DRV

DD

=

3 V

See Note 3

5 %FS

NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero

occurs 1/2 LSB before the first code transition. The full–scale point is defined as a level 1/2 LSB beyond the last code transition.

The deviation is measured from the center of each particular code to the true straight line between these two endpoints.

2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure
indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under
test (i.e., (last transition level – first transition level) ÷ (2n – 2)). Using this definition for DNL separates the effects of gain and offset
error. A minimum DNL better than –1 LSB ensures no missing codes.

3. Zero error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch
the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the
bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (256).

Full-scale error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch
the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5
LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references
divided by the number of ADC output levels (256).

analog input

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

C

I

Input capacitance 4 pF

reference input (AVDD = DVDD = DRVDD = 3.6 V)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

R

ref

Reference input resistance 200 Ω

I

ref

Reference input current 5 mA

reference outputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

(REFTO)

Reference top offset voltage

Absolute min/max values valid

2.07 2 + [(AVDD – 3) ÷ 2] 2.21 V

V

(REFBO)

Reference bottom offset voltage

and tested for AVDD = 3.3 V

1.09 1 + [(AVDD – 3) ÷ 2] 1.21 V

TLV5580
8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions with f

CLK

= 80 MSPS and use

of external voltage references (unless otherwise noted) (continued)

dynamic performance

†

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fin = 1 MHz 6.6 7.0
fin = 4.43 MHz 6.6 7.0

Effective number of bits, ENOB

fin = 15 MHz 6.5

Bits

fin = 76 MHz 6.6
fin = 1 MHz 41.5 43.5
fin = 4.43 MHz 41.5 43.5

Signal-to-total harmonic distortion

+

noise, S/(THD+N)

fin = 15 MHz 41

dB

fin = 76 MHz 41.5
fin = 1 MHz –46 –50
fin = 4.43 MHz –45.5 –49

Total harmonic distortion (THD)

fin = 15 MHz –44

dB

fin = 76 MHz –45.5
fin = 1 MHz 48 53

p

fin = 4.43 MHz 48 53

Spurious free dynamic range (SFDR)

fin = 15 MHz 46.5

dB

fin = 76 MHz 48.5

Analog input full-power bandwidth, BW See Note 4 700 MHz

p

°

Differential phase, DP

f

clk

= 40 MHz, fin = 4.43 MHz,

0.8

°

clk in

20 IRE amplitude vs. full-scale of 140 IRE

Differential gain, DG

20 IRE am litude vs. full scale of 140 IRE

0.6

%

†

Based on analog input voltage of – 1 dBFS referenced to a 1.3 Vpp full-scale input range and using the external voltage references at
f

clk

= 80 MSPS with AVDD = DVDD = 3.3 V and DRVDD = 3.0 V at 25°C.

NOTE 4: The analog input bandwidth is defined as the maximum frequency of a –1 dBFS input sine that can be applied to the device for which

an extra 3 dB attenuation is observed in the reconstructed output signal.

TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions with f

CLK

= 80 MSPS and use

of external voltage references (unless otherwise noted) (continued)

timing requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

clk

Maximum conversion rate 80 MHz

f

clk

Minimum conversion rate 10 kHz

t

d(o)

Output delay time (see Figure 1) CL = 10 pF, See Notes 5 and 6 9 ns

t

h(o)

Output hold time CL = 2 pF, See Note 5 2 ns

t

d(pipe)

Pipeline delay (latency) See Note 6 4.5 4.5 4.5

CLK

cycles

t

d(a)

Aperture delay time 3 ns

t

j(a)

Aperture jitter

1.5 ps, rms

t

dis

Disable time, OE rising to Hi-Z

See Note 5

5 8 ns

t

en

Enable, OE falling to valid data 5 8 ns

NOTES: 5. Output timing t

d(o)

is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The digital

output load is not higher than 10 pF.

Output hold time t

h(o)

is measured from the 1.5 V level of the CLK input falling edge to the 10%/90% level of the digital output. The

digital output is load is not less than 2 pF.

Aperture delay t

d(A)

is measured from the 1.5 V level of the CLK input to the actual sampling instant.
The OE signal is asynchronous.
OE timing t

dis

is measured from the V

IH(MIN)

level of OE to the high-impedance state of the output data. The digital output load is

not higher than 10 pF.

OE timing ten is measured from the V

IL(MAX)

level of OE to the instant when the output data reaches V

OH(min)

or V

OL(max)

output

levels. The digital output load is not higher than 10 pF.

6. The number of clock cycles between conversion initiation on an input sample and the corresponding output data being made
available from the ADC pipeline. Once the data pipeline is full, new valid output data is provided on every clock cycle. In order to
know when data is stable on the output pins, the output delay time t

d(o)

(i.e., the delay time through the digital output buffers) needs

to be added to the pipeline latency . Note that since the max. t

d(o)

is more than 1/2 clock period at 80 MHz; data cannot be reliably

clocked in on a rising edge of CLK at this speed. The falling edge should be used.

D0–D7 N–4 N–3 N–2 N–1 N N+1

N

N+1

N+2

N+3

N+4

N+5

t

j(A)

t

d(A)

V

IL

(max)

1.5 V

t

w(CLKH)

t

w(CLKL)

1/f

CLK

t

h(o)

1.5 V

t

d(o)

t

dis

t

en

CLK

OE

90%
10%

V

IH(min)

t

d(pipe)

V

OH(min)

V

OL(max)

V

IL(max)

V

IH

(min)

Figure 1. Timing Diagram

TLV5580
8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

performance plots at 25°C

–0.4

–1

0 50 100 150

DNL – LSB

0

0.6

ADC Code

1

200 250

0.8

0.4

0.2

–0.2

–0.6
–0.8

Figure 2. DNL vs Input Code At 80 MSPS (With External Reference, PW Package)

–1

–2

0 50 100 150

INL – LSB

0

1

ADC Code

2

200 250

1.5

0.5

–0.5

–1.5

Figure 3. INL vs Input Code At 80 MSPS (With External Reference, PW Package)

TLV5580

8-BIT, 80 MSPS LOW-POWER A/D CONVERTER

SLAS205A – DECEMBER 1998 – REVISED JANUARY 1999

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

performance plots at 25°C (continued)

80 MSPS

40 MSPS

60 MSPS

25
20

10

0

0 102030405060

S(THD+N) – dB

40

45

Analog Input Frequency – MHz

50

70 80 90 100

35

30

15

5

Figure 4. S/(THD+N) vs VIN At 80 MSPS (Internal Reference),

60 MSPS (External Reference), 40 MSPS (External Reference)

–40

–60

–90

0 5 10 15 20 25 30

Power – dBFS

–30

–20

f – Frequency – MHz

–10

0

–50

–70
–80

Figure 5. Spectral Plot fIN = 1.011 MHz At 60 MSPS