Texas Instruments TLV320VD30PN Datasheet

D

General-Purpose Analog Interface Circuit
for VDSL System

D

12 Bit, 22 MHz ADC and DAC

D

Provides 11 MHz Bandwidth Performance

D

Supports Central Office and Remote
Terminal Applications

D

Excellent Power Management by
Enabling/Disabling Major Functional
Blocks When in Power Control Mode

D

Remote Activation Feature With Selectable
Wake-Up Tone Frequency

D

Integrated Equalizer to Partially
Compensate for the Roll Off in Twisted Pair
Telephone Cable

D

Numerically Controlled Oscillator With
Resolution <1 ppm, Range of 250 ppm
Using External Crystal

description

TLV320VD30

VDSL CODEC

SLWS086 – JUNE 1999

D

26 dB RFI Suppression

D

Programmable Receive Amplifier Operating
From 0 dB to 20 dB, in Steps of 1 dB

D

Programmable T ransmitter Output Power
Level From –13 dBm to 11 dBm

D

Enable/Disable of All Major Blocks During
Power Mode

D

Digital Loopback Test Mode

D

Internal Voltage References

D

Serial Control Port

D

Conversion Rate up to 22.08 MHz

D

Selectable Offset Binary or 2s Complement
Data Format

D

3.3 V Operation

D

80-Pin PN Package

The TLV320VD30 is an analog front end (AFE) device for VDSL systems. The TLV320VD30 provides a
transmitter and a receiver. Both the transmitter and receiver have up to 11 MHz-bandwidth performance. The
device can be used for central office and remote VDSL applications. The transmitter consists of a 12-bit/22 MHz
DAC and a programmable line driver interface. The receiver consists of a 12-bit/22 MHz ADC, a programmable
gain amplifier, a compromise equalizer , and an RFI cancellation circuit. The device includes a tone detect circuit,
and a numerically controlled crystal oscillator.

The TLV320VD30 provides two parallel ports for fast data transfers and a serial port for device control. The
parallel ports are 12-pin ports with data transfer rates of up to 22 MHz per 12-bit word. One parallel port is
dedicated to DAC input, the other parallel port is dedicated to ADC output. The serial port supports both write
and read operations. The serial data transfer rate is 1.38 MHz per bit. Data is transferred in 16-bit words.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

TLV320VD30
VDSL CODEC

SLWS086 – JUNE 1999

PN PACKAGE

(TOP VIEW)

VBG

AGND4

AVDD4

XIN

XOUT

CLKIN

EXTCLKEN

RESET

TEST3

RFIADAPTEN

TXENABLE
RXENABLE

SENABLE

SIN

DVDD

DGND

DAC<11>

DAC<10>

DAC<9>
DAC<8>

RSET

GUARDGND

59 58 57 56 5560 54

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

23

1

GUARDVDD

A VDD3

AGND3

SENSETXP

5678

4

A VDD2

RXP

RXM

49 48

TXP

TXBIASP

52 51 5053

TL V320VD30PN

10 11 12 13

9

TXBIASM

AGND2

47 46 45 44

14 15 16 17

TXM

SENSETXM

TDVREFM

TDVREFP

TESTM

VCM

43 42 41

18 19 20

TESTP

VCMSENSEM

40

VCMSENSEP

39

TESTCLK

38

AGND1

37

AVDD1

36

ADCGNDREF

35

NC

34

ADCGND

33

ADCVDD

32

GUARDGND

31

GUARDVDD

30

TONEDETECT

29

DGNDIO

28

DVDDIO

27

ADC<11>

26

ADC<10>

25

ADC<9>

24

ADC<8>

23

ADC<7>

22

ADC<6>

21

DAC<7>

DAC<6>

NC – No internal connection

DAC<5>

DAC<4>

DAC<3>

DAC<2>

DAC<1>

DAC<0>

CLK

DVDDIO

DGNDIO

SCLK

SOUT

ADC<0>

ADC<1>

SREADY

ADC<3>

ADC<4>

ADC<2>

ADC<5>

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

TLV320VD30

VDSL CODEC

SLWS086 – JUNE 1999

DAC<11:0>

CLKIN

XIN

XOUT

CLKOUT

ADC<11:0>

TXENABLE

RXENABLE

TONEDETECT

SENABLE

SCLK

SIN

SOUT

SREADY

12

bits

bits

12

9

bits

ADC

Control

Control

NCXO

Power

Serial

BUS

DAC

TXPOWER
M
U
X

2

bits

Compromise

Equalizer

NCXO
TXPOWER

CEQ

PGA

3 bits

Line Driver

Interface

RFI

Cancel

I

PGA

5

bits

Tone

Detect

TXP
TXM

SENSETXP
SENSETXM

VCMSENSEM
VCMSENSEP

RFIADAPTEN

Q

RXP
RXM

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TLV320VD30

I/O

DESCRIPTION

VDSL CODEC

SLWS086 – JUNE 1999

Terminal Functions

TERMINAL

NAME NO.

ADC<0,11> 15–26 O Digital receive data. Data format can be straight offset binary or 2s complement. Data output on falling

ADCGND 33 Analog ADC ground
ADCGNDREF 35 ADC ground reference
ADCVDD 32 Analog ADC VDD, 3.3 V
AGND1 37 Analog ground
AGND2 49 Analog ground
AGND3 56 Analog ground
AGND4 62 Analog ground
TESTM 43 I/O Reserved for test. No connection.
TESTP 41 I/O Reserved for test. No connection.
TESTCLK 38 I/O Reserved for test. No connection.
AVDD1 36 Analog VDD, 3.3 V
AVDD2 52 Analog VDD, 3.3 V
AVDD3 57 Analog VDD, 3.3 V
AVDD4 63 Analog VDD, 3.3 V
CLK 10 O System clock, 22.08 MHz
CLKIN 66 I External clock input
DAC<11:0> 77,78,

79,80,

1–8
DGND 76 Digital ground
DGNDIO 11 Digital I/O ground
DGNDIO 28 Digital I/O ground
DVDD 75 Digital VDD, 3.3 V
DVDDIO 9 Digital I/O VDD, 2.5 V/3.3 V
DVDDIO 27 Digital I/O VDD, 2.5 V/3.3 V
EXTCLKEN 67 I External Clock Enable
GAURDGND 31 Isolation ground.
GUARDGND 59 Isolation ground
GUARDVDD 30 Isolation VDD, 3.3 V
GUARDVDD 58 Isolation V
NC 34 No connection
RESET 68 I Device reset
RFIADAPTEN 70 I RFI cancellation adapt enable
RSET 60 I/O Resistor current set requires an external 621 Ω, 1% resistor
RXM 50 I Receiver input (–)
RXP 51 I Receiver input (+)
RXENABLE 72 I Receive enable (active high). RXENABLE signal provides a minimum of 5 µs warning of an impending

TEST3 69 I Reserved for test. No connection.
SCLK 13 O Serial bus clock (frequency = CLK/16 or 1.38 MHz)
SENABLE 73 I Serial bus enable (active high). SENABLE high indicates that the DSP interface is requesting activation of

edge of clock.

I Digital transmit data. Data format can be straight offset binary or 2s complement. Data input on rising edge

of clock.

DD

receive burst. This signal remains High until the DMT engine has received the last ADC data word.

the serial input.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

TLV320VD30

VDSL CODEC

SLWS086 – JUNE 1999

Terminal Functions (Continued)

TERMINAL

NAME NO.

SENSETXM 46 I/O Transmitter current sense(–). Connects to external line driver.
SENSETXP 55 I/O Transmitter current sense(+). Connects to external line driver.
SIN 74 I Serial bus input
SOUT 12 O Serial bus output. SOUT is high impedance when SENABLE is low.
SREADY 14 O SREADY indicates when the device is ready to output serial data.
TDVREFM 45 I/O T one detector reference V(–). Connects to an external resistor divider.
TDVREFP 44 I/O T one detector reference V(+). Connects to an external resistor divider
TONEDETECT 29 O Wake-up tone detector output. Remains low when the tone detector is disabled. When the tone detector is

TXM 47 I/O Transmitter output (–). Connects to external line driver.
TXP 54 I/O Transmitter output (+). Connects to external line driver.
TXBIASM 48 I/O Transmitter bias current (–). Connects to external line driver.
TXBIASP 53 I/O Transmitter bias current (+). Connects to external line driver.
TXENABLE 71 I Transmitter enable (active high). TXENABLE signal provides up to 5 µs of warning of an impending transmit

VBG 61 I/O Voltage bandgap reference, 1.25 V. Requires an external 0.1 µF capacitor.
VCM 42 I/O Common mode voltage reference. Connects to an internally generated 1.5 V reference, requires an external

VCMSENSEM 40 I/O Reference for VCMSENSEM
VCMSENSEP 39 I/O Transformer common mode input signal used by the RFI canceller . Connects to transformer line-side center

XIN 64 I/O 22.08 MHz crystal input
XOUT 65 I/O 22.08 MHz crystal output

enabled, goes high when a wake-up tone is present.

burst. This signal remains High until the last TX data word has been registered.

0.1 µF bypass capacitor.

tap through an external attenuator.

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage, AVDD, DVDD, DVDDIO –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range –0.5 V to AVDD+0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.5 V to DVDD+0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating
Operating
Storage temperature range, T

virtual junction temperature range, T
free-air temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

str

–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

J

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TLV320VD30

Power dissipation

mW

High-level input voltage, V

V

Low-level input voltage, V

V

High-level input current, I

A

Low-level input current, I

A

High-level output voltage, V

V

Low-level output voltage, V

V

High-level output current, I

mA

Low-level output current, I

mA

VDSL CODEC

SLWS086 – JUNE 1999

recommended operating conditions

power supply

MIN NOM MAX UNIT

AVDD 3 3.3 3.6

Supply voltage

p

PSRR (see Note 2) Frequency = 150 kHz –45 dB

NOTES: 1. Does not include line driver.

2. PSRR measurement are made with the TX and RX channels idle and a 400 mVpp signal.

digital inputs/outputs

p

p

p

p

p

p

p

p

DVDD 3 3.3 3.6
DVDDIO 2.5/3.3
TX active (see Note 1) 110 200
RX active 500 700
RX standby mode 100
Power-down mode, TX/RX disabled 60

MIN NOM MAX UNIT

DVDD, DVDDIO = 3.3 V 2.4

IH

DVDD = 3.3 V, DVDDIO = 2.5 V 2

IL

IH

iL

DVDD, DVDDIO = 3.3 V 0.6
DVDD = 3.3 V, DVDDIO = 2.5 V 0.6
DVDD, DVDDIO = 3.3 V 100
DVDD = 3.3 V, DVDDIO = 2.5 V 100
DVDD, DVDDIO = 3.3 V 100
DVDD = 3.3 V, DVDDIO = 2.5 V 100
DVDD, DVDDIO = 3.3 V 2.4

OH

DVDD = 3.3 V, DVDDIO = 2.5 V 2
DVDD, DVDDIO = 3.3 V 0.6

OL

DVDD = 3.3 V, DVDDIO = 2.5 V 0.6
DVDD, DVDDIO = 3.3 V 1

OH

DVDD = 3.3 V, DVDDIO = 2.5 V 1
DVDD, DVDDIO = 3.3 V 1

OL

DVDD = 3.3 V, DVDDIO = 2.5 V 1

V

µ

µ

clock inputs

Input clock frequency 22.08 MHz
Input clock duty cycle 45% 50% 55%

reference voltage

VCM (common mode) AVDD = 3.3 V 1.4 1.6 V
VBG (band gap) AVDD = 3.3 V 1.20 1.25 1.30 V

NCXO

Step size AVDD = 3.3 V 1 ppm
Range AVDD = 3.3 V 200 250 ppm

6

MIN NOM MAX UNIT

MIN NOM MAX UNIT

MIN NOM MAX UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV320VD30

VDSL CODEC

SLWS086 – JUNE 1999

electrical characteristics over recommended operating free-air temperature range, TA = 255C,
AVDD = 3.3 V, DVDD = 3.3 V, f

CLKIN

TXDAC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Signal bandwidth 43k 11.04M Hz
Conversion rate 22.08 MHz

AC Performance

Single tone
Transmit 2nd harmonic 1.4 MHz at –3 dbfs –77 –60 –55 dB
Transmit 3rd harmonic 1.4 MHz at –3 dbfs –75 –67 –67 dB
THD 1.4 MHz at –3 dbfs –64 –58 –54 dB
SNR 1.4 MHz at –3 dbfs –56 –55 –54 dB
SNDR (see Note 3) 1.4 MHz at 0 dbfs –46 –45 –44 dB

Channel delay 90 150 nS

NOTE 3: Signal-to-noise and distortion

= 22.08 MHz (unless otherwise noted)

1.4 MHz at –3 dbfs –54 –53 –51 dB

1.4 MHz at –6 dbfs –51 –50 –49 dB

1.4 MHz at –12 dbfs –42 –41 –40 dB

1.4 MHz at –18 dbfs –31 –30 –29 dB

1.4 MHz at –24 dbfs –22 –20 –21 dB

1.4 MHz at –30 dbfs –10 –9 –8 dB

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7