Texas Instruments TLV320DAC3101 Datasheet

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Low-Power Stereo Audio DAC With Audio Processing

and Stereo Class-D Speaker Amplifier

1 Introduction

1.1 Features

1

• Stereo Audio DAC With 95-dB SNR

• Supports 8-kHz to 192-kHz Sample Rates

• Stereo 1.29-W Class-D BTL 8-Ω Speaker Driver
With Direct Battery Connection

• 25 Built-In Processing Blocks (PRB_P1 –
PRB_P25) Providing Biquad Filters, DRC, and 3D

• Digital Sine-Wave Generator for Beeps and Key­Clicks (PRB_P25)

• User-Programmable Biquad and FIR Filters

• Two Single-Ended Inputs With Mixing and Output
Level Control

• Stereo Headphone or Lineout and Class-D
Speaker Outputs Available

• Microphone Bias

• Headphone Detection

• Digital Mixing Capability

• Pin Control or Register Control for Digital-Playback
Volume-Control Settings

• Programmable PLL for Flexible Clock Generation

• I2S, Left-Justified, Right-Justified, DSP, and TDM
Audio Interfaces

• I2C Control With Register Auto-Increment

• Full Power-Down Control

• Power Supplies:
– Analog: 2.7 V–3.6 V
– Digital Core: 1.65 V–1.95 V
– Digital I/O: 1.1 V–3.6 V
– Class-D: 2.7 V–5.5 V (SPLVDD and SPRVDD ≥

AVDD)

• 5-mm × 5-mm 32-QFN Package

TLV320DAC3101

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

1.2 Applications

• Portable Audio Devices

• Mobile Internet Devices

• e-Books

1.3 Description

The TLV320DAC3101 device is a low-power,
highly integrated, high-performance DAC with
selectable digital audio processing blocks and
24-bit stereo playback.

The device integrates headphone drivers and
speaker drivers. The TLV320DAC3101 device
has a suite of built-in processing blocks for
digital audio processing. The digital audio data
format is programmable to work with popular
audio standard protocols (I2S, left-justified, and
right-justified) in master, slave, DSP, and TDM
modes. Bass boost, treble, or EQ is supported
by the programmable digital signal-processing
block. An on-chip PLL provides the high-speed
clock needed by the digital signal-processing
block. The volume level is controlled by either
pin control or by register control. The audio
functions are controlled using the I2C serial
bus.

The TLV320DAC3101 device has a
programmable digital sine-wave generator and
is available in a 32-pin QFN package.

Device Information

PART NUMBER PACKAGE BODY SIZE

TLV320DAC3101 QFN (RHB) 5.00 mm x 5.00 mm

(1) For more information, see , Mechanical, Packaging, and

Orderable Information.

(1)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

Serial

Interface

and

Clocks

SDIN

BCLK

WCLK

MCLK PLL

HPVDDHPVSS

SPRVDDSPRVSS

AVDDAVSS

SPLVSS

SPLVDD

VOL/MICDET

SCL

SDA

GPIOGPIO1

DAC

DAC

MIXER
P1/R35

RESET

DVDDDVSS

IOVDD

IOVSS

AIN2

AIN2

AIN1

AIN1

2V/2.5V/AVDD

MICBIAS

Note:Normally,
MCLKisPLL input;
however,BCLKor
GPIO1canalsobe
PLL input.

AudioOutputStage
PowerManagement

De-Pop

and

SoftStart

RCCLK

P1/R33–R34

P1/R46

I C

2

LeftDAC

RightDAC

SPLP
SPLM

Class-DSpeaker

Driver

6dBto24dB

(6-dBsteps)

Analog

Attenuation

0dBto –78dB

andMute

(0.5-dBsteps)

P1/R42

P1/R38

Class A/B

Headphone/Lineout

Driver

0dBto9dB
(1-dBsteps)

Analog

Attenuation

HPL

P1/R36

P1/R40

P1/R30–R31

L Data

L Data

RData

RData

(L+R)/2Data

(L+R)/2Data

P0/R63/D3–D2

P0/R63/D5–D4

P0/R116

7-Bit

Vol

ADC

LeftandRight

Volume-ControlRegister

P0/R117

DigitalVol

24dBto

Mute

Process-

ing

Blocks

P0/R64–R66

S

0dBto –78dB

andMute

(0.5-dBsteps)

SPRP
SPRM

Class-DSpeaker

Driver

6dBto24dB

(6-dBsteps)

Analog

Attenuation

0dBto –78dB

andMute

(0.5-dBsteps)

P1/R43

P1/R39

Class A/B

Headphone/Lineout

Driver

0dBto9dB
(1-dBsteps)

Analog

Attenuation

HPR

P1/R37

P1/R41

P1/R30–R31

S

0dBto –78dB

andMute

(0.5-dBsteps)

B0360-02

TLV320DAC3101

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

1.4 Functional Block Diagram

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2

Introduction Copyright © 2010–2018, Texas Instruments Incorporated

Figure 1-1. Functional Block Diagram

This data manual is designed using PDF document-viewing features that allow quick access
to information. For example, performing a global search on page 0 / register 27 produces all
references to this page and register in a list. This makes it easy to traverse the list and find
all information related to a page and register. Note that the search string must be of the
indicated format. Also, this document includes document hyperlinks to allow the user to
quickly find a document reference. To come back to the original page, click the green left
arrow near the PDF page number at the bottom of the file. The hot-key for this function is alt­left arrow on the keyboard. A different way to find information quickly is to use the PDF

NOTE

bookmarks.

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SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (May 2012) to Revision B Page

• Added Device Information table, ESD Ratings table, Feature Description section, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation

Support section, and Mechanical, Packaging, and Orderable Information section. ......................................... 1

• Added Power-Supply Sequence section to the Device Initialization section ................................................ 19

• Changed Section 6.3.10.1.2 diagrams for PRB_P2/5/8/10/13/15/18/21/24/25 to reflect that the DRC_HPF filter

cannot be bypassed when the DRC is turned off .............................................................................. 26

• Added sequence for inserting a beep in the middle of an already-playing signal and note text following script in

the Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25) section........................................ 42

• Changed PRB_Rx to PRB_Px in DAC Setup section.......................................................................... 48

• Changed text from: "the rising edge of the word clock..." To: "the rising edge of the word clock..." in the DSP Mode 60

• Changed DOSR note in Page 0 / Register 14 by switching multiple value for Filter Type A and Filter Type C........ 68

• Changed description in Page 0 / Register 14 to remove parameters for miniDSP......................................... 68

• Changed reset value to include all bits instead of just two (xx) ............................................................... 74

• Deleted reference to Dig_Mic_In in Page 0 / Register 54 table for bits D2-D1 ............................................. 75

• Changed values in Page 0 / Register 69 (0x45): DRC Control 2 ............................................................. 78

• Changed Page 0, Register 70, bit D3-D0 decay rate value for 0000 from DR = 1.5625e

• Switched D1 and D0 descriptions so that D1 is for SP and D0 is for HP in Page 1 / Register 30 table ................ 81

• Changed Page 1 / Register 40, D1 to reserved................................................................................. 84

• Changed Page 1 / Register 41, D1 to reserved................................................................................. 84

• Added Figure 9-1 ................................................................................................................. 100

–3

to DR = 0.015625 ........ 78

Changes from Original (January, 2010) to Revision A Page

• Changed register 36 to register 35................................................................................................ 24

• Added D6–D0 to the Register Value column heading and changed Analog Attenuation to Analog Gain............... 45

• Deleted Analog Volume Control for Headphone and Speaker Outputs (for D7=0) table and added table note to

D7=1 table............................................................................................................................ 45

• Changed page 0 to page 1 in section 5.5.12.1. ................................................................................. 46

• Added 80 MHz ≤ (PLL_CLKIN × J.D × R/P) ≤ 110 MHz and 4 ≤ R × J ≤ 259 underneath Equation 8.................. 55

• Added Timer section and image after PLL section.............................................................................. 57

• Added table note to Page 0 / Register 64 (0x40): DAC VOLUME CONTROL.............................................. 76

• Changed D0=1 to Reserved in Page 1 / Register 33........................................................................... 82

• Removed extraneous cross-references for deleted table. ..................................................................... 83

• Added table note following Page 1 / Register 40 ............................................................................... 84

• Added table note to Page 1 / Register 41 (0x29): HPR Driver. ............................................................... 84

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Revision HistoryCopyright © 2010–2018, Texas Instruments Incorporated

3

P0048-14

AVSSSPRVSS

IOVSS

SPRVDD

24123222321420519618717

8

16

25

15

26

14

27

13

28

12

29

1130

1031

932

NC

SPRM

AIN2

SPLP

AIN1

SPLVDD

MICBIAS

SPLVSS

VOL/MICDET

SPLM

SCL

DVSS

SDA

AVDD

RHB Package

(Top View)

SPRP

IOVDD

HPL

DVDD

HPVDD

NC

HPVSS

DIN

HPR

WCLK

RESET

BCLK

GPIO1

MCLK

TLV320DAC3101

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

3 Pin Configuration and Functions

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3.1 Pin Attributes

Table 3-1. Pin Functions

PIN

NAME NO.

AIN1 13 I Analog input #1 routed to output mixer
AIN2 14 I Analog input #2 routed to output mixer
AVDD 17 – Analog power supply
AVSS 16 – Analog ground
BCLK 7 I/O Audio serial bit clock
DIN 5 I Audio serial data input
DVDD 3 – Digital power – digital core
DVSS 18 – Digital ground
GPIO1 32 I/O General-purpose input/output and multifunction pin
HPL 27 O Left-channel headphone/line driver output
HPR 30 O Right-channel headphone/line driver output
HPVDD 28 – Headphone/line driver and PLL power
HPVSS 29 – Headphone/line driver and PLL ground
IOVDD 2 – Interface power
IOVSS 1 – Interface ground
MCLK 8 I External master clock
MICBIAS 12 – Microphone bias for external microphone
NC 4, 15 I No connecton
RESET 31 I Device reset
SDL 10 I/O I2C control bus clock input
SDA 9 I/O I2C control bus data input
SPLM 19 O Left-channel class-D speaker-driver inverting output

4

Pin Configuration and Functions Copyright © 2010–2018, Texas Instruments Incorporated

I/O DESCRIPTION

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Table 3-1. Pin Functions (continued)

PIN

NAME NO.

SPLP 22 O Left-channel class-D speaker-driver noninverting output
SPLVDD 21 – Left-channel class-D speaker-driver power supply
SPLVSS 20 – Left-channel class-D speaker-driver power supply ground
SPRM 23 O Right-channel class-D speaker-driver inverting output
SPRP 26 O Right-channel class-D speaker-driver noninverting output
SPRVDD 24 – Right-channel class-D speaker-driver power supply
SPRVSS 25 – Right-channel class-D speaker-driver power-supply ground

VOL/MICDET 11 I
WCLK 6 I/O Audio serial word clock

I/O DESCRIPTION

Volume control or headphone detection. Note that microphone detection is also available on
devices that have an ADC.

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5

TLV320DAC3101

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

Table of Contents

1 Introduction............................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 1

1.3 Description............................................ 1

1.4 Functional Block Diagram ............................ 2

2 Revision History ......................................... 3

3 Pin Configuration and Functions..................... 4

3.1 Pin Attributes ......................................... 4

4 Specifications ............................................ 7

4.1 Absolute Maximum Ratings .......................... 7

4.2 ESD Ratings.......................................... 7

4.3 Recommended Operating Conditions................ 7

4.4 Thermal Information .................................. 8

4.5 Electrical Characteristics ............................. 8

4.6 Power Dissipation Ratings ........................... 9

2

4.7 I

S, LJF, and RJF Timing in Slave Mode ........... 10

4.8 DSP Timing in Master Mode ........................ 11

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4.9 DSP Timing in Slave Mode ......................... 12

2

4.10 I

C Interface Timing................................. 13

4.11 Typical Characteristics .............................. 14

5 Parameter Measurement Information .............. 17

6 Detailed Description ................................... 18

6.1 Overview ............................................ 18

6.2 Functional Block Diagram........................... 19

6.3 Feature Description ................................. 19

6.4 Register Map ........................................ 65

7 Application and Implementation .................... 97

7.1 Application Information.............................. 97

7.2 Typical Application .................................. 97

8 Power Supply Recommendations .................. 99

9 Layout................................................... 100

9.1 Layout Guidelines.................................. 100

9.2 Layout Example.................................... 100

6

Table of Contents Copyright © 2010–2018, Texas Instruments Incorporated

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4 Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

AVDD to AVSS -0.3 3.9 V
DVDD to DVSS -0.3 2.5 V
HPVDD to HPVSS -0.3 3.9 V
SPLVDD to SPLVSS -0.3 6 V
SPRVDD to SPRVSS -0.3 6 V
IOVDD to IOVSS -0.3 3.9 V
Digital input voltage IVOSS – 0.3 IVODD + 0.3 V
Analog input voltage AVSS – 0.3 AVDD + 0.3 V
Operating temperature –40 85 °C
Junction temperature (TJ Max) 105 °C
Storage temperature, T
Power dissipation (TJMax - TA)/R
R

thermal impedance (with thermal pad soldered to board) 35 °C/W

θJA

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

stg

(1)

MIN MAX UNIT

-55 150 °C

θJA

W

4.2 ESD Ratings

VALUE UNIT

V

(ESD)

Electrostatic
discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged-device model (CDM), per JEDEC specification JESD22-C101

(1)

(2)

±2000
±1000

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

(1)

AVDD

Referenced to AVSS
DVDD Referenced to DVSS
HPVDD Referenced to HPVSS
SPLVDD
SPRVDD

(1)

(1)

Power-supply voltage

Referenced to SPLVSS

Referenced to SPRVSS
IOVDD Referenced to IOVSS

Speaker impedance

Resistance applied across class-D

output pins (BTL)

Headphone impedance AC coupled to R

V

I

Analog audio full-scale input voltage AVDD = 3.3 V, single-ended 0.707 V
Stereo line output load impedance AC coupled to R

(3)

MCLK
f

SCL

T

A

Master clock frequency IOVDD = 3.3 V 50 MHz
SCL clock frequency 400 kHz
Operating free-air temperature –40 105 °C

(1) To minimize battery-current leakage, the SPLVDD and SPRVDD voltage levels must not be below the AVDD voltage level.
(2) All grounds on board are tied together, so they must not differ in voltage by more than 0.2-V maximum for any combination of ground

signals. By use of a wide trace or ground plane, ensure a low-impedance connection between HPVSS and DVSS.

(3) The maximum input frequency must be 50 MHz for any digital pin used as a general-purpose clock.

(2)

(2)

(2)

(2)

(2)

(2)

2.7 3.3 3.6

1.65 1.8 1.95

2.7 3.3 3.6

2.7 5.5

2.7 5.5

1.1 3.3 3.6

V

8 Ω

L

L

16 Ω

RMS

10 kΩ

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7

TLV320DAC3101

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

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4.4 Thermal Information

TLV320DAC3101

THERMAL METRIC

(1)

UNITRHB (VQFN)

32 PINS

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

R

θJC(bot)

Junction-to-ambient thermal resistance 32.7 °C/W
Junction-to-case (top) thermal resistance 23.2 °C/W
Junction-to-board thermal resistance 6.6 °C/W
Junction-to-top characterization parameter 0.3 °C/W
Junction-to-board characterization parameter 6.5 °C/W
Junction-to-case (bottom) thermal resistance 2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

4.5 Electrical Characteristics

At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPLVDD, SPRVDD = 3.6 V, DVDD = 1.8 V, fS(audio) = 48 kHz, CODEC_CLKIN
= 256 × fS, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INTERNAL OSCILLATOR—RC_CLK

Oscillator frequency 8.2 MHz

VOLUME CONTROL PIN (ADC); VOL/MICDET pin enabled

Input voltage range
Input capacitance 2 pF

Volume control steps 128 Steps

MICROPHONE BIAS

Voltage output

Voltage regulation

DAC HEADPHONE OUTPUT, AC-coupled load = 16 Ω (single-ended), driver gain = 0 dB, parasitic capacitance = 30 pF

Full-scale output voltage (0 dB) Output common-mode setting = 1.65 V 0.707 V
SNR Signal-to-noise ratio Measured as idle-channel noise, A-weighted
THD Total harmonic distortion 0-dBFS input –85 –65 dB
THD+N Total harmonic distortion + noise 0-dBFS input –82 –60 dB

Mute attenuation 87 dB
PSRR Power-supply rejection ratio

P

O

Maximum output power

(3)

VOL/MICDET pin configured as volume control (page 0 / register 116, bit D7 = 1 and
page 0 / register 67, bit D7 = 0)

Page 1 / register 46, bits D1–D0 = 10 2.25 2.5 2.75
Page 1 / register 46, bits D1–D0 = 01 2
At 4-mA load current, page 1 / register 46, bits D1–D0 = 10 (MICBIAS = 2.5 V) 5
At 4-mA load current, page 1 / register 46, bits D1–D0 = 01 (MICBIAS = 2 V) 7

(1) (2)

Ripple on HPVDD (3.3 V) = 200 mVp-p at 1 kHz –62 dB
RL= 32 Ω, THD+N = –60 dB 20
RL= 16 Ω, THD+N = –60 dB 60

0

80 95 dB

(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a

20-Hz to 20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may

result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.

(3) DAC to headphone-out PSRR measurement is calculated as PSRR = 20 × log(ΔV

HPL

/ ΔV

HPVDD

).

0.5 x

AVDD

V

V

mV

RMS

mW

8

Specifications Copyright © 2010–2018, Texas Instruments Incorporated

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Electrical Characteristics (continued)

At 25°C, AVDD = HPVDD = IOVDD = 3.3 V, SPLVDD, SPRVDD = 3.6 V, DVDD = 1.8 V, fS(audio) = 48 kHz, CODEC_CLKIN
= 256 × fS, PLL = Off, VOL/MICDET pin disabled (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DAC LINEOUT (HP Driver in Lineout Mode)

SNR Signal-to-noise ratio Measured as idle-channel noise, A-weighted 95 dB
THD Total harmonic distortion 0-dBFS input, 0-dB gain –86 dB
THD+N Total harmonic distortion + noise 0-dBFS input, 0-dB gain –82 dB

DAC Digital Interpolation Filter Characteristics

See Section 6.3.10.1.4 for DAC interpolation filter characteristics.

DAC Output to Class-D Speaker Output; Load = 8 Ω (Differential), 50 pF

SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM = 1.8 V, DAC input = 0 dBFS,

Output voltage

Output, common-mode

SNR Signal-to-noise ratio

THD Total harmonic distortion SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM = 1.8 V, class-D gain = 6 dB –67 dB
THD+N Total harmonic distortion + noise SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM = 1.8 V, class-D gain = 6 dB –66 dB

PSRR Power-supply rejection ratio

Mute attenuation 110 dB

P

O

DAC Power Consumption

For DAC power consumption based on the selected processing block, see Section 6.3.8.

DIGITAL INPUT/OUTPUT

V

IH

V

IL

V

OH

V

OL

Maximum output power

Output-stage leakage current

SPLVDD = SPRVDD = 4.3 V, device

is powered for direct battery

connection

Logic family CMOS

Logic Level

Capacitive load 10 pF

(4)

(4) DAC to speaker-out PSRR measurement is calculated as PSRR = 20 × log(ΔV

class-D gain = 6 dB, THD = –16.5 dB
SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM = 1.8 V, DAC input = –2 dBFS,

class-D gain = 6 dB, THD = –20 dB
SPLVDD = SPRVDD = 3.6 V, BTL measurement, DAC input = mute, CM = 1.8 V,

class-D gain = 6 dB
SPLVDD = SPRVDD = 3.6 V, BTL measurement, class-D gain = 6 dB, measured as

idle-channel noise, A-weighted (with respect to full-scale output value of 2.2 VRMS)

(2)

SPLVDD = SPRVDD = 3.6 V, BTL measurement, ripple on SPLVDD/SPRVDD = 200
mVp-p at 1 kHz

SPLVDD = SPRVDD = 3.6 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB,
THD = 10%

SPLVDD = SPRVDD = 4.3 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB,
THD = 10%

SPLVDD = SPRVDD = 5.5 V, BTL measurement, CM = 1.8 V, class-D gain = 18 dB,
THD = 10%

SPLVDD = SPRVDD = 4.3 V, device is powered down (power-up-reset condition) 80 nA

IIH= 5 µA, IOVDD ≥ 1.6 V
IIH= 5 µA, IOVDD < 1.6 V IOVDD
IIL= 5 µA, IOVDD ≥ 1.6 V –0.3
IIL= 5 µA, IOVDD < 1.6 V 0
IOH= 2 TTL loads

IOL= 2 TTL loads

SPL(P + M)

/ ΔV

SPLVDD

(1)

0.7 ×

IOVDD

0.8 ×

IOVDD

).

2.2

2.1

1.8 V

87 dB

–44 dB

540 mW

790 mW

1.29 W

IOVDD

IOVDD

V

0.3 ×

0.1 ×

RMS

V

4.6 Power Dissipation Ratings

This data was taken using 2-oz. (0,071-mm thick) trace and copper pad that is soldered to a JEDEC high-K, standard 4-layer
3-inch × 3-inch (7,62-cm × 7,62-cm) PCB.

Power Rating at 25°C Derating Factor Power Rating at 70°C Power Rating at 85°C

2.3 W 28.57 mW/°C 1 W 0.6 W

SpecificationsCopyright © 2010–2018, Texas Instruments Incorporated

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9

T0145-11

WCLK

BCLK

DIN

t (WS)

h

t (BCLK)

H

t (DI)

S

t (BCLK)

L

t (DI)

h

t (WS)

S

t

r

t

f

TLV320DAC3101

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

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4.7 I2S, LJF, and RJF Timing in Slave Mode

All specifications at 25°C, DVDD = 1.8 V

Note: All timing specifications are measured at characterization.

PARAMETER

tH(BCLK) BCLK high period 35 35 ns
tL(BCLK) BCLK low period 35 35 ns
ts(WS) WCLK setup 8 6 ns
th(WS) WCLK hold 8 6 ns
ts(DI) DIN setup 8 6 ns
th(DI) DIN hold 8 6 ns
t

r

t

f

Rise time 4 4 ns
Fall time 4 4 ns

Figure 4-1. I2S, LJF, and RJF Timing in Slave Mode

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

UNIT

10

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T0146-09

WCLK

BCLK

DIN

t (WS)

d

t (WS)

d

t (DI)

S

t (DI)

h

t

f

t

r

TLV320DAC3101

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4.8 DSP Timing in Master Mode

All specifications at 25°C, DVDD = 1.8 V
Note: All timing specifications are measured at characterization.

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

PARAMETER

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

UNIT

td(WS) WCLK delay 45 20 ns
ts(DI) DIN setup 8 8 ns
th(DI) DIN hold 8 8 ns
t

r

t

f

Rise time 25 10 ns
Fall time 25 10 ns

Figure 4-2. DSP Timing in Master Mode

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T0146-10

WCLK

BCLK

DIN

t (WS)

h

t (WS)

h

t (BCLK)

L

t

r

t

f

t (DI)

S

t (BCLK)

H

t (DI)

h

t (WS)

S

t (WS)

S

TLV320DAC3101

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

4.9 DSP Timing in Slave Mode

All specifications at 25°C, DVDD = 1.8 V

Note: All timing specifications are measured at characterization.

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PARAMETER

IOVDD = 1.1 V IOVDD = 3.3 V

MIN MAX MIN MAX

UNIT

tH(BCLK) BCLK high period 35 35 ns
tL(BCLK) BCLK low period 35 35 ns
ts(WS) WCLK setup 8 8 ns
th(WS) WCLK hold 8 8 ns
ts(DI) DIN setup 8 8 ns
th(DI) DIN hold 8 8 ns
t

r

t

f

Rise time 4 4 ns
Fall time 4 4 ns

Figure 4-3. DSP Timing in Slave Mode

12

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STO

STA STA

STO

SDA

SCL

t

BUF

t

LOW

t

SU;STA

t

HIGH

t

HD;STA

t

r

t

HD;STA

t

HD;DAT

t

SU;DAT

t

SU;STO

t

f

T0295-02

TLV320DAC3101

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4.10 I2C Interface Timing

All specifications at 25°C, DVDD = 1.8 V

Note: All timing specifications are measured at characterization.

PARAMETER

f

SCL

t

HD;STA

t

LOW

t

HIGH

t

SU;STA

t

HD;DAT

t

SU;DAT

t

r

t

f

t

SU;STO

t

BUF

C

b

SCL clock frequency 0 100 0 400 kHz
Hold time (repeated) START condition.

After this period, the first clock pulse is
generated.

LOW period of the SCL clock 4.7 1.3 μs
HIGH period of the SCL clock 4 0.6 μs
Setup time for a repeated START

condition
Data hold time: for I2C bus devices 0 3.45 0 0.9 μs
Data set-up time 250 100 ns
SDA and SCL rise time 1000 20 + 0.1C
SDA and SCL fall time 300 20 + 0.1C
Set-up time for STOP condition 4 0.8 μs
Bus free time between a STOP and

START condition
Capacitive load for each bus line 400 400 pF

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

Standard Mode Fast Mode

MIN TYP MAX MIN TYP MAX

4 0.8 μs

4.7 0.8 μs

4.7 1.3 μs

Figure 4-4. I2C Interface Timing

UNIT

b
b

300 ns
300 ns

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13

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14

G025

THD+N − T otal Harmonic Distortion + Noise − dB

PO − Output Power − W

HPVDD = 3.3 V
CM = 1.65 V

HPVDD = 3.6 V
CM = 1.8 V

HPVDD = 3 V
CM = 1.5 V

HPVDD = 2.7 V
CM = 1.35 V

IOVDD = 3.3 V
DVDD = 1.8 V
Gain = 9 dB
RL = 16 Ω

f − Frequency − kHz

−160

−140

−120

−100

−80

−60

−40

−20

0

20

0 5 10 15 20

Amplitude − dBFS

G023

AVDD = HPVDD = 3.3 V
IOVDD = SPLVDD = 3.3 V
DVDD = 1.8 V

f − Frequency − kHz

−160

−140

−120

−100

−80

−60

−40

−20

0

20

0 5 10 15 20

Amplitude − dBFS

G026

AVDD = HPVDD = 3.3 V
IOVDD = SPLVDD = 3.3 V
DVDD = 1.8 V

TLV320DAC3101

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

4.11 Typical Characteristics

4.11.1 DAC Performance

Figure 4-5. Amplitude vs Frequency

FFT – DAC to Line Output

Figure 4-6. Amplitude vs Frequency

FFT – DAC to Headphone Output

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Specifications Copyright © 2010–2018, Texas Instruments Incorporated

Figure 4-7. Total Harmonic Distortion + Noise vs Output Power

Headphone Output Power

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−80

−70

−60

−50

−40

−30

−20

−10

0

0.0 0.5 1.0 1.5 2.0

G014

THD+N − T otal Harmonic Distortion + Noise − dB

PO − Output Power − W

Driver Gain
= 6 dB

Driver Gain
= 12 dB

AVDD = HPVDD = 3.3 V
IOVDD = 3.3 V
SPLVDD = 5.5 V
DVDD = 1.8 V
RL = 8 Ω

Driver Gain
= 24 dB

Driver Gain
= 18 dB

−80

−70

−60

−50

−40

−30

−20

−10

0

0.0 0.5 1.0 1.5 2.0

G015

THD+N − T otal Harmonic Distortion + Noise − dB

PO − Output Power − W

AVDD = 3.3 V
HPVDD = 3.3 V
IOVDD = 3.3 V
DVDD = 1.8 V
Gain = 18 dB
RL = 8 Ω

SPLVDD = 5.5 V

SPLVDD = 4.3 V

SPLVDD = 3.3 V

SPLVDD = 3.6 V

TLV320DAC3101

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4.11.2 Class-D Speaker Driver Performance

Figure 4-8. Total Harmonic Distortion + Noise vs Output Power

Max Class-D Speaker-Driver Output Power

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

Figure 4-9. Total Harmonic Distortion + Noise vs Output Power

Class-D Speaker-Driver Output Power

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15

I − Current − mA

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

V − Voltage − V

G016

Micbias = 2 V

Micbias = 2.5 V

Micbias = AVDD (3.3 V)

f − Frequency − kHz

−160

−140

−120

−100

−80

−60

−40

−20

0

20

0 5 10 15 20

Amplitude − dBFS

G024

AVDD = HPVDD = 3.3 V
IOVDD = SPLVDD = 3.3 V
DVDD = 1.8 V

f − Frequency − kHz

−160

−140

−120

−100

−80

−60

−40

−20

0

20

0 5 10 15 20

Amplitude − dBFS

G027

AVDD = HPVDD = 3.3 V
IOVDD = SPLVDD = 3.3 V
DVDD = 1.8 V

TLV320DAC3101

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

4.11.3 Analog Bypass Performance

H

Figure 4-10. Amplitude vs Frequency

FFT – Line-In Bypass to Line Output

4.11.4 MICBIAS Performance

H

Figure 4-11. Amplitude vs Frequency

FFT – Line-In Bypass to Headphone Output

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Specifications Copyright © 2010–2018, Texas Instruments Incorporated

Figure 4-12. Voltage vs Current

MICBIAS

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5 Parameter Measurement Information

All parameters are measured according to the conditions described in Section 4.

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6 Detailed Description

6.1 Overview

The device is a highly integrated stereo-audio DAC for portable computing, communication, and
entertainment applications. A register-based architecture eases integration with microprocessor-based
systems through standard serial-interface buses. This device supports the two-wire I2C bus interface
which provides full register access. All peripheral functions are controlled through these registers and the
onboard state machines.

The device consists of the following blocks:

• Stereo Audio DAC

• Dynamic Range Compressor (DRC)

• Digital sine-wave generator for clicks and beeps

• Stereo headphone and lineout amplifier

• Pin-controlled or register-controlled volume level

• Power-down de-pop and power-up soft start

• Analog inputs

• I2C control interface

• Power-down control block
Following a toggle of the RESET pin or a software reset, the device operates in the default mode. The I2C

interface is used to write to the control registers to configure the device.

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The I2C address assigned to the device is 001 1000. This device always operates in an I2C slave mode.
All registers are 8-bit, and all writable registers have read-back capability. The device auto-increments to
support sequential addressing and can be used with the I2C fast mode. When the device is reset, all
appropriate registers are updated by the host processor to configure the device as needed by the user.

18

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Serial

Interface

and

Clocks

SDIN

BCLK

WCLK

MCLK PLL

HPVDDHPVSS

SPRVDDSPRVSS

AVDDAVSS

SPLVSS

SPLVDD

VOL/MICDET

SCL

SDA

GPIOGPIO1

DAC

DAC

MIXER
P1/R35

RESET

DVDDDVSS

IOVDD

IOVSS

AIN2

AIN2

AIN1

AIN1

2V/2.5V/AVDD

MICBIAS

Note:Normally,
MCLKisPLL input;
however,BCLKor
GPIO1canalsobe
PLL input.

AudioOutputStage
PowerManagement

De-Pop

and

SoftStart

RCCLK

P1/R33–R34

P1/R46

I C

2

LeftDAC

RightDAC

SPLP
SPLM

Class-DSpeaker

Driver

6dBto24dB

(6-dBsteps)

Analog

Attenuation

0dBto –78dB

andMute

(0.5-dBsteps)

P1/R42

P1/R38

Class A/B

Headphone/Lineout

Driver

0dBto9dB
(1-dBsteps)

Analog

Attenuation

HPL

P1/R36

P1/R40

P1/R30–R31

L Data

L Data

RData

RData

(L+R)/2Data

(L+R)/2Data

P0/R63/D3–D2

P0/R63/D5–D4

P0/R116

7-Bit

Vol

ADC

LeftandRight

Volume-ControlRegister

P0/R117

DigitalVol

24dBto

Mute

Process-

ing

Blocks

P0/R64–R66

S

0dBto –78dB

andMute

(0.5-dBsteps)

SPRP
SPRM

Class-DSpeaker

Driver

6dBto24dB

(6-dBsteps)

Analog

Attenuation

0dBto –78dB

andMute

(0.5-dBsteps)

P1/R43

P1/R39

Class A/B

Headphone/Lineout

Driver

0dBto9dB
(1-dBsteps)

Analog

Attenuation

HPR

P1/R37

P1/R41

P1/R30–R31

S

0dBto –78dB

andMute

(0.5-dBsteps)

B0360-02

TLV320DAC3101

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6.2 Functional Block Diagram

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

6.3 Feature Description

6.3.1 Power-Supply Sequence

The requires multiple power supply rails for operation. All the power rails must be powered up for the
device to operate at the fullest potention. The following is the recommended power-up sequencing for
proper operation:

1. Power up SPLVDD and SPRVDD

2. Power up IOVDD

3. Power up DVDD shortly after IOVDD

4. Power up AVDD and HPVDD
Although not necessary, if the system requires, during shutdown, remove the power supplies in the

reverse order of the above sequence.

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6.3.2 Reset

The internal logic must be initialized to a known condition for proper device function. To initialize the
device to its default operating condition, the hardware reset pin (RESET) must be pulled low for at least 10
ns. For this initialization to work, both the IOVDD and DVDD supplies must be powered up. TI
recommends that while the DVDD supply powers up, the RESET pin is pulled low.

The device can also be reset via software reset. Writing a 1 into page 0 / register 1, bit D0 resets the
device.

6.3.3 Device Start-Up Lockout Times

After the is initialized through hardware reset at power up or software reset, the internal memories are
initialized to default values. This initialization takes place within 1 ms after pulling the RESET signal high.
During this initialization phase, no register-read or register-write operation should be performed on DAC
coefficient buffers. Also, no block within the codec should be powered up during the initialization phase.

6.3.4 PLL Start-Up

Whenever the PLL is powered up, a start-up delay of approximately of 10 ms occurs after the power-up
command of the PLL and before the clocks are available to the codec. This delay is to ensure stable
operation of the PLL and clock-divider logic.

6.3.5 Power-Stage Reset

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The power-stage-only reset is used to reset the device after an overcurrent latching shutdown has
occurred. Using this reset re-enables the output stage without resetting all of the registers in the device.
Each of the four power stages has its own dedicated reset bit. The headphone power-stage reset is
performed by setting page 1 / register 31, bit D7 for HPL and by setting page 1 / register 31, bit D6 for
HPR. The speaker power-stage reset is performed by setting page 1 / register 32, bit D7 for SPLP and
SPLM, and by setting page 1 / register 32, bit D6 for SPRP and SPRM.

6.3.6 Software Power Down

By default, all circuit blocks are powered down following a reset condition. Hardware power up of each
circuit block can be controlled by writing to the appropriate control register. This approach allows the
lowest power-supply current for the functionality required. However, when a block is powered down, all of
the register settings are maintained as long as power is still being applied to the device.

6.3.7 Audio Analog I/O

The has a stereo audio DAC. The device supports a wide range of analog interfaces to support different
headsets and analog outputs. The has features to interface output drivers (8-Ω, 16-Ω, 32-Ω). A special
circuit has also been included in the to insert a short key-click sound into the stereo audio output. The key­click sound is used to provide feedback to the user when a particular button is pressed or item is selected.
The specific sound of the keyclick can be adjusted by varying several register bits that control its
frequency, duration, and amplitude (see Section 6.3.10.7).

6.3.8 Digital Processing Low-Power Modes

The device can be tuned to minimize power dissipation, to maximize performance, or to an operating point
between the two extremes to best fit the application. The choice of processing blocks, PRB_P1 to
PRB_P25 for stereo playback, also influences the power consumption. In fact, the numerous processing
blocks have been implemented to offer a choice among configurations having a different balance of power
optimization and signal-processing capabilities.

6.3.8.1 DAC Playback on Headphones, Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V,

HPVDD = 3.3 V

DOSR = 128, Processing Block = PRB_P7 (Interpolation Filter B)

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Power consumption = 24.28 mW

DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 24.5 mW

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Table 6-1. PRB_P7 Alternative Processing Blocks, 24.28 mW

PROCESSING BLOCK FILTER ESTIMATED POWER CHANGE (mW)

PRB_P1 A 1.34
PRB_P2 A 2.86
PRB_P3 A 2.11
PRB_P8 B 1.18

PRB_P9 B 0.53
PRB_P10 B 1.89
PRB_P11 B 0.87
PRB_P23 A 1.48
PRB_P24 A 2.89
PRB_P25 A 3.23

Table 6-2. PRB_P7 Alternative Processing Blocks, 24.5 mW

PROCESSING BLOCK FILTER ESTIMATED POWER CHANGE (mW)

PRB_P1 A 1.17

PRB_P2 A 2.62

PRB_P3 A 2

PRB_P8 B 0.99

PRB_P9 B 0.5
PRB_P10 B 1.46
PRB_P11 B 0.66
PRB_P23 A 1.43
PRB_P24 A 2.69
PRB_P25 A 2.92

6.3.8.2 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V

DOSR = 128, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 15.4 mW

Table 6-3. PRB_P12 Alternative Processing Blocks, 15.4 mW

PROCESSING BLOCK FILTER ESTIMATED POWER CHANGE (mW)

PRB_P4 A 0.57
PRB_P5 A 1.48

PRB_P6 A 1.08
PRB_P13 B 0.56
PRB_P14 B 0.27
PRB_P15 B 0.89
PRB_P16 B 0.31

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DOSR = 64, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 15.54 mW

Table 6-4. PRB_P12 Alternative Processing Blocks, 15.54 mW

PROCESSING BLOCK FILTER ESTIMATED POWER CHANGE (mW)

PRB_P4 A 0.37

PRB_P5 A 1.23

PRB_P6 A 1.15
PRB_P13 B 0.43
PRB_P14 B 0.13
PRB_P15 B 0.85
PRB_P16 B 0.21

6.3.8.3 DAC Playback on Headphones, Stereo, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V

DOSR = 768, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 22.44 mW

Table 6-5. PRB_P7 Alternative Processing Blocks, 22.44 mW

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PROCESSING BLOCK FILTER ESTIMATED POWER CHANGE (mW)

PRB_P1 A 0.02
PRB_P2 A 0.31
PRB_P3 A 0.23
PRB_P8 B 0.28

PRB_P9 B –0.03
PRB_P10 B 0.14
PRB_P11 B 0.05
PRB_P23 A 0.29
PRB_P24 A 0.26
PRB_P25 A 0.47

DOSR = 384, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 22.83 mW

Table 6-6. PRB_P7 Alternative Processing Blocks, 22.83 mW

PROCESSING BLOCK FILTER ESTIMATED POWER CHANGE (mW)

PRB_P1 A 0.27

PRB_P2 A 0.4

PRB_P3 A 0.34

PRB_P8 B 0.2

PRB_P9 B 0.08
PRB_P10 B 0.24
PRB_P11 B 0.12
PRB_P23 A 0.23
PRB_P24 A 0.42
PRB_P25 A 0.46

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6.3.8.4 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V

DOSR = 768, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 14.49 mW

Table 6-7. PRB_P12 Alternative Processing Blocks, 14.49 mW

PROCESSING BLOCK FILTER ESTIMATED POWER CHANGE (mW)

PRB_P4 A –0.04
PRB_P5 A 0.2

PRB_P6 A –0.01
PRB_P13 B 0.1
PRB_P14 B 0.05
PRB_P15 B –0.03
PRB_P16 B 0.07

DOSR = 384, Processing Block = PRB_P12 (Interpolation Filter B)

Power consumption = 14.42 mW

Table 6-8. PRB_P12 Alternative Processing Blocks, 14.42 mW

PROCESSING BLOCK FILTER ESTIMATED POWER CHANGE (mW)

PRB_P4 A 0.16

PRB_P5 A 0.3

PRB_P6 A 0.2
PRB_P13 B 0.15
PRB_P14 B 0.07
PRB_P15 B 0.18
PRB_P16 B 0.09

6.3.8.5 DAC Playback on Headphones, Stereo, 192 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V

DOSR = 32, Processing Block = PRB_P17 (Interpolation Filter C)

Power consumption = 27.05 mW

Table 6-9. PRB_P17 Alternative Processing Blocks, 27.05 mW

PROCESSING BLOCK FILTER ESTIMATED POWER CHANGE (mW)

PRB_P18 C 5.28
PRB_P19 C 1.98

6.3.8.6 DAC Playback on Line Out (10 k-Ω load), Stereo, 48 kHz, DVDD = 1.8 V, AVDD = 3 V, HPVDD = 3 V

DOSR = 64, Processing Block = PRB_P7 (Interpolation Filter B)

Power consumption = 12.85 mW

6.3.9 Analog Signals

The analog signals consist of:

• Microphone bias (MICBIAS)

• Analog inputs AIN1 and AIN2

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• Analog outputs, class-D speaker driver and headphone and lineout driver, providing output capability
for the DAC, AIN1, AIN2 or a mix of the three

6.3.9.1 MICBIAS

The device includes a microphone bias circuit that sources up to 4 mA of current and is programmable to
a 2-V, 2.5-V, or AVDD level. The level is controlled by writing to page 1 / register 46, bits D1–D0. Table 6-

10 lists this functionality.

D1 D0 FUNCTIONALITY

0 0 MICBIAS output is powered down
0 1 MICBIAS output is powered to 2 V
1 0 MICBIAS output is powered to 2.5 V
1 1 MICBIAS output is powered to AVDD

During normal operation, MICBIAS can be set to 2.5 V for better performance. However, based on the
model of the selected microphone, optimal performance can be obtained at another setting and therefore
the performance at a given setting must be verified.

The lowest current consumption occurs when MICBIAS is powered down. The next-lowest current
consumption occurs when MICBIAS is set at AVDD.

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Table 6-10. MICBIAS Settings

6.3.9.2 Analog Inputs AIN1 and AIN2

AIN1 (pin 13) and AIN2 (pin 14) are inputs to the output mixer along with the DAC output. Page 1 /
register 35 provides control signals for determining the signals routed through the output mixer. The output
of the output mixer then can be attenuated or gained through the class-D and, or, headphone and lineout
drivers.

6.3.10 Audio DAC and Audio Analog Outputs

Each channel of the stereo audio DAC consists of a digital-audio processing block, a digital interpolation
filter, a digital delta-sigma modulator, and an analog reconstruction filter. This high oversampling ratio
(typically DOSR is between 32 and 128) exhibits good dynamic range by ensuring that the quantization
noise generated within the delta-sigma modulator stays outside of the audio frequency band. Audio analog
outputs include stereo headphone, or lineouts, and stereo class-D speaker outputs.

6.3.10.1 DAC

The stereo-audio DAC supports data rates from 8 kHz to 192 kHz. Each channel of the stereo audio-DAC
consists of a signal-processing engine with fixed processing blocks, a digital interpolation filter, a multibit
digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide
enhanced performance at low sampling rates through increased oversampling and image filtering, thereby
keeping quantization noise generated within the delta-sigma modulator and signal images strongly
suppressed within the audio band to beyond 20 kHz. To handle multiple input rates and optimize power
dissipation and performance, the device allows the system designer to program the oversampling rates
over a wide range from 1 to 1024 by configuring page 0 / register 13 and page 0 / register 14. The system
designer can choose higher oversampling ratios for lower input data rates and lower oversampling ratios
for higher input data rates.

24

The DAC channel includes a built-in digital interpolation filter to generate oversampled data for the delta­sigma modulator. The interpolation filter can be chosen from three different types, depending on required
frequency response, group delay, and sampling rate.

Detailed Description Copyright © 2010–2018, Texas Instruments Incorporated

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DAC power up is controlled by writing to page 0 / register 63, bit D7 for the left channel and bit D6 for the
right channel. The left-channel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit
D7. The right-channel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit D6.

6.3.10.1.1 DAC Processing Blocks

The device implements signal-processing capabilities and interpolation filtering through processing blocks.
These fixed processing blocks give users the choice of how much and what type of signal processing they
use and which interpolation filter is applied.

The choices among these processing blocks allow the system designer to balance power conservation
and signal-processing flexibility. Table 6-11 gives an overview of all available processing blocks of the
DAC channel and their properties. The resource-class column gives an approximate indication of power
consumption for the digital (DVDD) supply; however, based on the out-of-band noise spectrum, the analog
power consumption of the drivers (HPVDD) may differ.

The signal processing blocks available are:

• First-order IIR

• Scalable number of biquad filters

• 3D effect

• Digital sine-wave (beep) generator

The processing blocks are tuned for common cases and can achieve high image rejection or low group
delay in combination with various signal-processing effects such as audio effects and frequency shaping.
The available first-order IIR and biquad filters have fully user-programmable coefficients.

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

Table 6-11. Overview – DAC Predefined Processing Blocks

PROCESSING

BLOCK NO.

PRB_P1 A Stereo No 3 No No No 8
PRB_P2 A Stereo Yes 6 Yes No No 12
PRB_P3 A Stereo Yes 6 No No No 10
PRB_P4 A Left No 3 No No No 4
PRB_P5 A Left Yes 6 Yes No No 6
PRB_P6 A Left Yes 6 No No No 6
PRB_P7 B Stereo Yes 0 No No No 6
PRB_P8 B Stereo No 4 Yes No No 8

PRB_P9 B Stereo No 4 No No No 8
PRB_P10 B Stereo Yes 6 Yes No No 10
PRB_P11 B Stereo Yes 6 No No No 8
PRB_P12 B Left Yes 0 No No No 3
PRB_P13 B Left No 4 Yes No No 4
PRB_P14 B Left No 4 No No No 4
PRB_P15 B Left Yes 6 Yes No No 6
PRB_P16 B Left Yes 6 No No No 4
PRB_P17 C Stereo Yes 0 No No No 3
PRB_P18 C Stereo Yes 4 Yes No No 6
PRB_P19 C Stereo Yes 4 No No No 4
PRB_P20 C Left Yes 0 No No No 2
PRB_P21 C Left Yes 4 Yes No No 3
PRB_P22 C Left Yes 4 No No No 2
PRB_P23 A Stereo No 2 No Yes No 8
PRB_P24 A Stereo Yes 5 Yes Yes No 12
PRB_P25 A Stereo Yes 5 Yes Yes Yes 12

INTERPOLATION

FILTER

CHANNEL

FIRST-ORDER

IIR AVAILABLE

NUMBER OF

BIQUADS

DRC 3D

BEEP

GENERATOR

RESOURCE

CLASS

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Detailed DescriptionCopyright © 2010–2018, Texas Instruments Incorporated

25

Interp.

Filter

B,C

IIR

to

Modulator

Digital

Volume

Ctrl

from

Interface

´

Interp.

Filter

A,B

BiQuad

F

BiQuad

E

BiQuad

D

BiQuad

C

BiQuad

B

BiQuad

A

IIR

to

Modulator

Digital

Volume

Ctrl

from

Interface

´

Interp.

Filter

A or B

*

DRC

HPF

BiQuad

F

BiQuad

E

BiQuad

D

BiQuad

C

BiQuad

B

BiQuad

A

IIR

to

modulator

Digital

Volume

Ctrl

from

interface

Interp.

Filter A

BiQuad

C

BiQuad

B

BiQuad

A

to

Modulator

Digital

Volume

Ctrl

from

Interface

´

TLV320DAC3101

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

6.3.10.1.2 DAC Processing Blocks — Details

6.3.10.1.2.1 Three Biquads, Filter A

Figure 6-1. Signal Chain for PRB_P1 and PRB_P4

6.3.10.1.2.2 Six Biquads, First-Order IIR, DRC, Filter A or B

Figure 6-2. Signal Chain for PRB_P2, PRB_P5, PRB_P10, and PRB_P15

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6.3.10.1.2.3 Six Biquads, First-Order IIR, Filter A or B

Figure 6-3. Signal Chain for PRB_P3, PRB_P6, PRB_P11, and PRB_P16

6.3.10.1.2.4 IIR, Filter B or C

Figure 6-4. Signal Chain for PRB_P7, PRB_P12, PRB_P17, and PRB_P20

26

Detailed Description Copyright © 2010–2018, Texas Instruments Incorporated

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Interp.

FilterC

BiQuad

D

BiQuad

C

BiQuad

B

BiQuad

A

IIR

to

modulator

Digital

Volume

Ctrl

from

Interface

´

Interp.

Filter C

*

DRC

HPF

IIR

to

modulator

Digital

Volume

Ctrl

BiQuad

D

BiQuad

C

BiQuad

B

BiQuad

A

from

interface

Interp.

FilterB

BiQuad

D

BiQuad

C

BiQuad

B

BiQuad

A

to

Modulator

Digital

Volume

Ctrl

from

Interface

´

Interp.

Filter B

*

DRC

HPF

to

modulator

Digital

Volume

Ctrl

BiQuad

D

BiQuad

C

BiQuad

B

BiQuad

A

from

interface

TLV320DAC3101

www.ti.com

6.3.10.1.2.5 Four Biquads, DRC, Filter B

Figure 6-5. Signal Chain for PRB_P8 and PRB_P13

6.3.10.1.2.6 Four Biquads, Filter B

Figure 6-6. Signal Chain for PRB_P9 and PRB_P14

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

6.3.10.1.2.7 Four Biquads, First-Order IIR, DRC, Filter C

Figure 6-7. Signal Chain for PRB_P18 and PRB_P21

6.3.10.1.2.8 Four Biquads, First-Order IIR, Filter C

Figure 6-8. Signal Chain for PRB_P19 and PRB_P22

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27

BiQuad

A

L

Interp.

Filter A

*

DRC

BiQuad

F

L

BiQuad

E

L

BiQuad

A

R

IIR
left

3D

PGA

+

+

Interp.

Filter A

*

DRC

BiQuad

F

R

BiQuad

E

R

BiQuad

D

R

BiQuad

C

R

BiQuad

B

R

IIR

right

+

+

-

+

-

+

+

from

left

channel

interface

to

modulator

to

modulator

Digital

Volume

Ctrl

Digital

Volume

Ctrl

from
right

channel

interface

BiQuad

B

L

BiQuad

C

L

BiQuad

D

L

HPF

HPF

3D

PGA

+

+

+

+

–

+

–

+

+

From

Left-

Channel

Interface

To

Modulator

Digital
Volume
Ctrl

Biquad

B

L

To

Modulator

´

´

Biquad

C

L

Biquad

A

L

Biquad

A

R

Biquad

B

R

Biquad

C

R

From

Right-

Channel

Interface

Interp.

Filter A

Interp.

Filter A

Digital
Volume
Ctrl

TLV320DAC3101

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

6.3.10.1.2.9 Two Biquads, 3D, Filter A

NOTE: ALmeans biquad A of the left channel, and similarly, BRmeans biquad B of the right channel.

Figure 6-9. Signal Chain for PRB_P23

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6.3.10.1.2.10 Five Biquads, DRC, 3D, Filter A

Figure 6-10. Signal Chain for PRB_P24

28

Detailed Description Copyright © 2010–2018, Texas Instruments Incorporated

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BiQuad

A

L

Interp.

Filter A

*

+

DRC

HPF

BiQuad

F

L

BiQuad

E

L

BiQuad

A

R

IIR
left

3D

PGA

+

+

Interp.

Filter A

*

+

DRC

*

Beep

Gen.

BiQuad

F

R

BiQuad

E

R

BiQuad

D

R

BiQuad

C

R

BiQuad

B

R

IIR

right

+

+

-

+

-

+

+

from

left

channel

interface

to

modulator

to

modulator

Digital

Volume

Ctrl

Digital

Volume

Ctrl

Beep

Volume

Ctrl

from
right

channel

interface

BiQuad

B

L

BiQuad

C

L

BiQuad

D

L

*

HPF

TLV320DAC3101

www.ti.com

6.3.10.1.2.11 Five Biquads, DRC, 3D, Beep Generator, Filter A

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

Figure 6-11. Signal Chain for PRB_P25

6.3.10.1.3 DAC User-Programmable Filters

Based on the selected processing block, different types and orders of digital filtering are available. Up to
six biquad sections are available for specific processing blocks.

The coefficients of the available filters are arranged as sequentially-indexed coefficients in two banks. If
adaptive filtering is chosen, the coefficient banks can be switched in real time.

When the DAC is running, the user-programmable filter coefficients are locked and cannot be accessed
for either read or write.

However, the device offers an adaptive filter mode as well. Setting page 8 / register 1, bit D2 = 1 turns on
double buffering of the coefficients. In this mode, filter coefficients are updated through the host and
activated without stopping and restarting the DAC which enables advanced adaptive filtering applications.

In the double-buffering scheme, all coefficients are stored in two buffers (buffers A and B). When the DAC
is running and the adaptive filtering mode is turned on, setting page 8 / register 1, bit D0 = 1 switches the
coefficient buffers at the next start of a sampling period. This bit is set back to 0 after the switch occurs. At
the same time, page 8 / register 1, bit D1 toggles.

The flag in page 8 / register 1, bit D1 indicates which of the two buffers is actually in use.
Page 8 / register 1, bit D1 = 0: buffer A is in use by the DAC processing block; bit D1 = 1: buffer B is in

use.
While the device is running, coefficient updates are always made to the buffer not in use by the DAC,

regardless of the buffer to which the coefficients have been written.

DAC POWERED

UP

No 0 None Buffer A (Pages 8 and9)Buffer A (Pages 8

No 0 None Buffer B (Pages 12 and

Table 6-12. Adaptive-Mode Filter-Coefficient Buffer Switching

PAGE 8 / REGISTER 1, BIT D1

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COEFFICIENT BUFFER IN

USE

13)

WRITING TO UPDATES

Detailed DescriptionCopyright © 2010–2018, Texas Instruments Incorporated

and 9)
Buffer B (Pages 12

and 13)

29

1 2

0 1 2

15 1 2

1 2

N 2 N z N z

H(z)

2 2 D z D z

- -

- -

+ ´ +

=

- ´ -

1

0 1

15 1

1

N N z

H(z)

2 D z

-

-

+

=

-

LargestPositiveNumber:

=0.111 1111 1111 111
=0.999969482421875=1.0 – 1LSB

1

LargestNegativeNumber:

=1.0000 0000 0000 000
=0x8000= –1.0(bydefinition)

1 1 1

1 1 1

S.xxxx xxxx xxxx xxx.. x x x

SignBit

2 Bit

–1

2 Bit

–4

2 Bit

–15

Fraction

Point

TLV320DAC3101

SLAS666B –JANUARY 2010–REVISED OCTOBER 2018

Table 6-12. Adaptive-Mode Filter-Coefficient Buffer Switching (continued)

DAC POWERED

UP

Yes 0 Buffer A Buffer A (Pages 8 and9)Buffer B (Pages 12

Yes 0 Buffer A Buffer B (Pages 12 and

Yes 1 Buffer B Buffer A (Pages 8 and9)Buffer A (Pages 8

Yes 1 Buffer B Buffer B (Pages 12 and

PAGE 8 / REGISTER 1, BIT D1

The user-programmable coefficients for the DAC processing blocks are defined on pages 8 and 9 for
buffer A and pages 12 and 13 for buffer B.

The coefficients of these filters are each 16-bit, 2s-complement format, occupying two consecutive 8-bit
registers in the register space. Specifically, the filter coefficients are in 1.15 (one dot 15) format with a
range from –1.0 (0x8000) to 0.999969482421875 (0x7FFF) as shown in Figure 6-12.

COEFFICIENT BUFFER IN

USE

WRITING TO UPDATES

and 13)

13)

13)

Buffer B (Pages 12
and 13)

and 9)
Buffer A (Pages 8

and 9)

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Figure 6-12. 1.15 2s-Complement Coefficient Format

6.3.10.1.3.1 First-Order IIR Section

The IIR is of first order and its transfer function is given by Equation 1.

The frequency response for the first-order IIR section with default coefficients is flat.

Table 6-13. DAC IIR Filter Coefficients

FILTER COEFFICIENT LEFT DAC CHANNEL RIGHT DAC CHANNEL

First-order IIR N0 Page 9 / register 2 and page 9 / register 3 Page 9 / register 8 and page 9 / register 9 0x7FFF (decimal 1.0 –

N1 Page 9 / register 4 and page 9 / register 5 Page 9 / register 10 and page 9 / register 11 0x0000
D1 Page 9 / register 6 and page 9 / register 7 Page 9 / register 12 and page 9 / register 13 0x0000

LSB value)

6.3.10.1.3.2 Biquad Section

The transfer function of each of the biquad filters is given by Equation 2.

30

Detailed Description Copyright © 2010–2018, Texas Instruments Incorporated

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(1)

DEFAULT (RESET)

VALUE

(2)