Texas Instruments TLV320AIC23B-Q1 Datasheet

TLV320AIC23B-Q1

Stereo Audio Codec, 8- to 96-kHz, With Integrated Headphone Amplifier

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SGLS240C

March 2004–Revised June 2012

TLV320AIC23B-Q1

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SGLS240C –MARCH 2004–REVISED JUNE 2012

Stereo Audio Codec, 8- to 96-kHz, With Integrated Headphone

Amplifier

Check for Samples: TLV320AIC23B-Q1

1 1 Introduction

1.1 Features

1

• Qualified for Automotive Applications • Integrated Total Electret-Microphone Biasing

• High-Performance Stereo Codec – 90-dB SNR Multibit Sigma-Delta ADC (A-

weighted at 48 kHz)

– 100-dB SNR Multibit Sigma-Delta DAC (A-

weighted at 48 kHz)

– 1.42 V – 3.6 V Core Digital Supply:

Compatible With TI C54x DSP Core Voltages

– 2.7 V – 3.6 V Buffer and Analog Supply:

Compatible Both TI C54x DSP Buffer – Integrated Programmable Gain Amplifier Voltages

– 8-kHz – 96-kHz Sampling-Frequency Support

• Software Control Via TI McBSP-Compatible and Microphone Multiprotocol Serial Port

– 2-wire-Compatible and SPI-Compatible

Serial-Port Protocols

– Glueless Interface to TI McBSPs

• Audio-Data Input/Output Via TI McBSPCompatible Programmable Audio Interface

– I2S-Compatible Interface Requiring Only One

McBSP for both ADC and DAC

– Standard I2S, MSB, or LSB Justified-Data

Transfers – 16/20/24/32-Bit Word Lengths – Audio Master/Slave Timing Capability

Optimized for TI DSPs (250/272 fs), USB

mode – Industry-Standard Master/Slave Support

Provided Also (256/384 fs), Normal mode – Glueless Interface to TI McBSPs

and Buffering Solution – Low-Noise MICBIAS pin at 3/4 AVDD for

Biasing of Electret Capsules

– Integrated Buffer Amplifier With Tunable

Fixed Gain of 1 to 5

– Additional Control-Register Selectable Buffer

Gain of 0 dB or 20 dB

• Stereo-Line Inputs

– Analog Bypass Path of Codec

• ADC Multiplexed Input for Stereo-Line Inputs

• Stereo-Line Outputs – Analog Stereo Mixer for DAC and Analog

Bypass Path

• Volume Control With Mute on Input and Output

• Highly Efficient Linear Headphone Amplifier – 30 mW into 32 Ω From a 3.3-V Analog Supply

Voltage

• Flexible Power Management Under Total Software Control

– 23-mW Power Consumption During Playback

Mode – Standby Power Consumption < 150 µW – Power-Down Power Consumption < 15 µW

• 28-Pin TSSOP (62 mm2Total Board Area)

• Ideally Suitable for Portable Solid-State Audio Players and Recorders

1.2 Description

The TLV320AIC23B-Q1 is a high-performance stereo audio codec with highly integrated analog functionality. The analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) within the TLV320AIC23B-Q1 use multibit sigma-delta technology with integrated oversampling digital interpolation filters. Data-transfer word lengths of 16, 20, 24, and 32 bits, with sample rates from 8 kHz to 96 kHz, are supported. The ADC sigma-delta modulator features third-order multibit architecture with up to 90-dBA signal-to-noise ratio (SNR) at audio sampling rates up to 96 kHz, enabling high-fidelity audio recording in a compact, power-saving design. The DAC sigma-delta modulator features a second-order multibit architecture with up to 100-dBA SNR at audio sampling rates up to 96 kHz, enabling high-quality digital audio-playback capability, while consuming less than 23 mW during playback only. The TLV320AIC23BQ1 is the ideal analog input/output (I/O) choice for portable digital audio-player and recorder applications,

1

such as MP3 digital audio players.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TLV320AIC23B-Q1

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Integrated analog features consist of stereo-line inputs with an analog bypass path, a stereo headphone amplifier, with analog volume control and mute, and a complete electret-microphone-capsule biasing and buffering solution. The headphone amplifier is capable of delivering 30 mW per channel into 32 Ω. The analog bypass path allows use of the stereo-line inputs and the headphone amplifier with analog volume control, while completely bypassing the codec, thus enabling further design flexibility, such as integrated FM tuners. A microphone bias-voltage output provides a low-noise current source for electret-capsule biasing. The AIC23B has an integrated adjustable microphone amplifier (gain adjustable from 1 to 5) and a programmable gain microphone amplifier (0 dB or 20 dB). The microphone signal can be mixed with the output signals if a sidetone is required.

While the TLV320AIC23B-Q1 supports the industry-standard oversampling rates of 256 fsand 384 fs, unique oversampling rates of 250 fsand 272 fsare provided, which optimize interface considerations in designs using TI C54x digital signal processors (DSPs) and universal serial bus (USB) data interfaces. A single 12-MHz crystal can supply clocking to the DSP, USB, and codec. The TLV320AIC23B-Q1 features an internal oscillator that, when connected to a 12-MHz external crystal, provides a system clock to the DSP and other peripherals at either 12 MHz or 6 MHz, using an internal clock buffer and selectable divider. Audio sample rates of 48 kHz and compact-disc (CD) standard 44.1 kHz are supported directly from a 12-MHz master clock with 250 fsand 272 fsoversampling rates.

Low power consumption and flexible power management allow selective shutdown of codec functions, thus extending battery life in portable applications. This design solution makes powerful portable stereo audio designs easily realizable in a cost-effective, space-saving total analog I/O solution: the TLV320AIC23B-Q1.

SGLS240C –MARCH 2004–REVISED JUNE 2012

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Σ

Σ−∆

DAC

Σ

OSC

SDIN

SCLK

MODE

DVDD

BVDD

DGND

LRCIN

DIN

LRCOUT

DOUT

BCLK

B0486-01

AVDD

VMID

AGND

RLINEIN

LLINEIN

HPVDD

HPGND

RHPOUT

ROUT

LOUT

LHPOUT

XTI/MCLK

XTO

CLKOUT

1.0X

VADC

VMID

50 kΩ

VDAC

Σ−∆

ADC

VMID

50 kΩ

10 kΩ

VADC

1.0X

1.5X

VDAC

MICBIAS

MICIN

Sidetone Mute

NOTE: MCLK, BCLK, and SCLK are all asynchronous to each other.

50 kΩ

DSPcodec

TLV320AIC23B

Mute,

0 dB, 20 dB

Bypass Mute

Line

Mute

2:1

MUX

Σ−∆

ADC

12 to 34.5 dB,

1.5-dB Steps

–

CS

Control

Interface

12 to 34 dB,

1.5-dB Steps

–

6 to 73 dB,

1-dB Steps

–

Σ−∆

DAC

Bypass Mute

6 to 73 dB,

1-dB Steps

–

Headphone

Driver

Headphone

Driver

CLKIN Divider

(1x, x)½

CLKOUT

Divider

(1x, x)½

Digital

Audio

Interface

Digital Filters

2:1

MUX

Line

Mute

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1.3 Functional Block Diagram

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1

2

3

4

5

6

7

11

8

12

9

13

10

14

21

28

27

26

25

24

23

22

18

17

20

16

19

15

BVDD

CLKOUT

BCLK

DIN

LRCIN

DOUT

LRCOUT

HPGND

HPVDD

LOUT

LHPOUT

ROUT

RHPOUT

AVDD

DGND

DVDD

XTO

XTI/MCLK

SCLK

SDIN

MODE

MICIN

CS

MICBIAS

LLINEIN

VMID

RLINEIN

AGND

P0043-05

PW Package

(Top View)

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1.4 Pin Assignments

1.5 Ordering Information

T

A

−40°C to 85°C TSSOP 2000 TLV320AIC23BIPWRQ1 AIC23BIQ1

SGLS240C –MARCH 2004–REVISED JUNE 2012

PACKAGE REEL ORDERABLE PART NUMBER TOP-SIDE MARKING

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1.6 Pin Functions

Table 1-1. Pin Functions

NAME NO.

AGND 15 Analog supply return AVDD 14 Analog supply input. Voltage level is 3.3 V nominal.

BCLK 3 I/O BVDD 1 Buffer supply input. Voltage range is from 2.7 V to 3.6 V. CLKOUT 2 O

CS 21 I For 2-wire control mode this input defines the seventh bit in the device address field. See Section 3.1 for

DIN 4 I I2S format serial data input to the sigma-delta stereo DAC DGND 28 Digital supply return DOUT 6 O I2S format serial data output from the sigma-delta stereo ADC DVDD 27 Digital supply input. Voltage range is 1.4 V to 3.6 V. HPGND 11 Analog headphone amplifier supply return HPVDD 8 Analog headphone amplifier supply input. Voltage level is 3.3 V nominal.

LHPOUT 9 O

LLINEIN 20 I LOUT 12 O Left stereo mixer-channel line output. Nominal output level is 1.0 VRMS. LRCIN 5 I/O

LRCOUT 7 I/O

MICBIAS 17 O

MICIN 18 I MODE 22 I Serial-interface-mode input. See Section 3.1 for details.

NC Not Used—No internal connection RHPOUT 10 O

RLINEIN 19 I ROUT 13 O Right stereo mixer-channel line output. Nominal output level is 1.0 VRMS. SCLK 24 I

SDIN 23 I

VMID 16 I XTI/MCLK 25 I Crystal or external-clock input. Used for derivation of all internal clocks on the AIC23B. XTO 26 O

I/O DESCRIPTION

I2S serial-bit clock. In audio master mode, the AIC23B generates this signal and sends it to the DSP. In audio slave mode, the signal is generated by the DSP.

Clock output. This is a buffered version of the XTI input and is available in 1X or 1/2X frequencies of XTI. Bit 07 in the sample rate control register controls frequency selection.

Control port input latch/address select. For SPI control mode this input acts as the data latch control. details.

Left stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS. Gain of –73 dB to 6 dB is provided in 1-dB steps.

Left stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is provided in 1.5-dB steps.

I2S DAC-word clock signal. In audio master mode, the AIC23B generates this framing signal and sends it to the DSP. In audio slave mode, the signal is generated by the DSP.

I2S ADC-word clock signal. In audio master mode, the AIC23B generates this framing signal and sends it to the DSP. In audio slave mode, the signal is generated by the DSP.

Buffered low-noise-voltage output suitable for electret-microphone-capsule biasing. Voltage level is 3/4 AVDD nominal.

Buffered amplifier input suitable for use with electret-microphone capsules. Without external resistors a default gain of 5 is provided. See Section 2.3.1.2 for details.

Right stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS. Gain of

−73 dB to 6 dB is provided in 1-dB steps. Right stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is

provided in 1.5-dB steps.

Control-port serial-data clock. For SPI and 2-wire control modes this is the serial-clock input. See Section 3.1 for details.

Control-port serial-data input. For SPI and 2-wire control modes this is the serial-data input and also is used to select the control protocol after reset. See Section 3.1 for details.

Midrail voltage decoupling input. 10-μF and 0.1-μF capacitors should be connected in parallel to this terminal for noise filtering. Voltage level is 1/2 AVDD nominal.

Crystal output. Connect to external crystal for applications where the AIC23B is the audio timing master. Not used in applications where external clock source is used.

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2 Electrical Specifications

2.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

Supply voltage range Analog supply return to digital supply return AGND to DGND –0.3 to 3 .63 V

Input voltage range, all input signals

Case temperature for 10 seconds 240 °C Operating free-air temperature range: Industrial, T Storage temperature range, T

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) DVDDmay not exceed BVDD0.3 V; BVDDmay not exceed AVDD0.3 V or HPVDD0.3.

(2)

stg

2.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

DD

(1)

DD

(1)

A

Analog supply voltage, AVDD, HPV Digital buffer supply voltage, BV Digital core supply voltage, DV Analog input voltage, full scale − 0 dB (AVDD= 3.3 V) 1 V Stereo-line output load resistance 10 kΩ Headphone-amplifier output load resistance 0 Ω CLKOUT digital output load capacitance 20 pF All other digital output load capacitance 10 pF Stereo-line output load capacitance 50 pF XTI master clock Input 18.43 MHz ADC or DAC conversion rate 96 kHz Operating free-air temperature, T

(1) Digital voltage values are with respect to DGND; analog voltage values are with respect to AGND.

(1)

VALUE UNIT

AVDDto AGND, DVDDto DGND, BVDDto DGND, HPVDDto HPGND

Digital –0.3 to DV Analog –0.3 to AV

A

–0.3 to 3.63 V

DD DD

–40 to 85 °C

–65 to 150 °C

MIN NOM MAX UNIT

2.7 3.3 3.6 V

1.42 1.5 3.6 V

Industrial –40 85 °C

V V

RMS

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2.3 Electrical Characteristics

over recommended operating conditions, AVDD, HPVDD, BVDD= 3.3 V, DVDD= 1.5 V, slave mode, XTI/MCLK = 256 fs, fs= 48 kHz (unless otherwise stated)

2.3.1 ADC

2.3.1.1 Line Input to ADC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input signal level (0 dB) 1 V

Signal-to-noise ratio, A-weighted, 0-dB gain

(1)(2)

Dynamic range, A-weighted, –60-dB full-scale input

Total harmonic distortion, –1-dB input, 0-dB gain dB

Power supply rejection ratio 1 kHz, 100 mV

fs= 48 kHz (3.3 V) 85 90 fs= 48 kHz (2.7 V) 90 AVDD= 3.3 V 85 90

(2)

AVDD= 2.7 V 90 AVDD= 3.3 V –80 AVDD= 2.7 V 80

pp

50 dB ADC channel separation 1 kHz input tone 90 dB Programmable gain 1 kHz input tone, R

< 50 Ω –34.5 12 dB

SOURCE

Programmable gain step size Monotonic 1.5 dB Mute attenuation 0 dB, 1 kHz input tone 80 dB

Input resistance kΩ

12 dB input gain 10 20 0 dB input gain 28 35

Input capacitance 10 pF

(1) Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to

20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in

higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.

RMS

dB

2.3.1.2 Microphone Input to ADC

0-dB Gain, fs= 8 kHz (40-KΩ source impedance, see Section 1.3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input signal level (0 dB) 1 V

Signal-to-noise ratio, A-weighted, 0-dB gain

(1)(2)

Dynamic range, A-weighted, –60-dB full-scale input

Total harmonic distortion, –1-dB input, 0-dB gain dB

Power supply rejection ratio 1 kHz, 100 mV Programmable gain boost 1 kHz input tone, R Microphone-path gain MICBOOST = 0, R

AVDD= 3.3 V 77 85 AVDD= 2.7 V 84 AVDD= 3.3 V 77 85

(2)

AVDD= 2.7 V 84 AVDD= 3.3 V –60 AVDD= 2.7 V –60

pp

< 50 Ω 20 dB

SOURCE

< 50 Ω 14 dB

SOURCE

50 dB

Mute attenuation 0 dB, 1 kHz input tone 60 80 dB Input resistance 8 14 kΩ Input capacitance 10 pF

(1) Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to

20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in

higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.

RMS

dB

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2.3.1.3 Microphone Bias

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Bias voltage 3/4 AVDD− 100 m 3/4 AV

3/4 AVDD+ 100 m V

DD

Bias-current source 3 mA Output noise voltage 1 kHz to 20 kHz 25 nV/√Hz

2.3.2 DAC

Line output, load = 10 kΩ, 50 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

0-dB full-scale output voltage (FFFFFF) 1 V

Signal-to-noise ratio, A-weighted, 0-dB gain

Dynamic range, A-weighted

(2)

(1)(2)(3)

Total harmonic distortion

Power supply rejection ratio 1 kHz, 100 mV

AVDD= 3.3 V fs= 48kHz 90 100 AVDD= 2.7 V fs= 48 kHz 100 AVDD= 3.3 V 85 90 AVDD= 2.7 V TBD

AVDD= 3.3 V dB

AVDD= 2.7 V dB

1 kHz, 0 dB –88 –80 1 kHz, –3 dB –92 –86 1 kHz, 0 dB –85 1 kHz, –3 dB –88

pp

50 dB

DAC channel separation 100 dB

(1) Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to

20-kHz bandwidth using an audio analyzer

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in

higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.

(3) Ratio of output level with 1-kHz full-scale input, to the output level with all zeros into the digital input, measured A-weighted over a 20-Hz

to 20-kHz bandwidth.

RMS

dB

2.3.3 Analog Line Input to Line Output (Bypass)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

0-dB full-scale output voltage 1 V

AVDD= 3.3 V 90 95

Signal-to-noise ratio, A-weighted, 0-dB gain

Total harmonic distortion

Power supply rejection ratio 1 kHz, 100 mV

(1)(2)

AVDD= 2.7 V 95

AVDD= 3.3 V dB

AVDD= 2.7 V dB

1 kHz, 0 dB –86 –80 1 kHz, –3 dB –92 –86 1 kHz, 0 dB –86 1 kHz, –3 dB –92

pp

50 dB DAC channel separation (left to right) 1 kHz, 0 dB 80 dB

(1) Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to

20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in

higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.

RMS

dB

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2.3.4 Stereo Headphone Output

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

0-dB full-scale output voltage 1 VRMS

Maximum output power, P

Signal-to-noise ratio, A-weighted

O

(1)

Total harmonic distortion %

Power supply rejection ratio 1 kHz, 100 mV

RL = 32 Ω 30 RL = 16 Ω 40

mW

AVDD= 3.3 V 88 97 dB AVDD= 3.3 V,

1 kHz output

pp

PO = 10 mW 0.1 PO = 20 mW 1

50 dB Programmable gain 1 kHz output −73 6 dB Programmable-gain step size 1 dB Mute attenuation 1 kHz output 80 dB

(1) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in

higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.

2.3.5 Analog Reference Levels

PARAMETER MIN TYP MAX UNIT

Reference voltage AVDD/2 − 50 mV AVDD/2 + 50 mV V Divider resistance 40 50 60 kΩ

2.3.6 Digital I/O

PARAMETER MIN TYP MAX UNIT

V

IL

V

IH

V

OL

V

OH

Input low level 0.3 × BV Input high level 0.7 × BV

DD

Output low level 0.1 × BV Output high level 0.9 × BV

DD

2.3.7 Supply Current

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Record and playback (all active) 20 24 26 Record and playback (osc, clk, and MIC output powered down) 16 18 20 Line playback only 6 7.5 9

Total supply current, No input signal I

Record only 11 13.5 15

TOT

Analog bypass (line in to line out) 4 4.5 6 Power down, DVDD= 1.5 V, Oscillator enabled 0.8 1.5 3

AV

DD

= BVDD= HPVDD= 3.3 V

Oscillator disabled 0.01

2.4 Digital-Interface Timing

PARAMETER MIN TYP MAX UNIT

tw(1) High 18 ns tw(2) Low 18 tc(1) System-clock period, MCLK/XTI 54 ns

tpd(1) Propagation delay, CLKOUT 0 10 ns

System-clock pulse duration, MCLK/XTI

Duty cycle, MCLK/XTI 40/60 60/40 %

V V V V

mA

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BCLK

LRCIN

DIN

DOUT

LRCOUT

t

su(1)

t

h(1)

t

pd(2)

t

pd(3)

T0548-01

t

pd(1)

MCLK/XTI

CLKOUT

(Div 2)

t

c(1)

t

w(1)

t

w(2)

T0547-01

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Figure 2-1. System-Clock Timing Requirements

2.4.1 Audio Interface (Master Mode)

PARAMETER MIN TYP MAX UNIT

tpd(2) Propagation delay, LRCIN/LRCOUT 0 10 ns tpd(3) Propagation delay, DOUT 0 10 ns tsu(1) Setup time, DIN 10 ns th(1) Hold time, DIN 10 ns

Figure 2-2. Master-Mode Timing Requirements

2.4.2 Audio Interface (Slave-Mode)

PARAMETER MIN TYP MAX UNIT

tw(3) High 20 tw(4) Low 20 tc(2) Clock period, BCLK 50 ns tpd(4) Propagation delay, DOUT 0 10 ns tsu(2) Setup time, DIN 10 ns th(2) Hold time, DIN 10 ns tsu(3) Setup time, LRCIN 10 ns th(3) Hold time, LRCIN 10 ns

Pulse duration, BCLK ns

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LSB

t

w(8)

t

w(5)

t

w(6)

t

c(3)

t

su(5)

t

su(4)

t

h(4)

CS

SCLK

DIN

T0550-01

BCLK

LRCIN

DIN

DOUT

LRCOUT

t

c(2)

t

w(4)

t

w(3)

t

su(2)

t

h(3)

t

h(2)

t

su(3)

t

pd(2)

T0549-01

TLV320AIC23B-Q1

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Figure 2-3. Slave-Mode Timing Requirements

2.4.3 3-Wire Control Interface (SDIN)

PARAMETER MIN TYP MAX UNIT

tw(5) High 20 tw(6) Low 20 tc(3) Clock period, SCLK 80 ns tsu(4) Clock rising edge to CS rising edge, SCLK 60 ns tsu(5) Setup time, SDIN to SCLK 20 ns th(4) Hold time, SCLK to SDIN 20 ns tw(7) High 20 tw(8) Low 20

Clock pulse duration, SCLK ns

Pulse duration, CS ns

Figure 2-4. 3-Wire Control Interface Timing Requirements

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Texas Instruments TLV320AIC23B-Q1 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

1 1 Introduction

1.1 Features

1.2 Description

1.3 Functional Block Diagram

1.4 Pin Assignments

1.5 Ordering Information

1.6 Pin Functions

2 Electrical Specifications

2.1 Absolute Maximum Ratings

2.2 Recommended Operating Conditions

2.3 Electrical Characteristics

2.3.1 ADC

2.3.1.1 Line Input to ADC

2.3.1.2 Microphone Input to ADC

2.3.1.3 Microphone Bias

2.3.2 DAC

2.3.3 Analog Line Input to Line Output (Bypass)

2.3.4 Stereo Headphone Output

2.3.5 Analog Reference Levels

2.3.6 Digital I/O

2.3.7 Supply Current

2.4 Digital-Interface Timing

2.4.1 Audio Interface (Master Mode)

2.4.2 Audio Interface (Slave-Mode)

2.4.3 3-Wire Control Interface (SDIN)