Datasheet TLV320AIC23B-Q1 Datasheet (Texas Instruments)

TLV320AIC23B-Q1

Stereo Audio Codec, 8- to 96-kHz, With Integrated Headphone Amplifier

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SGLS240C

March 2004–Revised June 2012

TLV320AIC23B-Q1

www.ti.com

SGLS240C –MARCH 2004–REVISED JUNE 2012

Stereo Audio Codec, 8- to 96-kHz, With Integrated Headphone

Amplifier

Check for Samples: TLV320AIC23B-Q1

1 1 Introduction

1.1 Features

• Qualified for Automotive Applications • Integrated Total Electret-Microphone Biasing

• High-Performance Stereo Codec – 90-dB SNR Multibit Sigma-Delta ADC (A-

weighted at 48 kHz)

– 100-dB SNR Multibit Sigma-Delta DAC (A-

weighted at 48 kHz)

– 1.42 V – 3.6 V Core Digital Supply:

Compatible With TI C54x DSP Core Voltages

– 2.7 V – 3.6 V Buffer and Analog Supply:

Compatible Both TI C54x DSP Buffer – Integrated Programmable Gain Amplifier Voltages

– 8-kHz – 96-kHz Sampling-Frequency Support

• Software Control Via TI McBSP-Compatible and Microphone Multiprotocol Serial Port

– 2-wire-Compatible and SPI-Compatible

Serial-Port Protocols

– Glueless Interface to TI McBSPs

• Audio-Data Input/Output Via TI McBSPCompatible Programmable Audio Interface

– I2S-Compatible Interface Requiring Only One

McBSP for both ADC and DAC

– Standard I2S, MSB, or LSB Justified-Data

Transfers – 16/20/24/32-Bit Word Lengths – Audio Master/Slave Timing Capability

Optimized for TI DSPs (250/272 fs), USB

mode – Industry-Standard Master/Slave Support

Provided Also (256/384 fs), Normal mode – Glueless Interface to TI McBSPs

and Buffering Solution – Low-Noise MICBIAS pin at 3/4 AVDD for

Biasing of Electret Capsules

– Integrated Buffer Amplifier With Tunable

Fixed Gain of 1 to 5

– Additional Control-Register Selectable Buffer

Gain of 0 dB or 20 dB

• Stereo-Line Inputs

– Analog Bypass Path of Codec

• ADC Multiplexed Input for Stereo-Line Inputs

• Stereo-Line Outputs – Analog Stereo Mixer for DAC and Analog

Bypass Path

• Volume Control With Mute on Input and Output

• Highly Efficient Linear Headphone Amplifier – 30 mW into 32 Ω From a 3.3-V Analog Supply

Voltage

• Flexible Power Management Under Total Software Control

– 23-mW Power Consumption During Playback

Mode – Standby Power Consumption < 150 µW – Power-Down Power Consumption < 15 µW

• 28-Pin TSSOP (62 mm2Total Board Area)

• Ideally Suitable for Portable Solid-State Audio Players and Recorders

1.2 Description

The TLV320AIC23B-Q1 is a high-performance stereo audio codec with highly integrated analog functionality. The analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) within the TLV320AIC23B-Q1 use multibit sigma-delta technology with integrated oversampling digital interpolation filters. Data-transfer word lengths of 16, 20, 24, and 32 bits, with sample rates from 8 kHz to 96 kHz, are supported. The ADC sigma-delta modulator features third-order multibit architecture with up to 90-dBA signal-to-noise ratio (SNR) at audio sampling rates up to 96 kHz, enabling high-fidelity audio recording in a compact, power-saving design. The DAC sigma-delta modulator features a second-order multibit architecture with up to 100-dBA SNR at audio sampling rates up to 96 kHz, enabling high-quality digital audio-playback capability, while consuming less than 23 mW during playback only. The TLV320AIC23BQ1 is the ideal analog input/output (I/O) choice for portable digital audio-player and recorder applications,

such as MP3 digital audio players.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TLV320AIC23B-Q1

www.ti.com

Integrated analog features consist of stereo-line inputs with an analog bypass path, a stereo headphone amplifier, with analog volume control and mute, and a complete electret-microphone-capsule biasing and buffering solution. The headphone amplifier is capable of delivering 30 mW per channel into 32 Ω. The analog bypass path allows use of the stereo-line inputs and the headphone amplifier with analog volume control, while completely bypassing the codec, thus enabling further design flexibility, such as integrated FM tuners. A microphone bias-voltage output provides a low-noise current source for electret-capsule biasing. The AIC23B has an integrated adjustable microphone amplifier (gain adjustable from 1 to 5) and a programmable gain microphone amplifier (0 dB or 20 dB). The microphone signal can be mixed with the output signals if a sidetone is required.

While the TLV320AIC23B-Q1 supports the industry-standard oversampling rates of 256 fsand 384 fs, unique oversampling rates of 250 fsand 272 fsare provided, which optimize interface considerations in designs using TI C54x digital signal processors (DSPs) and universal serial bus (USB) data interfaces. A single 12-MHz crystal can supply clocking to the DSP, USB, and codec. The TLV320AIC23B-Q1 features an internal oscillator that, when connected to a 12-MHz external crystal, provides a system clock to the DSP and other peripherals at either 12 MHz or 6 MHz, using an internal clock buffer and selectable divider. Audio sample rates of 48 kHz and compact-disc (CD) standard 44.1 kHz are supported directly from a 12-MHz master clock with 250 fsand 272 fsoversampling rates.

Low power consumption and flexible power management allow selective shutdown of codec functions, thus extending battery life in portable applications. This design solution makes powerful portable stereo audio designs easily realizable in a cost-effective, space-saving total analog I/O solution: the TLV320AIC23B-Q1.

SGLS240C –MARCH 2004–REVISED JUNE 2012

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

Σ−∆

DAC

OSC

SDIN

SCLK

MODE

DVDD

BVDD

DGND

LRCIN

DIN

LRCOUT

DOUT

BCLK

B0486-01

AVDD

VMID

AGND

RLINEIN

LLINEIN

HPVDD

HPGND

RHPOUT

ROUT

LOUT

LHPOUT

XTI/MCLK

XTO

CLKOUT

1.0X

VADC

VMID

50 kΩ

VDAC

Σ−∆

ADC

VMID

50 kΩ

10 kΩ

VADC

1.0X

1.5X

VDAC

MICBIAS

MICIN

Sidetone Mute

NOTE: MCLK, BCLK, and SCLK are all asynchronous to each other.

50 kΩ

DSPcodec

TLV320AIC23B

Mute,

0 dB, 20 dB

Bypass Mute

Line

Mute

2:1

MUX

Σ−∆

ADC

12 to 34.5 dB,

1.5-dB Steps

–

Control

Interface

12 to 34 dB,

1.5-dB Steps

–

6 to 73 dB,

1-dB Steps

–

Σ−∆

DAC

Bypass Mute

6 to 73 dB,

1-dB Steps

–

Headphone

Driver

Headphone

Driver

CLKIN Divider

(1x, x)½

CLKOUT

Divider

(1x, x)½

Digital

Audio

Interface

Digital Filters

2:1

MUX

Line

Mute

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

1.3 Functional Block Diagram

www.ti.com

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

BVDD

CLKOUT

BCLK

DIN

LRCIN

DOUT

LRCOUT

HPGND

HPVDD

LOUT

LHPOUT

ROUT

RHPOUT

AVDD

DGND

DVDD

XTO

XTI/MCLK

SCLK

SDIN

MODE

MICIN

MICBIAS

LLINEIN

VMID

RLINEIN

AGND

P0043-05

PW Package

(Top View)

TLV320AIC23B-Q1

www.ti.com

1.4 Pin Assignments

1.5 Ordering Information

−40°C to 85°C TSSOP 2000 TLV320AIC23BIPWRQ1 AIC23BIQ1

SGLS240C –MARCH 2004–REVISED JUNE 2012

PACKAGE REEL ORDERABLE PART NUMBER TOP-SIDE MARKING

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

www.ti.com

1.6 Pin Functions

Table 1-1. Pin Functions

NAME NO.

AGND 15 Analog supply return AVDD 14 Analog supply input. Voltage level is 3.3 V nominal.

BCLK 3 I/O BVDD 1 Buffer supply input. Voltage range is from 2.7 V to 3.6 V. CLKOUT 2 O

CS 21 I For 2-wire control mode this input defines the seventh bit in the device address field. See Section 3.1 for

DIN 4 I I2S format serial data input to the sigma-delta stereo DAC DGND 28 Digital supply return DOUT 6 O I2S format serial data output from the sigma-delta stereo ADC DVDD 27 Digital supply input. Voltage range is 1.4 V to 3.6 V. HPGND 11 Analog headphone amplifier supply return HPVDD 8 Analog headphone amplifier supply input. Voltage level is 3.3 V nominal.

LHPOUT 9 O

LLINEIN 20 I LOUT 12 O Left stereo mixer-channel line output. Nominal output level is 1.0 VRMS. LRCIN 5 I/O

LRCOUT 7 I/O

MICBIAS 17 O

MICIN 18 I MODE 22 I Serial-interface-mode input. See Section 3.1 for details.

NC Not Used—No internal connection RHPOUT 10 O

RLINEIN 19 I ROUT 13 O Right stereo mixer-channel line output. Nominal output level is 1.0 VRMS. SCLK 24 I

SDIN 23 I

VMID 16 I XTI/MCLK 25 I Crystal or external-clock input. Used for derivation of all internal clocks on the AIC23B. XTO 26 O

I/O DESCRIPTION

I2S serial-bit clock. In audio master mode, the AIC23B generates this signal and sends it to the DSP. In audio slave mode, the signal is generated by the DSP.

Clock output. This is a buffered version of the XTI input and is available in 1X or 1/2X frequencies of XTI. Bit 07 in the sample rate control register controls frequency selection.

Control port input latch/address select. For SPI control mode this input acts as the data latch control. details.

Left stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS. Gain of –73 dB to 6 dB is provided in 1-dB steps.

Left stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is provided in 1.5-dB steps.

I2S DAC-word clock signal. In audio master mode, the AIC23B generates this framing signal and sends it to the DSP. In audio slave mode, the signal is generated by the DSP.

I2S ADC-word clock signal. In audio master mode, the AIC23B generates this framing signal and sends it to the DSP. In audio slave mode, the signal is generated by the DSP.

Buffered low-noise-voltage output suitable for electret-microphone-capsule biasing. Voltage level is 3/4 AVDD nominal.

Buffered amplifier input suitable for use with electret-microphone capsules. Without external resistors a default gain of 5 is provided. See Section 2.3.1.2 for details.

Right stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS. Gain of

−73 dB to 6 dB is provided in 1-dB steps. Right stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is

provided in 1.5-dB steps.

Control-port serial-data clock. For SPI and 2-wire control modes this is the serial-clock input. See Section 3.1 for details.

Control-port serial-data input. For SPI and 2-wire control modes this is the serial-data input and also is used to select the control protocol after reset. See Section 3.1 for details.

Midrail voltage decoupling input. 10-μF and 0.1-μF capacitors should be connected in parallel to this terminal for noise filtering. Voltage level is 1/2 AVDD nominal.

Crystal output. Connect to external crystal for applications where the AIC23B is the audio timing master. Not used in applications where external clock source is used.

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

TLV320AIC23B-Q1

www.ti.com

SGLS240C –MARCH 2004–REVISED JUNE 2012

2 Electrical Specifications

2.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

Supply voltage range Analog supply return to digital supply return AGND to DGND –0.3 to 3 .63 V

Input voltage range, all input signals

Case temperature for 10 seconds 240 °C Operating free-air temperature range: Industrial, T Storage temperature range, T

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) DVDDmay not exceed BVDD0.3 V; BVDDmay not exceed AVDD0.3 V or HPVDD0.3.

(2)

stg

2.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

(1)

Analog supply voltage, AVDD, HPV Digital buffer supply voltage, BV Digital core supply voltage, DV Analog input voltage, full scale − 0 dB (AVDD= 3.3 V) 1 V Stereo-line output load resistance 10 kΩ Headphone-amplifier output load resistance 0 Ω CLKOUT digital output load capacitance 20 pF All other digital output load capacitance 10 pF Stereo-line output load capacitance 50 pF XTI master clock Input 18.43 MHz ADC or DAC conversion rate 96 kHz Operating free-air temperature, T

(1) Digital voltage values are with respect to DGND; analog voltage values are with respect to AGND.

(1)

VALUE UNIT

AVDDto AGND, DVDDto DGND, BVDDto DGND, HPVDDto HPGND

Digital –0.3 to DV Analog –0.3 to AV

–0.3 to 3.63 V

DD DD

–40 to 85 °C

–65 to 150 °C

MIN NOM MAX UNIT

2.7 3.3 3.6 V

1.42 1.5 3.6 V

Industrial –40 85 °C

V V

RMS

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

www.ti.com

2.3 Electrical Characteristics

over recommended operating conditions, AVDD, HPVDD, BVDD= 3.3 V, DVDD= 1.5 V, slave mode, XTI/MCLK = 256 fs, fs= 48 kHz (unless otherwise stated)

2.3.1 ADC

2.3.1.1 Line Input to ADC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input signal level (0 dB) 1 V

Signal-to-noise ratio, A-weighted, 0-dB gain

(1)(2)

Dynamic range, A-weighted, –60-dB full-scale input

Total harmonic distortion, –1-dB input, 0-dB gain dB

Power supply rejection ratio 1 kHz, 100 mV

fs= 48 kHz (3.3 V) 85 90 fs= 48 kHz (2.7 V) 90 AVDD= 3.3 V 85 90

(2)

AVDD= 2.7 V 90 AVDD= 3.3 V –80 AVDD= 2.7 V 80

50 dB ADC channel separation 1 kHz input tone 90 dB Programmable gain 1 kHz input tone, R

< 50 Ω –34.5 12 dB

SOURCE

Programmable gain step size Monotonic 1.5 dB Mute attenuation 0 dB, 1 kHz input tone 80 dB

Input resistance kΩ

12 dB input gain 10 20 0 dB input gain 28 35

Input capacitance 10 pF

(1) Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to

20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in

higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.

RMS

2.3.1.2 Microphone Input to ADC

0-dB Gain, fs= 8 kHz (40-KΩ source impedance, see Section 1.3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input signal level (0 dB) 1 V

Signal-to-noise ratio, A-weighted, 0-dB gain

(1)(2)

Dynamic range, A-weighted, –60-dB full-scale input

Total harmonic distortion, –1-dB input, 0-dB gain dB

Power supply rejection ratio 1 kHz, 100 mV Programmable gain boost 1 kHz input tone, R Microphone-path gain MICBOOST = 0, R

AVDD= 3.3 V 77 85 AVDD= 2.7 V 84 AVDD= 3.3 V 77 85

(2)

AVDD= 2.7 V 84 AVDD= 3.3 V –60 AVDD= 2.7 V –60

< 50 Ω 20 dB

SOURCE

< 50 Ω 14 dB

SOURCE

50 dB

Mute attenuation 0 dB, 1 kHz input tone 60 80 dB Input resistance 8 14 kΩ Input capacitance 10 pF

(1) Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to

20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in

RMS

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

TLV320AIC23B-Q1

www.ti.com

SGLS240C –MARCH 2004–REVISED JUNE 2012

2.3.1.3 Microphone Bias

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Bias voltage 3/4 AVDD− 100 m 3/4 AV

3/4 AVDD+ 100 m V

Bias-current source 3 mA Output noise voltage 1 kHz to 20 kHz 25 nV/√Hz

2.3.2 DAC

Line output, load = 10 kΩ, 50 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

0-dB full-scale output voltage (FFFFFF) 1 V

Signal-to-noise ratio, A-weighted, 0-dB gain

Dynamic range, A-weighted

(2)

(1)(2)(3)

Total harmonic distortion

Power supply rejection ratio 1 kHz, 100 mV

AVDD= 3.3 V fs= 48kHz 90 100 AVDD= 2.7 V fs= 48 kHz 100 AVDD= 3.3 V 85 90 AVDD= 2.7 V TBD

AVDD= 3.3 V dB

AVDD= 2.7 V dB

1 kHz, 0 dB –88 –80 1 kHz, –3 dB –92 –86 1 kHz, 0 dB –85 1 kHz, –3 dB –88

50 dB

DAC channel separation 100 dB

(1) Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to

20-kHz bandwidth using an audio analyzer

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in

(3) Ratio of output level with 1-kHz full-scale input, to the output level with all zeros into the digital input, measured A-weighted over a 20-Hz

to 20-kHz bandwidth.

RMS

2.3.3 Analog Line Input to Line Output (Bypass)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

0-dB full-scale output voltage 1 V

AVDD= 3.3 V 90 95

Signal-to-noise ratio, A-weighted, 0-dB gain

Total harmonic distortion

Power supply rejection ratio 1 kHz, 100 mV

(1)(2)

AVDD= 2.7 V 95

AVDD= 3.3 V dB

AVDD= 2.7 V dB

1 kHz, 0 dB –86 –80 1 kHz, –3 dB –92 –86 1 kHz, 0 dB –86 1 kHz, –3 dB –92

50 dB DAC channel separation (left to right) 1 kHz, 0 dB 80 dB

(1) Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to

20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in

RMS

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

www.ti.com

2.3.4 Stereo Headphone Output

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

0-dB full-scale output voltage 1 VRMS

Maximum output power, P

Signal-to-noise ratio, A-weighted

(1)

Total harmonic distortion %

Power supply rejection ratio 1 kHz, 100 mV

RL = 32 Ω 30 RL = 16 Ω 40

AVDD= 3.3 V 88 97 dB AVDD= 3.3 V,

1 kHz output

PO = 10 mW 0.1 PO = 20 mW 1

50 dB Programmable gain 1 kHz output −73 6 dB Programmable-gain step size 1 dB Mute attenuation 1 kHz output 80 dB

(1) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in

2.3.5 Analog Reference Levels

PARAMETER MIN TYP MAX UNIT

Reference voltage AVDD/2 − 50 mV AVDD/2 + 50 mV V Divider resistance 40 50 60 kΩ

2.3.6 Digital I/O

PARAMETER MIN TYP MAX UNIT

Input low level 0.3 × BV Input high level 0.7 × BV

Output low level 0.1 × BV Output high level 0.9 × BV

2.3.7 Supply Current

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Record and playback (all active) 20 24 26 Record and playback (osc, clk, and MIC output powered down) 16 18 20 Line playback only 6 7.5 9

Total supply current, No input signal I

Record only 11 13.5 15

TOT

Analog bypass (line in to line out) 4 4.5 6 Power down, DVDD= 1.5 V, Oscillator enabled 0.8 1.5 3

= BVDD= HPVDD= 3.3 V

Oscillator disabled 0.01

2.4 Digital-Interface Timing

PARAMETER MIN TYP MAX UNIT

tw(1) High 18 ns tw(2) Low 18 tc(1) System-clock period, MCLK/XTI 54 ns

tpd(1) Propagation delay, CLKOUT 0 10 ns

System-clock pulse duration, MCLK/XTI

Duty cycle, MCLK/XTI 40/60 60/40 %

V V V V

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

BCLK

LRCIN

DIN

DOUT

LRCOUT

su(1)

h(1)

pd(2)

pd(3)

T0548-01

pd(1)

MCLK/XTI

CLKOUT

(Div 2)

c(1)

w(1)

w(2)

T0547-01

TLV320AIC23B-Q1

www.ti.com

SGLS240C –MARCH 2004–REVISED JUNE 2012

Figure 2-1. System-Clock Timing Requirements

2.4.1 Audio Interface (Master Mode)

PARAMETER MIN TYP MAX UNIT

tpd(2) Propagation delay, LRCIN/LRCOUT 0 10 ns tpd(3) Propagation delay, DOUT 0 10 ns tsu(1) Setup time, DIN 10 ns th(1) Hold time, DIN 10 ns

Figure 2-2. Master-Mode Timing Requirements

2.4.2 Audio Interface (Slave-Mode)

PARAMETER MIN TYP MAX UNIT

tw(3) High 20 tw(4) Low 20 tc(2) Clock period, BCLK 50 ns tpd(4) Propagation delay, DOUT 0 10 ns tsu(2) Setup time, DIN 10 ns th(2) Hold time, DIN 10 ns tsu(3) Setup time, LRCIN 10 ns th(3) Hold time, LRCIN 10 ns

Pulse duration, BCLK ns

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

LSB

w(8)

w(5)

w(6)

c(3)

su(5)

su(4)

h(4)

SCLK

DIN

T0550-01

BCLK

LRCIN

DIN

DOUT

LRCOUT

c(2)

w(4)

w(3)

su(2)

h(3)

h(2)

su(3)

pd(2)

T0549-01

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

www.ti.com

Figure 2-3. Slave-Mode Timing Requirements

2.4.3 3-Wire Control Interface (SDIN)

PARAMETER MIN TYP MAX UNIT

tw(5) High 20 tw(6) Low 20 tc(3) Clock period, SCLK 80 ns tsu(4) Clock rising edge to CS rising edge, SCLK 60 ns tsu(5) Setup time, SDIN to SCLK 20 ns th(4) Hold time, SCLK to SDIN 20 ns tw(7) High 20 tw(8) Low 20

Clock pulse duration, SCLK ns

Pulse duration, CS ns

Figure 2-4. 3-Wire Control Interface Timing Requirements

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

SCLK

DIN

w(9)

w(10)

h(5)

h(6)

su(7)

su(8)

T0551-01

TLV320AIC23B-Q1

www.ti.com

SGLS240C –MARCH 2004–REVISED JUNE 2012

2.4.4 2-Wire Control Interface

PARAMETER MIN TYP MAX UNIT

tw(9) High 1.3 µs tw(10) Low 600 ns f(sf) Clock frequency, SCLK 0 400 kHz th(5) Hold time (start condition) 600 ns tsu(6) Setup time (start condition) 600 ns th(6) Data hold time 900 ns tsu(7) Data setup time 100 ns tr Rise time, SDIN, SCLK 300 ns tf Fall time, SDIN, SCLK 300 ns tsu(8) Setup time (stop condition) 600 ns tsp Pulse width of spikes suppressed by input filter 0 50 ns

Clock pulse duration, SCLK

Figure 2-5. 2-Wire Control Interface Timing Requirements

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

MSB LSB

B15

B14

B13

B12 B11

B10 B9 B8

B2 B1

SCLK

SDIN

T0552-01

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

3 How to Use the TLV320AIC23B-Q1

3.1 Control Interfaces

The TLV320AIC23B-Q1 has many programmable features. The control interface is used to program the registers of the device. The control interface complies with SPI (3-wire operation) and 2-wire operation specifications. The state of the MODE terminal selects the control interface type. The MODE pin must be hardwired to the required level.

MODE INTERFACE

0 2-wire 1 SPI

3.1.1 SPI

In SPI mode, SDIN carries the serial data, SCLK is the serial clock and CS latches the data word into the TLV320AIC23B-Q1. The interface is compatible with microcontrollers and DSPs with an SPI interface.

A control word consists of 16 bits, starting with the MSB. The data bits are latched on the rising edge of SCLK. A rising edge on CS after the 16th rising clock edge latches the data word into the AIC (see

Figure 3-1).

The control word is divided into two parts. The first part is the address block, the second part is the data block:

www.ti.com

3.1.2 2-Wire

In 2-wire mode, the data transfer uses SDIN for the serial data and SCLK for the serial clock. The start condition is a falling edge on SDIN while SCLK is high. The seven bits following the start condition determine which device on the 2-wire bus receives the data. R/W determines the direction of the data transfer. The TLV320AIC23B-Q1 is a write only device and responds only if R/W is 0. The device operates only as a slave device whose address is selected by setting the state of the CS pin as follows.

B[15:9] Control Address Bits B[8:0] Control Data Bits

Figure 3-1. SPI Timing

CS STATE ADDRESS

(Default = 0)

0 0011010 1 0011011

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

ADDR R/W ACK

Start Stop

8 9

B15–B8

B7–B0

ACK

SCLK

SDI

T0553-01

TLV320AIC23B-Q1

www.ti.com

The device that recognizes the address responds by pulling SDIN low during the ninth clock cycle, acknowledging the data transfer. The control follows in the next two eight-bit blocks. The stop condition after the data transfer is a rising edge on SDIN when SCLK is high (see Figure 3-2).

The 16-bit control word is divided into two parts. The first part is the address block, the second part is the data block:

SGLS240C –MARCH 2004–REVISED JUNE 2012

B[15:9] Control Address Bits B[8:0] Control Data Bits

Figure 3-2. 2-Wire Compatible Timing

3.1.3 Register Map

The TLV320AIC23B-Q1 has the following set of registers, which are used to program the modes of operation. To minimize corruption and potential noise injection due to improper sequencing, program the registers while the device is powered down (Register 0x06, value 0x80). After the registers are programmed, power on the device (Register 0x06, value 0x28).

ADDRESS REGISTER

0000000 Left line input channel volume control 0000001 Right line input channel volume control 0000010 Left channel headphone volume control 0000011 Right channel headphone volume control 0000100 Analog audio path control 0000101 Digital audio path control 0000110 Power down control 0000111 Digital audio interface format 0001000 Sample rate control 0001001 Digital interface activation 0001111 Reset register

Table 3-1. Left Line Input Channel Volume Control (Address: 0000000)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function LRS LIM X X LIV4 LIV3 LIV2 LIV1 LIV0 Default 0 1 0 0 1 0 1 1 1

LRS Left/right line simultaneous volume/mute update

Simultaneous update 0 = Disabled 1 = Enabled LIM Left line input mute 0 = Normal 1 = Muted LIV[4:0] Left line input volume control (10111 = 0 dB default)

11111 = 12 dB down to 00000 = –34.5 dB in 1.5-dB steps X Reserved

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

www.ti.com

Table 3-2. Right Line Input Channel Volume Control (Address: 0000001)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function RLS RIM X X RIV4 RIV3 RIV2 RIV1 RIV0 Default 0 1 0 0 1 0 1 1 1

RLS Right/left line simultaneous volume/mute update

Simultaneous update 0 = Disabled 1 = Enabled RIM Right line input mute 0 = Normal 1 = Muted RIV[4:0] Right line input volume control (10111 = 0 dB default)

11111 = 12 dB down to 00000 = –34.5 dB in 1.5-dB steps X Reserved

Table 3-3. Left Channel Headphone Volume Control (Address: 0000010)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function LRS LZC LHV6 LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 Default 0 1 1 1 1 1 0 0 1

LRS Left/right headphone channel simultaneous volume/mute update

Simultaneous update 0 = Disabled 1 = Enabled LZC Left channel zero-cross detect

Zero-cross detect 0 = Off 1 = On LHV[6:0] Left Headphone volume control (1111001 = 0 dB default)

1111111 = 6 dB, 79 steps between 6 dB and −73 dB (mute), 0110000 = −73 dB (mute), anything below 0110000 does nothing −

you are still muted

Table 3-4. Right Channel Headphone Volume Control (Address: 0000011)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function RLS RZC RHV6 RHV5 RHV4 RHV3 RHV2 RHV1 RHV0 Default 0 1 1 1 1 1 0 0 1

LRS Right/left headphone channel simultaneous volume/mute update

Simultaneous update 0 = Disabled 1 = Enabled

RZC Right channel zero-cross detect

Zero-cross detect 0 = Off 1 = On

RHV[6:0] Right headphone volume control (1111001 = 0 dB default)

1111111 = 6 dB, 79 steps between 6 dB and −73 dB (mute), 0110000 = −73 dB (mute), any thing below 0110000 does nothing − you are still muted

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

TLV320AIC23B-Q1

www.ti.com

SGLS240C –MARCH 2004–REVISED JUNE 2012

Table 3-5. Analog Audio Path Control (Address: 0000100)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function STA2 STA1 STA0 STE DAC BYP INSEL MICM MICB Default 0 0 0 0 1 1 0 1 0

STA[2:0] and STE

STE STA2 STA1 STA0 ADDED SIDETONE

1 1 X X 0 dB 1 0 0 0 -6 dB 1 0 0 1 -9 dB 1 0 1 0 -12 dB 1 0 1 1 -18 dB 0 X X X Disabled

DAC DAC select 0 = DAC off 1 = DAC selected BYP Bypass 0 = Disabled 1 = Enabled INSEL Input select for ADC 0 = Line 1 = Microphone MICM Microphone mute 0 = Normal 1 = Muted MICB Microphone boost 0 = dB 1 = 20 dB X Reserved

Table 3-6. Digital Audio Path Control (Address: 0000101)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function X X X X X DACM DEEMP1 DEEMP0 ADCHP Default 0 0 0 0 0 0 1 0 0

DACM DAC soft mute 0 = Disabled 1 = Enabled DEEMP[1:0] De-emphasis control 00 = Disabled 01 = 32 kHz 10 = 44.1 kHz 11 = 48 kHz ADCHP ADC high-pass filter 1 = Disabled 0 = Enabled X Reserved

Table 3-7. Power Down Control (Address: 0000110)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function X OFF CLK OSC OUT DAC ADC MIC LINE Default 0 0 0 0 0 0 1 1 1

OFF Device power 0 = On 1 = Off CLK Clock 0 = On 1 = Off OSC Oscillator 0 = On 1 = Off OUT Outputs 0 = On 1 = Off DAC DAC 0 = On 1 = Off ADC ADC 0 = On 1 = Off MIC Microphone input 0 = On 1 = Off LINE Line input 0 = On 1 = Off X Reserved

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

www.ti.com

Table 3-8. Digital Audio Interface Format (Address: 0000111)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function X X MS LRSWAP LRP IWL1 IWL0 FOR1 FOR0 Default 0 0 0 0 0 0 0 0 1

MS Maser/slave mode 0 = Slave 1 = Master LRSWAP DAC left/right swap 0 = Disabled 1 = Enabled LRP DAC left/right phase 0 = Right channel on, LRCIN high

1 = Right channel on, LRCIN low DSP mode 1 = MSB is available on second BCLK rising edge after LRCIN rising edge

0 = MSB is available on first BCLK rising edge after LRCIN rising edge IWL[1:0] Input bit length 00 = 16 bit 01 = 20 bit 10 = 24 bit 11 = 32 bit FOR[1:0] Data format 11 = DSP format, frame sync followed by two data words

10 = I2S format, MSB first, left – 1 aligned

01 = MSB first, left aligned

00 = MSB first, right aligned X Reserved NOTES: 1. In master mode, the TLV320AIC23B-Q1 supplies the BCLK, LRCOUT, and LRCIN. In slave mode, BCLK, LRCOUT, and

LRCIN are supplied to the TLV320AIC23B-Q1.

2. In normal mode, BCLK = MCLK/4 for all sample rates except for 88.2 kHz and 96 kHz. For 88.2 kHz and 96 kHz sample rate, BCLK = MCLK.

3. In USB mode, bit BCLK = MCLK

Table 3-9. Sample Rate Control (Address: 0001000)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Norma

Default 0 0 0 1 0 0 0 0 0 CLKIN Clock input divider 0 = MCLK 1 = MCLK/2

CLKOUT Clock output divider 0 = MCLK 1 = MCLK/2 SR[3:0] Sampling rate control (see Section 3.3.2.1 and Section 3.3.2.2) BOSR Base oversampling rate

USB mode: 0 = 250 f

Normal mode: 0 = 256 f USB/Normal Clock mode select: 0 = Normal 1 = USB X Reserved

1 = 272 f

1 = 384 f

s s

Table 3-10. Digital Interface Activation (Address: 0001001)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function X RES RES X X X X X ACT Default 0 0 0 0 0 0 0 0 0

ACT Activate interface 0 = Inactive 1 = Active X Reserved

Table 3-11. Reset Register (Address: 0001111)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function RES RES RES RES RES RES RES RES RES Default 0 0 0 0 0 0 0 0 0

RES Write 000000000 to this register triggers reset

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

50 kΩ

10 kΩ

VMID

0 dB/20 dB

To ADC

MICIN

S0527-01

C2 +

CDIN LINEIN

S0526-01

AGND

Where:

R1 = 5 kΩ R2 = 5 kΩ C1 = 47 pF C2 = 470 nF

TLV320AIC23B-Q1

www.ti.com

3.2 Analog Interface

3.2.1 Line Inputs

The TLV320AIC23B-Q1 has line inputs for the left and the right audio channels (RLINEIN and LLINEIN). Both line inputs have independently programmable volume controls and mutes. Active and passive filters for the two channels prevent high frequencies from folding back into the audio band.

The line-input gain is logarithmically adjustable from 12 dB to –34.5 dB in 1.5-dB steps. The ADC fullscale range is 1 V AVDD. To avoid distortions, it is important not to exceed the full-scale range.

The gain is independently programmable on both left and right line-inputs. To reduce the number of software write cycles required. Both channels can be locked to the same value by setting the RLS and LRS bits (see Section 3.1.3).

The line inputs are biased internally to VMID. When the line inputs are muted or the device is set to standby mode, the line inputs are kept biased to VMID using special antithump circuitry. This reduces audible clicks that otherwise might be heard when reactivating the inputs.

For interfacing to a CD system, the line input should be scaled to 1 V shown in Figure 3-3.

SGLS240C –MARCH 2004–REVISED JUNE 2012

at AVDD= 3.3 V. The full-scale range tracks linearly with analog supply voltage

RMS

to avoid clipping, using the circuit

RMS

R1 and R2 divide the input signal by two, reducing the 2 V the AIC23B inputs. The C1 filters high-frequency noise, and C2 removes any dc component from the signal.

3.2.2 Microphone Input

MICIN is a high-impedance, low-capacitance input that is compatible with a wide range of microphones. It has a programmable volume control and a mute function. Active and passive filters prevent high frequencies from folding back into the audio band.

The MICIN signal path has two gain stages. The first stage has a nominal gain of G1 = 50 k/10 k = 5. By adding an external resistor (R 50 k/(10 k + R programmable gain of 0 dB or 20 dB (see Section 3.1.3).

). For example, R

MIC

Figure 3-3. Analog Line Input Circuit

from the CD player to the nominal 1 V

RMS

) in series with MICIN, the gain of the first stage can be adjusted by G1 =

MIC

= 40 k gives a gain of 0 dB. The second stage has a software

MIC

RMS

Figure 3-4. Microphone Input Circuit

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

The microphone input is biased internally to VMID. When the line inputs are muted, the MICIN input is kept biased to VMID using special antithump circuitry. This reduces audible clicks that may otherwise be heard when reactivating the input.

The MICBIAS output provides a low-noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. The maximum source current capability is 3 mA. This limits the smallest value of external biasing resistors that safely can be used.

The MICBIAS output is not active in standby mode.

3.2.3 Line Outputs

The TLV320AIC23B-Q1 has two low-impedance line outputs (LLINEOUT and RLINEOUT) capable of driving line loads with 10-kΩ and 50-pF impedances.

The DAC full-scale output voltage is 1 V analog supply voltage AVDD. The DAC is connected to the line outputs via a low-pass filter that removes out-of-band components. No further external filtering is required in most applications.

The DAC outputs, line inputs, and the microphone signal are summed into the line outputs. These sources can be switched off independently. For example, in bypass mode, the line inputs are routed to the line outputs, bypassing the ADC and the DAC. If sidetone is enabled, the microphone signal is routed to both line outputs via a four-step programmable attenuation circuit.

The line outputs are muted by either muting the DAC (analog) or soft muting (digital) and disabling the bypass and sidetone paths (see Section 3.1.3).

at AVDD= 3.3 V. The full-scale range tracks linearly with the

RMS

www.ti.com

3.2.4 Headphone Output

The TLV320AIC23B-Q1 has stereo headphone outputs (LHPOUT and RHPOUT), and is designed to drive 16-Ω or 32-Ω headphones. The headphone output includes a high-quality volume control and mute function.

The headphone volume is logarithmically adjustable from 6 dB to –73 dB in 1-dB steps. Writing 000000 to the volume-control registers (see Section 3.1.3) mutes the headphone output. When the headphone output is muted or the device is placed in standby mode, the dc voltage is maintained at the outputs to prevent audible clicks.

A zero-cross detection circuit is provided under the control of the LZC and RZC bits. If this circuit is enabled, the volume-control values are updated only when the input signal to the gain stage is close to the analog ground level.

This minimizes audible clicks as the volume is changed or the device is muted. This circuit has no timeout, so, if only dc levels are being applied to the gain stage input of more than 20 mV, the gain is not updated.

The gain is independently programmable on the left and right channels. Both channels can be locked to the same value by setting the RLS and LRS bits (see Section 3.1.3).

3.2.5 Analog Bypass Mode

The TLV320AIC23B-Q1 includes a bypass mode in which the analog line inputs are directly routed to the analog line outputs, bypassing the ADC and DAC. This is enabled by selecting the bypass bit in the analog audio path control register (see Section 3.1.3).

For a true bypass mode, the output from the DAC and the sidetone should be disabled. The line input and headphone output volume controls and mutes are still operational in bypass mode. Therefore the line inputs, DAC output, and microphone input can be summed together. The maximum signal at any point in the bypass path must be no greater than 1 V

at AVDD= 3.3 V to avoid clipping and distortion. This

RMS

amplitude tracks linearly with AVDD.

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

n−1

1 n−1

1/fs

MSB LSB

LRCIN/

LRCOUT

BCLK

DIN/

DOUT

Left Channel Right Channel

T0554-01

TLV320AIC23B-Q1

www.ti.com

3.2.6 Sidetone Insertion

The TLV320AIC23B-Q1 has a sidetone insertion made where the microphone input is routed to the line and headphone outputs. This is useful for telephony and headset applications. The attenuation of the sidetone signal may be set to −6 dB, −9 dB, −12 dB, −15 dB, or 0 dB, by software selection (see

Section 3.1.3). If this mode is used to sum the microphone input with the DAC output and line inputs, care

must be taken not to exceed signal level to avoid clipping and distortion.

3.3 Digital Audio Interface

3.3.1 Digital Audio-Interface Modes

The TLV320AIC23B-Q1 supports four audio-interface modes.

• Right justified

• Left justified

• I2S mode

• DSP mode The four modes are MSB first and operate with a variable word width between 16 to 32 bits (except right-

justified mode, which does not support 32 bits). The digital audio interface consists of clock signal BCLK, data signals DIN and DOUT, and

synchronization signals LRCIN and LRCOUT. BCLK is an output in master mode and an input in slave mode.

SGLS240C –MARCH 2004–REVISED JUNE 2012

3.3.1.1 Right-Justified Mode

In right-justified mode, the LSB is available on the rising edge of BCLK, preceding a falling edge on LRCIN or LRCOUT (see Figure 3-5).

3.3.1.2 Left-Justified Mode

In left-justified mode, the MSB is available on the rising edge of BCLK, following a rising edge on LRCIN or LRCOUT (see Figure 3-6).

Figure 3-5. Right-Justified Mode Timing

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

n−1

1 n−1

MSB LSB

LRCIN/

LRCOUT

BCLK

DIN/

DOUT

Left Channel Right Channel

MSB LSB

T0557-01

n−1

1 n−1

1/fs

MSB LSB

LRCIN/

LRCOUT

BCLK

DIN/

DOUT

Left Channel Right Channel

1BCLK

T0556-01

n−1

1 n−1

1/fs

MSB LSB

LRCIN/

LRCOUT

BCLK

DIN/

DOUT

Left Channel Right Channel

T0555-01

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

3.3.1.3 I2S Mode

In I2S mode, the MSB is available on the second rising edge of BCLK, after the falling edge on LRCIN or LRCOUT (see Figure 3-7).

www.ti.com

Figure 3-6. Left-Justified Mode Timing

Figure 3-7. I2S Mode Timing

3.3.1.4 DSP Mode

The DSP mode is compatible with the McBSP ports of TI DSPs. LRCIN and LRCOUT must be connected to the Frame Sync signal of the McBSP. A falling edge on LRCIN or LRCOUT starts the data transfer. The left-channel data consists of the first data word, which is immediately followed by the right channel data word (see Figure 3-8). Input word length is defined by the IWL register. Figure 3-8 shows LRP = 1 (default LRP = 0).

Figure 3-8. DSP Mode Timing

Product Folder Link(s): TLV320AIC23B-Q1

Submit Documentation Feedback

TLV320AIC23B-Q1

www.ti.com

SGLS240C –MARCH 2004–REVISED JUNE 2012

3.3.2 Audio Sampling Rates

The TLV320AIC23B-Q1 can operate in master or slave clock mode. In the master mode, the TLV320AIC23B-Q1 clock and sampling rates are derived from a 12-MHz MCLK signal. This 12-MHz clock signal is compatible with the USB specification. The TLV320AIC23B-Q1 can be used directly in a USB system.

In the slave mode, an appropriate MCLK or crystal frequency and the sample rate control register settings control the TLV320AIC23B-Q1 clock and sampling rates.

The settings in the sample rate control register control the clock mode and sampling rates.

Table 3-12. Sample Rate Control (Address: 0001000)

BIT D8 D7 D6 D5 D4 D3 D2 D1 D0

Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Normal Default 0 0 0 1 0 0 0 0 0

CLKIN Clock input divider 0 = MCLK 1 = MCLK/2 CLKOUT Clock output divider 0 = MCLK 1 = MCLK/2 SR[3:0] Sampling rate control (see Sections 3.3.2.1 AND 3.3.2.2) BOSR Base oversampling rate

USB mode: 0 = 250 f

Normal mode: 0 = 256 f USB/Normal Clock mode select: 0 = Normal 1 = USB X Reserved

1 = 272 f

1 = 384 f

s s

The clock circuit of the AIC23B has two internal dividers. The first, controlled by CLKIN, applies to the sampling-rate generator of the codec. The second, controlled by CLKOUT, applies only to the CLKOUT terminal. By setting CLKIN to 1, the entire codec is clocked with half the frequency, effectively dividing the resulting sampling rates by two. The following sampling-rate tables are based on CLKIN = MCLK.

3.3.2.1 USB-Mode Sampling Rates (MCLK = 12 MHz)

In the USB mode, the following ADC and DAC sampling rates are available:

SAMPLING RATE

ADC (kHz) DAC (kHz) SR3 SR2 SR1 SR0 BOSR

96 96 3 0 1 1 1 0

88.2 88.2 2 1 1 1 1 1 48 48 0 0 0 0 0 0

44.1 44.1 1 1 0 0 0 1 32 32 0 0 1 1 0 0

8.021 8.021 1 1 0 1 1 1 8 8 0 0 0 1 1 0

48 8 0 0 0 0 1 0

44.1 8.021 1 1 0 0 1 1 8 48 0 0 0 1 0 0

8.021 44.1 1 1 0 1 0 1

(1) The sampling rates are derived from the 12-MHz master clock. The available oversampling rates do not produce exactly 8-kHz, 44.1-

kHz, and 88.2-kHz sampling rates, but 8.021 kHz, 44.117 kHz, and 88.235 kHz, respectively. See Figure 3-9 through Figure 3-26 for filter responses.

(1)

FILTER TYPE

SAMPLING-RATE CONTROL SETTINGS

3.3.2.2 Normal-Mode Sampling Rates

In normal mode, the following ADC and DAC sampling rates, depending on the MCLK frequency, are available:

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

MCLK = 12.288 MHz

SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS

ADC (kHz) DAC (kHz) SR3 SR2 SR1 SR0 BOSR

FILTER TYPE

96 96 2 0 1 1 1 0 48 48 1 0 0 0 0 0 32 32 1 0 1 1 0 0

8 8 1 0 0 1 1 0

48 8 1 0 0 0 1 0

8 48 1 0 0 1 0 0

MCLK = 11.2896 MHz

SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS

ADC (kHz) DAC (kHz) SR3 SR2 SR1 SR0 BOSR

FILTER TYPE

88.2 88.2 2 1 1 1 1 0

44.1 44.1 1 1 0 0 0 0

8.021 8.021 1 1 0 1 1 0

44.1 8.021 1 1 0 0 1 0

8.021 44.1 1 1 0 1 0 0

MCLK = 18.432 MHz

SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS

ADC (kHz) DAC (kHz) SR3 SR2 SR1 SR0 BOSR

FILTER TYPE

96 96 2 0 1 1 1 1 48 48 1 0 0 0 0 1 32 32 1 0 1 1 0 1

8 8 1 0 0 1 1 1

48 8 1 0 0 0 1 1

8 48 1 0 0 1 0 1

www.ti.com

MCLK = 16.9344 MHz

SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS

ADC (kHz) DAC (kHz) SR3 SR2 SR1 SR0 BOSR

FILTER TYPE

88.2 88.2 2 1 1 1 1 1

44.1 44.1 1 1 0 0 0 1

8.021 8.021 1 1 0 1 1 1

44.1 8.021 1 1 0 0 1 1

8.021 44.1 1 1 0 1 0 1

3.3.3 Digital Filter Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Filter Characteristics (TI DSP 250 fsMode Operation)

Passband ±0.05 dB 0.416 f Stopband –6 dB 0.5 f

Passband ripple ±0.05 dB Stopband attenuation f > 0.584 f

–60 dB

ADC Filter Characteristics (TI DSP 272 fsand Normal Mode Operation)

Passband ±0.05 dB 0.4535 f Stopband –6 dB 0.5 f

Passband ripple ±0.05 dB Stopband attenuation f > 0.5465 f

–60 dB

Hz Hz

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

−10

−8

−6

−4

−2

0 0.1 0.2 0.3 0.4 0.5

Normalized Audio Sampling Frequency

Filter Response (dB)

G001

−10

−8

−6

−4

−2

0 0.1 0.2 0.3 0.4 0.5

Normalized Audio Sampling Frequency

Filter Response (dB)

G002

TLV320AIC23B-Q1

www.ti.com

SGLS240C –MARCH 2004–REVISED JUNE 2012

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC High-Pass Filter Characteristics

Corner frequency –3 dB, fs= 44.1 kHz 3.7 Hz

–3 dB, fs= 48 kHz 4 Hz –0.5 dB, fs= 44.1 kHz 10.4 Hz –0.5 dB, fs= 48 kHz 11.3 Hz –0.1 dB fs= 44.1 kHz 21.6 Hz –0.1 dB, fs= 48 kHz 23.5 Hz

DAC Filter Characteristics (48-kHz Sampling Rate)

Passband ±0.03 dB 0.416 f

Stopband –6 dB 0.5 f

Hz Passband ripple ±0.03 dB Stopband attenuation f > 0.584 f

–50 dB

DAC Filter Characteristics (44.1-kHz Sampling Rate)

Passband ±0.03 dB 0.4535 f

Stopband –6 dB 0.5 f

Hz Passband ripple ±0.03 dB Stopband attenuation f > 0.5465 f

–50 dB

SPACE SPACE SPACE SPACE SPACE SPACE

FILTER RESPONSE FILTER RESPONSE

vs vs

NORMALIZED AUDIO SAMPLING FREQUENCY NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-9. Digital De-Emphasis Filter Response − Figure 3-10. Digital De-Emphasis Filter Response −

44.1 kHz Sampling 48 kHz Sampling

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

−0.1

−0.08

−0.06

−0.04

−0.02

0.02

0.04

0.06

0.08

0.1

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Audio Sampling Frequency

Filter Response (dB)

G004

−90

−70

−50

−30

−10

0 0.5 1 1.5 2 2.5 3

Normalized Audio Sampling Frequency

Filter Response (dB)

G003

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

www.ti.com

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-11. ADC Digital Filter Response 0: USB Mode (Group Delay = 12 Output Samples)

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-12. ADC Digital Filter Ripple 0: USB (Group Delay = 20 Output Samples)

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

−0.1

0.1

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Audio Sampling Frequency

Filter Response (dB)

G006

−90

−70

−50

−30

−10

0 0.5 1 1.5 2 2.5 3

Normalized Audio Sampling Frequency

Filter Response (dB)

G005

TLV320AIC23B-Q1

www.ti.com

SGLS240C –MARCH 2004–REVISED JUNE 2012

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-13. ADC Digital Filter Response 1: USB Mode Only

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-14. ADC Digital Filter Ripple 1: USB Mode Only

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Audio Sampling Frequency

Filter Response (dB)

G008

−90

−70

−50

−30

−10

0 0.5 1 1.5 2 2.5 3

Normalized Audio Sampling Frequency

Filter Response (dB)

G007

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

www.ti.com

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-15. ADC Digital Filter Response 2: USB Mode and Normal Modes (Group Delay = 3 Output

Samples)

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-16. ADC Digital Filter Ripple 2: USB Mode and Normal Modes

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Audio Sampling Frequency

Filter Response (dB)

G010

−90

−70

−50

−30

−10

0 0.5 1 1.5 2 2.5 3

Normalized Audio Sampling Frequency

Filter Response (dB)

G009

TLV320AIC23B-Q1

www.ti.com

SGLS240C –MARCH 2004–REVISED JUNE 2012

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-17. ADC Digital Filter Response 3: USB Mode Only

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-18. ADC Digital Filter Ripple 3: USB Mode Only

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

−0.1

−0.08

−0.06

−0.04

−0.02

0.02

0.04

0.06

0.08

0.1

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Audio Sampling Frequency

Filter Response (dB)

G012

−90

−70

−50

−30

−10

0 0.5 1 1.5 2 2.5 3

Normalized Audio Sampling Frequency

Filter Response (dB)

G011

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

www.ti.com

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-19. DAC Digital Filter Response 0: USB Mode

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-20. DAC Digital Filter Ripple 0: USB Mode

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

−0.1

−0.08

−0.06

−0.04

−0.02

0.02

0.04

0.06

0.08

0.1

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Audio Sampling Frequency

Filter Response (dB)

G014

−90

−70

−50

−30

−10

0 0.5 1 1.5 2 2.5 3

Normalized Audio Sampling Frequency

Filter Response (dB)

G013

TLV320AIC23B-Q1

www.ti.com

SGLS240C –MARCH 2004–REVISED JUNE 2012

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-21. DAC Digital Filter Response 1: USB Mode Only

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-22. DAC Digital Filter Ripple 1: USB Mode Only

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Audio Sampling Frequency

Filter Response (dB)

G016

−90

−70

−50

−30

−10

0 0.5 1 1.5 2 2.5 3

Normalized Audio Sampling Frequency

Filter Response (dB)

G015

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

www.ti.com

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-23. DAC Digital Filter Response 2: USB Mode and Normal Modes

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-24. DAC Digital Filter Ripple 2: USB Mode and Normal Modes

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

−0.4

−0.3

−0.2

−0.1

0.1

0.2

0.3

0.4

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Normalized Audio Sampling Frequency

Filter Response (dB)

G018

−90

−70

−50

−30

−10

0 0.5 1 1.5 2 2.5 3

Normalized Audio Sampling Frequency

Filter Response (dB)

G017

TLV320AIC23B-Q1

www.ti.com

SGLS240C –MARCH 2004–REVISED JUNE 2012

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-25. DAC Digital Filter Response 3: USB Mode Only

SPACE SPACE SPACE

FILTER RESPONSE

NORMALIZED AUDIO SAMPLING FREQUENCY

Figure 3-26. DAC Digital Filter Ripple 3: USB Mode Only

The delay between the converter is a function of the sample rate. The group delays for the AIC23B are shown in the following table. Each delay is one LR clock (1/sample rate).

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

TLV320AIC23B-Q1

SGLS240C –MARCH 2004–REVISED JUNE 2012

www.ti.com

Table 3-13. Group Delays

FILTER GROUP DELAY

DAC type 0 11 DAC type 1 18 DAC type 2 5 DAC type 3 5 ADC type 0 12 ADC type 1 20 ADC type 2 3 ADC type 3 6

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

TLV320AIC23B-Q1

www.ti.com

SGLS240C –MARCH 2004–REVISED JUNE 2012

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (June 2008) to Revision C Page

• Added sentences after: The TLV320AIC23B-Q1 has the following set of registers, which are used to

program the modes of operation, in the Register Map section. ......................................................... 15

Submit Documentation Feedback

Product Folder Link(s): TLV320AIC23B-Q1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status

6PAIC23BIPWRG4Q1 ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AIC23BIQ1

TLV320AIC23BIPWRQ1 ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AIC23BIQ1

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Samples

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

OTHER QUALIFIED VERSIONS OF TLV320AIC23B-Q1 :

Catalog: TLV320AIC23B

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

10-Dec-2020

Addendum-Page 2

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Datasheet TLV320AIC23B-Q1 Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual

1 1 Introduction

1.1 Features

1.2 Description

1.3 Functional Block Diagram

1.4 Pin Assignments

1.5 Ordering Information

1.6 Pin Functions

2 Electrical Specifications

2.1 Absolute Maximum Ratings

2.2 Recommended Operating Conditions

2.3 Electrical Characteristics

2.3.1 ADC

2.3.1.1 Line Input to ADC

2.3.1.2 Microphone Input to ADC

2.3.1.3 Microphone Bias

2.3.2 DAC

2.3.3 Analog Line Input to Line Output (Bypass)

2.3.4 Stereo Headphone Output

2.3.5 Analog Reference Levels

2.3.6 Digital I/O

2.3.7 Supply Current

2.4 Digital-Interface Timing

2.4.1 Audio Interface (Master Mode)

2.4.2 Audio Interface (Slave-Mode)

2.4.3 3-Wire Control Interface (SDIN)

2.4.4 2-Wire Control Interface

3 How to Use the TLV320AIC23B-Q1

3.1 Control Interfaces

3.1.1 SPI

3.1.2 2-Wire

3.1.3 Register Map

3.2 Analog Interface

3.2.1 Line Inputs

3.2.2 Microphone Input

3.2.3 Line Outputs

3.2.4 Headphone Output

3.2.5 Analog Bypass Mode

3.2.6 Sidetone Insertion

3.3 Digital Audio Interface

3.3.1 Digital Audio-Interface Modes

3.3.1.1 Right-Justified Mode

3.3.1.2 Left-Justified Mode

3.3.1.3 I2S Mode

3.3.1.4 DSP Mode

3.3.2 Audio Sampling Rates

3.3.2.1 USB-Mode Sampling Rates (MCLK = 12 MHz)

3.3.2.2 Normal-Mode Sampling Rates

3.3.3 Digital Filter Characteristics

Revision History