Texas Instruments TLV320AD543PTR, TLV320AD543PT Datasheet
TLV320AD543
Single Channel Data/Fax Codec
Data Manual
1999 Mixed-Signal Products
Printed in U.S.A.
03/99
SLAS214
TL V320AD543
Data Manual
Single Channel Data/Fax Codec
Literature Number: SLAS214
March 1999
Printed on Recycled Paper
IMPORTANT NOTICE
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or to discontinue any product or service without notice, and advise customers to obtain the latest
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is current and complete. All products are sold subject to the terms and conditions of sale supplied
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infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the
time of sale in accordance with TI’s standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing
of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUIT ABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
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operating safeguards must be provided by the customer to minimize inherent or procedural
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TI assumes no liability for applications assistance or customer product design. TI does not
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Copyright 1999, Texas Instruments Incorporated
iii
Contents
Section Title Page
1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Functional Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Analog Block Diagram 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Terminal Assignments 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Ordering Information 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Terminal Functions 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Functional Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Device Requirements and System Overview 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Codec Functions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Hybrid Functions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Miscellaneous Logic and Other Circuitry 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Codec Functional Description 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Operating Frequencies 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 ADC Signal Channel 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 DAC Signal Channel 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Sigma-Delta ADC 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Decimation Filter 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Sigma-Delta DAC 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Interpolation Filter 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Analog and Digital Loopbacks 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 Software Power Down 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Test Module 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Serial Communications 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Primary Serial Communication 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 FS High Mode Primary Communication Timing 4–2. . . . . . . . . . . . . . . . . . . . . .
4.2 FS Low Mode Primary Communication Timing 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Secondary Serial Communication 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 FS High Mode Secondary Communication Timing 4–4. . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 FS Low Mode Secondary Communication Timing 4–4. . . . . . . . . . . . . . . . . . . . . . . . . .
5 Specifications 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range 5–1. . . .
5.2 Recommended Operating Conditions 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Electrical Characteristics Over Recommended Operating Free-Air
Temperature Range DVDD = 3 V, A VDD = 3 V, MVDD = 3 V 5–1. . . . . . . . . . . . . . . . .
5.3.1 Digital Inputs and Outputs, fs = 8 kHz, Outputs Not Loaded 5–1. . . . . . . . . . .
5.3.2 ADC Path Filter, fs = 8 kHz 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 ADC Dynamic Performance, fs = 8 kHz 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
5.3.4 ADC Characteristics 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.5 DAC Path Filter, fs = 8 kHz 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.6 DAC Dynamic Performance 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.7 DAC Characteristics 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.8 Logic DC Electrical Characteristics 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.9 Power-Supply Rejection 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.10 Power-Supply 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.11 Flash Write Enable Circuit 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Timing Characteristics (see Parameter Measurement Information) 5–5. . . . . . . . . . .
5.4.1 Timing Requirements 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4.2 Switching Characteristics 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 Parameter Measurement Information 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Application Information 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Programmable Register Set A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Illustrations
Figure Title Page
4–1 Primary Communication DIN and DOUT Data Format 4–1. . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 FS High Mode Primary Serial Communication Timing 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 FS Low Mode Primary Serial Communication Timing 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Secondary Communication DIN and DOUT Data Format 4–3. . . . . . . . . . . . . . . . . . . . . . . .
4–5 FS Output During Software Secondary Serial Communication Request
(FS High Mode) 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–6 FS Output During Software Secondary Serial Communication Request
(FS Low Mode) 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 SCLK Timing 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Serial Communication Timing 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 ADC Decimation Filter Response 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 ADC Decimation Filter Passband Ripple 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 DAC Interpolation Filter Response 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 DAC Interpolation Filter Passband Ripple 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Functional Block of a Typical Application 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Differential Configuration Typical Application 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 Single-Ended Configuration Typical Application 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables
Table Title Page
4–1 Least-Significant-Bit Control Function 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–1
1 Introduction
The TLV320AD543 single channel data/fax codec is a mixed signal broadband connectivity device. The
TLV320AD543 is comprised of a single channel codec and analog hybrid circuitry with a serial port for
communication with the host processor. The device also contains programmable gain control and one A T41
speaker driver. The device operates with a 3-V analog, a 3-V digital, or a 3-V monitor power supply. The
device will be packaged in a single 48-pin PT (TQFP) package
.
1.1 Features
• Analog, Digital, and Monitor Amp Power Supplies: 3 V
• Differential and Single-Ended Driving of Analog Output
• Software Power-Down Mode
• Sample Rate Up to 11.025 kHz
• 16-Bit Signal Processing in the Codec With 2s-Complement Data Format
• Typical 79-db Dynamic Range
• Total Signal-to-Noise + Distortion of 76 dB for the ADCs
• Total Signal-to-Noise + Distortion of 78 dB for the DACs
• Programmable Gain Amplifier
• 600-Ω Driver
• 8-Ω AT41 Differential Speaker Driver With Programmable Gain Amplifier
• Flash Write Enable Circuit Provide Power for Writing the Flash Memory Device
• Available in 48-Pin PT (TQFP) Package Operating from 0_C to 70_C
• Transformer Reference ( 2.5 mA Source and Sink at 1.5 V for 3-V Supply) to Allow Single-Ended
Driving
1–2
1.2 Functional Block Diagram
Data
Channel
Serial
Port
Data Channel
Codec
H
Y
B
R
I
D
A
M
P
DRVR
Flash
Write
Enable
Control
Logic
1–3
1.3 Analog Block Diagram
+
–
DTRX_FB
DTRXM
CAP_D
DTRXP
+
–
16-Bit
ADC
Data (Hybrid)
1.5 V
Data_In PGA
0/6/12/18 dB Gain
with Mute
+
–
Data (Hybrid)
DTTX_OUTP
DT_REF
DTTX_INM
1.5 V
+
–
1.5 V
16-Bit
DAC
DT_BUFP
+
–
+
–
0/-6/-12/-18 dB or Mute
600-Ω Data_Out PGA
8-Ω Speaker Buffer
0 dB or Mute
MonOut PGA
0/3/6/9/12 dB Gain
with Mute
MONOUTP
MONOUTM
1.5 V
M
U
X
+
–
DTTX_INP
DTTX_OUTM
+
–
DT_BUFM
1–4
1.4 Terminal Assignments
1
2
3
4
5
6
7
8
9
10
27
28
29
30
31
32
33
34
35
36
NC
DREFP_DAC
NC
DT_MCLK
DREFM_DAC
RESET
DV
SS
DTRXM
DT_DIN
DT_SCLK
DAV
DD
DAV
SS
NC
CAP_D
DTRX_FB
DT_DOUT
NC
DT_FS
11
12
25
26
NC
DTRXP
NC
NC
1314 1516 171819 20 21 22 23 24
48474645 4443 42 41 40 39
3837
DT_REF
DTTX_OUTM
DT_BUFP
DT_BUFM
DV
DD
V
NC
FLSH_OUT
FLSH_IN
DTTX_OUTP
DTTX_INM
DTTX_INP
NC
NC
DREFM_ADC
TEST1
MONOUTM
MV
SS
MV
MONOUTP
TCLK
SI_SEL
FILTNCDREFP_ADC
TEST2
DD
TLV320AD543
NC–Make no external connection
SS
1.5 Ordering Information
PACKAGE
T
A
PLASTIC QUAD
FLATPACK (PT)
0°C to 70°C TLV320AD543
1–5
1.6 Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
CAP_D 7 I To eliminate dc offset, a capacitor is placed between CAP_D and DTRX_FB,
ac-coupling the input to the ADC.
DAV
DD
5 I Analog power supply (3 V)
DAV
SS
6 I Analog ground
DREFM_ADC 48 O ADC voltage reference filter output. DREFM_ADC provides lowpass filtering for the
internal band gap reference. The optimal ceramic capacitor value is 0.1 uF connected
between DREFM_ADC and DREFP_ADC. The nominal dc voltage at this terminal is
0V.
DREFP_ADC 47 O ADC voltage reference filter output. DREFP_ADC provides low-pass filtering for the
internal band gap reference. The optimal ceramic capacitor value is 0.1 µF connected
between DREFM_ADC and DREFP_ADC. The dc voltage at this terminal is 2.25 V
with a 3-V supply.
DREFM_DAC 2 O DAC voltage reference filter output. DREFM_DAC provides for low-pass filtering the
internal band gap reference. The optimal ceramic capacitor value is 0.1 µF connected
between DREFM_ADC and DREFP_ADC. The nominal dc voltage at this terminal is
0V.
DREFP_DAC 1 O DAC voltage reference filter output. DREFP_DAC provides for lowpass filtering the
internal band gap reference. The optimal ceramic capacitor value is 0.1 µF connected
between DREFM_DAC and DREFP_DAC. The dc voltage at this terminal is 2.25 V
at 3-V supply.
DT_BUFM 19 O Buffer amp analog inverting output. DT_BUFM can be programmed for 0 dB, -6 dB,
-12 dB, and -18 dB gain or muted using the control registers. This output is normally
fed to the DTTX_INM terminal through an input resistor.
DT_BUFP 18 O Buffer amp analog noninverting output. DT_BUFP can be programmed for 0 dB, -6 dB,
-12 dB and -18 dB gain or muted using the control registers. This output is normally
fed to the DTTX_INP terminal through an input resistor. DT_BUFP must be left
unconnected in single-ended hybrid.
DT_DIN 33 I Digital data input. DT_DIN handles DAC input data as well as control register
programming information during frame sync interval and is synchronized to
DT_SCLK.
DT_DOUT 31 O Digital data output. ADC output bits transmit data during the frame sync period which
is synchronized to DT_SCLK. DT_DOUT is at high impedance when DT_FS is not
activated.
DT_FS 30 O Serial port frame sync signal. DT_FS signals the beginning of transmit for ADC data
and receiving of DAC data. This signal can be active high (FS high mode) or active
low (FS low mode) depending on the voltage applied to SI_SEL (see Section 4,
Serial
Communications
).
DT_MCLK 34 I Master clock input. All internal clocks are derived from this clock.
DT_REF 13 O Reference voltage for the transformer at 1.5 V for 3-V supply. The maximum source
or sink current at this terminal is 2.5 mA. DT_REF must be left unconnected in
differential hybrid.
DTRX_FB 9 O Receive path amplifier feedback node. DTRX_FB terminal is connected to the
noninverting output of the receive path amplifier and allows a parallel
resistor/capacitor to be placed in the amplifier feedback path for setting gain and filter
poles.
DTRXM 10 I Receive path amplifier analog inverting input
DTRXP 12 I Receive path amplifier analog noninverting input
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