Input Common-Mode Range Exceeds Both
Supply Rails ... – 0.2V to V
D
Gain Bandwidth Product . . . 6.4MHz
D
Supply Current ...500µA/channel
D
Input Offset Voltage . . . 100 µV
D
Input Noise Voltage ...11nV/√Hz
D
Rail-to-Rail Output Swing
D
Slew Rate . . . 1.6 V/µs
D
±90mA Output Drive Capability
D
Micropower Shutdown Mode
DD+
+ 0.2V
OUT
GND
IN+
TLV2460
DBV PACKAGE
(TOP VIEW)
1
6
2
5
3
4
V
DD+
SHDN
IN–
(TLV2460/3/5) . . . 0.3 µA/channel
D
Available in 5- or 6-pin SOT23 and
8- or 10-Pin MSOP
D
Characterized From T
D
Universal Op Amp EVM
= –40°C to 125°C
A
description
The TLV246x is a family of low-power rail-to-rail input/output operational amplifiers specifically designed for
portable applications. The input common-mode voltage range extends beyond the supply rails for maximum
dynamic range in low-voltage systems. The amplifier output has rail-to-rail performance with high-output-drive
capability, solving one of the limitations of older rail-to-rail input/output operational amplifiers. This rail-to-rail
dynamic range and high output drive make the TLV246x ideal for buffering analog-to-digital converters.
The operational amplifier has 6.4 MHz of bandwidth and 1.6 V/µs of slew rate with only 500 µA of supply current,
providing good ac performance with low power consumption. Three members of the family offer a shutdown
terminal, which places the amplifier in an ultra-low supply current mode (I
= 0.3 µA/ch). While in shutdown,
DD
the operational-amplifier output is placed in a high-impedance state. DC applications are also well served with
an input noise voltage of 11 nV/√Hz and input offset voltage of 100 µV.
This family is available in the low-profile SOT23, MSOP, and TSSOP packages. The TLV2460 is the first
rail-to-rail input/output operational amplifier with shutdown available in the 6-pin SOT23, making it perfect for
high-density circuits. The family is specified over an expanded temperature range (T
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE
Θ
(°C/W)
D (8)38.3176725 mW
D (14)26.9122.6725 mW
D (16)25.7114.7725 mW
DBV (5)55324.1437 mW
DBV (6)55294.3437 mW
DGK54.23259.96424 mW
DGS54.1257.71424 mW
N (14)32781150 mW
N (16)32781150 mW
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (R
shown in Figure 49. A minimum value of 20 Ω should work well for most applications.
R
F
R
Input
G
_
+
R
NULL
C
) with the output of the amplifier, as
NULL
Output
LOAD
Figure 49. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
R
F
I
VOO+
R
G
R
S
V
ǒ
IO
Figure 50. Output Offset Voltage Model
1
)ǒ
R
R
IB–
I
IB+
+
V
I
F
Ǔ
"
I
Ǔ
IB
G
)
–
+
R
1
)ǒ
F
Ǔ
R
G
R
ǒ
S
V
O
"
I
Ǔ
IB–RF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
23
TLV2460, TLV2461, TLV2462, TLV2463, TLV2464, TLV2465, TLV246xA
FAMILY OF LOW-POWER RAIL-TO-RAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIERS WITH SHUTDOWN
SLOS220F – JULY 1998 – REVISED OCT OBER 1999
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifer
(see Figure 51).
R
G
R
F
–
R
R
C1
F
G
+
ǒ
Ǔ
1)sR1C1
f
1
–3dB
Ǔ
V
I
R1
V
O
+ǒ
1
V
I
)
+
2pR1C1
V
O
1
Figure 51. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
V
I
R2R1
C2
R
G
+
_
R
F
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
Three members of the TLV246x family (TLV2460/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.3 µA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care
should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place
the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to V
Therefore, when operating the device with split supply voltages (e.g. ±2.5 V), the shutdown terminal needs to
be pulled to V
The amplifier’s output with a shutdown pulse is shown in Figures 22, 23, 24, and 25. The amplifier is powered
with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon
and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output
waveform. The times for the single, dual, and quad are listed in the data tables.
circuit layout considerations
T o achieve the levels of high performance of the TL V246x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
– (not GND) to disable the operational amplifier.
DD
DD
/2.
D
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
Sockets – Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
D
Short trace runs/compact part placements – Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
D
Surface-mount passive components – Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
25
TLV2460, TLV2461, TLV2462, TLV2463, TLV2464, TLV2465, TLV246xA
FAMILY OF LOW-POWER RAIL-TO-RAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIERS WITH SHUTDOWN
SLOS220F – JULY 1998 – REVISED OCT OBER 1999
APPLICATION INFORMATION
general power dissipation considerations
For a given θJA, the maximum power dissipation is shown in Figure 53 and is calculated by the following formula:
T
MAX–TA
Where:
ǒ
PD+
P
= Maximum power dissipation of THS246x IC (watts)
D
T
= Absolute maximum junction temperature (150°C)
MAX
T
= Free-ambient air temperature (°C)
A
θ
= θ
JA
JC
+θ
q
θJC= Thermal coefficient from junction to case
θCA= Thermal coefficient from case to ambient air (°C/W)
2
1.75
Ǔ
JA
CA
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
PDIP Package
Low-K Test PCB
θJA = 104°C/W
TJ = 150°C
1.5
SOIC Package
1.25
Low-K Test PCB
θJA = 176°C/W
1
0.75
0.5
Maximum Power Dissipation – W
SOT-23 Package
0.25
Low-K Test PCB
θJA = 324°C/W
0
–55–40 –25 –10 5
TA – Free-Air Temperature – °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
20 35 50
MSOP Package
Low-K Test PCB
θJA = 260°C/W
65 80 95 110 125
Figure 53. Maximum Power Dissipation vs Free-Air Temperature
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
0.010 (0,25)
M
0.310 (7,87)
0.290 (7,37)
Seating Plane
0°–15°
0.010 (0,25) NOM
4040082/B 03/95
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
35
TLV2460, TLV2461, TLV2462, TLV2463, TLV2464, TLV2465, TLV246xA
FAMILY OF LOW-POWER RAIL-TO-RAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIERS WITH SHUTDOWN
SLOS220F – JULY 1998 – REVISED OCT OBER 1999
MECHANICAL DATA
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,65
14
1
1,20 MAX
0,30
0,19
8
4,50
4,30
7
A
0,15
0,05
6,60
6,20
M
0,10
Seating Plane
0,10
0,15 NOM
Gage Plane
0,25
0°–8°
0,75
0,50
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
8
3,10
2,90
14
5,10
4,90
16
5,10
20
6,60
6,404,90
24
7,90
7,70
28
9,80
9,60
4040064/E 08/96
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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