TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Wide Range of Supply Voltages
2 V to 8 V
D
Fully Characterized at 3 V and 5 V
D
Very-Low Supply-Current Drain
240 µA Typ at 3 V
D
Common-Mode Input Voltage Range
Includes Ground
D
High Input Impedance ...1012 Ω Typ
D
Fast Response Time . . . 200 ns Typ for
TTL-Level Input Step
D
Extremely Low Input Bias Current
5 pA Typ
D
Output Compatible With TTL, MOS, and
CMOS
D
Built-In ESD Protection
description
The TLV2354 consists of four independent,
low-power comparators specifically designed for
single power-supply applications and operateS
with power-supply rails as low as 2 V. When
powered from a 3-V supply, the typical supply
current is only 240 µA.
The TLV2354 is designed using the Texas Instruments LinCMOS technology and, therefore, features an
extremely high input impedance (typically greater than 10
12
Ω), which allows direct interfacing with
high-impedance sources. The outputs are N-channel open-drain configurations that require an external pullup
resistor to provide a positive output voltage swing, and they can be connected to achieve positive-logic
wired-AND relationships. The TL V2354I is fully characterized for operation from – 40°C to 85°C. The TLV2354M
is fully characterized for operation from – 55°C to 125°C.
The TLV2354 has internal electrostatic-discharge (ESD)-protection circuits and has been classified with a
1000-V ESD rating using Human Body Model testing. However, care should be exercised in handling this device
as exposure to ESD may result in degradation of the device parametric performance.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
VIOmax
at 25°C
SMALL
OUTLINE
(D)
†
CHIP
CARRIER
(FK)
CERAMIC
DIP
(J)
PLASTIC
DIP
(N)
TSSOP
(PW)
‡
CERAMIC
FLATPACK
(W)
CHIP
FORM
(Y)
–40°C to
85°C
5 mV TLV2354ID — — TLV2354IN TLV2354IPWLE —
–55°C to
125°C
5 mV — TLV2354MFK TLV2354MJ — — TLV2354MW
TLV2354Y
†
The D package is available taped and reeled. Add the suffix R to the device type (e.g., TL V2352IDR).
‡
The PW packages are only available left-ended taped and reeled (e.g., TLV2354IPWLE).
These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
LINCMOS is a trademark of Texas Instruments Incorporated.
OUT
symbol (each comparator)
IN+
IN–
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
2
3
4
5
6
7
14
13
12
11
10
9
8
TLV2354M
J OR W PACKAGE
(TOP VIEW)
NC – No internal connection
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
V
DD–
/GND
NC
4IN+
NC
4IN–
V
DD+
NC
2IN–
NC
2IN+
2OUT
1OUT
NC
3IN–
3IN +
3OUT
4OUT
1IN–
1IN+
NC
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
2OUT
V
DD
+
2IN–
2IN+
1IN–
1IN+
3OUT
4OUT
V
DD–
/GND
4IN+
4IN–
3IN+
3IN–
TLV2354I
D OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
2OUT
V
DD+
2IN–
2IN+
1IN–
1IN+
3OUT
4OUT
V
DD–
/GND
4IN+
4IN–
3IN+
3IN–
TLV2354I
PW PACKAGE
(TOP VIEW)
TLV2354AM, TLV2354M
FK PACKAGE
3OUT
4OUT
V
DD–
/GND
4IN+
4IN–
3IN+
3IN–
1OUT
2OUT
V
DD
+
2IN–
2IN+
1IN–
1IN+
TLV2254, TLV2254Y
SLCS012B – MAY 1992 – REVISED MARCH 1999
QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORSLinCMOS
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• 3
equivalent schematic
Common to All Channels
V
DD
GND
OUT
IN+
IN–
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2354Y chip information
This chip, when properly assembled, displays characteristics similar to the TL V2354. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. This chip may be mounted with
conductive epoxy or a gold-silicon preform.
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (11) INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
+
–
OUT
IN+
IN–
V
DD
GND
(10)
(7)
(6)
(11)
(1)
–
+
(13)
IN+
IN–
OUT
(12)
(4)
(5)
–
+
(2)
+
–
(9)
(8)
(14)
OUT
IN+
IN–
OUT
IN+
IN–
(3)
BONDING PAD ASSIGNMENTS
65
90
(13)
(1)
(3)
(4)
(5)
(6)
(7)
(8)
(9)(10)
(11)
(12)
(14)
(2)
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, VDD (see Note 1) 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
–0.3 to 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, VO 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of output short-circuit current to GND (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: TLV2354I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLV2354M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or PW package 260°C. . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FK, J, or W package 300°C. . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at the noninverting input terminal with respect to the inverting input terminal.
3. Short circuits from outputs to VDD can cause excessive heating and eventual device destruction.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING
FACTOR
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
FK
J
N
PW
W
950 mW
1375 mW
1375 mW
1150 mW
700 mW
700 mW
7.6 mW/°C
11.0 mW/°C
11.0 mW/°C
9.2 mW/°C
5.6 mW/°C
5.5 mW/°C
494 mW
715 mW
715 mW
598 mW
364 mW
370 mW
—
275 mW
275 mW
—
—
150 mW
recommended operating conditions
MIN MAX UNIT
Supply voltage, V
DD
2 8 V
p
VDD = 3 V 0 1.75
Common-mode input voltage, V
IC
VDD = 5 V 0 3.75
V
p
p
TLV2354I –40 85
°
O erating free-air tem erature, T
A
TLV2354M –55 125
°C
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature
†
TLV2354I
PARAMETER TEST CONDITIONS
T
A
‡
VDD = 3 V VDD = 5 V
UNIT
A
MIN TYP MAX MIN TYP MAX
p
25°C
1 5 1 5
VIOInput offset voltage
V
IC
=
V
ICR
min
,
See Note 4
Full range
7 7
mV
p
25°C
1 1
pA
IIOInput offset current
85°C
1 1
nA
p
25°C
5 5
pA
IIBInput bias current
85°C
2 2
nA
p
25°C 0 to 2 0 to 4
V
ICR
Common-mode input
voltage range
Full range
0 to
1.75
0 to
3.75
V
High-level output
25°C
0.1 0.1
nA
I
OH
g
current
V
ID
= 1
V
Full range
1 1
µA
Low-level output
25°C
115 300 150 400
V
OL
voltage
V
ID
= –1 V,
I
OL
= 2
mA
Full range
600 700
mA
I
OL
Low-level output
current
VID = –1 V, VOL = 1.5 V 25°C 6 16 6 16 mA
pp
25°C
240 500 290 600
IDDSupply current
V
ID
= 1 V,
No load
Full range
700 800
µ
A
†
All characteristics are measured with zero common-mode input voltage unless otherwise noted.
‡
Full range is –40°C to 85°C. IMPORTANT: See Parameter Measurement Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V with VDD = 5 V , 2 V with VDD = 3 V , or
below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and
checking for the appropriate output state.
switching characteristics, V
DD
= 3 V, T
A
= 25°C
TLV2354I
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
p
RL = 5.1 kΩ,
CL = 15 pF§,
p
p
Response time
See Note 5
L
100-mV input step with 5-mV overdrive
640
ns
§
CL includes probe and jig capacitance.
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses VO = 1 V with
VDD = 3 V or when the output crosses VO = 1.4 with VDD = 5 V.
switching characteristics, VDD = 5 V, TA = 25°C
TLV2354I
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
p
RL = 5.1 kΩ,
C
= 15 pF§,
100-mV input step with 5-mV overdrive 650
Response time
L
See Note 5
L
,
TTL-level input step 200
ns
§
CL includes probe and jig capacitance.
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses VO = 1 V with
VDD = 3 V or when the output crosses VO = 1.4 with VDD = 5 V.
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature
†
TLV2354M
PARAMETER TEST CONDITIONS
T
A
‡
VDD = 3 V VDD = 5 V
UNIT
A
MIN TYP MAX MIN TYP MAX
p
25°C
1 5 1 5
VIOInput offset voltage
V
IC
=
V
ICR
min
,
See Note 4
Full range
10 10
mV
p
25°C
1 1
pA
IIOInput offset current
125°C
10 10
nA
p
25°C
5 5
pA
IIBInput bias current
125°C
20 20
nA
p
25°C 0 to 2 0 to 4
V
ICR
Common-mode input
voltage range
Full range
0 to
1.75
0 to
3.75
V
High-level output
25°C
0.1 0.1
nA
I
OH
g
current
V
ID
= 1
V
Full range
1 1
µA
Low-level output
25°C
115 300 150 400
V
OL
voltage
V
ID
= –1 V,
I
OL
= 2
mA
Full range
600 700
mA
I
OL
Low-level output
current
VID = –1 V, VOL = 1.5 V 25°C 6 16 6 16 mA
pp
25°C
240 500 290 600
IDDSupply current
V
ID
= 1 V,
No load
Full range
700 800
µ
A
†
All characteristics are measured with zero common-mode input voltage unless otherwise noted.
‡
Full range is –55°C to 125°C. IMPORTANT: See Parameter Measurement Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V with VDD = 5 V , 2 V with VDD = 3 V , or
below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and
checking for the appropriate output state.
switching characteristics, V
DD
= 3 V, T
A
= 25°C
TLV2354M
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
p
RL = 5.1 kΩ,
CL = 100 pF§,
p
p
Response time
See Note 5
L
100-mV input step with 5-mV overdrive
1400
ns
§
CL includes probe and jig capacitance.
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses VO = 1 V with
VDD = 3 V or when the output crosses VO = 1.4 with VDD = 5 V.
switching characteristics, VDD = 5 V, TA = 25°C
TLV2354M
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
p
RL = 5.1 kΩ,
C
= 100 pF§,
100-mV input step with 5-mV overdrive 1300
Response time
L
See Note 5
L
,
TTL-level input step 900
ns
§
CL includes probe and jig capacitance.
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses VO = 1 V with
VDD = 3 V or when the output crosses VO = 1.4 with VDD = 5 V.
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, TA = 25°C
†
TLV2354Y
PARAMETER TEST CONDITIONS
VDD = 3 V VDD = 5 V
UNIT
MIN TYP MAX MIN TYP MAX
V
IO
Input offset voltage VIC = V
ICR
min, See Note 4 1 5 1 5 mV
I
IO
Input offset current 1 1 pA
I
IB
Input bias current 5 5 pA
V
ICR
Common-mode input voltage range 0 to 2 0 to 4 V
I
OH
High-level output current VID = 1 V 0.1 0.1 nA
V
OL
Low-level output voltage VID = –1 V, IOL = 2 mA 115 300 150 400 mV
I
OL
Low-level output current VID = –1 V, VOL = 1.5 V 6 16 6 16 mA
I
DD
Supply current VID = 1 V, No load 240 500 290 600 µA
†
All characteristics are measured with zero common-mode input voltage unless otherwise noted.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V with VDD = 5 V , 2 V with VDD = 3 V , or
below 400 mV with a 10-kΩ resistor between the output and VDD. They can be verified by applying the limit value to the input and
checking for the appropriate output state.
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 1
550
440
220
110
0
990
330
024681012
770
660
880
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1100
14 16
IOL – Low-Level Output Current – mA
VDD = 3 V
TA = 25°C
V
OL
– Low-Level Output Voltage – mV
Figure 2
300
280
240
220
200
380
260
– 75 – 50 –25 0 25 50 75
340
320
360
100 125
I
DD
– Supply Current –
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
No Load
VDD = 5 V
VDD = 3 V
Aµ
180
Figure 3
0
– 0.5
– 1
– 75 – 50 – 25 0 25 50
2
2.5
COMMON-MODE INPUT VOLTAGE RANGE
vs
FREE-AIR TEMPERATURE
3
75 100 125
1.5
0.5
TA – Free-Air Temperature – °C
– Common-Mode Input Voltage Range – V
ICR
V
VDD = 3 V
Negative Limit
Positive Limit
1
Figure 4
25
20
10
5
0
45
15
0 102030405060
35
30
40
OUTPUT FALL TIME
vs
CAPACITIVE LOAD
50
70 80 90 100
CL – Capacitive Load – pF
VDD = 3 V
Overdrive = 10 mV
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
t
– Output Fall Time – nsf
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
0
100
0
0 100 200 300 400 500 600
3
HIGH-TO-LOW-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS OVERDRIVE VOLTAGES
700 800 900 1000
t
PHL
– High-to-Low-Level Output
Propagation Delay Time – ns
VDD = 3 V
CL = 15 pF
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
20 mV
10 mV
5 mV
– Differential
Input Voltage – mV
– Output
Voltage – V
V
O
V
ID
Figure 6
0
100
0
0 100 200 300 400 500 6003700 800 900 1000
HIGH-TO-LOW-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS CAPACITIVE LOADS
t
PHL
– High-to-Low-Level Output
Propagation Delay Time – ns
VDD = 3 V
Overdrive = 10 mV
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
CL = 100 pF
CL = 15 pF
– Differential
Input Voltage – mV
– Output
Voltage – V
V
O
V
ID
CL = 50 pF
Figure 7
0
100
0
0 100 200 300 400 500 600
3
LOW-TO-HIGH-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS OVERDRIVE VOLTAGES
700 800 900 1000
t
PLH
– Low-to-High-Level Output
Propagation Delay Time – ns
VDD = 3 V
CL = 15 pF
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
20 mV
10 mV
5 mV
– Differential
Input Voltage – mV
– Output
Voltage – V
V
O
V
ID
Figure 8
0
100
0
0 100 200 300 400 500 6003700 800 900 1000
LOW-TO-HIGH-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS CAPACITIVE LOADS
t
PLH
– Low-to-High-Level Output
Propagation Delay Time – ns
VDD = 3 V
Overdrive = 10 mV
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
CL = 100 pF
CL = 50 pF
CL = 15 pF
– Differential
Input Voltage – mV
– Output
Voltage – V
V
O
V
ID
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
The digital output stage of the TLV2354 can be damaged if it is held in the linear region of the transfer curve.
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the
following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are
offered.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 9(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 9(b) for the V
ICR
test rather than changing the input voltages to provide greater
accuracy.
+
–
5 V
Applied V
IO
Limit
V
O
+
–
1 V
Applied V
IO
Limit
V
O
– 4 V
(a) VIO WITH VIC = 0 (b) VIO WITH VIC = 4 V
5.1 kΩ 5.1 kΩ
Figure 9. Method for Verifying That Input Offset Voltage Is Within Specified Limits
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal but
opposite in polarity to the input offset voltage, the output changes states.
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 10 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator in the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer , with C2 and R4 removing any residual
dc offset. The signal is then applied to the inverting input of the comparator under test while the noninverting input
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input
exactly equals the input offset voltage.
Voltage dividers R9 and R10 provide a step up of the input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is
suggested that their tolerance level be 1% or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage
can be measured with no device in the socket. Subsequently , this open-socket leakage value can be subtracted from
the measurement obtained with a device in the socket to obtain the actual input current of the device.
–
+
DUT
V
DD
+
–
–
+
–
+
C2
1 µF
R4
47 kΩ
R5
1.8 kΩ, 1%
C3
0.68 µF
U1c 1/4
TLV2354
U1b 1/4
TLV2354
U1a 1/4
TLV2354
R7
1 MΩ
R8
1.8 kΩ, 1%
R9
10 kΩ, 1%
R1
240 kΩ
R2
10 kΩ
C1
0.1 µF
R3
100 Ω
C4
0.1 µF
Integrator
R10
100 Ω, 1%
Buffer
Triangle
Generator
V
IO
(×100)
R6
5.1 kΩ
Figure 10. Circuit for Input Offset Voltage Measurement
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Propagation delay time is defined as the interval between the application of an input step function and the instant when
the output crosses VO = 1 V with VDD = 3 V or when the output crosses VO = 1.4 V with VDD = 5 V . Propagation delay
time, low-to-high-level output, is measured from the leading edge of the input pulse, while propagation delay time,
high-to-low-level output, is measured from the trailing edge of the input pulse. Propagation-delay-time measurement
at low input signal levels can be greatly affected by the input offset voltage. The offset voltage should be balanced
by the adjustment at the inverting input (as shown in Figure 3) so that the circuit is just at the transition point. Then
a low signal, for example a 105-mV or 5-mV overdrive, causes the output to change state.
+
–
DUT
V
DD
C
L
(see Note A)
Pulse
Generator
10 Ω
10 Turn
+ 1 V
– 1 V
1 kΩ
50 Ω
1 µF
0.1 µF
TEST CIRCUIT
100 mV
Input
Overdrive
t
PLH
100 mVInput
Overdrive
90%
10%
t
f
t
PHL
Low- to High-
Level Output
High- to LowLevel Output
VOLTAGE WAVEFORMS
5.1 kΩ
Input Offset Voltage
Compensation
Adjustment
90%
10%
t
r
VO = 1 V With VDD = 3 V
or
VO = 1.4 V With VDD = 5 V
NOTE A: CL includes probe and jig capacitance.
Figure 11. Propagation Delay, Rise, and Fall Times Test Circuit and Voltage Waveforms
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/B 03/95
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Four center pins are connected to die mount pad.
E. Falls within JEDEC MS-012
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/C 11/95
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.740
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ
22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
J (R-GDIP-T**) CERAMIC DUAL-IN-LINE PACKAGE
4040083/B 04/95
14 PIN SHOWN
22
0.410
(10,41)
0.390
(28,00)
1.100
(9,91)
0.388
(9,65)
20181614
PINS **
0.310
(7,87)
0.290
0.755
(19,18)
(19,94)
0.785
(7,37)
0.310
(7,87)
(7,37)
0.290
(23,10)
0.910
0.300
(7,62)
(6,22)
0.245
A
0.300
(7,62)
(6,22)
0.245
0.290
(7,87)
0.310
0.785
(19,94)
(19,18)
0.755
(7,37)
A MIN
A MAX
B MAX
B MIN
0.245
(6,22)
(7,11)
0.280
C MIN
C MAX
DIM
0.245
(6,22)
(7,62)
0.300
0.975
(24,77)
(23,62)
0.930
0.290
(7,37)
(7,87)
0.310
Seating Plane
0.014 (0,36)
0.008 (0,20)
C
8
7
0.020 (0,51) MIN
B
0.070 (1,78)
0.100 (2,54)
0.065 (1,65)
0.045 (1,14)
14
1
0.015 (0,38)
0.023 (0,58)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, GDIP1-T20, and GDIP1-T22
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE
20
0.975
(24,77)
0.940
(23,88)
18
0.920
0.850
14
0.775
0.745
(19,69)
(18,92)
16
0.775
(19,69)
(18,92)
0.745
A MIN
DIM
A MAX
PINS **
0.310 (7,87)
0.290 (7,37)
(23.37)
(21.59)
Seating Plane
0.010 (0,25) NOM
14/18 PIN ONL Y
4040049/C 08/95
9
8
0.070 (1,78) MAX
A
0.035 (0,89) MAX
0.020 (0,51) MIN
16
1
0.015 (0,38)
0.021 (0,53)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.240 (6,10)
0.260 (6,60)
M
0.010 (0,25)
0.100 (2,54)
0°–15°
16 PIN SHOWN
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040064/D 10/95
14 PIN SHOWN
Seating Plane
0,10 MIN
1,20 MAX
1
A
7
14
0,19
4,50
4,30
8
6,10
6,70
0,32
0,75
0,50
0,25
Gage Plane
0,15 NOM
0,65
M
0,13
0°–8°
0,10
PINS **
A MIN
A MAX
DIM
2,90
3,10
8
4,90
5,10
14
6,60
6,404,90
5,10
16
7,70
20
7,90
24
9,60
9,80
28
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
TLV2354, TLV2354Y
LinCMOS QUADRUPLE LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS012B – MAY 1992 – REVISED MARCH 1999
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
W (R-GDFP-F14) CERAMIC DUAL FLATPACK
0.360 (9,14)
0.240 (6,10)
87
141
0.735 (18,67)
0.235 (5,97)
0.004 (0,10)
0.026 (0,66)
0.015 (0,38)
0.015 (0,38)
0.045 (1,14)
0.335 (8,51)
0.007 (0,18)
0.045 (1,14)
Base and Seating Plane
0.025 (0,64)
0.019 (0,48)
0.390 (9,91)
0.260 (6,60)
0.080 (2,03)
1.000 (25,40)
4040180-2/B 03/95
0.360 (9,14)
0.240 (6,10)
0.280 (7,11)
0.255 (6,48)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only.
E. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Loading...