Texas Instruments TLV2344IPWR, TLV2344IPWLE, TLV2344IPW, TLV2344IN, TLV2344IDR Datasheet

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TLV2342, TLV2342Y, TLV2344, TLV2344Y

LinCMOS LOW-VOLTAGE HIGH-SPEED

OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Wide Range of Supply Voltages Over Specified Temperature Range:

–40°C to 85°C...2 V to 8 V

Fully Characterized at 3 V and 5 V

Single-Supply Operation

Common-Mode Input-Voltage Range Extends Below the Negative Rail and Up to V

–1 V at 25°C

Output Voltage Range Includes Negative Rail

High Input Impedance...10

Ω Typical

ESD-Protection Circuitry

Designed-In Latch-Up Immunity

description

The TL V234x operational amplifiers are in a family of devices that has been specifically designed for use in low-voltage single-supply applications. Unlike other products in this family designed primarily to meet aggressive power consumption specifications, the TLV234x was developed to offer ac performance approaching that of a BiFET operational amplifier while operating from a single-supply rail. At 3 V, the TLV234x has a typical slew rate of 2.1 V/µs and 790-kHz unity-gain bandwidth.

Each amplifier is fully functional down to a minimum supply voltage of 2 V and is fully characterized, tested, and specified at both 3-V and 5-V power supplies over a temperature range of –40°C to 85°C. The common-mode input voltage range includes the negative rail and extends to within 1 V of the positive rail.

AVAILABLE OPTIONS

PACKAGED DEVICES

max

AT 25°C

SMALL OUTLINE

†

(D)

PLASTIC DIP

(N)

PLASTIC DIP

(P)

TSSOP

‡

(PW)

CHIP FORM

(Y)

9 mV TLV2342ID — TLV2342IP TLV2342IPWLE TLV2342Y

–

40°C to 85°C

10 mV TLV2344ID TLV2344IN — TLV2344IPWLE TLV2344Y

†

The D package is available taped and reeled. Add R suffix to the device type (e.g., TL V2342IDR).

‡

The PW package is only available left-end taped and reeled (e.g., TLV2342IPWLE).

Chip forms are tested at 25°C only.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinCMOS is a trademark of Texas Instruments Incorporated.

1 2 3 4

8 7 6 5

1OUT

1IN– 1IN+

DD–

/GND

2OUT 2IN– 2IN+

1 2 3 4

8 7 6 5

1OUT

1IN–

1IN+

DD –

/GND

DD+

2OUT 2IN– 2IN+

1 2 3 4 5 6 7

14 13 12 11 10

9 8

1OUT

1IN– 1IN+

DD+

2IN+

2N–

2OUT

4OUT 4IN– 4IN+ V

DD–/GND

3IN+ 3IN– 3OUT

4OUT 4IN – 4IN + V

DD –

/GND 3IN + 3IN – 3OUT

1OUT

1IN – 1IN + V

DD+

2IN +

2IN –

2OUT

TLV2342

D OR P PACKAGE

(TOP VIEW)

TLV2342

PW PACKAGE

(TOP VIEW)

TLV2344

D OR N PACKAGE

(TOP VIEW)

TLV2344

PW PACKAGE

(TOP VIEW)

TLV2342, TLV2342Y, TLV2344, TLV2344Y LinCMOS LOW-VOLTAGE HIGH-SPEED OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

Low-voltage and low-power operation has been made possible by using the Texas Instruments silicon-gate LinCMOS technology . The LinCMOS process also features extremely high input impedance and ultra-low input bias currents. These parameters combined with good ac performance make the TLV234x effectual in applications such as high-frequency filters and wide-bandwidth sensors.

T o facilitate the design of small portable equipment, the TL V234x is made available in a wide range of package options, including the small-outline and thin-shrink small-outline packages (TSSOP). The TSSOP package has significantly reduced dimensions compared to a standard surface-mount package. Its maximum height of only

1.1 mm makes it particularly attractive when space is critical. The device inputs and outputs are designed to withstand –100-mA currents without sustaining latch-up. The

TLV234x incorporates internal ESD-protection circuits that prevents functional failures at voltages up to 2000 V as tested under MIL-PRF-38535, Method 3015.2; however, care should be exercised in handling these devices as exposure to ESD may result in the degradation of the device parametric performance.

TLV2342Y chip information

This chip, when properly assembled, displays characteristics similar to the TL V2342. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS.

–

1OUT

1IN+

1IN–

(8)

(6)

(3)

(2)

(5)

(1)

(7)

(4)

DD–

/GND

–

2OUT

2IN+

2IN–

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(1)

TLV2342, TLV2342Y, TLV2344, TLV2344Y

LinCMOS LOW-VOLTAGE HIGH-SPEED

OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2344Y chip information

This chip, when properly assembled, displays characteristics similar to the TL V2344. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

CHIP THICKNESS: 15 MILS TYPICAL BONDING PADS: 4 × 4 MILS MINIMUM TJmax = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS.

–

1OUT

1IN+

1IN–

(4)

(3)

(2)

(1)

DD–

/GND

–

3OUT

3IN+

3IN–

(10)

(9)

(8)

–

2OUT

2IN+

2IN–

(3)

(5)

(6)

(7)

–

4OUT

4IN+

4IN–

(12)

(13)

(14)

(11)

108

(8)

(9)(10)

(11)(12)

(13)

(14)

(1)

(2)

(3) (4) (5)

(6)

(7)

TLV2342, TLV2342Y, TLV2344, TLV2344Y LinCMOS LOW-VOLTAGE HIGH-SPEED OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

equivalent schematic (each amplifier)

IN+

P3 P4

IN–

N1 N2

OUT

GND

ACTUAL DEVICE COMPONENT COUNT

†

COMPONENT TLV2342 TLV2344

Transistors 54 108 Resistors 14 28 Diodes 4 8 Capacitors 2 4

†

Includes both amplifiers and all ESD, bias, and trim circuitry.

TLV2342, TLV2342Y, TLV2344, TLV2344Y

LinCMOS LOW-VOLTAGE HIGH-SPEED

OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage, V

(see Note 1) 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Differential input voltage, V

(see Note 2) V

DD±

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(any input) –0.3 V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input current, I

±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current, I

±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Duration of short-circuit current at (or below) T

= 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.

2. Differential voltages are at the noninverting input with respect to the inverting input.

3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded (see application selection).

DISSIPATION RATING TABLE

≤ 25°C DERATING FACTOR T

= 85°C

PACKAGE

POWER RATING ABOVE TA = 25°C

POWER RATING

D–8 725 mW 5.8 mW/°C 377 mW

D–14 950 mW 7.6 mW/°C 494 mW

N 1575 mW 5.6 mW/°C 364 mW P 1000 mW 8.0 mW/°C 520 mW

PW–8 525 mW 4.2 mW/°C 273 mW

PW–14 700 mW 6.0 mW/°C 340 mW

recommended operating conditions

MIN MAX UNIT

Supply voltage, V

2 8 V

VDD = 3 V –0.2 1.8

Common-mode input voltage, V

VDD = 5 V –0.2 3.8

Operating free-air temperature, T

–40 85 °C

TLV2342, TLV2342Y, TLV2344, TLV2344Y LinCMOS LOW-VOLTAGE HIGH-SPEED OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2342I electrical characteristics at specified free-air temperature

TLV2342I

PARAMETER TEST CONDITIONS

†

VDD = 3 V VDD = 5 V

UNIT

MIN TYP MAX MIN TYP MAX

= 1 V,

25°C

0.691.1

VIOInput offset voltage

= 50 Ω,

= 10

Ω

Full range

Average temperature

25°C to

VIO

coefficient of input offset

voltage

85°C

2.7

2.7µV/°C

Input offset current

25°C 0.1 0.1

(see Note 4)

= 1 V,

= 1

85°C 22 1000 24 1000

25°C 0.6 0.6

IIBInput bias current (see Note 4)

1 V

85°C 175 2000 200 2000

–0.2 –0.3 –0.2 –0.3

25°C

to to to to

Common-mode input voltage

2 2.3 4 4.2

ICR

range (see Note 5)

–0.2 –0.2

Full range

to to

1.8 3.8

= 1 V,

25°C

1.75

1.9

3.2

3.7

VOHHigh-l

evel output voltage

100 mV

IOH = –1 mA

Full range 1.7 3

= 1 V,

25°C

120

15090150

VOLL

ow-level output voltage

= –

100 mV

IOL = 1 mA

Full range 190 190

Large-signal differential

= 1 V,

25°C311523

voltage amplification

= 10 kΩ,

See Note 6

Full range 2 3.5

V/mV

= 1 V,

25°C65786580

CMRR

ommon-mode rejection ratio

ICR

min,

RS = 50 Ω

Full range 60 60

Supply-voltage rejection ratio VIC = 1 V, VO = 1 V,

25°C70957095

SVR

ygj

(∆VDD/∆VIO)

RS = 50 Ω

Full range 65 65

VO = 1 V, VIC = 1 V,

25°C

0.6531.4

3.2

IDDSu ly current

No load

Full range 4 4.4

†

Full range is –40°C to 85°C.

NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.

5. This range also applies to each input individually.

6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.

TLV2342, TLV2342Y, TLV2344, TLV2344Y

LinCMOS LOW-VOLTAGE HIGH-SPEED

OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2342I operating characteristics at specified free-air temperature, VDD = 3 V

TLV2342I

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

= 1 V,

I(PP)

= 1 V,

25°C

2.1

Slew rate at unity gain

= 10 kΩ,

= 20 F,

V/µs

ee Figure 34

85°C

1.7

f = 1 kHz, R

= 20 Ω,

VnEquivalent input noise voltage

See Figure 35

25°C

V/√H

= V

, C

= 20 pF,

25°C 170

BOMMaximum output-swing bandwidth

OOH

RL = 10 kΩ,

See Figure 34

85°C

145

= 10 mV, C

= 20 pF,

25°C 790

B1Unity-gain bandwidth

RL = 10 kΩ,

See Figure 36

85°C

690

–40°C 53°

Phase margin

= 10 mV,

CL = 20 pF,

f = B

RL = 10 kΩ,

25°C

49°

See Figure 36

85°C 47°

TLV2342I operating characteristics at specified free-air temperature, VDD = 5 V

TLV2342I

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

25°C 3.6

= 1 V,

= 10 kΩ,

I(PP)

1 V

85°C 2.8

Slew rate at unity gain

CL = 20 pF,

25°C 2.9

V/µs

See Figure 34VI(PP)

= 2.5

85°C 2.3

f = 1 kHz, R

= 20 Ω,

VnEquivalent input noise voltage

See Figure 35

25°C

V/√H

= V

, C

= 20 pF,

25°C 320

BOMMaximum output-swing bandwidth

OOH

RL = 10 kΩ,

See Figure 34

85°C

250

= 10 mV, C

= 20 pF,

25°C 1.7

B1Unity-gain bandwidth

RL = 10 kΩ,

See Figure 36

85°C

1.2

–40°C

Phase margin

= 10 mV,

CL = 20 pF,

f = B

RL = 10 kΩ,

25°C

46°

See Figure 36

85°C 43°

TLV2342, TLV2342Y, TLV2344, TLV2344Y LinCMOS LOW-VOLTAGE HIGH-SPEED OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2344I electrical characteristics at specified free-air temperature

TLV2344I

PARAMETER

TEST

†

VDD = 3 V VDD = 5 V

UNIT

CONDITIONS

MIN TYP MAX MIN TYP MAX

= 1 V

VI = 1 V,

25°C

1.1101.1

VIOInput offset voltage

RS = 50 Ω,

RL = 10 kΩ

Full range

VIO

Average temperature coefficient of input offset voltage

25°C to

85°C

2.7 2.7 µV/°C

= 1 V,

25°C 0.1 0.1

IIOInput offset current (see Note 4)

VIC = 1 V

85°C 22 1000 24 1000

= 1 V,

25°C 0.6 0.6

IIBInput bias current (see Note 4)

VIC = 1 V

85°C 175 2000 200 2000

–0.2 –0.3 –0.2 –0.3

25°C

to to to to

Common-mode input voltage range

2 2.3 4 4.2

ICR

(see Note 5)

–0.2 –0.2

Full range

to to

1.8 3.8

= 1 V,

25°C

1.75

1.9

3.2

3.7

VOHHigh-l

evel output voltage

100 mV

IOH = –1 mA

Full range 1.7 3

= 1 V,

25°C

120

15090150

VOLL

ow-level output voltage

= –

100 mV

IOL = 1 mA

Full range 190 190

Large-signal differential

= 1 V,

25°C311523

voltage amplification

= 10 kΩ,

See Note 6

Full range 2 3.5

V/mV

= 1 V,

25°C65786580

CMRR

ommon-mode rejection ratio

ICR

min,

RS = 50 Ω

Full range 60 60

Supply-voltage rejection ratio

= 1 V,

25°C70957095

SVR

ygj

(∆VDD/∆VIO)

= 1 V,

RS = 50 Ω

Full range 65 65

= 1 V,

25°C

1.362.7

6.4

IDDS

upply curren

= 1 V,

No load

Full range 8 8.8

†

Full range is –40°C to 85°C.

NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.

5. This range also applies to each input individually.

6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.

TLV2342, TLV2342Y, TLV2344, TLV2344Y

LinCMOS LOW-VOLTAGE HIGH-SPEED

OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2344I operating characteristics at specified free-air temperature, VDD = 3 V

TLV2344I

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

= 1 V,

I(PP)

= 1 V,

25°C

2.1

Slew rate at unity gain

= 10 kΩ,

= 20 pF,

V/µs

ee Figure 34

85°C

1.7

f = 1 kHz, R

= 20 Ω,

VnEquivalent input noise voltage

See Figure 35

25°C

V/√H

= V

, C

= 20 pF,

25°C 170

BOMMaximum output-swing bandwidth

OOH

RL = 10 kΩ,

See Figure 34

85°C

145

= 10 mV, C

= 20 pF,

25°C 790

B1Unity-gain bandwidth

RL = 10 kΩ,

See Figure 36

85°C

690

= 10 mV

f = B

–40°C 53°

Phase margin

mV,

CL = 20 pF,

f B1,

RL = 10 kΩ,

25°C

49°

See Figure 36

85°C 47°

TLV2344I operating characteristics at specified free-air temperature, VDD = 5 V

TLV2344I

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

25°C 3.6

= 1 V,

RL = 10 kΩ,

I(PP)

1 V

85°C 2.8

Slew rate at unity gain

CL = 20 pF,

25°C 2.9

V/µs

See Figure 34

I(PP)

= 2.5

85°C 2.3

f = 1 kHz, R

= 20 Ω,

VnEquivalent input noise voltage

See Figure 35

25°C

V/√H

= V

, C

= 20 pF,

25°C 320

BOMMaximum output-swing bandwidth

OOH

RL = 10 kΩ,

See Figure 34

85°C

250

= 10 mV, C

= 20 pF,

25°C 1.7

B1Unity-gain bandwidth

RL = 10 kΩ,

See Figure 36

85°C

1.2

= 10 mV

f = B

–40°C

Phase margin

mV,

CL = 20 pF,

f B1,

RL = 10 kΩ,

25°C

46°

See Figure 36

85°C 43°

TLV2342, TLV2342Y, TLV2344, TLV2344Y LinCMOS LOW-VOLTAGE HIGH-SPEED OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2342Y electrical characteristics, T

= 25°C

TLV2342Y

PARAMETER TEST CONDITIONS

VDD = 3 V VDD = 5 V

UNIT

MIN TYP MAX MIN TYP MAX

Input offset voltage

VO = 1 V, RS = 50 Ω,

VIC = 1 V, RL = 10 kΩ

0.6 1.1 mV

Input offset current (see Note 4) VO = 1 V, VIC = 1 V 0.1 0.1 pA

Input bias current (see Note 4) VO = 1 V, VIC = 1 V 0.6 0.6 pA

ICR

Common-mode input voltage range (see Note 5)

–0.3

2.3

–0.3

4.2

High-level output voltage

VIC = 1 V, IOH = –1 mA

VID = 100 mV ,

1.9 3.7 V

Low-level output voltage

VIC = 1 V IOL = 1 mA

VID = 100 mV ,

120 90 mV

Large-signal differential voltage amplification

VIC = 1 V, See Note 6

RL = 10 kΩ,

11 23 V/mV

CMRR Common-mode rejection ratio

VO = 1 V, RS = 50 Ω

VIC = V

ICR

min,

78 80 dB

SVR

Supply-voltage rejection ratio (∆VDD/∆VID)

VO = 1 V RS = 50 Ω

VIC = 1 V,

95 95 dB

Supply current

VO = 1 V, No load

VIC = 1 V,

0.65 1.4 mA

NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.

5. This range also applies to each input individually.

6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.

TLV2342, TLV2342Y, TLV2344, TLV2344Y

LinCMOS LOW-VOLTAGE HIGH-SPEED

OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV2344Y electrical characteristics, T

= 25°C

TLV2344Y

PARAMETER TEST CONDITIONS

VDD = 3 V VDD = 5 V

UNIT

MIN TYP MAX MIN TYP MAX

Input offset voltage

VO = 1 V, RL = 10 kΩ

VIC = 1 V, RL = 10 kΩ

1.1 1.1 mV

Input offset current (see Note 4) VO = 1 V, VIC = 1 V 0.1 0.1 pA

Input bias current (see Note 4) VO = 1 V, VIC = 1 V 0.6 0.6 pA

ICR

Common-mode input voltage range (see Note 5)

–0.3

2.3

–0.3

4.2

High-level output voltage

VIC = 1 V, IOH = –1 mA

VID = 100 mV , 1.9 3.7 V

Low-level output voltage

VIC = 1 V, IOL = 1 mA

VID = –100 mV, 120 90 mV

Large-signal differential voltage amplification

VIC = 1 V, See Note 6

RL = 10 kΩ,

11 23 V/mV

CMRR Common-mode rejection ratio

VO = 1 V, RS = 50 Ω

VIC = V

ICR

min,

78 80 dB

SVR

Supply-voltage rejection ratio (∆VDD/∆VID)

VO = 1 V, RS = 50 Ω

VIC = 1 V,

95 95 dB

Supply current

VO = 1 V, No load

VIC = 1 V,

1.3 2.7 µA

NOTES: 4. The typical values of input bias current and input offset current below 5 pA are determined mathematically.

5. This range also applies to each input individually.

6. At VDD = 5 V, VO = 0.25 V to 2 V; at VDD = 3 V, VO = 0.5 V to 1.5 V.

TLV2342, TLV2342Y, TLV2344, TLV2344Y LinCMOS LOW-VOLTAGE HIGH-SPEED OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

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TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

Input offset voltage Distribution 1 – 4

VIO

Input offset voltage temperature coefficient Distribution 5 – 8

Input bias current vs Free-air temperature 9

Input offset current vs Free-air temperature 9

Common-mode input voltage vs Supply voltage 10

High-level output voltage

vs High-level output current vs Supply voltage vs Free-air temperature

11 12 13

Low-level output voltage

vs Common-mode input voltage vs Free-air temperature vs Differential input voltage vs Low-level output current

15, 16

17 18

Large-signal differential voltage amplification

vs Supply voltage vs Free-air temperature vs Frequency

19 20, 21 22, 23

Supply current

vs Supply voltage vs Free-air temperature

SR Slew rate

vs Supply voltage vs Free-air temperature

O(PP)

Maximum peak-to-peak output voltage vs Frequency 28

Unity-gain bandwidth

vs Supply voltage vs Free-air temperature

Phase margin

vs Supply voltage vs Free-air temperature vs Load capacitance

Phase shift vs Frequency 22, 23

Equivalent input noise voltage vs Frequency 34

TLV2342, TLV2342Y, TLV2344, TLV2344Y

LinCMOS LOW-VOLTAGE HIGH-SPEED

OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 1

–5 –4 –3 –2

–1 0 1

Percentage of Units – %

2345

DISTRIBUTION OF TLV2342

INPUT OFFSET VOLTAGE

VIO – Input Offset Voltage – mV

VDD = 3 V TA = 25°C P Package

Figure 2

–1 0 1602345

Percentage of Units – %

VIO – Input Offset Voltage – mV

DISTRIBUTION OF TLV2342

INPUT OFFSET VOLTAGE

VDD = 5 V TA = 25°C P Package

–5 –4 –3 –2

Figure 3

–5 –4 –3 –2

Percentage of Units – %

2345

DISTRIBUTION OF TLV2344

INPUT OFFSET VOLTAGE

VIO – Input Offset Voltage – mV

VDD = 3 V TA = 25°C N Package

–1

Figure 4

01602345

Percentage of Units – %

VIO – Input Offset Voltage – mV

DISTRIBUTION OF TLV2344

INPUT OFFSET VOLTAGE

VDD = 5 V TA = 25°C N Package

–1

–5 –4 –3 –2

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TYPICAL CHARACTERISTICS

Figure 5

–8 –6 –4 –2–10 0246810

VIO

– Temperature Coefficient – µV/°C

DISTRIBUTION OF TLV2342

INPUT OFFSET VOLTAGE

TEMPERATURE COEFFICIENT

Percentage of Units – %

VDD = 3 V TA = 25°C to 85°C P Package

Figure 6

Percentage of Units – %

–10 0246810

DISTRIBUTION OF TLV2342

INPUT OFFSET VOLTAGE

TEMPERATURE COEFFICIENT

VDD = 5 V TA = 25°C to 85°C P Package Outliers: (1) 20.5 mV/°C

–8 –6 –4 –2

VIO

– Temperature Coefficient – µV/°C

Figure 7

Percentage of Units – %

46810

VIO

– Temperature Coefficient – µV/°C

VDD = 3 V TA = 25°C to 85°C N Package

DISTRIBUTION OF TLV2344

INPUT OFFSET VOLTAGE

TEMPERATURE COEFFICIENT

–10 –8 –6 –4 –2

Figure 8

VIO

– Temperature Coefficient – µV/°C

Percentage of Units – %

0246810

DISTRIBUTION OF TLV2344

INPUT OFFSET VOLTAGE

TEMPERATURE COEFFICIENT

VDD = 5 V TA = 25°C to 85°C N Package Outliers: (1) 20.5 mV/°C

–10 –8 –6 –4 –2

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TYPICAL CHARACTERISTICS

Figure 9

INPUT BIAS CURRENT AND INPUT OFFSET CURREN

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – °C

IIB and IIO – Input Bias and Offset Currents – pA

0.1 25 45 65 85 105 125

VDD = 3 V VIC = 1 V See Note A

NOTE: The typical values of input bias current and input offset

current below 5 pA were determined mathematically.

Figure 10

VIC – Common-Mode Input Voltage – V

COMMON-MODE INPUT VOLTAGE

SUPPLY VOLTAGE

02468

– Supply Voltage – V

TA = 25°C Positive Limit

Figure 11

V0H – High-Level Output Voltage – V

IOH – High-Level Output Current – mA

HIGH-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

VIC = 1 V VID = 100 mV TA = 25°C

VDD = 3 V

VDD = 5 V

–2 –4 –6 –8

Figure 12

V0H – High-Level Output Voltage – VV

02468

HIGH-LEVEL OUTPUT VOLTAGE

SUPPLY VOLTAGE

VDD – Supply Voltage – V

VIC = 1 V VID = 100 mV RL = 10 kΩ TA = 25°C

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TYPICAL CHARACTERISTICS

Figure 13

1.8

1.2

0.6

2.4

HIGH-LEVEL OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

V0H – High-Level Output Voltage – V

VDD = 3 V VIC = 1 V VID = 100 mV

IOH = –500µA IOH = –1 mA IOH = –2 mA IOH = –3 mA IOH = –4 mA

Figure 14

VOL – Low-Level Output V oltage – mV

500

400

350

300

0 0.5 1 1.5 2 2.5

600

650

700

3 3.5 4

550

450

LOW-LEVEL OUTPUT VOLTAGE

COMMON-MODE INPUT VOLTAGE

VIC – Common-Mode Input Voltage – V

VDD = 5 V IOL = 5 mA TA = 25°C

VID = –100 mV

VID = –1 V

Figure 15

–75 –50 –25 0 25 50 75 100 125

175

150

100

125

200

LOW-LEVEL OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – °C

VOL – Low-Level Output V oltage – mV

VDD = 3 V VIC = 1 V VID = –100 mV IOL = 1 mA

400

200

100

600

700

800

500

300

LOW-LEVEL OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

900

–75 –50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

VOL – Low-Level Output V oltage – mV

VDD = 5 V VIC = 0.5 V VID = –1 V IOL = 5 mA

Figure 16

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TYPICAL CHARACTERISTICS

Figure 17

0–2–4–6–8–1 –3 –5 –7

400

200

100

600

700

800

500

300

LOW-LEVEL OUTPUT VOLTAGE

DIFFERENTIAL INPUT VOLTAGE

VOL – Low-Level Output V oltage – mV

VID – Differential Input Voltage – V

VDD = 5 V VIC = |VID/ 2| IOL = 5 mA TA = 25°C

Figure 18

0.5

0.4

0.2

0.1 0

0.9

0.3

0123456

0.7

0.6

0.8

LOW-LEVEL OUTPUT VOLTAGE

LOW-LEVEL OUTPUT CURRENT

VOL – Low-Level Output Voltage – V

IOL – Low-Level Output Current – mA

VDD = 3 V

VDD = 5 V

VIC = 1 V VID = –100 mV TA = 25°C

Figure 19

02468

LARGE-SIGNAL

DIFFERENTIAL VOLTAGE AMPLIFICATION

SUPPLY VOLTAGE

VDD – Supply Voltage – V

RL = 10 kΩ

TA = –40°C

TA = 25°C

TA = 85°C

– Large-Signal Differential Voltage A

Amplification – V/mV

Figure 20

TA – Free-Air Temperature – °C

20 15

–75 –50 –25 0 25 50 75 100 125

VDD = 5 V

VDD = 3 V

RL = 10 kΩ

– Large-Signal Differential Voltage A

Amplification – V/mV

TLV2342

LARGE-SIGNAL

DIFFERENTIAL VOLTAGE AMPLIFICATION

FREE-AIR TEMPERATURE

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TYPICAL CHARACTERISTICS

Figure 21

1000

800

400 200

1800

600

1400

1200

1600

2000

–75 –50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

RL = 1 MΩ

VDD = 5 V

VDD = 3 V

– Large-Signal Differential Voltage A

Amplification – V/mV

TLV2344

LARGE-SIGNAL

DIFFERENTIAL VOLTAGE AMPLIFICATION

FREE-AIR TEMPERATURE

LARGE-SIGNAL DIFFERENTIAL VOLTAGE

AMPLIFICATION AND PHASE MARGIN

FREQUENCY

10 100 1 k 10 k 100 k 1 M

f – Frequency – Hz

10 M

Phase Shift

–60°

–30°

0°

30°

60°

90°

120°

150°

180°

0.1

VDD = 3 V RL = 1 MΩ CL = 20 pF TA = 25°C

Phase Shift

– Large-Signal Differential Voltage Amplification A

Figure 22

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TYPICAL CHARACTERISTICS

LARGE-SIGNAL DIFFERENTIAL VOLTAGE

AMPLIFICATION AND PHASE MARGIN

FREQUENCY

10 100 1 k 10 k 100 k 1 M 10 M

f – Frequency – Hz

Phase Shift

–60°

–30°

0°

30°

60°

90°

120°

150°

180°

Phase Shift

0.1

VDD = 5 V RL = 1 MΩ CL = 20 pF TA = 25°C

– Large-Signal Differential Voltage Amplification A

Figure 23

Figure 24

02468

– Supply Voltage – V

TA = 85°C

TA = –40°C

SUPPLY CURRENT

SUPPLY VOLTAGE

VIC = 1 V VO = 1 V No Load

IDD – Supply Current – mA

TA = 25°C

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TYPICAL CHARACTERISTICS

Figure 25

0.5

3.5

2.5

1.5

TA – Free-Air Temperature – °C

VDD = 5 V

VDD = 3 V

VIC = 1 V VO = 1 V No Load

–75 –50 –25 0 25 50 75 100 125

IDD – Supply Current – mA

SUPPLY CURRENT

FREE-AIR TEMPERATURE

Figure 26

02468

SLEW RATE

SUPPLY VOLTAGE

VDD – Supply Voltage – V

I(PP)

= 1 V AV = 1 RL = 10 kΩ CL = 20 pF TA = 25°C

SR – Slew Rate – V/us

sµV/

Figure 27

SR – Slew Rate – V/us

sµV/

SLEW RATE

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – °C

I(PP)

= 1 V AV = 1 RL = 10 kΩ CL = 20 pF

VDD = 5 V

VDD = 3 V

–75 –50 –25 0 25 50 75 100 125

Figure 28

10 100 1000 10000

VO9PP) – Maximum Peak-to-Peak Output Voltage – V

f – Frequency – kHz

O(PP)

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE

FREQUENCY

RL = 10 kΩ

TA = 85°C

TA = 25°C

VDD = 5 V

VDD = 3 V

TA = –40°C

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TYPICAL CHARACTERISTICS

Figure 29

1.3

0.9

0.7

0.5

1.7

1.9

1.5

1.1

2.1

012345678

= 3 mV RL = 10 kΩ CL = 20 pF TA = 25°C

UNITY-GAIN BANDWIDTH

SUPPLY VOLTAGE

VDD – Supply Voltage – V

0.3

0.1

B1 – Unity-Gain Bandwidth – MHz

Figure 30

–75 –50 –25 0 25 50 75 100 125

B1 – Unity-Gain Bandwidth – MHz

1.1

2.3

2.9

3.5

1.7

0.5

VDD = 5 V

VDD = 3 V

VI = 10 mV RL = 10 kΩ CL = 20 pF

UNITY-GAIN BANDWIDTH

FREE-AIR TEMPERATURE

TA – Free-Air Temperature – °C

Figure 31

om – Phase Margin

53°

51°

49°

47°

45°

024 68

PHASE MARGIN

SUPPLY VOLTAGE

VDD – Supply Voltage – V

VI = 10 mV RL = 10 kΩ CL = 20 pF TA = 25°C

Figure 32

PHASE MARGIN

FREE-AIR TEMPERATURE

–75 –50 –25 0 25 50 75 100 125

TA – Free-Air Temperature – °C

VDD = 5 V

VI = 10 mV RL = 10 kΩ CL = 20 pF

om – Phase Margin

60° 58°

56° 54°

52° 50°

48° 46°

44°

42° 40°

VDD = 3 V

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TYPICAL CHARACTERISTICS

Figure 33

om – Phase Margin

50°

40°

35°

30°

25°

PHASE MARGIN

LOAD CAPACITANCE

CL – Load Capacitance – pF

VDD = 3 V

VDD = 5 V

VI = 10 mV RL = 10 kΩ TA = 25°C

45°

02040608010010 30 50 70 90

Figure 34

300

200

100

400

Vn – Equivalent Input Noise Voltage – nV Hz

nV/ Hz

350

150

f – Frequency – Hz

EQUIVALENT INPUT NOISE VOLTAGE

FREQUENCY

1 10 100 1000

RS = 20 Ω TA = 25°C

VDD = 3 V

VDD = 5 V

250

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PARAMETER MEASUREMENT INFORMATION

single-supply versus split-supply test circuits

Because the TL V234x is optimized for single-supply operation, circuit configurations used for the various tests often present some inconvenience since the input signal, in many cases, must be offset from ground. This inconvenience can be avoided by testing the device with split supplies and the output load tied to the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The use of either circuit gives the same result.

– +

DD+

DD–

(a) SINGLE SUPPLY

(b) SPLIT SUPPL Y

Figure 35. Unity-Gain Amplifier

– +

1/2 V

20 Ω

2 kΩ

DD–

20 Ω

(a) SINGLE SUPPLY

2 kΩ

DD+

(b) SPLIT SUPPL Y

Figure 36. Noise-Test Circuit

– +

10 kΩ

1/2 V

100 Ω

(a) SINGLE SUPPLY

(b) SPLIT SUPPL Y

10 kΩ

DD+

DD–

Figure 37. Gain-of-100 Inverting Amplifier

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PARAMETER MEASUREMENT INFORMATION

input bias current

Because of the high input impedance of the TL V234x operational amplifier , attempts to measure the input bias current can result in erroneous readings. The bias current at normal ambient temperature is typically less than 1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are offered to avoid erroneous measurements:

• Isolate the device from other potential leakage sources. Use a grounded shield around and between the

device inputs (see Figure 38). Leakages that would otherwise flow to the inputs are shunted away.

• Compensate for the leakage of the test socket by actually performing an input bias current test (using a

picoammeter) with no device in the test socket. The actual input bias current can then be calculated by subtracting the open-socket leakage readings from the readings obtained with a device in the test socket.

Many automatic testers as well as some bench-top operational amplifier testers use the servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage drop across the series resistor is measured and the bias current is calculated). This method requires that a device be inserted into a test socket to obtain a correct reading; therefore, an open-socket reading is not feasible using this method.

V = V

Figure 38. Isolation Metal Around Device Inputs

(N or P package )

low-level output voltage

To obtain low-level supply-voltage operation, some compromise is necessary in the input stage. This compromise results in the device low-level output voltage being dependent on both the common-mode input voltage level as well as the differential input voltage level. When attempting to correlate low-level output readings with those quoted in the electrical specifications, these two conditions should be observed. If conditions other than these are to be used, please refer to the Typical Characteristics section of this data sheet.

input offset voltage temperature coefficient

Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This parameter is actually a calculation using input offset voltage measurements obtained at two different temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device and the test socket. This moisture results in leakage and contact resistance which can cause erroneous input offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the moisture also covers the isolation metal itself, thereby rendering it useless. These measurements should be performed at temperatures above freezing to minimize error.

full-power response

Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is

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PARAMETER MEASUREMENT INFORMATION

generally measured by monitoring the distortion level of the output while increasing the frequency of a sinusoidal input signal until the maximum frequency is found above which the output contains significant distortion. The full-peak response is defined as the maximum output frequency , without regard to distortion, above which full peak-to-peak output swing cannot be maintained.

Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified in this data sheet and is measured using the circuit of Figure 35. The initial setup involves the use of a sinusoidal input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same amplitude. The frequency is then increased until the maximum peak-to-peak output can no longer be maintained (Figure 39). A square wave is used to allow a more accurate determination of the point at which the maximum peak-to-peak output is reached.

(d) f > B

(b) BOM > f > 100 Hz(a) f = 100 Hz

Figure 39. Full-Power-Response Output Signal

test time

Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume, short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET devices, and require longer test times than their bipolar and BiFET counterparts. The problem becomes more pronounced with reduced supply levels and lower temperatures.

APPLICATION INFORMATION

single-supply operation

While the TLV234x performs well using dualpower supplies (also called balanced or split supplies), the design is optimized for singlesupply operation. This includes an input commonmode voltage range that encompasses ground as well as an output voltage range that pulls down to ground. The supply voltage range extends down to 2 V, thus allowing operation with supply levels commonly available for TTL and HCMOS.

Many single-supply applications require that a voltage be applied to one input to establish a reference level that is above ground. This virtual ground can be generated using two large resistors, but a preferred technique is to use a virtual-ground generator such as the TLE2426 (see Figure 40).

– +

TLE2426

Figure 40. Inverting Amplifier With

Voltage Reference

+ ǒ

VDD–V

R2 R1

)

DD 2

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APPLICATION INFORMATION

single-supply operation (continued)

The TLE2426 supplies an accurate voltage equal to VDD/2 while consuming very little power and is suitable for supply voltages of greater than 4 V.

The TLV234x works well in conjunction with digital logic; however, when powering both linear devices and digital logic from the same power supply, the following precautions are recommended:

• Power the linear devices from separate bypassed supply lines (see Figure 41); otherwise, the linear

device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital logic.

• Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive

decoupling is often adequate; however, RC decoupling may be necessary in high-frequency applications.

– +

Logic Logic Logic

Power Supply

– +

Logic Logic Logic

Power Supply

(a) COMMON-SUPPLY RAILS

(b) SEPARATE-BYPASSED SUPPLY RAILS (preferred)

Figure 41. Common Versus Separate Supply Rails

input characteristics

The TL V234x is specified with a minimum and a maximum input voltage that, if exceeded at either input, could cause the device to malfunction. Exceeding this specified range is a common problem, especially in single-supply operation. The lower range limit includes the negative rail, while the upper range limit is specified at V

– 1 V at TA = 25°C and at VDD – 1.2 V at all other temperatures.

The use of the polysilicon-gate process and the careful input circuit design gives the TL V234x very good input offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS devices is highly influenced by threshold voltage shifts caused by polarization of the phosphorus dopant implanted in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of operation.

Because of the extremely high input impedance and resulting low bias-current requirements, the TLV234x is well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can easily exceed bias-current requirements and cause a degradation in device performance.

– +

Figure 43. Compensation for Input Capacitance

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APPLICATION INFORMATION

input characteristics (continued)

It is good practice to include guard rings around inputs (similar to those of Figure 38 in the Parameter Measurement Information section). These guards should be driven from a low-impedance source at the same voltage level as the common-mode input (see Figure 42).

The inputs of any unused amplifiers should be tied to ground to avoid possible oscillation.

– +

(a) NONINVERTING AMPLIFIER (b) INVERTING AMPLIFIER

Figure 42. Guard-Ring Schemes

noise performance

The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage differential amplifier . The low input bias-current requirements of the TLV234x results in a very low noise current, which is insignificant in most applications. This feature makes the device especially favorable over bipolar devices when using values of circuit impedance greater than 50 kΩ, since bipolar devices exhibit greater noise currents.

feedback

Operational amplifiers circuits nearly always employ feedback, and since feedback is the first prerequisite for oscillation, a little caution is appropriate. Most oscillation problems result from driving capacitive loads and ignoring stray input capacitance. A small-value capacitor connected in parallel with the feedback resistor is an effective remedy (see Figure 43). The value of this capacitor is optimized empirically.

electrostatic-discharge protection

The TLV234x incorporates an internal electrostatic-discharge (ESD)-protection circuit that prevents functional failures at voltages up to 2000 V as tested under MIL-PRF-38535. Method 3015.2. Care should be exercised, however, when handling these devices as exposure to ESD may result in the degradation of the device parametric performance. The protection circuit also causes the input bias currents to be temperature dependent and have the characteristics of a reverse-biased diode.

– +

RP+

VDD*

IF)

IL)

IP = Pullup Current Required by the Operational Amplifier (typically 500 µA)

Figure 44. Resistive Pullup to Increase V

– +

2.5 V

TA = 25°C f = 1 kHz V

I(PP)

= 1 V

–2.5 V

Figure 45. Test Circuit for Output Characteristics

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APPLICATION INFORMATION

latch-up

Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TL V234x inputs and outputs are designed to withstand –100-mA surge currents without sustaining latch-up; however, techniques should be used to reduce the chance of latch-up whenever possible. Internal protection diodes should not by design be forward biased. Applied input and output voltage should not exceed the supply voltage by more than 300 mV . Care should be exercised when using capacitive coupling on pulse generators. Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails as close to the device as possible.

The current path established if latch-up occurs is usually between the positive supply rail and ground and can be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of latch-up occurring increases with increasing temperature and supply voltages.

output characteristics

The output stage of the TLV234x is designed to sink and source relatively high amounts of current (see Typical Characteristics). If the output is subjected to a short-circuit condition, this high-current capability can cause device damage under certain conditions. Output current capability increases with supply voltage.

Although the TLV234x possesses excellent high-level output voltage and current capability, methods are available for boosting this capability if needed. The simplest method involves the use of a pullup resistor (R

) connected from the output to the positive supply rail (see Figure 44). There are two disadvantages to the use of this circuit. First, the NMOS pulldown transistor N4 (see equivalent schematic) must sink a comparatively large amount of current. In this circuit, N4 behaves like a linear resistor with an on resistance between approximately 60 Ω and 180 Ω, depending on how hard the operational amplifier input is driven. With very low values of R

, a voltage offset from 0 V at the output occurs. Secondly , pullup resistor R

acts as a drain load to N4 and the gain of the operational amplifier is reduced at output voltage levels where N5 is not supplying the output current.

All operating characteristics of the TLV234x are measured using a 20-pF load. The device drives higher capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at lower frequencies thereby causing ringing, peaking, or even oscillation (see Figure 45 and Figure 46). In many cases, adding some compensation in the form of a series resistor in the feedback loop alleviates the problem.

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TYPICAL APPLICATION DATA

output characteristics (continued)

(a) CL = 20 pF, RL = NO LOAD (b) CL = 130 pF, RL = NO LOAD (c) CL = 150 pF, RL = NO LOAD

Figure 46. Effect of Capacitive Loads

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MECHANICAL INFORMATION

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047/B 03/95

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

0.014 (0,35)

0.020 (0,51)

0.157 (4,00)

0.150 (3,81)

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

(8,55)

(8,75)

0.337

0.344

(9,80)

0.394

(10,00)

0.386

0.004 (0,10)

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Four center pins are connected to die mount pad.

E. Falls within JEDEC MS-012

TLV2342, TLV2342Y, TLV2344, TLV2344Y

LinCMOS LOW-VOLTAGE HIGH-SPEED

OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL INFORMATION

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

0.975

(24,77)

0.940

(23,88)

0.920

0.850

0.775

0.745

(19,69)

(18,92)

0.775

(19,69)

(18,92)

0.745

A MIN

DIM

A MAX

PINS **

0.310 (7,87)

0.290 (7,37)

(23.37)

(21.59)

Seating Plane

0.010 (0,25) NOM

14/18 PIN ONL Y

4040049/C 08/95

0.070 (1,78) MAX

0.035 (0,89) MAX

0.020 (0,51) MIN

0.015 (0,38)

0.021 (0,53)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.240 (6,10)

0.260 (6,60)

0.010 (0,25)

0.100 (2,54)

0°–15°

16 PIN SHOWN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)

TLV2342, TLV2342Y, TLV2344, TLV2344Y LinCMOS LOW-VOLTAGE HIGH-SPEED OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL INFORMATION

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE

4040082/B 03/95

0.310 (7,87)

0.290 (7,37)

0.010 (0,25) NOM

0.400 (10,60)

0.355 (9,02)

0.020 (0,51) MIN

0.070 (1,78) MAX

0.240 (6,10)

0.260 (6,60)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.015 (0,38)

0.021 (0,53)

Seating Plane

0.010 (0,25)

0.100 (2,54)

0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001

TLV2342, TLV2342Y, TLV2344, TLV2344Y

LinCMOS LOW-VOLTAGE HIGH-SPEED

OPERATIONAL AMPLIFIERS

SLOS194 – FEBRUARY 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL INFORMATION

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040064/D 10/95

14 PIN SHOWN

Seating Plane

0,10 MIN

1,20 MAX

0,19

4,50 4,30

6,10

6,70

0,32

0,75 0,50

0,25

Gage Plane

0,15 NOM

0,65

0,13

0°–8°

0,10

PINS **

A MIN

A MAX

DIM

2,90

3,10

4,90

5,10

6,60

6,404,90

5,10

7,70

7,90

9,60

9,80

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Texas Instruments TLV2344IPWR, TLV2344IPWLE, TLV2344IPW, TLV2344IN, TLV2344IDR Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual