Texas Instruments TLV1578IDA, TLV1578IDAR, TLV1578EVM, TLV1578CDAR, TLV1571IDW Datasheet
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TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
features
D
Fast Throughput Rate: 1.25 MSPS at 5 V,
625 KSPS at 3 V
D
Wide Analog Input: 0 V to AV
DD
D
Differential Nonlinearity Error: < ± 1 LSB
D
Integral Nonlinearity Error: < ± 1 LSB
D
8-to-1 Analog MUX – TLV1578
D
Internal OSC
D
Single 2.7-V to 5.5-V Supply Operation
D
Low Power: 12 mW at 3 V and 35 mW at 5 V
D
Auto Power Down of 1 mA Max
D
Software Power Down: 10 µA Max
D
Hardware Configurable
D
DSP and Microcontroller Compatible
Parallel Interface
D
Binary/Twos Complement Output
D
Hardware Controlled Extended Sampling
D
Channel Sweep Mode Operation and
Channel Select
D
Hardware or Software Start of Conversion
applications
D
Mass Storage and HDD
D
Automotive
D
Digital Servos
D
Process Control
D
General-Purpose DSP
D
Image Sensor Processing
description
The TLV1571/1578 is a 10-bit data acquisition system that combines an 8-channel input multiplexer (MUX), a
high-speed 10-bit ADC, and a parallel interface. The device contains two on-chip control registers allowing
control of channel selection, software conversion start, and power down via the bidirectional parallel port. The
control registers can be set to a default mode by applying a dummy RD
signal when WR is tied low. This allows
the TLV1571/1578 to be configured by hardware. The MUX is independently accessible. This allows the user to
insert a signal conditioning circuit such as an antialiasing filter or an amplifier, if required, between the MUX and
the ADC. Therefore, one signal conditioning circuit can be used for all eight channels. The TL V1571 is a single
channel analog input device with all the same functions as the TLV1578.
The TL V1571/TLV1578 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range
from 0 V to A VDD and digitizes the input at a maximum 1.25 MSPS throughput rate at 5 V . The power dissipations
are only 12 mW with a 3-V supply or 35 mW with a 5-V supply . The device features an auto power-down mode
that automatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, the
ADC is further powered down to only 10 µA.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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13
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15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CH0
CH1
CH2
CH3
CS
WR
RD
CLK
DGND
DV
DD
INT
/EOC
D0
D1
D2
D3
D4
CH7
CH6
CH5
CH4
MO
AIN
AV
DD
AGND
REFM
REFP
CSTART
D9/A1
D8/A0
D7
D6
D5
TLV1578
DA PACKAGE
(TOP VIEW)
NC – No internal connection
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2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CS
WR
RD
CLK
DGND
DV
DD
INT/EOC
D0
D1
D2
D3
D4
NC
AIN
AV
DD
AGND
REFM
REFP
CSTART
D9/A1
D8/A0
D7
D6
D5
TLV1571
DW OR PW PACKAGE
(TOP VIEW)
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Very high throughput rate, simple parallel interface, and low power consumption make the TLV1571/TLV1578
an ideal choice for high-speed digital signal processing requiring multiple analog inputs.
AVAILABLE OPTIONS
PACKAGE
T
A
32 TSSOP
(DA)
24 SOP
(DW)
24 TSSOP
(PW)
0°C to 70°C TLV1578CDA TLV1571CDW TLV1571CPW
–40°C to 85°C TLV1578IDA TLV1571IDW TLV1571IPW
functional block diagram – TLV1571/78
Internal
Clock
CLK
CS
RD
INT/EOC
MUX
10-BIT
SAR ADC
Input Registers
and Control Logic
WR
CSTART
REFP
Three
State
Latch
AV
DD
D0 – D7
D8/A0
D9/A1
REFM DV
DD
DGNDAGND
MUX
CH0 – CH7
MO AIN
TLV1578 Only
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NO.
I/O DESCRIPTION
NAME
TLV1571 TLV1578
AGND 21 25 Analog ground
AIN 23 27 I ADC analog input (used as single analog input channel for TLV1571)
AV
DD
22 26 Analog supply voltage, 2.7 V to 5.5 V
CH0 – CH7 – 1–4,
29–32
I Analog input channels
CLK 4 8 I External clock input
CS 1 5 I Chip select. A logic low on CS enables the TLV1571/TLV1578.
CSTAR T 18 22 I Hardware sample and conversion start input. The falling edge of CSTART starts sampling and
the rising edge of CSTART
starts conversion.
DGND 5 9 Digital ground
DV
DD
6 10 Digital supply voltage, 2.7 V to 5.5 V
D0 – D7 8–12,
13–15
12–16,
17–19
I/O Bidirectional 3-state data bus
D8/A0 16 20 I/O Bidirectional 3-state data bus. D8/A0 along with D9/A1 is used as address lines to access CR0
and CR1 for initialization.
D9/A1 17 21 I/O Bidirectional 3-state data bus. D9/A1 along with D8/A0 is used as address lines to access CR0
and CR1 for initialization.
INT/EOC
7 11 O End-of-conversion/interrupt
MO 28 O On-chip mux analog output
NC 24 Not connected
RD
3 7 I Read data. A falling edge on RD enables a read operation on the data bus when CS is low.
REFM 20 24 I Lower reference voltage (nominally ground). REFM must be supplied or REFM pin must be
grounded.
REFP 19 23 I Upper reference voltage (nominally AVDD). The maximum input voltage range is determined by
the difference between the voltage applied to REFP and REFM.
WR
2 6 I Write data. A rising edge on the WR latches in configuration data when CS is low. When using
software conversion start, a rising edge on WR
also initiates an internal sampling start pulse.
When WR
is tied to ground, the ADC in nonprogrammable (hardware configuration mode).
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
_
+
Charge
Redistribution
DAC
SAR
Register
REFM
ADC Code
Control
Logic
Ain
Figure 1. Analog-to-Digital SAR Converter
The TLV1571/78 is a successive-approximation ADC utilizing a charge redistribution DAC. Figure 1 shows a
simplified version of the ADC.
The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process
starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.
sampling frequency, f
s
The TLV1571/ TLV1578 requires 16 CLKs for each conversion, therefore the equivalent maximum sampling
frequency achievable with a given CLK frequency is:
f
s(max)
= (1/16) f
CLK
The TL V1571 and TLV1578 are software configurable. The first two MSB bits, D(9,8) are used to address which
register to set. The rest of the eight bits are used as control data bits. There are two control registers, CR0 and
CR1, that are user configurable. All of the register bits are written to the control register during write cycles. A
description of the control registers is shown in Figure 2.
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
control registers
Output =
Output =
Output =
0:
Binary
1:
2s
Complement
0:
Reserved
Bit,
Always
Write 0
0:
INT. OSC.
SLOW
1:
INT. OSC.
FAST
7h
6h
5h
STARTSEL
A1 A0 D6 D5 D4 D3 D2 D1 D0D7
Control Register Zero (CR0)
D6D7 D5 D4 D3 D2 D1 D0
Channels Swept
PROGEOC
CLKSEL SWPWDN MODESEL CHSEL(2–0)
†
0:
HARDWARE
START
(CSTART)
A(1:0)=00
1:
SOFTWARE
START
0:
INT
1:
EOC
0:
Internal
Clock
1:
External
Clock
0:
NORMAL
1:
Powerdown
0:
Single
Channel
1:
Sweep
Mode
D(2–0)
0h
1h
2h
3h
4h
0,1
0,1,2,3
0,1,2,3,4,5,
0,1,2,3,4,5,6,7
N/A
N/A
N/A
N/A
3h
2h
1h
RESERVED
Control Register One (CR1)
D6D7
‡
D3 D2 D1 D0
IF READREG = 0
OSCSPD 0 Reserved 0 Reserved OUTCODE READREG
0:
Reserved
Bit
Always
Write 0
A(1:0)=01
0:
Reserved
Bit
Always
Write 0
0:
Enable Self
Test
ACTION
1:
Enable
Register
Read back
0h
1h
2h
3h
CONVERSION result
SELF TEST 1 result
SELF TEST 2 result
Output Contents of
CR1
RESERVED
RESERVED
STEST1 STEST0
CR1.(1–0)
SELF TEST 3 result
IF READREG = 1
Output Contents of
CR0
0h
7
6
5
Single
Input
0
1
2
3
4
Output =
D5
‡
D4
‡
†
Don’t care for TLV1571
‡
When in read back mode, the values read from the control register reserved bits are don’t care.
Figure 2. Input Data Format
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
hardware configuration option
The TLV1571/TLV1578 can configure itself. This option is enabled when the WR pin is tied to ground and a
dummy RD signal is applied. The ADC is now fully configured. Zeros or default values are applied to both control
registers. The ADC is configured ideally for 3-V operation, which means the internal OSC is set at 10 MHz, single
channel input mode, and hardware start of conversion using CSTART
.
ADC conversion modes
The TL V1571/TLV1578 provides two conversion modes and two start of conversion modes. In single channel
input mode, a single channel is continuously sampled and converted. In sweep mode (only available for the
TLV1578), a predetermined set of channels is continuously sampled and converted. Table 1 explains these
modes in more detail.
Table 1. Conversion Modes
MODES
START OF
CONVER-
SION
OPERATION
COMMENT–SET BITS
CR0.D(2–0) FOR INPUT
Single
Channel
Input
†
CR0.D3 = 0
CR1.D7 = 0
Hardware
Start
(CSTART)
CR0.D7 = 0
• Repeated conversions from a selected channel
• CSTART
falling edge to start sampling
• CSTART
rising edge to start conversion
• If in INT mode, one INT
pulse generated after each conversion
• If in EOC mode, EOC will go high to low at start of conversion, and return high
at end of conversion.
CSTAR T rising edge must
be applied a minimum of
5 ns before or after CLK
rising edge.
Software
Start
CR0.D7 = 1
• Repeated conversions from a selected channel
• WR
rising edge to start sampling initially . Thereafter, sampling occurs at the rising
edge of RD
.
• Conversion begins after 6 clocks after sampling has begun. Thereafter, if in INT
mode, one INT
pulse is generated after each conversion
• If in EOC mode, EOC will go high to low at start of conversion and return high at
end of conversion.
With external clock, WR
and RD rising edge must be
a minimum 5 ns before or
after CLK rising edge.
Channel
Sweep
CR0.D3 = 1
CR1.D7 = 0
Hardware
Start
(CSTART)
CR0.D7 = 0
• One conversion per channel from a predetermined sequence of channels
• CSTART
falling edge to start sampling
• CSTART
rising edge to start conversion
• If in INT mode, one INT pulse generated after each conversion
• If in EOC mode, EOC will go high to low at start of conversion, and return high
at end of conversion.
CSTAR T rising edge must
be applied a minimum of
5 ns before or after CLK
rising edge.
Software
Start
CR0.D7 = 1
• One conversion per channel from a sequence of channels
• WR
rising edge to start sampling
• ADC proceeds to sample next channel at rising edge of RD
. Conversion begins
after 6 clocks and lasts 10 clocks
• If in INT mode, one INT
pulse generated after each conversion
• If in EOC mode, EOC will go high to low at start of conversion and return high at
end of conversion.
With external clock, WR
and RD rising edge must be
a minimum 5 ns before or
after CLK rising edge.
†
Single channel input mode repeatedly samples and converts from the channel until WR is applied.
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
configure the device
The device can be configured by writing to control registers CR0 and CR1.
Table 2. TLV1571/TLV1578 Programming Examples
INDEX
REGISTER
D9 D8
D7D6D5D4D3D2D1D0COMMENT
EXAMPLE1
CR0 0 0 0 0 0 0 0 0 0 0 Single channel
CR1 0 1 0 0 0 0 0 1 0 0 Single Input
EXAMPLE2
CR0 0 0 0 1 1 0 1 0 1 1 Sweep mode
CR1 0 1 0 0 0 0 1 1 0 0 2’s complement output
register read back
Control data written to the TL V1571/78 can be read back from the control registers CR0 and CR1. See Figure 2.
NOTE:
Data read out of CR1 reserved bits is don’t care.
power down
The TL V1571/TLV1578 offers two power-down modes, auto power down and software power down. This device
will automatically proceed to auto power-down mode if RD is not present one clock after conversion. Software
power down is controlled directly by the userby pulling CS to DV
DD
.
Table 3. Power Down Modes
PARAMETERS/MODES AUTO POWER DOWN
SOFTWARE POWER DOWN
(CS
= DVDD)
Maximum power down dissipation current 1 mA 10 µA
Comparator Power down Power down
Clock buffer Power down Power down
Reference Active Power down
Control registers Saved Saved
Minimum power down time 1 CLK 2 CLK
Minimum resume time 1 CLK 2 CLK
self-test modes
The TL V1571/TLV1578 provides three self test modes. These modes can be used to check whether the ADC
itself is working properly without having to supply an external signal. There are three tests that are controlled
by writing to CR1(D1,D0) (see Table 4).
Table 4. Self Tests
CR1(D1,D0) SELF TEST VOLTAGE APPLIED DIGITAL OUTPUT
0h Normal, no self test applied N/A
1h VREFM applied to ADC input internally 000h
2h (VREFP–VREFM)/2 applied to ADC input internally 200h
3h VIN = VREFP applied to ADC input internally 3FFh
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
reference voltage input
The TL V1571/TLV1578 has two reference input pins: REFP and REFM. The voltage levels applied to these pins
establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading
respectively . The values of REFP , REFM, and the analog input should not exceed the positive supply or be less
than GND consistent with the specified absolute maximum ratings. The digital output is at full scale when the
input signal is equal to or higher than REFP and is at zero when the input signal is equal to or lower than REFM.
sampling/conversion
All sampling, conversion, and data output in the device are started by a trigger. This could be the RD, WR, or
CST ART signal depending on the mode of conversion and configuration. The rising edge of RD, WR, and
CSTART signal are extremely important, since they are used to start the conversion. These edges need to stay
close to the rising edge of the external clock (if they are used as CLK). The minimum setup and hold time with
respect to the rising edge of the external clock should be 5 ns minimum. When the internal clock is used, this
is not an issue since these two edges will start the internal clock automatically. Therefore, the setup time is
always met. Software controlled sampling lasts 6 clock cycles. This is done via the CLK input or the internal
oscillator if enabled. The input clock frequency can be 1 MHz to 20 MHz, translating into a sampling time from
0.6 µs to 0.3 µs. The internal oscillator frequency is 9 MHz minimum (oscillator frequency is between 9 MHz
to 22 MHz), translating into a sampling time from 0.6 µs to 0.3 µs. Conversion begins immediately after sampling
and lasts 10 clock cycles. This is again done using the external clock input (1 MHz–20 MHz) or the internal
oscillator (9 MHz minimum) if enabled. Hardware controlled sampling, via CST ART
, begins on falling CST ART
lasts the length of the active CST AR T signal. This allows more control over the sampling time, which is useful
when sampling sources with large output impedances. On rising CSTART, conversion begins. Conversion in
hardware controlled mode also lasts 10 clock cycles. This is done using the external clock input (1 MHz–20 MHz)
or the internal oscillator (9 MHz minimum) as is the case in software controlled mode.
NOTE: tsu = setup time, th = hold time
ExtClk
WR
RD
CSTART
t
su(WRH_EXTCLKH)
≥5 ns
t
h(WRL_EXTCLKH)
≥5 ns
t
h(RDL_EXTCLKH)
≥5 ns
t
d(EXTCLK_CSTARTL)
≥5 ns
t
h(CSTARTL_EXTCLKH)
≥5 ns
t
su(CSTARTH_EXTCLKH)
≥5 ns
OR
OR
t
su(RDH_EXTCLKH)
≥5 ns
Figure 3. Trigger Timing – Software Start Mode Using External Clock
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
start of conversion mechanism
There are two ways to convert data: hardware and software. In the hardware conversion mode the ADC begins
sampling at the falling edge of CSTART and begins conversion at the rising edge of CSTART. Software start
mode ADC samples for 6 clocks, then conversion occurs for ten clocks. The total sampling and conversion
process lasts only 16 clocks in this case. If RD
is not detected during the next clock cycle, the ADC automatically
proceeds to a power down state. Data is valid on the rising edge of INT in both conversion modes.
hardware CST ART conversion
external clock
With CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART and
conversion begins at the rising edge of CST AR T. At the end of conversion, EOC goes from low to high, telling
the host that conversion is ready to be read out. The external clock is active and is used as the reference at all
times. With this mode, it is required that CST ART is not applied at the rising edge of the clock (see Figure 4).
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