TEXAS INSTRUMENTS TLV0831C, TLV0831I, TLV0832C, TLV0832I Technical data
查询TLV0831供应商
D
8-Bit Resolution
D
2.7 V to 3.6 V V
D
Easy Microprocessor Interface or
Standalone Operation
D
Operates Ratiometrically or With V
Reference
D
Single Channel or Multiplexed Twin
Channels With Single-Ended or Differential
Input Options
D
Input Range 0 V to VCC With VCC Reference
D
Inputs and Outputs Are Compatible With
TTL and MOS
D
Conversion Time of 32 µs at
f
= 250 kHz
(CLK)
D
Designed to Be Functionally Equivalent to
the National Semiconductor ADC0831 and
ADC0832 at 3 V Supply
D
Total Unadjusted Error...±1 LSB
description
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
TLV0831...D OR P PACKAGE
CC
CC
TLV0832...D OR P PACKAGE
CS
IN+
IN–
GND
CS
CH0
CH1
GND
(TOP VIEW)
1
8
2
7
3
6
4
5
(TOP VIEW)
1
2
3
4
8
7
6
5
V
CC
CLK
DO
REF
V
CC
CLK
DO
DI
/REF
These devices are 8-bit successive-approximation analog-to-digital converters. The TL V0831 has single input
channels; the TLV0832 has multiplexed twin input channels. The serial output is configured to interface with
standard shift registers or microprocessors.
The TL V0832 multiplexer is software configured for single-ended or dif ferential inputs. The dif ferential analog
voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the
voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of
resolution.
The operation of the TL V0831 and TLV0832 devices is very similar to the more complex TL V0834 and TL V0838
devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum analog input
signal value, which gives the highest possible conversion resolution. Typically, REF is set equal to V
CC
(done
internally on the TLV0832).
The TL V0831C and TL V0832C are characterized for operation from 0°C to 70°C. The TL V0831I and TL V0832I
are characterized for operation from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°C TLV0831CD TL V0832CD TLV0831CP TLV0832CP
–40°C to 85°C TLV0831ID TLV0832ID TLV0831IP TLV0832IP
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
functional block diagram
CLK
CS
(TLV0832
only)
CH0/IN+
CH1/IN–
(TLV0831
DI
only)
REF
To Internal
Circuits
Shift Register
D
CLK
SGL/DIF
Analog
MUX
EN
EN
Ladder
and
Decoder
ODD/EVEN
Start
Comparator
Bits 0–7
One
Shot
EN
CS
R
SAR
Logic
and
Latch
MSB
First
Bits 0–7
Bit 1
LSB
First
Time
Delay
CLK
Register
CS
9-Bit
Shift
Start
Flip-Flop
CLK
S
R
CLK
S
R
CS
CS
R
EOC
R
CLK
D
CS
DO
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
functional description
The TL V0831 and TL V0832 use a sample-data-comparator structure that converts differential analog inputs by
a successive-approximation routine. The input voltage to be converted is applied to an input terminal and is
compared to ground (single ended), or to an adjacent input (differential). The TLV0832 input terminals can be
assigned a positive (+) or negative (–) polarity . The TLV0831 contains only one differential input channel with
fixed polarity assignment; therefore it does not require addressing. The signal can be applied differentially,
between IN+ and IN–, to the TL V0831 or can be applied to IN+ with IN– grounded as a single ended input. When
the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the
converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A conversion is initiated by setting CS
conversion process. A clock input is then received from the processor. An interval of one clock period is
automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance
state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares
successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates
whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds,
conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock
periods, the conversion is complete. When CS
output circuits go to the high-impedance state. If another conversion is desired, CS
transition followed by address information.
A TLV0832 input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. In addition to selecting the differential mode, the polarity
may also be selected. Either channel of the channel pair may be designated as the negative or positive input.
On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift
register. The first logic high on the input is the start bit. A 2-bit assignment word follows the start bit on the
TLV0832. On each successive low-to-high transition of the clock input, the start bit and assignment word are
shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register,
the input channel is selected and conversion starts. The TLV0832 DI terminal to the multiplexer shift register
is disabled for the duration of the conversion.
The TLV0832 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. The DI and DO
terminals can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This
is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.
low, which enables all logic circuits. CS must be held low for the complete
goes high, all internal registers are cleared. At this time, the
must make a high-to-low
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
sequence of operation
TLV0831
10987654321
CLK
t
su
CS
t
conv
CLK
CS
DI
(TLV0832
only)
DO
Bit
DO
t
su
SGL
DIF
MUX
+Sign Bit
MUX
Settling Time
Start
Settling Time
Hi-Z
ODD
EVEN
MSB
MSB
MSB-First Data
t
conv
MSB-First Data
TLV0832
Don’t Care
1765 243
LSB-First Data
LSB
0
Hi-Z
21201918141312123456 1011
Hi-Z
MSBLSB
176201267
TLV0832 MUX-ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS
SGL/DIF
L
L
H
H
H = high level, L = low level,
– or + = terminal polarity for the selected input channel
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ODD/EVEN CH0 CH1
L
H
L
H
CHANNEL NUMBER
+
–
+
–
+
+
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