查询TLV0831供应商
D
8-Bit Resolution
D
2.7 V to 3.6 V V
D
Easy Microprocessor Interface or
Standalone Operation
D
Operates Ratiometrically or With V
Reference
D
Single Channel or Multiplexed Twin
Channels With Single-Ended or Differential
Input Options
D
Input Range 0 V to VCC With VCC Reference
D
Inputs and Outputs Are Compatible With
TTL and MOS
D
Conversion Time of 32 µs at
f
= 250 kHz
(CLK)
D
Designed to Be Functionally Equivalent to
the National Semiconductor ADC0831 and
ADC0832 at 3 V Supply
D
Total Unadjusted Error...±1 LSB
description
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
TLV0831...D OR P PACKAGE
CC
CC
TLV0832...D OR P PACKAGE
CS
IN+
IN–
GND
CS
CH0
CH1
GND
(TOP VIEW)
1
8
2
7
3
6
4
5
(TOP VIEW)
1
2
3
4
8
7
6
5
V
CC
CLK
DO
REF
V
CC
CLK
DO
DI
/REF
These devices are 8-bit successive-approximation analog-to-digital converters. The TL V0831 has single input
channels; the TLV0832 has multiplexed twin input channels. The serial output is configured to interface with
standard shift registers or microprocessors.
The TL V0832 multiplexer is software configured for single-ended or dif ferential inputs. The dif ferential analog
voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the
voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of
resolution.
The operation of the TL V0831 and TLV0832 devices is very similar to the more complex TL V0834 and TL V0838
devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum analog input
signal value, which gives the highest possible conversion resolution. Typically, REF is set equal to V
CC
(done
internally on the TLV0832).
The TL V0831C and TL V0832C are characterized for operation from 0°C to 70°C. The TL V0831I and TL V0832I
are characterized for operation from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°C TLV0831CD TL V0832CD TLV0831CP TLV0832CP
–40°C to 85°C TLV0831ID TLV0832ID TLV0831IP TLV0832IP
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
functional block diagram
CLK
CS
(TLV0832
only)
CH0/IN+
CH1/IN–
(TLV0831
DI
only)
REF
To Internal
Circuits
Shift Register
D
CLK
SGL/DIF
Analog
MUX
EN
EN
Ladder
and
Decoder
ODD/EVEN
Start
Comparator
Bits 0–7
One
Shot
EN
CS
R
SAR
Logic
and
Latch
MSB
First
Bits 0–7
Bit 1
LSB
First
Time
Delay
CLK
Register
CS
9-Bit
Shift
Start
Flip-Flop
CLK
S
R
CLK
S
R
CS
CS
R
EOC
R
CLK
D
CS
DO
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
functional description
The TL V0831 and TL V0832 use a sample-data-comparator structure that converts differential analog inputs by
a successive-approximation routine. The input voltage to be converted is applied to an input terminal and is
compared to ground (single ended), or to an adjacent input (differential). The TLV0832 input terminals can be
assigned a positive (+) or negative (–) polarity . The TLV0831 contains only one differential input channel with
fixed polarity assignment; therefore it does not require addressing. The signal can be applied differentially,
between IN+ and IN–, to the TL V0831 or can be applied to IN+ with IN– grounded as a single ended input. When
the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the
converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A conversion is initiated by setting CS
conversion process. A clock input is then received from the processor. An interval of one clock period is
automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance
state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares
successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates
whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds,
conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock
periods, the conversion is complete. When CS
output circuits go to the high-impedance state. If another conversion is desired, CS
transition followed by address information.
A TLV0832 input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. In addition to selecting the differential mode, the polarity
may also be selected. Either channel of the channel pair may be designated as the negative or positive input.
On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift
register. The first logic high on the input is the start bit. A 2-bit assignment word follows the start bit on the
TLV0832. On each successive low-to-high transition of the clock input, the start bit and assignment word are
shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register,
the input channel is selected and conversion starts. The TLV0832 DI terminal to the multiplexer shift register
is disabled for the duration of the conversion.
The TLV0832 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. The DI and DO
terminals can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This
is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.
low, which enables all logic circuits. CS must be held low for the complete
goes high, all internal registers are cleared. At this time, the
must make a high-to-low
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
sequence of operation
TLV0831
10987654321
CLK
t
su
CS
t
conv
CLK
CS
DI
(TLV0832
only)
DO
Bit
DO
t
su
SGL
DIF
MUX
+Sign Bit
MUX
Settling Time
Start
Settling Time
Hi-Z
ODD
EVEN
MSB
MSB
MSB-First Data
t
conv
MSB-First Data
TLV0832
Don’t Care
1765 243
LSB-First Data
LSB
0
Hi-Z
21201918141312123456 1011
Hi-Z
MSBLSB
176201267
TLV0832 MUX-ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS
SGL/DIF
L
L
H
H
H = high level, L = low level,
– or + = terminal polarity for the selected input channel
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ODD/EVEN CH0 CH1
L
H
L
H
CHANNEL NUMBER
+
–
+
–
+
+
Clock frequenc
f
Operating free-air temperature, T
°C
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
absolute maximum ratings over recommended operating free-air temperature range (unless
otherwise noted)
Supply voltage, V
Input voltage range, V
Input current, I
Total input current ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: P package 260°C. . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.
†
(see Note 1) 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
: Logic –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
Analog –0.3 V to V
±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
CC
I suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC (see clock operating conditions) 2.7 3.3 3.6 V
High-level input voltage, V
Low-level input voltage, V
y,
Clock duty cycle (see Note 2) 40% 60%
Pulse duration, CS high, t
Setup time, CS low or TLV0832 data valid before CLK↑, t
Hold time, TLV0832 data valid after CLK↑, t
p
NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outside the
recommended duty-cycle range, the minimum pulse duration (high or low) is 1 µs.
(CLK)
p
IH
IL
wH(CS)
VCC = 2.7 V 250 kHz
VCC = 3.3 V 10 600 kHz
su
h
A
C suffix 0 70
I suffix –40 85
2 V
0.8 V
220 ns
350 ns
90 ns
°
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TLV0831C, TLV0831I
PARAMETER
TEST CONDITIONS
†
UNIT
VOHHigh-level output voltage
V
I
g
A
I
Standby input current (see Note 4)
A
I
Supply current
mA
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
electrical characteristics over recommended range of operating free-air temperature, VCC = 3.3 V ,
f
digital section
†
‡
= 250 kHz (unless otherwise noted)
(CLK)
C SUFFIX I SUFFIX
MIN TYP‡MAX MIN TYP‡MAX
p
V
I
I
I
I
C
C
Low-level output voltage VCC = 3 V, IOL = 1.6 mA 0.34 0.4 V
OL
High-level input current VIH = 3.6 V 0.005 1 0.005 1 µA
IH
Low-level input current VIL = 0 –0.005 –1 –0.005 –1 µA
IL
High-level output
OH
(source) current
Low-level output (sink) current At VOL, DO= 0 V, TA = 25°C 8 –16 8 –16 mA
OL
High-impedance-state output
OZ
current (DO)
Input capacitance 5 5 pF
i
Output capacitance 5 5 pF
o
All parameters are measured under open-loop conditions with zero common-mode input voltage.
All typical values are at VCC = 3.3 V, TA = 25°C.
VCC = 3 V, IOH = –360 µA 2.8 2.4
VCC = 3 V, IOH = –10 µA 2.9 2.8
At VOH, DO= 0 V, TA = 25°C –6.5 –15 –6.5 –15 mA
VO = 3.3 V, TA = 25°C 0.01 3 0.01 3
VO = 0, TA = 25°C
–0.01 –3 –0.01 –3
µ
analog and converter section
PARAMETER TEST CONDITIONS
V
IC
I(stdby)
r
i(REF)
†
All parameters are measured under open-loop conditions with zero common-mode input voltage.
‡
All typical values are at VCC = 3.3 V, TA = 25°C.
NOTES: 3. When channel IN– is more positive than channel IN+, the digital output code is 0000 0000. Connected to each analog input are two
Common-mode input voltage See Note 3
On channel VI = 3.3 V 1
p
Input resistance to REF 1.3 2.4 5.9 kΩ
on-chip diodes that conduct forward current for analog input voltages one diode drop above VCC. Care must be taken during testing
at low VCC levels (3 V) because high-level analog input voltage (3.6 V) can, especially at high temperatures, cause the input diode
to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply
voltage by more than 50 mV, the output code is correct. To achieve an absolute 0- to 3.3-V input range requires a minimum VCC of
3.25 V for all variations of temperature and load.
4. Standby input currents go in or out of the on or off channels when the A/D converter is not performing conversion and the clock is
in a high or low steady-state conditions.
Off channel VI = 0 –1
On channel VI = 0 –1
Off channel VI = 3.3 V 1
†
MIN TYP‡MAX UNIT
–0.05
to
VCC+0.05
V
µ
total device
PARAMETER MIN TYP‡MAX UNIT
CC
‡
All typical values are at VCC = 3.3 V, TA = 25°C.
pp
TLV0831 0.2 0.75
TLV0832 1.5 2.5
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t
CLK↑
C
100 pF
ns
t
Output disable ti
CS↑
ns
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
operating characteristics VCC = V
= 3.3 V, f
ref
= 250 kHz, tr = tf = 20 ns, TA = 25°C (unless
(CLK)
otherwise noted)
PARAMETER
Supply-voltage variation error VCC = 3 V to 3.6 V ±1/16 ±1/4 LSB
Total unadjusted error (see Note 5)
Common-mode error Differential mode ±1/16 ±1/4 LSB
Propagation delay time,
p
output data after
pd
(see Note 6)
dis
t
†
NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
Conversion time (multiplexer-addressing
conv
time not included)
All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions.
6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response
time. LSB-first data applies only to TL V0832.
me, DO after
MSB-first data
LSB-first data
TEST CONDITIONS
V
= 3.3 V,
ref
TA = MIN to MAX
p
=
L
CL = 10 pF, RL = 10 kΩ 80 125
CL = 100 pF, RL = 2 kΩ 250
†
MIN TYP MAX UNIT
200 500
80 200
±1 LSB
clock
8
periods
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
PARAMETER MEASUREMENT INFORMATION
V
CC
CLK
CS
0.4 V
2 V
DI
Figure 1. TLV0832 Data-Input Timing
50%
50%
GND
t
su
t
h
2 V
t
su
V
CC
GND
t
h
V
CC
0.4 V0.4 V
GND
CLK
DO
50%
50%
Figure 2. Data-Output Timing
V
CC
V
CC
GND
t
pd
V
OH
V
OL
From Output
Under Test
t
r
10%
90%
90%
t
dis
CS
DO
Output
VOLTAGE WAVEFORMS
NOTE A: CL includes probe and jig capacitance.
50%
S1 open
S2 closed
Figure 3. Output Disable Time Test Circuit and Voltage Waveforms
V
CC
GND
V
CC
GND
Test
Point
R
C
L
(see Note A)
LOAD CIRCUIT
S1
L
S2
t
CS
DO
Output
r
50%
S1 closed
S2 open
VOLTAGE WAVEFORMS
90%
10%
10%
t
dis
V
GND
V
CC
GND
CC
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(
)
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
TYPICAL CHARACTERISTICS
UNADJUSTED OFFSET ERROR
REFERENCE VOLTAGE
16
VI+ = VI– = 0 V
14
12
10
8
6
– Unadjusted Offset Error – LSB
4
2
O(unadj)
E
0
– Reference Voltage – V
ref
Figure 4 Figure 5
LINEARITY ERROR
FREE-AIR TEMPERATURE
0.5
V
= 3.3 V
ref
f
= 250 kHz
0.45
(CLK)
vs
vs
LINEARITY ERROR
vs
REFERENCE VOLTAGE
1.5
VCC = 3.3 V
f
= 250 kHz
(CLK)
TA = 25°C
1.25
1.0
0.75
0.5
– Linearity Error – LSB
L
E
0.25
101.00.10.01
0
0
V
Reference Voltage – VV
ref –
4321
LINEARITY ERROR
vs
CLOCK FREQUENCY
2.0
V
= 3.3 V
1.8
1.6
ref
VCC = 3.3 V
0.4
0.35
– Linearity Error – LSB
L
E
0.3
0.25
–50
1.4
1.2
1
0.8
0.6
– Linearity Error – LSB
L
E
0.4
0.2
0
1007550250–25
0
f
– Clock Frequency – kHzTA – Free-Air Tempertature – °C
CLK
Figure 6 Figure 7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
–40°C
85°C
600500400300200100
25°C
700 800
9
TLV0831C, TLV0831I
(
)
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
TYPICAL CHARACTERISTICS
FREE-AIR TEMPERATURE
0.3
VCC = 3.6 V
VCC = 3.3 V
0.2
VCC = 3 V
– Supply Current – mA
CC
I
0.1
–50
TLV0831
SUPPLY CURRENT
TLV0831
SUPPLY CURRENT
vs
CLOCK FREQUENCY
0.5
f
(CLK)
CS
= 250 kHz
= High
– Supply Current – mA
CC
I
1007550250–25
0.4
0.3
0.2
0.1
0
VCC = 3.3 V
TA = 25°C
f
CLK
– Clock Frequency – kHzTA – Free-Air Temperature — °C
Figure 8 Figure 9
vs
5004003002001000
FREE-AIR TEMPERATURE
16.5
VCC = 3.3 V
16
15.5
15
– Output Current – mA
O
I
14.5
14
–IOH
IOL
(DO = 0.4 V)
TA – Free-Air Temperature – ° C
OUTPUT CURRENT
vs
IOL
(DO = 3.3 V)
–IOH
(DO = 0 V)
(DO = 2.4 V)
Figure 10
1007550250–25–50
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
TYPICAL CHARACTERISTICS
1
0.5
0
V
= 3.3 V
–0.5
Differential Nonlinearity – LSB
ref
TA = 25°C
F
= 250 kHz
(CLK)
VDD = 3.3 V
–1
0 32 64 96 128 160 192 224 256
Output Code
Figure 11. Differential Nonlinearity With Output Code
1
V
= 3.3 V
ref
TA = 25°C
F
0.5
= 250 kHz
(CLK)
VDD = 3.3 V
0
–0.5
Integral Nonlinearity – LSB
–1
0 32 64 96 128 160 192 224 256
Output Code
Figure 12. Integral Nonlinearity With Output Code
1
V
= 3.3 V
ref
TA = 25°C
0.5
F
= 250 kHz
(CLK)
VDD = 3.3 V
0
–0.5
Total Unadjusted Error – LSB
–1
0 32 64 96 128 160 192 224 256
Output Code
Figure 13. Total Unadjusted Error With Output Code
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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BE FULLY AT THE CUSTOMER’S RISK.
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Copyright 1998, Texas Instruments Incorporated
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