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4.25-GBPS CABLE AND PC BOARD EQUALIZER
FEATURES APPLICATIONS
• Multirate Operation up to 4.25 Gbps
• Compensates up to 12 dB Loss at 2.1 GHz
• Suitable to Receive 4.25 Gbps Data Over up
to 36 Inches (0.91 Meters) of FR4 PC Boards
• Suitable to Receive 4.25 Gbps Data Over up
to 30 Feet (9.1 Meters) of CX4 Cable
• Ultralow Power Consumption
• Input Offset Cancellation
• High-Input Dynamic Range
• Output Disable
• Output Polarity Select
• Selectable Loss-of-Signal (LOS) Detection
• Selectable Squelch Function
• CML Data Outputs
• Single 3.3-V Supply
• Surface-Mount, Small-Footprint,
3-mm × 3-mm, 16-Pin QFN Package
TLK4201EA
SLLS719 – APRIL 2006
• 1.0625-Gbps, 2.125-Gbps, and 4.25-Gbps
Fibre Channel Systems
• High-Speed Links in Communication and
Data Systems
• Backplane Interconnect
• Rack-to-Rack Interconnect
A
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DESCRIPTION
The TLK4201EA is a versatile, high-speed limiting equalizer for applications in digital high-speed links with data
rates up to 4.25 Gbps.
This device provides a high-frequency boost of 12 dB at 2.1 GHz as well as sufficient gain to ensure a fully
differential output swing for input signals as low as 100 mV
The high input signal dynamic range ensures low-jitter output signals even when overdriven with input signal
swings as high as 2000 mV
.
P-P
The TLK4201EA includes fixed loss-of-signal (LOS) detection, which can be used to implement a squelch
function by connecting the LOS output to the adjacent DISABLE input. The LOS function can be disabled by
pulling LOSDIS to high level.
The TLK4201EA is available in a small-footprint, 3-mm × 3-mm, 16-pin QFN package. It requires a single 3.3-V
supply.
This very power-efficient equalizer is characterized for operation from –40°C to 85°C.
(at the input of the interconnect line or cable).
P-P
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
www.ti.com
DOUT+
DOUT−
DIN+
DIN−
+
Gain Stage
++ +
COC2 COC1
DISABLE
LOS
VCC
GND
OUTPOL
Bandgap Voltage
Reference and
Bias Current
Generation
Gain Stage Gain Stage
Loss of
Signal Detection
Offset
Cancellation
−
LOSDIS
CML
Output
Buffer
Stage
− − −
B0052-03
Fixed Equalizer
Stage
TLK4201EA
SLLS719 – APRIL 2006
BLOCK DIAGRAM
A simplified block diagram of the TLK4201EA is shown in Figure 1 . This compact, low-power, 4.25-Gbps
equalizer consists of a high-speed data path with an offset cancellation circuitry, a loss-of-signal detection block,
and a band-gap voltage reference and bias current generation block.
The equalizer requires a single 3.3-V supply voltage. All circuit parts are described in detail as follows.
Figure 1. Simplified Block Diagram of the TLK4201EA
HIGH-SPEED DATA PATH
The high-speed data signal with frequency dependent loss is applied to the data path by means of the input
signal pins DIN+/DIN–. The data path consists of the fixed equalizer input stage with 100- Ω on-chip differential
line termination, three gain stages, which provide the required gain to ensure a limited output signal, and a CML
output stage. The equalized and amplified data output signal is available at the output pins DOUT+/DOUT–,
which provide 2 × 50- Ω back-termination to VCC. The output stage also includes a data polarity switching
function, which is controlled by the OUTPOL input, and a disable function, controlled by the signal applied to the
DISABLE input pin. An offset cancellation circuit compensates for inevitable internal offset voltages and thus
ensures proper operation even for very small input data signals.
The low-frequency cutoff is as low as 10 kHz with the built-in filter capacitor. For applications which require even
lower cutoff frequencies, an additional external filter capacitor can be connected to the COC1/COC2 pins.
LOSS OF SIGNAL DETECTION
The output signal of the second gain stage is monitored by the loss-of-signal detection circuitry. In this block, the
input signal is compared to a fixed threshold. If the low-frequency components of the input signal fall below this
threshold, a loss of signal is indicated at the LOS pin.
A squelch function can be easily implemented by connecting the LOS output to the adjacent DISABLE input.
This measure avoids chattering of the output when no input signal is present. The LOS function can be disabled
by pulling LOSDIS to high level.
BAND-GAP VOLTAGE AND BIAS GENERATION
The TLK4201EA equalizer is supplied by a single 3.3V ±10% supply voltage connected to the VCC pins. This
voltage is referred to ground (GND).
An on-chip band-gap voltage circuit generates a supply-voltage-independent reference from which all internally
required voltages and bias currents are derived.
2
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DEVICE INFORMATION
GND
COC2
COC1
NC
1
2
3
4
VCC
DIN+
DIN−
VCC
RGT PACKAGE
(TOP VIEW)
12
11
10
9
16
VCC
DOUT+
DOUT−
OUTPOL
15 14 13
5 6 7 8
LOSDIS
DISABLE
LOS
GND
P0019-03
EP
The TLK4201EA is available in a small-footprint, 3-mm × 3-mm, 16-pin QFN Package.
This quad package has a lead pitch of 0.5 mm. The pinout is shown in Figure 2 .
TLK4201EA
SLLS719 – APRIL 2006
Figure 2. Pinout of TLK4201EA
TERMINAL FUNCTIONS
TERMINAL
NAME NO.
VCC 1, 4, 12 Supply 3.3V ± 10% supply voltage.
DIN+ 2 Analog In Noninverted data input. On-chip 100- Ω terminated to DIN–.
DIN– 3 Analog In Inverted data input. On-chip 100- Ω terminated to DIN+.
LOSDIS 5 CMOS In enables LOS function. This pin has approximately 825-k Ω internal electronic pulldown
DISABLE 6 CMOS In Disables CML output stage when set to high level. 400-k Ω on-chip pulldown resistor.
LOS 7 CMOS Out High level indicates that the input signal amplitude is below the fixed threshold level.
GND 8, 16 Supply Circuit ground
OUTPOL 9 CMOS In
DOUT– 10 CML Out Inverted data output. On-chip 50- Ω back-terminated to VCC.
DOUT+ 11 CML Out Noninverted data output. On-chip 50- Ω back-terminated to VCC.
NC 13 — Not connected
COC1 14 Analog this pin and COC2 (pin 15).
COC2 15 Analog this pin and COC1 (pin 14).
EP EP Exposed die pad (EP) must be grounded.
TYPE DESCRIPTION
LOS disable input. High level disables LOS circuitry and sets LOS pin to low level. Low level
resistor.
Output data signal polarity select with approximately 715-k Ω internal electronic pullup
resistor:
Setting to high-level or leaving pin open selects normal polarity. Low-level selects inverted
polarity.
Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between
To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between
To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).
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TLK4201EA
SLLS719 – APRIL 2006
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
V
CC
V
, V
DIN+
DIN–
V
, V
LOSDIS
V
OUTPOL
V
COC2
V
COC,DIFF
V
DIN,DIFF
I
DIN+
DISABLE
, V
COC1
, I
DIN–
Supply voltage at VCC
Input voltage at DIN+, DIN–
, Input voltage at LOSDIS, DISABLE, OUTPOL, COC1, COC2
,
Differential input voltage between COC1 and COC2 ±1 V
Differential input voltage between DIN+ and DIN– ± 2.5 v
Continuous input current at input pins DIN+ and DIN– –25 to 25 mA
ESD ESD ratings at all pins, human body model (HBM) 2.5 kV
T
J,max
T
stg
T
A
Maximum junction temperature 125 °C
Storage temperature range –65 to 85 °C
Free-air operating temperature –40 to 85 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(2)
(2)
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
V
CC
V
IH
V
IL
T
A
Supply voltage 3 3.3 3.6 V
High-level input voltage, CMOS 2.1 V
Low-level input voltage, CMOS 0.6 V
Free-air operating temperature –40 85 °C
(1)
(1)
VALUE
–0.3 to 4 V
0.5 to 4 V
(2)
–0.3 to 4 V
MIN NOM MAX UNIT
UNIT
DC ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
V
CC
I
CC
R
I
R
O
V
OH
V
OL
(1) Typical values are measured at V
Supply voltage 3 3.3 3.6 V
Supply current 32 38 mA
LOSDIS = low, DISABLE = low,
including CML output current
Input resistance, data Differential 100 Ω
Output resistance, data Single-ended to V
High-level output voltage, LOS I
Low-level output voltage, LOS I
= 3.3 V and TA= 25°C
CC
source
= 1 mA 0.4 V
sink
(1)
CC
50 Ω
MAX UNIT
= 30 µ A 2.4 V
4
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TLK4201EA
SLLS719 – APRIL 2006
AC ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
C
= open 10 50
Low frequency –3dB bandwidth kHz
OC
C
= 0.1 µ F 0.8
OC
Maximum data rate 4.25 Gbps
V
IN,MIN
Data input voltage sensitivity
(2)
BER < 10
over 36 inches of 7-mil-wide stripline
-12
, input signal applied 100 120 mV
interconnect on standard FR4,
voltage at the input of the
interconnect line, K28.5 pattern at
4.25 Gbps.
V
IN,MAX
Data input voltage overload Voltage at the interconnect input 2000 mV
High-frequency boost f = 2.1 GHz 9 12 16 dB
V
OD
Data differential output voltage
swing
DISABLE = high 0.25 10
DISABLE = low 600 780 1200
No board or cable 20
24 inches of 25
f = 4.25 GHz,
K28.5 pattern,
VIN= 200 mV
DJ Deterministic jitter (differential 36 inches of 20 ps
7-mil-wide
stripline on
standard FR4
P-P
voltage at the 7-mil-wide
interconnect stripline on
input) standard FR4
30 feet CX4 cable 20
50 feet CX4 cable 35
RJ Random jitter VIN= 200 mV
at the interconnect input)
(differential voltage 4 ps
P-P
Latency From DIN+/DIN– to DOUT+/DOUT– 250 ps
t
r
t
f
t
DIS
Output rise time 20% to 80%, 4.25 Gbps, no board or 55 85 ps
cable
Output fall time 20% to 80%, 4.25 Gbps, no board or 55 85 ps
cable
Disable response time 20 ns
Input signal applied over 36 inches of
7-mil-wide stripline interconnect on
V
AS
LOS assert threshold voltage standard FR4, voltage at the input of 40 80 mV
the interconnect line, K28.5 pattern at
4.25 Gbps.
(3)
Input signal applied over 36 inches of
7-mil-wide stripline interconnect on
V
DAS
t
AS/DAS
LOS de-assert threshold voltage standard FR4, voltage at the input of 130 200 mV
the interconnect line, K28.5 pattern at
4.25 Gbps.
LOS hysteresis 3 4.5 dB
LOS assert/de-assert time 2 100 µ s
K28.5 at 4.25 Gbps over 36 inches of
7-mil-wide stripline on standard FR4
K28.5 at 4.25 Gbps over 36 inches of
7-mil-wide stripline on standard FR4
(3)
(1)
MAX UNIT
P-P
P-P
mV
P-P
P-P
RMS
P-P
P-P
(1) Typical values are measured at V
(2) The given differential input signal swing is measured at the input of the interconnect. The high-frequency components of the signal at the
= 3.3 V and TA= 25°C.
CC
output of the interconnect (connected to input pins DIN+/DIN– of the TLK4201EA) may be attenuated by as much as 12 dB at 2.1 GHz
depending on the interconnect length and attenuation characteristics of the interconnect.
(3) Depending on the interconnect line length and performance, the bit pattern, and the data rate, the assert and de-assert threshold
voltage levels vary. For more information, see the Typical Characteristics section.
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TLK4201EA
SLLS719 – APRIL 2006
Typical operating condition is at V
TYPICAL CHARACTERISTICS
= 3.3 V, TA= 25°C, and V
CC
= 200 mV
IN
(unless otherwise noted)
P-P
DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT
4.25 GBPS USING A PRBS 2
31
– 1 PATTERN
Figure 3. Equalizer Input And Output Signals With Different Interconnect Lines at 4.25 GHz
6
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f − Frequency − GHz
−35
−30
−25
−20
−15
−10
−5
0
0 1 2 3 4 5 6
Differential S11 − dB
G007
f − Frequency − GHz
−35
−30
−25
−20
−15
−10
−5
0
0 1 2 3 4 5 6
Differential S22 − dB
G008
Data Rate − Gbps
0
20
40
60
80
100
120
140
160
180
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
LOS Assert Threshold Voltage − mV
P−P
G009
K28.5 Pattern
48 Inch
36 Inch
24 Inch
12 Inch
No line
Data Rate − Gbps
0
20
40
60
80
100
120
140
160
180
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
LOS De-assert Threshold Voltage − mV
P−P
G010
K28.5 Pattern
48 Inch
36 Inch
24 Inch
12 Inch
No line
Typical operating condition is at V
TYPICAL CHARACTERISTICS (continued)
= 3.3 V, TA= 25°C, and V
CC
TLK4201EA
SLLS719 – APRIL 2006
= 200 mV
IN
(unless otherwise noted)
P-P
DIFFERENTIAL INPUT RETURN LOSS DIFFERENTIAL OUTPUT RETURN LOSS
vs vs
FREQUENCY FREQUENCY
Figure 9. Figure 10.
LOS ASSERT THRESHOLD VOLTAGE LOS DE-ASSERT THRESHOLD VOLTAGE
vs vs
DATA RATE (K28.5 PATTERN) DATA RATE (K28.5 PATTERN)
Figure 11. Figure 12.
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VCC
DIN+
DIN−
LOSDIS
DOUT−
DOUT+
GND
DIN+
DIN−
DOUT−
DOUT+
GND
VCC
OUTPOL
VCC
VCC
NC
LOS
DISABLE
TLK4201EA
16-Pin QFN
COC2
COC1
OUTPOL
LOSDIS
C
OC
Optional
C
1
C
2
C
3
C
4
S0072-03
0 Inch to 36 Inches
Stripline on FR4
DISABLE LOS
Optional Connection
for Squelch Function
f − Frequency − GHz
−60
−55
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
0 1 2 3 4 5 6
Differential Stripline Attenuation − dB
G011
12” Stripline
24” Stripline
36” Stripline
48” Stripline
TLK4201EA
SLLS719 – APRIL 2006
APPLICATION INFORMATION
Figure 13 shows the TLK4201EA connected with an ac-coupled interface to the data signal source via a stripline
interconnect line. The output load is ac-coupled as well.
The ac-coupling capacitors C
components. In addition, if a very low cutoff frequency is required, as an option, an external filter capacitor C
may be used.
through C
1
in the input and output data signal lines are the only required external
4
OC
10
Figure 13. Basic Application Circuit with AC-Coupled I/Os
Figure 14. Attenuation Characteristics of Stripline Interconnect Lines
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
TLK4201EARGTR ACTIVE QFN RGT 16 3000 Green (RoHS &
no Sb/Br)
TLK4201EARGTRG4 ACTIVE QFN RGT 16 3000 Green (RoHS &
no Sb/Br)
TLK4201EARGTT ACTIVE QFN RGT 16 250 Green (RoHS &
no Sb/Br)
TLK4201EARGTTG4 ACTIVE QFN RGT 16 250 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
(3)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device Package Pins Site Reel
Diameter
(mm)
TLK4201EARGTR RGT 16 CRS 330 0 3.3 3.3 1.1 8 12 Q2
TLK4201EARGTT RGT 16 CRS 330 0 3.3 3.3 1.1 8 12 Q2
Reel
Width
(mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
7-May-2007
Pin1
Quadrant
TAPE AND REEL BOX INFORMATION
Device Package Pins Site Length (mm) Width (mm) Height (mm)
TLK4201EARGTR RGT 16 CRS 418.0 350.0 62.0
TLK4201EARGTT RGT 16 CRS 418.0 350.0 62.0
Pack Materials-Page 2
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