Texas Instruments TLK3134 XAUI User Manual

User’s Guide Rev 0.1

SLLU104A - September 2007

September 2007

TLK3134 XAUI Transceiver / 4 Channel Multi-Rate

Transceiver Evaluation Module (EVM) Users’ Guide

ABSTRACT

This User’s Guide describes the usage and construction of the TLK3134 evaluation module
(EVM). This document provides guidance on proper use by showing some de
and test modes. In addition, design, layout and schematic information is provided to the
customer. Information in this guide can be used to assist the customer in choosing the optimal
design methods and materials in designing a complete system.

vice configurations

This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy
and has not bee
designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case the user at own expense will be required to take whatever
measures may be required to correct this interference.

n tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules, which are

WARNING

1

SLLU104A - September 2007

Contents

Introduction.................................................................................................................................................... 4

TLK3134 EVM Kit Contents........................................................................................................................... 5

Power .............................................................................................................................................................. 6

Power Monitoring LEDs ................................................................................................................................ 9

Control Signals ............................................................................................................................................ 12

MDIO ............................................................................................................................................................. 16

JTAG ............................................................................................................................................................. 17

Reset ............................................................................................................................................................. 18

Parallel Signals ............................................................................................................................................ 19

XAUI Mode (XGMII) Test and Setup Configuration ................................................................................... 21

Gigabit Ethernet Mode (RGMII) Test and Setup Configuration ............................................................... 24

Schematics................................................................................................................................................... 27

Board Layouts.............................................................................................................................................. 45

Figures

Figure 1. TLK3134 EVM Power Source Selection Example.....................................................................6

Figure 2. TLK3134 EVM VDDM Voltage Source Selection.......................................................................6

Figure 3. TLK3134 EVM VDDM Voltage Source Selection.......................................................................7

Figure 4. TLK3134 EVM Regulator Margin Selection...............................................................................7

Figure 5. TLK3134 EVM Voltage Monitor LED Enabled Example ...........................................................9

Figure 6. TLK3134 EVM Voltage Monitor LED Disabled Example ........................................................10

Figure 7. TLK3134 EVM Voltage Monitor LED Connected Directly to Plane Example........................10

Figure 8. Control Connectors (JMP13, JMP15, JMP20, JMP21, JMP25, JMP26).................................12

Figure 9. TLK3134 EVM MDIO Connector (JMP22) ................................................................................16

Figure 10. TLK3134 EVM JTAG Connector (JMP23).............................................................................17

Figure 11. RESET Switch (SW1, JMP10, or JMP11)..............................................................................18

Figure 12. Parallel Signal Header Block Example.................................................................................19

Figure 13. Parallel Signal Header Block Example.................................................................................19

Figure 14. Parallel Loop Back with Static Data Pattern Example........................................................20

Figure 15. Parallel Loop Back with Static Data Pattern Example........................................................20

Figure 16. Example TLK3134 EVM Test Configuration – XAUI Mode (XGMII) Parallel Loopback ....23

Figure 17. Example TLK3134 EVM Test Configuration – Gigabit Ethernet Mode (RGMII) Serial

Loopback ................................................................................................................................................26

Figure 18. TLK3134 EVM Schematic, Sheet 1 Index .............................................................................27

Figure 19. TLK3134 EVM Schematic, Sheet 2 Device Power and Ground..........................................28

Figure 20. TLK3134 EVM Schematic, Sheet 3 Global Signals .............................................................29

Figure 21. TLK3134 EVM Schematic, Sheet 4 High Speed Differential...............................................30

Figure 22. TLK3134 EVM Schematic, Sheet 5 Jitter Cleaner Clock.....................................................31

Figure 23. TLK3134 EVM Schematic, Sheet 6 JTAG and MDIO ...........................................................32

Figure 24. TLK3134 EVM Schematic, Sheet 7 TX and RX Data Lines .................................................33

Figure 25. TLK3134 EVM Schematic, Sheet 8 TX/RX Clocks and Control..........................................34

Figure 26. TLK3134 EVM Schematic, Sheet 9 Power Regulation ........................................................35

Figure 27. TLK3134 EVM Schematic, Sheet 10 Power Distribution ....................................................36

Figure 28. TLK3134 EVM Schematic, Sheet 11 1P2V and 2P5V Supply LEDs ...................................37

Figure 29. TLK3134 EVM Schematic, Sheet 12 1P5V, 1P8V, and 5V Supply LEDs............................38

Figure 30. TLK3134 EVM Schematic, Sheet 13 VDDM Supply LEDs...................................................39

Figure 31. TLK3134 EVM Schematic, Sheet 14 VDDR Supply LEDs ...................................................40

Figure 32. TLK3134 EVM Schematic, Sheet 15 VREF Supply LEDs....................................................41

Figure 33. TLK3134 EVM Schematic, Sheet 16 VJIT Supply LEDs......................................................42

Figure 34. TLK3134 EVM Layout, Top Signal (Layer 1) ........................................................................45

2 TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide

Figure 35. TLK3134 EVM Layout, Ground (Layers 2,4,6,8,10,11) .......................................................46

SLLU104A - September 2007

Figure 36. TLK3134 EVM Layout, Internal Signal (Layer 3).................................................................47

Figure 37. TLK3134 EVM Layout, Internal Signal (Layer 5).................................................................48

Figure 38. TLK3134 EVM Layout, Power (Layer 7)................................................................................49

Figure 39. TLK3134 EVM Layout, Power (Layer 9)................................................................................50

Figure 40. TLK3134 EVM Layout, Internal Signal (Layer 12)...............................................................51

Figure 41. TLK3134 EVM Layout, Ground (Layer 13) ...........................................................................52

Figure 42. TLK3134 EVM Layout, Internal Signal (Layer 14)................................................................53

Figure 43. TLK3134 EVM Layout, Ground (Layers 15) .........................................................................54

Figure 44. TLK3134 EVM Layout, Bottom Signal (Layers 16) ..............................................................55

TLK3134 EVM Layer Construction ..............................................................................................................56

Tables

Table 1. TLK3134 EVM Bill of Materials.................................................................................................43

.

TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide 3

SLLU104A - September 2007

Introduction

The Texas Instruments (TI™) TLK3134 SerDes evaluation module (EVM) board is used to
evaluate the functionality and the performance of TLK3134 XAUI Transceiver/4 Channel Multi­Rate Transceiver device (289-ball BGA). The TLK3134 is a flexible four channel independently
configurable serial transceiver that can be configured to be compliant with the 10Gbps Ethernet
XAUI Specification, the 1000Base-X 1Gbps Ethernet Specification and will also support
1X/2X/10X Fibre Channel (FC), CPRI (x1/x2/x3), OBSAI (x1/x2/x4) data rates. Many common
applications may be enabled by way of externally available control pins and detailed control of
the TLK3134 on a per channel basis is available by way of accessing a register space of control
bits available through a two-wire access port called the Management Data Input/Output (MDIO)

interface.

1

EVM PCB and High-speed Design Considerations

The board can be used to evaluate device parameters in addition to acting as a guide for high­speed board layout. As the frequency of op
special care to ensure that the highest signal integrity is maintained. To achieve this, the board's
impedance is controlled to 50 Ω for both the high-speed differential serial and low-speed parallel
data and clock connections. Vias are minimized and, when necessary, are designed to minimize
impedance discontinuities along the transmission line. Since the board contains both, serial and
parallel transmission lines, care was taken also to control trace length mismatch (board skew) to
less than +/- 1MIL.

Overall, the board layout is designed and optimized to support high-speed operation. Thus,
understanding impedance control and transmission line eff
speed boards. Some of the advanced features offered by this board include:

• PCB (printed circuit board) is designed for optimal high-speed signal integrity.

• SMP and parallel header fixtures are easily connected to test equipment.

• All input/output signals are accessible for rapid prototyping.

• The entire board can be powered from a single 5V power supply where the power planes

can be supplied through on-board regulators or t

• On-board capacitors provide AC coupling of high-speed receive signals.

• External parallel loop-back function can be achieved easily using simple 0.1 inch jumpers.

eration increases, the board designer must take

ects are crucial when designing high-

hrough separate banana jacks for isolation.

• Entire Board can operate from a single 5V power supply, or from individual power supplies.

•

Voltage Monitoring LED circuits provide quick indication that the voltage is within
specification.

1

The MDIO register map is located within the TLK3134 XAUI Transceiver/4 Channel Multi-Rate Transceiver datasheet.

4 TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide

SLLU104A - September 2007

TLK3134 EVM Kit Contents

The TLK3134 EVM kit contains the following:

• TLK3134 EVM board

• TLK3134 EVM User’s Guide (this document)

• TLK3134 XAUI Transceiver/4 Channel Multi-Rate Transceiver datasheet

• MDIO Interface EVM

• MDIO Interface EVM Documentation

• RS-232 Cable

• 20-conductor MDIO Ribbon Cable

• CD-ROM Containing MDIO Software

• 18 3-Foot SMA to SMP cables

.

• 8 1-Foot SMP to SMP cables

TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide 5

SLLU104A - September 2007

Power

The TLK3134 EVM can be operated off of a single 5V Power Supply utilizing the on-board
voltage regulators to generate the voltages required to correctly operate the TLK3134, off of
individual 1.2V, 1.5V or 1.8V, 2.5V, and 5V Power supplies, or a combination of both regulators
and separate individual supplies.

To modify your power supply configuration between either all Individual Supplies, all on-board
regulators, or a combinat
supply headers (JMP37, JMP40, and JMP50) selecting either the “BANANA” or the “REG” pin in
combination with the center pin. The following figure shows how to use the on-board regulators
for the 1.5V or 1.8V and 2.5V supply rails, and an individual power supply connected to the 1.2V
Banana Jack (P21). The 5V power supply is required for operation of the LEDs on this board
even if you are not using the on-board voltage regulators.

ion of both, simply change the jumper position on the appropriate power

Figure 1. TLK3134 EVM Power Source Selection Example

The MDIO power supply VDDM can be operated off of either 1.2V or 2.5V depending upon your
specific setup. If

you are using the supplied MDIO controller board that came with this

EVM kit, the 2.5V setting should be selected on the VDDM Power Select Header (JMP43).

Figure 2. TLK3134 EVM VDDM Voltage Source Selection

JMP43

1P2V

VDDM

2P5V

2.5V SELECTED AS

VDDM SUPPLY VOLTAGE

6 TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide

The PTH05010WAS voltage regulators included on the TLK3134 EVM are adjustable and are

SLLU104A - September 2007

set with a single external resistor. Separate regulators have been provided and set to output

1.2V and 2.5V because both voltages are required simultaneously. However, since 1.5V and

1.8V are not necessarily required simultaneously, a single regulator has been configured to
provide both of those voltages, although not at the same time depending upon the jumper
position on JMP115 shown in the following figure. JMP115 selects between the 1.5V set resistor
and the 1.8V set resistor and connects one or the other to the Voltage Adjust pin of the regulator.

Figure 3. TLK3134 EVM VDDM Voltage Source Selection

.

JMP115

1P8V

SELECTED

1P5V

VOLTAGE SELECT

1P8V

JMP115

1P5V

VOLTAGE SELECT

1P8V

1P5V

SELECTED

The PTH05010WAS voltage regulators are also equipped with a +/- 5% selectable Margin
Control allowing easy t

esting of the device near the

min/max voltage limits specified in the
datasheet. Place the jumper position to either the “UP 5%”, “DN 5%”, or “NOM” positions
keeping the center pin in common as demonstrated in the following figure.

Figure 4. TLK3134 EVM Regulator Margin Selection

DN

5%

UP

5%

TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide 7

DN

UP

5%

5%

DN

UP

5%

5%

SLLU104A - September 2007

When the on-board regulators are not being used and independent power supplies are being
used instead, i.e. the case of a voltage tolerance test, the on-board regulators should be disabled
to prevent the regulator’s voltage sense line from trying to regulate the voltage supplied through
the banana jack and not from its own output. This is accomplished by placing a short on the
headers (JMP108, JMP110, and JMP114) labeled “DISABLE”. The remote sense feature is not
designed to compensate for the forward drop of non-linear or frequency dependent components
that may be placed in series with the converter output. Examples include OR-ing diodes, filter
inductors, ferrite beads, and fuses. When these components are enclosed by the remote sense
connection they are effectively placed inside the regulation control loop, which can adversely
affect the stability of the regulator. A large 0 ohm resistor has been installed at the voltage
entrance point of each power plane and can be replaced with a ferrite bead of desired. In this
situation, the 0 ohm resistors on the sense lines can be interchanged to connect the sense line
directly to its output and eliminate the additional components that could otherwise create
instability on the regulator’s output. For the 1.2V regulator, the R223 0 ohm resistor should be
removed and the R222 populated with a 0 ohm resistor. For the 1.5V or 1.8V regulator, R221
should be removed and placed on R220, and similarly R223 should be moved to R222 for the

2.5V regulator.

The VREF plane is sourced through a Voltage Divider providing half of the voltage on the 1P5/8V
plane. The VDDQ and VDDR power

pins of the TLK3134 can both be operated off of either 1.5V
or 1.8V with VREF being half of whatever voltage is on the VDDQ pins. The VREF plane can be
powered through the plane monitoring header (JMP3) and removing the 0 ohm resistor (R71)
although this is not recommended. A separate VDDR plane has been added as there is no
relationship between the VDDR pin and the VDDQ pins, however, the VDDR plane is sourced
through a 0 ohm resistor (R67) from the voltage on the 1P5/8V plane that provides power the
VDDQ pins. This resistor can be replaced with a ferrite bead or removed completely and an
external supply can be connected to the VDDR Header (JMP5) in the case different voltages are
desired on the two planes.

Furthermore, for more accurate current readings the PULLUP_EN Jumpers on all control pin
headers can be removed quickly disconnecting the pullu

p resistors from the voltage plane.
However, the removal of the PULLUP_EN jumpers will also require manual high/low control of
the control pins.

Better Performance can be achieved when the Jitter Cleaner is enabled by using an external
power supply on the 1.2

V Banana Jack. A dedicated LDO 1.2V Regulator powering the Jitter

Cleaner Power Plane should be considered for the end application.

8 TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide

Power Monitoring LEDs

SLLU104A - September 2007

Each plane of the TLK3134 EVM has been equipped with a Voltage Monitoring circuit that will
monitor the voltage on the plane and light the LEDs when the voltage is within the min/max
datasheet limits for that power supply. A precision TI Voltage Reference chip is used along with

0.1% precision resistors setting min and max reference levels providing a detection circuit that is
accurate to approximately +/- 10mV. The LEDs should be used as a basic indication of the
status of power on the board being within the acceptable min/max limits given in the datasheet,
and not as a precise measurement tool as some LED circuits may turn off at slightly different
voltages when approaching the limits due to the manufacturing tolerances and available
component values.

The voltage monitor circuits can also be bypassed and the LEDs driven directly from the voltage
on the individual planes such as when performing voltage tolerance tests. Inste
only when the voltage on the plane is within the min/max range, the LED will be lit when the
voltage is greater than the voltage needed to turn on the LED drive circuit’s NPN transistor,
allowing current to flow, and the LED to be lit from the 5V source. In the Direct Connect mode,
the base resistors has been given extra margin to allow the LEDs to light when the voltage on
the plane is a little below the minimum limit of that supply in order to provide a LED indicator of
power on the plane during voltage tolerance tests near the lower supply limits.

.

ad of being lit

Figure 5. TLK3134 EVM Voltage Monitor LED Enabled Example

Placing the jumper on the ENABLE side of the Voltage Monitor Enable/Disable header connects
the power plane to the input of the voltage moni

toring circuit. This input is high impedance and

will not load down the power source providing the voltage to the plane.

Placing the header on the MONITOR side of the LED Monitor/Direct Connect selection header
connects the LED drive circui

t to the output of the Voltage Monitor circuit causing the LED to be

lit only when the voltage is within the acceptable range.

TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide 9

SLLU104A - September 2007

Figure 6. TLK3134 EVM Voltage Monitor LED Disabled Example

Placing the jumper on the DISABLE side of the Voltage Monitor Enable/Disable header
disconnects the power plane to the input of the voltage monitoring cir

cuit and instead ties the
input to GND. This prevents the output of the Voltage Monitoring Circuit from floating and
possibly causing the LED to flicker during contact with the board.

Placing the jumper on the MONITOR side of the LED Monitor/Direct Connect selection header
connects the LED drive circui

t to the output of the Voltage Monitor circuit causing the LED to be
off since the voltage monitor circuit will sense that the plane voltage is GND which is less than
the acceptable plane voltage.

Figure 7. TLK3134 EVM Voltage Monitor LED Connected Directly to Plane Example

10 TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide

Placing the jumper on the DIRECT side of the LED Monitor/Direct Connect selection header

SLLU104A - September 2007

connects the LED drive circuit to the power plane itself causing the LED to be lit when the
voltage is great enough to cause current to flow through the LED drive circuit. This LED
configuration has been designed to be used when pushing the lower limits of the acceptable
voltage range to continue to provide an indicator that power is on the plane, however without
regards to what that voltage may actually be.

The jumper on the Voltage Monitor Enable/Disable header does not matter as this is only the
input to the voltage monitor circuit which has been bypassed when the LED dri

ve circuit is

connected directly to the power plane itself.

.

TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide 11

SLLU104A - September 2007

Control Signals

All of the external control pins on the TLK3134 EVM have been consolidated to a single location
on the board and broken out into several header blocks for easier reference. LEDs have been
added to the GPO[4:0] lines in addition to the headers for scope probes, to allow easy monitoring
of the High/Low value on the line. The LED will be ON when the line is a Logic High, and the
LED will be OFF when the line is a Logic Low.

Figure 8. Control Connectors (JMP13, JMP15, JMP20, JMP21, JMP25, JMP26)

THE VCO_TL_TST PIN

GND. A LOCATION FOR

A SERIES INDUCTOR TO

GND HAS BEEN ADDED

HEADER BLOCKS ARE

PULLUP_EN HEADERS

WILL DISCONNECT THE

ACCURATE CURRENT

GPO[4:0] LEDS

SHOULD BE TIED TO

SHOULD IT BECOME

NEEDED.

THE RESISTORS ON

THIS SIDE OF ALL

PULL UP RESISTORS

REMOVING THE

JUMPER ON THE

PULL UP RESISTORS
FROM THE VOLTAGE

PLANE FOR MORE

MEASUREMENTS

R4

R15

R16

R17

R24

PULLUP_EN

PULLUP_EN

PULLUP_EN

D1

GPO0

D2

GPO1

D3

GPO2

D4

GPO3

D5

GPO4

JMP14

JMP12

JMP24

JMP20

GND

JMP21

JMP26

JMP13

GND

VCO_TL_TST

INDUCTOR/GND

GND

TST_OUT

GPO3

GPO2

GPO1

GPO0

GPI1

ST

AMUX0

AMUX1

TESTEN

CODE

PRBS_EN

SLOOP

PLOOP

SPEED0

SPEED1

ENABLE

PRTAD0

PRTAD1

PRTAD2

PRTAD3

PRTAD4

THE PINS ON THIS SIDE

THE TST_OUT PIN

SHOULD BE LEFT OPEN

IN THE APPLICATION

GPO4 HAS NOT BEEN
CONNECTED TO THIS

HEADER BLOCK BUT

RATHER TO A SMP

CONNECTOR LOCATED

ON THE BOTTOM OF

THE BOARD WITH THE

HIGH SPEED LINES.

LEDS HAVE BEEN

CONNECTED TO EACH

OF THE GP0[4:0] PINS

AND ARE LOCATED

BELOW JMP24 AND

JMP25

OF ALL HEADER

BLOCKS ARE GND

L1

JMP15

R39

R38

R37

R36

R35

R55

R14

R13

R12

R11

R10

R9

R8

R7

R6

R5

JMP25

R50

R51

R52

R53

R54

U3

U4

U5

12 TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide

Control Signal Pin Description:

SLLU104A - September 2007

.

VCO_TL_TST: This pin is the VCO Testability Input and should be grounded in the

application.

TST_OUT: This is the Jitter Cleaner Testability Pin. This signal should be left open
(unconnected) in the System Application.

GPO[4:0]:

These are General Purpose Outputs and must be left open (unconnected) in the

System Application.

GPI1: This is the General Purpose I

ST: This is the MDIO

Select pin and used to select Clause 22 (ST =1) or Clause 45 (ST=0)

nput and must be Grounded in the System Application.

operation.

AMU

X0: This is the SERDES Analog Mux 0 TX pin and must be open (unconnected) in the

System Application.

AMUX1:

This is the SERDES Analog Mux 1 RX pin and must be open (unconnected) in the

System Application.

TESTEN:

This is the Test Mode Enable Input pin and must be Grounded in the System

Application.

CODE

: This is the Code Enable pin. Th

is signal selects different functionality based on the

setting of the ST primary chip input pin.

: This signal is logically OR’d with the XAUI_ORDER register bit (Register

ST=0

Bit 32809.15). XAUI applications can either tie this input signal high (preferred)
or tie this signal low (must program the XAUI_ORDER register bit after device
reset to high if CODE is tied off low). 10GFC applications MUST tie this signal
low.

ST=1

: This signal is logically OR’d with the PCS_EN register bit (Register Bit

17.3). RGMII/GMII applications can either tie this input signal high (preferred) or
tie this signal low (must program the PCS_EN 17.3 register bit after device reset
to high if CODE is tied off low). Nom RGMII/GMII applications MUST tie this
input signal low.

PRBS_EN: This is th

e PRBS Enable Pin. When this pin is asserted HIGH, the internal PRBS
generator and comparator circuits are enabled on the transmit and receive data paths of all
channels. The PRBS results for each channel can be read through MDIO counters. Primary
chip output signals GPO3/GPO2/GPO2/GPO0 remain low during PRBS testing when the input
serial stream PRBS pattern is correct, and pulse high when PRBS errors are detected on the
input serial stream on a per channel basis.

GPO3

GPO2

GPO1

GPO0

: Contains the Channel 3 PRBS currently passing (when low) indication.

: Contains the Channel 2 PRBS currently passing (when low) indication.

: Contains the Channel 1 PRBS currently passing (when low) indication.

: Contains the Channel 0 PRBS currently passing (when low) indication.

An external loopback connection (via external cables) is required during PRBS
testing.

TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide 13

SLLU104A - September 2007

ST=0: PRBS 223-1 is transmitted on each transmit channel serial output, and
compared on each receive channel serial input.

: PRBS 27-1 is transmitted on each transmit channel serial output, and

ST=1

compared on each receive channel serial input.

SLOOP: This pin is the Serial Loop Enable pin. When SLOOP is asserted HIGH, the serial
input from each channel is internally looped back to that

channel’s serial output, making that
channel a serial repeater. In device configurations where clock tolerance compensation is not
performed in the transmit direction, there are two options for error free serial loopback operation:

1) Frequency lock (0 ppm) the incoming serial data rate to the local reference
clock device

input.

2) Provision the TX SERDES REFCLK to run from

a jitter cleaned version of the

RX SERDES RXBCLK (Receive Byte Clock).

PLOOP: This pin is the Parallel Loop Enable pin. When PLOOP is asserted HIGH, the serial
output for each channel is internally looped back to its serial input so t

hat the transmit parallel

interface input data is output onto the receive parallel interface.

SPEED[1:0]: These are the Speed Selection Pins and put all four channels of the TLK3134 into
one of the three supported (full/half/

quarter) channel operation speeds.

00 – All Four Channels in Full Rate mode

01 – All Four Channels in Half Rate mode

10 – All Four Channels in Quarter Rate mode

11 – Software Selectable Rate

In the Software selectable rate mode, the rate for each channel may be
configured independently by the

The SPEED[1:0] inputs

control both RX and TX directions for all four channels

(Including XAUI and 10GFC

MDIO interface.

modes).

Please see Appendix A of the TLK3134 Datasheet for further information on
speed selection (full/half/quarter) for proper settings as a function

of the

application mode and reference clock frequency.

Please note that if these pins are not configured on the application board to
select “Software Selectable Rate”, then th
cannot be used to control the rate settings, and the full/half/quarter rate
selection is fixed.

ENABLE: This is the Device Enable pin. When ENABLE is held low, the device is in a low
power state. When ENABLE is high the device operates normally. A hard or soft reset muc

be applied after a change of state occurs on this input signal.

14 TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide

e internal speed register bits

h

PRTAD[4:0]: These are the Port Address Assignment Pins and are used to select the Device

SLLU104A - September 2007

ID/Port ID in Clause 22/Clause 45 MDIO modes.

.

ST=0 (Clause 45 Mode)

:

If PRTAD[0] is a 0, then a PHY device is selected for XAUI/10GFC register
accesses (4.x

xxxx.x).

If PRTAD[0] is a 1, then a DTE device is selected for XAUI/10GFC register
accesses (5.x

xxxx.x).

PRTAD[4:1] selects the Clause 45 port address (TLK3134 must be located on
even boundaries since the lowest port address bit determines DTE/PHY, and is
used as a d

ST=1 (Clause 22 Mode)

evice address instead of port address).

:

PRTAD[4:2] selects a block of four sequential Clause 22 port addresses. Each
channel is implemented as a different port address, and can be accessed by
setting the a

ppropriate port address field within the Clause 22 MDIO transaction.

PRTAD[1:0] pins are not used in Clause 22 mode.

Channel 0 responds to port address 0 within the block of four port addresses.

Channel 1 responds to port address 1 within the block of four port addresses.

Channel 2 responds to port address 2 within the block of four port addresses.

Channel 3 responds to port address 3 within the block of four port addresses.

TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide 15

SLLU104A - September 2007

MDIO

The TLK3134 supports the Management Data Input/Output (MDIO) Interface as defined in Clauses 22
and 45 of the IEEE 802.3ae Ethernet Specification. The MDIO allows register-based management and
control of the serial links. Normal operation of the TLK3134 is possible without the use of this interface,
however, some additional features are accessible only through this interface.

The MDIO Management Interface consists of a bi-directional data path (MDI

O) and a clock reference
(MDC). The device ID and port address are determined by control pins PRTAD[4:0]. The ST pin
controls whether the device responds as a Clause 22 or Clause 45 device.

In Clause 45 (ST=0), the top 4 control pins PRTAD[4:1] determine the device port address. In Clause
45 mode the TLK3134 can be accessed only through even port addresses. In th

is mode, the TLK3134
will respond if the PHY address field on the MDIO protocol (PA[4:0]) matches {PRTAD[4:1], 1’b0}. The
PRTAD[0] pin acts as a device ID pin where it determines whether the TLK3134 is a DTE or PHY
device and is required to be either 4 (PHY) or 5 (DTE), so only one bit is required to differentiate. If
PRTAD[0] is a 0, then a PHY device is selected for the XGXS. If PRTAD[0] is a 1, then a DTE device is
selected for the XGXS. In this mode, TLK3134 will respond as PHY if the Device address field
(DA[4:0]) on the MDIO protocol is 5’b00100 and as DTE if it is 5’b00101. Note, each register is
accessed as either DTE or PHY devices in the TLK3134, although physically there is only one register
accessed two different ways.

In Clause 22 (ST=1), the top 3 control pins PRTAD[4:2] determine the device port address. In this
mode the 4 individual channels in TLK3134 are classif

ied as 4 different ports. So for any PRTAD[4:2]
value there will be 4 ports per TLK3134. The TLK3134 will respond if the 3 MSB’s of PHY address field
on MDIO protocol (PA[4:2]) matches PRTAD[4:2]. The 2 LSB’s of PHY address field (PA[1:0]) will
determine which channel/port within the TLK3134 to respond.

If PA[1:0] = 2’b00, TLK3134’s Channel 0 will respond.

If PA[1:0] = 2’b01, TLK3134’s Channel 1 will respond.

If PA[1:0] = 2’b10, TLK3134’s Channel 2 will respond.

If PA[1:0] = 2’b11, TLK3134’s Channel 3 will respond.

Write transactions to invalid registers or read only registers will be ignored. Read transactions of invalid
registers will return a “0”.

The bi-directional MDIO pin is pulled up to 1.2V or 2.5V (VDDM) with a 1.5k Ω re

sistor as per the MDI

O

Standard.

Figure 9. TLK3134 EVM MDIO Connector (JMP22)

MDIO

MDC

NC

NC

NC

NC

NC

NC

NC

NC

JMP22

16 TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide

GND

GND

NC

NC

NC

NC

NC

NC

NC

NC

JTAG

SLLU104A - September 2007

The EVM also provides a separate connector to support the full five-pin JTAG interface of the TLK3134
as defined in IEEE 1149.1 for manufacturing tests.

.

TDI: This pin is the JTAG Input Data pin and is used

to serially shift test data and test

instructions into the device during the operation of the test port.

TDO: This pin is the JTAG Outp

ut Data pin and is used to serially shift test data and test
instructions out of the device during operation of the test port. When JTAG port is not in use,
TDO is in a high impedance state.

TMS: This pin is the JTAG Mode Select pin and is used to control the state of the internal test­port controller.

TCK: This is the JTAG Clock pin and is used to clock stat

e information and test data into and

out of the device during the operation of the test port.

TRST_N: This is the JTAG Test Reset pin and is used to reset the JTAG logic into system
operational mode. NOTE

: TRST_N should be tied low when the JTAG port is not in use and

during normal operation of the port as shown in the following figure.

Figure 10. TLK3134 EVM JTAG Connector (JMP23)

TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide 17

SLLU104A - September 2007

Reset

The TLK3134 EVM comes configured for Manual Reset operations involving the Pushbutton
Reset Switch (SW1). When switch SW1 is pressed, the TLK3134 device RESET pin (RST_N)
goes LOW and the entire TLK3134 device is reinitialized. A TI TPS3125J18 Ultra Low Voltage
Processor Supervisory Circuit is used to control the Reset line. During power-on, /RESET pin of
U2 is asserted when the supply voltage becomes higher than 0.75V. Thereafter, the supply
voltage supervisor monitors the voltage and keeps /RESET output active as long as the Voltage
remains below the threshold voltage (V
inactive state (high) to ensure proper system reset. The delay time, t
voltage has risen above the threshold voltage (V

There is also a manual reset input to the supervisory circuit, /MR, which accepts the input from
the pushbutton switch SW
the TLK3134 device whenever the pushbutton RESET is pressed. By placing a jumper on
JMP11, the Manual Reset (/MR) is tied hard to ground causing the TLK3134 to be held in a
constant state of Reset without the need to continually hold the Reset Pushbutton SW1. The
Supervisory circuit will release the Reset line to a HIGH 180mS (t
becomes greater than the threshold voltage (V

By removing the jumper from JMP10, the Supervised Reset Circuit is disconnected from the
RST_N line. Reset control from an external controller or piec
directly to pin 2 (RST_N) of JMP10 and a ground pin GND has been added to the JMP10 header
next to the RST_N pin to allow easy access for the return current on that cable.

). An internal timer delays the return of the output to the

IT

=180ms, starts after the

d

).

IT

1. A low level at /MR causes /RESET to become active, thus resetting

) from the time the /MR line

d

).

IT

e of equipment can be connected

Figure 11. RESET Switch (SW1, JMP10, or JMP11)

NOTE: The Jumper on JMP10 connecting RESET SW to RST_N must be connected as shown
in order to cause the TLK3134 to be reset and reinitialized If switch

SW1 is pressed, the device

RESET pin (RST_N) goes LOW, the entire TLK3134 device is reinitialized.

18 TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide

Parallel Signals

SLLU104A - September 2007

The parallel signals have on the TLK3134 EVM have been routed to a 0.1” header block that is
configured like the following figure. All RXD pins on all 4 header blocks (RXD[7:0], RXD[15:8],
RXD[23:16], RXD[31:24]), as well as all TXD pins on all 4 header blocks (TXD[7:0], TXD[15:8],
TXD[23:16], TXD[31:24]), have matched trace lengths to themselves +/- 1MIL. Due to routing
constraints RXD[31:0] and TXD[31:0] trace lengths are not matched to each other, but only to
themselves.

.

Figure 12. Parallel Signal Header Block Example

Parallel Loop back, shown in the following figure, can be easily implemented by placing Jumper

s
on the RX/TX pins of the header. For example, placing a jumper on pins 2 and 3 of JMP30 will
loop back TXD7 to RXD7.

Figure 13. Parallel Signal Header Block Example

TXD 7:0

JMP30

12

6

7

1

RXD 7:0

484218 24 30 36

VDD

TX

GND

TX

RX

GND

433713 19 25 31

PARALLEL

LOOPBACK

TLK3134 XAUI Transceiver / 4 Channel Multi-Rate Transceiver Evaluation Module (EVM) Users’ Guide 19