TEXAS INSTRUMENTS TLK100 Technical data

Magnetics

MPU/CPU

Media AccessController

MII

10/100Mb/s

TLK100

25-MHz

Clock

Source

Status

LEDs

RJ-45

10BASE-T

100BASE-TX

B0312-01

TLK100

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Industrial Temp, Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver

Check for Samples: TLK100

1 Introduction

1.1 Features

• Temperature From –40°C to 85°C

• Low Power Consumption, < 200mW Typical

• Cable Diagnostics

• Error-free Operation up to 200 meters under typical conditions • Integrated ANSI X3.263 Compliant TP-PMD

• 3.3V MAC Interface

• Auto-MDIX for 10/100 Mb/s

• Energy Detection Mode

• 25 MHz Clock Out

• MII Serial Management Interface (MDC and MDIO)

• IEEE 802.3u MII

• IEEE 802.3u Auto-Negotiation and Parallel Detection

• IEEE 802.3u ENDEC, 10BASE-T

Transceivers and Filters

• Bus I/O Protection - ±16kV JEDEC HBM

• IEEE 802.3u PCS, 100BASE-TX Transceivers

• IEEE 1149.1 JTAG

Physical Sublayer with Adaptive Equalization and Baseline Wander Compensation

• Programmable LED Support Link, 10/100 Mb/s Mode, Activity, and Collision Detect

• 10/100 Mb/s Packet BIST (Built in Self Test)

• 48-pin TQFP Package (7mm) × (7mm)

1.2 Applications

• Industrial Controls and Factory Automation

• General Embedded Applications

1.3 General Description

The TLK100 is a single-port Ethernet PHY for 10BaseT and 100Base TX signaling. It integrates all the physical-layer functions needed to transmit and receive data on standard twisted-pair cables. This device supports the standard Media Independent Interface (MII) for direct connection to a Media Access Controller (MAC).

The TLK100 is designed for power-supply flexibility, and can operate with a single 3.3V power supply or with combinations of 3.3V, 1.8V, and 1.1V power supplies for reduced power operation.

The TLK100 uses mixed-signal processing to perform equalization, data recovery, and error correction to achieve robust operation over CAT 5 twisted-pair wiring. It not only meets the requirements of IEEE 802.3, but maintains high margins in terms of cross-talk and alien noise.

1.4 System Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testingof all parameters.

TX_CLK

TXD[3:0]

TX_EN

MDIO

MDC

COL

CRS/CRS_DV

RX_ER

RX_DV

RXD[3:0]

RX_CLK

TX_DATA RX_CLK

Reference Clock

TD± RD± LEDs

MII Interface

Auto-MDIX

DAC ADC

JTAG

MII

Serial

Management

TX_CLK RX_DATA

10BASE-T

and

100BASE-TX

10BASE-T

and

100BASE-TX

Transmit

Block

Receive

Block

MII

Registers

Auto-Negotiation

StateMachine

Clock

Generation

Boundary

Scan

LED

Drivers

B0313-01

Cable

Diagnostics

BIST

TLK100

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Figure 1-1. TLK100 Functional Block Diagram

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VSS

4 8

4 7

4 6

4 5

4 4

4 3

4 2

4 1

4 0

3 9

3 8

3 7

109

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

TLK100

RBIAS

CLK25OUT

MII_TXD_0

MII_TXD_1

MII_TXD_2

MII_TXD_3

MII_RX_CLK

MII_CRS / LED_CFG

MII_TX_EN

MII_TX_CLK

MII_COL / PHYAD0

MII_RX_DV

MII_RXD_0 / PHYAD1

MII_RXD_1 / PHYAD2

MII_RXD_2 / PHYAD3

MII_RXD_3 / PHYAD4

MDC

MDIO

LED_ACT / AN_EN

LED_SPEED/ AN_1

LED_LINK / AN_0

PWRDNN/INT

RESETN

JTAG_TCK

JTAG_TDI

JTAG_TMS

JTAG_TDO

JTAG_TRSTN

MII_RX_ERR / MDIX_EN

TD-

TD+

RD-

RD+

VA11_PFBOUT

V18_PFBOUT

VA11_PFBIN1

VA11_PFBIN2

V18_PFBIN1

V18_PFBIN2

VDD33_ VA11

VDD11

VDD33_IO

VDD33_V18

VDD33_VD11

TLK100

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1.5 Pin Layout

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Figure 1-2. TLK100 PIN DIAGRAM, TOP VIEW

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Contents

1 Introduction .............................................. 1 3.7 Cable Diagnostics .................................. 19

1.1 Features .............................................. 1

1.2 Applications .......................................... 1

1.3 General Description .................................. 1

1.4 System Diagram ..................................... 1

1.5 Pin Layout ............................................ 3

2 Pin Descriptions ......................................... 5

2.1 Serial Management Interface ........................ 5

2.2 MAC Data Interface .................................. 6

2.3 Clock Interface ....................................... 6

2.4 LED Interface ........................................ 6

2.5 JTAG Interface ....................................... 7

2.6 Reset and Power Down .............................. 7

2.7 Jumper Options ...................................... 8

2.8 10 Mb/s and 100 Mb/s PMD Interface ............... 9

2.9 Power and Bias Connections ........................ 9

2.10 Power Supply Configuration ........................ 10

3 Configuration ........................................... 13

3.1 Auto-Negotiation .................................... 13

3.2 Auto-MDIX .......................................... 14

3.3 PHY Address ....................................... 15

3.4 LED Interface ....................................... 16

3.5 Loopback Functionality ............................. 17

3.6 BIST ................................................ 18

4 Reset and Power Down Operation ................. 21

4.1 Hardware Reset .................................... 21

4.2 Software Reset ..................................... 21

4.3 Power Down/Interrupt .............................. 21

4.4 Power Down Modes ................................ 22

5 Design Guidelines ..................................... 23

5.1 TPI Network Circuit ................................. 23

5.2 Clock In (XI) Requirements ......................... 23

5.3 Thermal Vias Recommendation .................... 25

6 Register Block ......................................... 26

6.1 Register Definition .................................. 30

6.2 Register Control Register (REGCR) ................ 39

6.3 Address or Data Register (ADDAR) ................ 39

6.4 Extended Registers ................................. 40

6.5 Cable Diagnostic Registers ......................... 47

7 Electrical Specifications ............................. 56

7.1 ABSOLUTE MAXIMUM RATINGS ................. 56

7.2 THERMAL CHARACTERISTICS ................... 56

7.3 RECOMMENDED OPERATING CONDITIONS .... 56

7.4 DC CHARACTERISTICS ........................... 57

7.5 POWER SUPPLY CHARACTERISTICS ........... 57

7.6 AC Specifications ................................... 58

8 Appendix A: Digital Spectrum Analyzer (DSA)

Output .................................................... 70

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2 Pin Descriptions

The TLK100 pins are classified into the following interface categories (each interface is described in the sections that follow):

• Serial Management Interface

• MAC Data Interface

• Clock Interface

• LED Interface

• JTAG Interface

• Reset and Power Down

• Configuration (Jumper) Options

• 10/100 Mb/s PMD Interface

• Special Connect Pins

• Power and Ground pins Note: Configuration pin option. See Section 2.7 for Jumper Definitions. The definitions below define the functionality of each pin.

Type: I Input Type: O Output Type: I/O Input/Output Type: OD Open Drain Type: PD, PU Internal Pulldown/Pullup Type: S Configuration Pin (All configuration pins have weak internal pullups or pulldowns. If

SLLS931–AUGUST 2009

a different default value is needed, then use an external 2.2kΩ resistor. See

Section 2.7 for details.)

2.1 Serial Management Interface

NAME NO.

MDC 32 I maximum MDC rate is 25 MHz; there is no minimum MDC rate. MDC is not required to be synchronous to the

MDIO 33 I/O

TYPE DESCRIPTION

MANAGEMENT DATA CLOCK: Clock signal for the management data input/output (MDIO) interface. The

MII_TX_CLK or the MII_RX_CLK. MANAGEMENT DATA I/O: Bidirectional command / data signal synchronized to MDC. Either the local

controller or the TLK100 may drive the MDIO signal. This pin requires a pull-up resistor with value 1.5 kΩ.

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2.2 MAC Data Interface

NAME NO.

MII_TX_CLK 19 O, PD

MII_TX_EN 18 I, PD MII_TX_CLK . It indicates the presence of valid data inputs on MII_TXD[3:0]. It is an

MII_TXD_0 13 MII_TXD_1 14 MII TRANSMIT DATA: The transmit data nibble received from the MAC that is MII_TXD_2 15 synchronous to the rising edge of the MII_TX_CLK. MII_TXD_3 16

MII_RX_CLK 23 O

MII_RX_DV 30 S, O, PD

MII_RX_ERR/MDIX_EN 31 S, O, PU MII_RXD_0/PHYAD1 25

MII_RXD_1/PHYAD2 26 MII_RXD_2/PHYAD3 27 MII_RXD_3/PHYAD4 28

MII_CRS/LED_CFG 22 S, O, PU MII CARRIER SENSE: This pin is asserted high when the receive medium is non-idle.

MII_COL/PHYAD0 24 S, O, PU 10BASE-T/100BASE-TX half-duplex modes, this pin is asserted HIGH only when both

TYPE DESCRIPTION

MII TRANSMIT CLOCK: : MII Transmit Clock provides 25MHz or 2.5MHz reference

clock depending on the speed. MII TRANSMIT ENABLE: MII_TX_EN is presented on the rising edge of the

active high signal.

IS, I, PD

MII RECEIVE CLOCK: MII receive clock provides a 25MHz or 2.5MHz reference clock, depending on the speed, that is derived from the received data stream.

MII RECEIVE DATA VALID: This pin indicates valid data is present on the corresponding MII_RXD[3:0].

MII RECEIVE ERROR: This pin indicates that an error symbol has been detected within a received packet.

MII RECEIVE DATA: Symbols received on the cable are decoded and presented on

S, O, PD these pins synchronous to MII_RX_CLK. They contain valid data when MII_RX_DV is

asserted.

MII COLLISION DETECT: In Full Duplex Mode this pin is always low. In the transmit and receive media are non-idle.

2.3 Clock Interface

NAME NO.

XI 39 I oscillator input. The TLK100 supports either an external crystal resonator connected across pins XI and

XO 37 O

CLK25OUT 12 O allows other devices to use the reference clock from the TLK100 without requiring additional clock

TYPE DESCRIPTION

CRYSTAL/OSCILLATOR INPUT: Reference clock. 25MHz ±50 ppm tolerance crystal reference or

XO, or an external CMOS-level oscillator source connected to pin XI only. CRYSTAL OUTPUT: Reference Clock output. XO pin is used for crystal only. This pin should be left

floating when an oscillator input is connected to XI. 25 MHz CLOCK OUTPUT: In MII mode, this pin provides a 25 MHz clock output to the system. This

sources.

2.4 LED Interface

(See Table 3-3 for LED Mode Selection)

NAME NO.

LED_LINK/AN_0 36 S, O, PU Mode 2 and Mode 3, this pin indicates transmit and receive activity in addition to the status of the

LED_SPEED/AN_1 35 S, O, PU

LED_ACT/AN_EN 34 S, O, PU present on either Transmit or Receive channel. In Mode 3, this LED output may be programmed to

TYPE DESCRIPTION

This pin indicates the status of the link in Mode 1. When the link is good the LED will be ON. In Link. The LED is ON when Link is good. It will blink when the transmitter or receiver is active.

This pin indicates the speed of the link. It is ON when the link speed is 100 Mb/s and OFF when it is 10 Mb/s.

In mode 1 this pin indicates if there is any activity on the link. It is ON (pulse) when activity is indicate Full-duplex status.

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2.5 JTAG Interface

NAME NO.

JTAG_TCK 44 I, PU This pin is the test clock.This pin has a weak internal pullup. JTAG_TDI 45 I, PU This pin is the test data input.This pin has a weak internal pullup. JTAG_TDO 47 O This pin is the test data output. JTAG_TMS 46 I, PU This pin selects the test mode. This pin has a weak internal pullup. JTAG_TRST This pin is an active low asynchronous test reset. This pin has a weak internal pullup.

TYPE DESCRIPTION

48 I, PU

2.6 Reset and Power Down

NAME NO.

RESETN 43 I, PU TLK100. Asserting this pin low for at least 1 μs will force a reset process to occur. All jumper

PWRDNN/INT 42 I, OD, PU device is power down mode.

TYPE DESCRIPTION

This pin is an active Low reset input that initializes or re-initializes all the internal registers of the options are reinitialized as well.

Register access is required for this pin to be configured either as power down or as an interrupt. The default function of this pin is power down.

When this pin is configured for a power down function, an active low signal on this pin will put the

When this pin is configured as an interrupt pin then this pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with a weak internal pull-up. Some applications may require an external pull-up resistor.

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2.7 Jumper Options

Jumper option is an elegant way to configure the TLK100 into specific modes of operation. Some of the functional pins are used as jumper options. The logic states of these pins are sampled during reset and are used to configure the device into specific modes of operation. Below table shows the pins used for the jumper option and its description. The functional pin name is indicated in parentheses.

A 2.2 kΩ resistor should be used for pull-down or pull-up to change the default jumper option. If the default option is required, then there is no need for external pull-up or pull down resistors. Since these pins may have alternate functions after reset is deasserted, they should not be connected directly to VCC or GND.

PIN TYPE

NAME NO. DESCRIPTION

PHYAD0 (MII_COL) 24 PHYAD1 (MII_RXD_0) 25 PHYAD2 (MII_RXD_1) 26 S, O, PD PHYAD3 (MII_RXD_2) 27 PHYAD4 (MII_RXD_3) 28

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The TLK100 provides five PHY address pins, the states of which are latched into an internal register at system hardware reset. The TLK100 supports PHY Address jumpering values 0 (<00000>) through 31 (<11111>). All PHYAD[4:0] pins have weak internal pull-down resistors.

AN_EN: When high, this puts the part into advertised Auto-Negotiation mode with the capability set by AN_0 and AN_1 pins. When low, this puts the part into Forced Mode with the capability set by AN_0 and AN_1 pins.

AN_0 / AN_1: These input pins control the forced or advertised operating mode of the TLK100 according to the following table. The value on these pins is set by connecting the input pins to GND (0) or VCC (1) through 2.2 kΩ resistors. These pins should NEVER be connected directly to GND or VCC.

The status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset.

The default is 111 since these pins have internal pull-ups.

AN_EN (LED_ACT) 34 AN_1 (LED_SPEED) 35 S, O, PU AN_0 (LED_LINK) 36

LED_CFG (MII_CRS) 22 S, O, PU the LED pins. Default is Mode 1. All modes are also configurable via register access. See

MDIX_EN (MII_RX_ERR) 31 S, O, PU

AN_EN AN_1 AN_0 Forced Mode

0 0 0 10BASE-T, Half-Duplex 0 0 1 10BASE-T, Full-Duplex 0 1 0 100BASE-TX, Half-Duplex 0 1 1 100BASE-TX, Full-Duplex

AN_EN AN_1 AN_0 Advertised Mode

1 0 0 10BASE-T, Half/Full-Duplex 1 0 1 10BASE-TX, Half/Full-Duplex

1 1 0

1 1 1

This jumpering option along with LEDCR register bit determines the mode of operation of the table in the LED Interface Section.

This jumpering option sets the Auto-MDIX mode. By default it enables MDIX. An external pull-down will disable Auto-MDIX mode.

10BASE-T, Half-Duplex 100BASE-TX, Half-Duplex

10BASE-T, Half/Full-Duplex 100BASE-TX, Half/Full-Duplex

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2.8 10 Mb/s and 100 Mb/s PMD Interface

NAME NO.

TD–, TD+ 8, 9 I/O

RD–, RD+ 5, 6 I/O

TYPE DESCRIPTION

Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling.

In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 1.8V or 3.3V bias for operation.

Differential receive input (PMD Input Pair). These differential inputs are automatically configured to accept either 100BASE-TX or 10BASE-T signaling.

In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair. These pins require

1.8V or 3.3V bias for operation.

2.9 Power and Bias Connections

NAME NO.

RBIAS 3 I Bias Resistor Connection. Use a 4.99kΩ 1% resistor connected from RBIAS to GND. V18_PFBOUT 40 O

VA11_PFBOUT 10 O

V18_PFBIN1 2

V18_PFBIN2 4

VA11_PFBIN1 1

VA11_PFBIN2 7 VDD11 20 O 1.1V Core Power Output. A capacitor of 1μF (Ceramic preferred) , should be placed close to the VDD11

VDD33_IO P I/O 3.3V Supply

VDD33_VA11 11 P This pin should be connected to 3.3V or 2.5V external supply, in single supply operation.

VDD33_V18 41 P In single supply operation, this pin should be connected to a 3.3V or 2.5V external supply. In multiple

VDD33_VD11 21 P This pin should be connected to 3.3V or 2.5V external supply, in single supply operation.

VSS 38 P Ground pin for Oscillator GNDPAD 49 P Ground Pad

TYPE DESCRIPTION

1.8V Power Feedback Output. A 1μF capacitor (ceramic preferred), should be placed close to the V18_PFBOUT.

In single supply operation, connect this pin should be connected to V18_PFBIN1 and V18_PFBIN2 (pin 2 and pin 4). See Figure 2-1 for proper placement pin.

In multiple supply operation, when supplying 1.8V from external supply, this pin should be connected together with VDD33_V18 (pin 41), V18_PFBIN1 and V18_PFBIN2 (pin 2 and pin 4) to the 1.8V external supply source. See Figure 2-2 for proper placement pin.

1.1V Analog Power Feedback Output. A 1 μF capacitor (Ceramic preferred), should be placed close to the VA11_PFBOUT.

In single supply operation this pin should be connected to VA11_PFBIN1 and V11_PFBIN2 (pin 1 and pin 7). See Figure 2-1 for proper placement pin.

In multiple supply operation, when supplying 1.1V from external supply, this pin should be connected together with VDD33_VA11 (pin 11), V11_PFBIN1 and V11_PFBIN2 (pin 1 and pin 7) to 1.1V external supply source. See Figure 2-3 for proper placement pin.

1.8V Power Feedback Input. These pins are fed with power from V18_PFBOUT (pin 40) in single supply operation.

1.8V from external source in multiple supply operation. A small 1μF capacitor should be connected close to each pin.

1.1V Analog Power Feedback Input. These pins are fed with power from: VA11_PFBOUT (pin 10) in single supply operation.

1.1V from external source in multiple supply operation. A small capacitor of 0.1 μF should be connected close to each pin.

17 29

External supply input to 1.1V analog regulator In multiple supply operation this pin should be connected to external 1.1V supply source.

External supply input to 1.8V regulator supply operation this pin should be connected to an external 1.8V supply source.

External supply input to 1.1V Core regulator In multiple supply operation this pin should be connected to external 1.1V supply source.

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Vdd

1 :1

RJ 45

3.3V

Supply

TLK100

VDD33_VA11

VA11_PFBOUT

VA11_PFBIN1

VA11_PFBIN2

VDD33_VD11

VDD11

VDD33_IO

RD–

RD+

49.9W

1.0 Fm

TD–

TD+

VDD33_V18

V18_PFBOUT

V18_PFBIN1

V18_PFBIN2

49.9W

0.1 Fm

3.3V

Supply

3.3V

Supply

0.1 Fm

1.0 Fm

TLK100

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2.10 Power Supply Configuration

The TLK100 provides best-in-class flexibility of power supplies.

• Single supply operation – If a single 3.3V power supply is desired, the TLK100 will sense the presence of the supply and configure the internal voltage regulators to provide all necessary supply voltages. To operate in this mode, connect the TLK100 supply pins according to the following scheme:

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Figure 2-1. Power Scheme for Single Supply Operation

• Multiple Supply operation – When additional 1.8V and/or 1.1V external power rails are available, the TLK100 can be configured in various ways as given in Table 2-1. This gives the highest flexibility for the user and enables significant reduction in power consumption. When using multiple external supplies, the internal regulators must be disabled by appropriate device connections.

– When an external 1.8V rail is available – Connect the external 1.8V to all following TLK100 pins to

enable proper operation: V18_PFBOUT (pin 40), V18_PFBIN1 (pin 2), V18_PFBIN2 (pin 4) and VDD33_V18 (pin 41). In addition, connect the 1.8V rail to the transformer center tap to further reduce the transmission power, as shown in Figure 2-2:

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Pin 5 (RD–)

RD–

Pin 6 (RD+)

RD+

Vdd

1.8 V Supply

Pin 8 (TD–)

TD–

Pin 9 (TD+)

TD+

Vdd

1:1

RJ45

Pin 41 (VDD33_V18)

Pin 40 (V18_PFBOUT)

Pin 2 (V18_PFBIN)

Pin 4 (V18_PFBIN2)

1.8 V Supply

TLK100

499 W

0.1 Fm

0.1 F*m

1.1 V

Supply

TLK100

Pin11 (VDD33_VA11)

Pin10 (VA11_PFBOUT)

Pin1 (VA11_PFBIN1)

Pin7 (VA11_PFBIN2)

Pin21 (VDD33_VA11)

Pin20 (VDD11)

TLK100

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Figure 2-2. Power Scheme for Operation With External 1.8V Supply

– External 1.1V rail – When external 1.1V rail is available – Connect the external 1.1V to the following

pins: VA11_PFBOUT (pin 10), VDD11 (pin 20), VA11_PFBIN1 (pin 1), VA11_PFBIN2 (pin 7), VDD33_VA11 (pin 11) and VDD33_VD11 (pin 21) as shown in Figure 2-3:

• Lowest-power operation – When 1.1V and 1.8V supplies are already available in addition to 3.3V, designers can take advantage of the lowest-power configuration of the TLK100. By supplying external

1.8 and 1.1V as explained above, all the internal regulators are powered down and the device is fully driven by the external supplies giving the lowest power operation.

Figure 2-3. Power Scheme for Operation With External 1.1V Supply

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Other power supply options – Because the TLK100 incorporates independent voltage regulators, designers may take advantage of several optional configurations, depending on available power supplies. See Table 2-1 for these options.

Table 2-1. Power Supply Options

MAC I/F Transformer CT

Mode

Single Supply 3.3V from 3.3V from 3.3V from 3.3V from

Operation external supply external supply external supply external supply

Lowest Power 3.3V from 1.8V from 1.8V from 1.1V from

Consumption external supply external supply external supply external supply

(3.3V) (3.3V or 1.8V)

Voltage Source Voltage Source Voltage Source Voltage Source

3.3V from 3.3V from 3.3V from 2.5V from

external supply external supply external supply external supply

3.3V from 3.3V from 3.3V from 1.1V from

external supply external supply external supply external supply

3.3V from 3.3V from 2.5V from 3.3V from

external supply external supply external supply external supply

3.3V from 3.3V from 2.5V from 2.5V from

external supply external supply external supply external supply

3.3V from 3.3V from 2.5V from 1.1V from

external supply external supply external supply external supply

3.3V from 1.8V from 1.8V from 3.3V from

external supply external supply external supply external supply

3.3V from 1.8V from 1.8V from 2.5V from

external supply external supply external supply external supply

Regulator Regulators (ON/OFF) (ON/OFF)

ON ON

ON OFF

ON ON

ON OFF

OFF ON

OFF OFF

(1.8V) (1.1V)

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3 Configuration

This section includes information on the various configuration options available with the TLK100. The configuration options described below include:

• Auto-Negotiation

• Auto-MDIX

• PHY Address

• LED Interface

• Loopback Functionality

• BIST

• Cable Diagnostics

3.1 Auto-Negotiation

The TLK100 device can auto-negotiate to operate in 10BASE-T or 100BASE-TX. If Auto-Negotiation is enabled, then the TLK100 device negotiates with the link partner to determine the speed and duplex with which to operate. If the link partner is unable to Auto-Negotiate, the TLK100 device would go into the parallel detect mode to determine the speed of the link partner. Under parallel detect mode, the duplex mode is fixed at half-duplex.

The TLK100 supports four different Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex), so the inclusion of Auto-Negotiation ensures that the highest performance protocol will be selected based on the advertised ability of the Link Partner. The Auto-Negotiation function within the TLK100 can be controlled either by internal register access or by the use of the AN_EN, AN_1 and AN_0 pins.

SLLS931–AUGUST 2009

The state of AN_EN, AN_0 and AN_1 pins determines whether the TLK100 is forced into a specific mode or Auto-Negotiation will advertise a specific ability (or set of abilities) as given in Table 2-1. These pins allow configuration options to be selected without requiring internal register access. The state of AN_EN, AN_0 and AN_1, upon power-up/reset, determines the state of bits [8:5] of the ANAR register (0x04h).

Table 3-1. Auto-Negotiation Modes

AN_EN AN_1 AN_0 Forced Mode

0 0 0 10BASE-T, Half-Duplex 0 0 1 10BASE-T, Full-Duplex 0 1 0 100BASE-TX, Half-Duplex 0 1 1 100BASE-TX, Full-Duplex

AN_EN AN_1 AN_0 Advertised Mode

1 0 0 10BASE-T, Half/Full-Duplex 1 0 1 10BASE-TX, Half/Full-Duplex 1 1 0 10BASE-T, Half Duplex

1 1 1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half Duplex

100BASE-TX, Half/Full-Duplex

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The Auto-Negotiation function can also be controlled by internal register access using registers as defined by the IEEE 802.3u specification. For further detail regarding Auto-Negotiation, see Clause 28 of the IEEE

802.3u specification.

3.2 Auto-MDIX

The TLK100 device automatically determines whether or not it needs to cross over between pairs so that an external crossover cable is not required. If the TLK100 device interoperates with a device that implements MDI/MDIX crossover, a random algorithm as described in IEEE 802.3 determines which device performs the crossover.

Auto-MDIX is enabled by default and can be configured via jumper or via PHYCR (0x10h) register, bits [6:5].

The crossover can be manually forced through bit 5 of PHYCR (0x10h) register. Neither Auto-Negotiation nor Auto-MDIX is required to be enabled in forcing crossover of the MDI pairs.

Auto-MDIX can be used in the forced 100BT mode but not in the forced MDIX mode. As in modern networks all the nodes are 100BT, having the Auto-MDIX working in the forced 100BT mode will resolve the link faster without the need for the long Auto-Negotiation.

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MII_COL

MII_RXD_0

MII_RXD_1

MII_RXD_2

MII_RXD_3

2.2kW

VCC

PHYAD4=0 PHYAD3=0 PHYAD2=0 PHYAD1=1 PHYAD0=1

B0314-01

TLK100

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3.3 PHY Address

The 5 PHY address inputs pins are shared with the MII_RXD[3:0] pins and COL pin as shown in

Table 3-2.

Each TLK100 or port sharing an MDIO bus in a system must have a unique physical address. With 5 address input pins, the TLK100 can support PHY Address values 0 (<00000>) through 31 (<11111>). The address-pin states are latched into an internal register at device power-up and hardware reset. Because all the PHYAD[4:0] pins have weak internal pull-down resistors, the default setting for the PHY address is 00000 (0x00h).

See Figure 3-1 for an example of a PHYAD connection to external components. In this example, the PHYAD configuration results in address 00010 (0x02h).

SLLS931–AUGUST 2009

Table 3-2. PHY Address Mapping

PIN # PHYAD FUNCTION RXD FUNCTION

24 PHYAD0 MII_COL 25 PHYAD1 MII_RXD_0 26 PHYAD2 MII_RXD_1 27 PHYAD3 MII_RXD_2 28 PHYAD4 MII_RXD_3

Figure 3-1. PHYAD Configuration Example

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LED_LINK

LED_SPEED

LED_ACT/COL

110 W 110 W110 W

2.2kW 2.2kW2.2kW

VCC

AN_EN=1 AN1=1 AN0=1

B0315-01

TLK100

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3.4 LED Interface

The TLK100 supports three configurable Light Emitting Diode (LED) pins. The device supports three LED configurations: Link, Speed, and Activity. Functions are multiplexed among the LEDs into three modes. The LEDs can be controlled by configuration pin and/or internal register bits. Bits 6:5 of the LED Direct Control register (LEDCR) selects the LED mode as described in Table 3-3.

Table 3-3. LED Mode Select

Mode LED_LINK LED_SPEED LED_ACT

1 don't care 1

2 0 0

3 1 0

LED_CFG[1] LED_CFG[0]

(bit 6) (bit 5) or (pin 22)

ON for Good Link ON in 100 Mb/s ON Pulse for Activity OFF for No Link OFF in 10 Mb/s OFF for No Activity

ON for Good Link ON in 100 Mb/s None BLINK for Activity OFF in 10 Mb/s

ON for Good Link ON in 100 Mb/s ON for Full Duplex BLINK for Activity OFF in 10 Mb/s OFF for Half Duplex

The LED_LINK pin in Mode 1 indicates the link status of the port. It is OFF when no LINK is present. In Mode 2 and Mode 3 it is ON to indicate Link is good and BLINK to indicate activity is present on either transmit or receive channel. The blink rate is decided by the bits 9:8 of the LEDCR register (0x18). The default blink rate is 5Hz.

The LED_SPEED pin indicates 10 or 100 Mb/s data rate of the port. This LED is ON when the device is operating in 100 Mb/s operation. The functionality of this LED is independent of mode selected.

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The LED_ACT pin in Mode 1 indicates the presence of either transmit or receive activity. The LED is ON (Pulse) for Activity and OFF for No Activity. The width of the pulse is determined by the bits 14:13 of the LEDCR register (0x18). The default pulse width is 200ms. In mode 3 this pin indicates the Duplex status of operation. The LED is ON for Full Duplex and OFF for Half Duplex.

Bits 2:0 of the LEDCR register defines the polarity of the signals on the LED pins. Since the Auto-Negotiation (AN) configuration options share the LED output pins, the external components

required for configuration-pin programming and those for LED usage must be considered in order to avoid contention.

See Figure 3-2 for an example of AN connections to external components. In this example, the AN programming results in Auto-Negotiation with 10/100 Half/Full-Duplex advertised.

Figure 3-2. AN Pin Configuration and LED Loading Example

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MAC/ Switch

PCS

Signal

Process

PHY AFE

DigitalLoopback

PHY Digital

ExternalLoopback

AnalogLoopbackPCSLoopback

XFMR

RJ45

2 3

4 5

6 7 8

I I

MIILoopback

TLK100

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3.5 Loopback Functionality

The TLK100 provides several options for Loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the TLK100 digital and analog data path. Generally, the TLK100 may be configured to one of the Near-end loopback modes or to the Far-end (reverse) loopback.

3.5.1 Near-End Loopback

Near-end loopback provides the ability to loop the transmitted data back to the receiver via the digital or analog circuitry. The point at which the signal is looped back is selected using loopback control bits with several options being provided. Figure 3-3 shows the PHY near-end loopback functionality.

SLLS931–AUGUST 2009

Figure 3-3. Block Diagram, Near-End Loopback Mode

The Near-end Loopback mode is selected by setting the respective bit in the BIST Control Register (BISCR), MII register address 0x16. Bits 3:0 of the BISCR register are used to set the loopback mode according to the following:

• Bit [0]: MII Loopback

• Bit [1]: PCS Loopback (in 100BaseTX only)

• Bit [2]: Digital Loopback

• Bit [3]: Analog Loopback

While in Loopback mode the data is looped back and also transmitted onto the media. To ensure proper operation in Analog Loopback mode 100Ω terminations should be attached to the RJ45 connector.

External Loopback can be performed while working in normal mode (Bits 3:0 of the BISCR register are assert to 0 and on RJ45 connector pin 1 is shorted to pin 3 and pin 2 is shorted to pin 6).

To maintain the desired operating mode, Auto-Negotiation should be disabled before selecting Loopback mode. This is not relevant for external-loopback mode.

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MAC/ Switch

PCS

Signal

Process

PHY AFE

PHY Digital

XFMR

RJ45

CAT5 Cable

LinkPartner

I I

ReverseLoopback

TLK100

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3.5.2 Far-End Loopback

Far-end (Reverse) loopback is a special test mode to allow testing the PHY from link partner side. In this mode data that is received from the link partner pass through the PHY's receiver, looped back on the MII and transmitted back to the link partner. Figure 3-4 shows Far-end loopback functionality.

The Reverse Loopback mode is selected by setting bit 4 in the BIST Control Register (BISCR), MII register address 0x16.

While in Reverse Loopback mode the data is looped back and also transmitted onto the MAC Interface and all data signals that come from the MAC are ignored.

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Figure 3-4. Block Diagram, Far-End Loopback Mode

3.6 BIST

The TLK100 incorporates an internal PRBS Built-in Self Test (BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be utilized to test the integrity of the transmit and receive data paths. The BIST testing can be performed using both internal loopback (digital or analog) or external loop back using a cable fixture. The BIST simulates a real data transfer scenarios using real packets on the lines. The BIST allows full control of the packets lengths and of the Inter Packet Gap (IPG)

The BIST is implemented with independent transmit and receive paths, with the transmit block generating a continuous stream of a pseudo random sequence. The TLK100 generates a 23-bit pseudo random sequence for doing the BIST test. The received data is compared to the generated pseudo-random data by the BIST Linear Feedback Shift Register (LFSR) to determine the BIST pass/fail status. The number of error bytes that the PRBS checker received is stored in the BISECR register (0x72h).The number of transmitted bytes that the PRBS checker received is stored in the BISBCR register (0x71h). The status of whether the PRBS checker is locked to the incoming receive bit stream, whether the PRBS is in sync or not and whether the packet generator is busy or not can be found by reading the BISSR register (0x17h).

The PRBS test can be put in a continuous mode or single mode by using the bit 15 of the BISCR register (0x16h). In the continuous mode, when one of the PRBS counter reaches the maximum value the counter starts counting from zero again. In the single mode when the PRBS counter reaches its maximum value the PRBS checker stops counting.

TLK100 allows the user to control the length of the PRBS packet. By programming the BISPLR register (0x7Bh) register one can set the length of the PRBS packet. There is also an option to generate a single packet transmission of two types 64 and 1518 bytes through register bit – bit13 of the BISCR register (0x16h). The single generated packet is composed of a constant data.

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TLK100

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3.7 Cable Diagnostics

With the vast deployment of Ethernet devices, the need for reliable, comprehensive and user-friendly cable diagnostic tool is more important than ever. The wide variety of cables, topologies, and connectors deployed results with the need to non-intrusively identify and report cable faults. TI cable diagnostic unit provides extensive information about cable integrity.

The TLK100 offers the following capabilities in its Cable Diagnostic tools kit:

1. Time Domain Reflectometry (TDR).

2. Active Link Cable Diagnostic (ALCD).

3. Digital Spectrum Analyzer (DSA)

3.7.1 TDR

The TLK100 uses Time Domain Reflectometry (TDR) to determine the quality of the cables, connectors, and terminations in addition to estimation of the cable length. Some of the possible problems that can be diagnosed include opens, shorts, cable impedance mismatch, bad connectors, termination mismatches, and any other discontinuities on the cable.

The TLK100 device transmits a test pulse of known amplitude (1V) down each of the two pairs of an attached cable. The transmitted signal continues down the cable and reflects from each cable imperfection, fault, bad connector and the end of the cable itself. After the pulse transmission the TLK100 measures the return time and amplitude of all these reflected pulses. This technique enables measuring the distance and magnitude (impedance) of non-terminated cables (open or short), discontinuities (bad connectors), and improperly-terminated cables with an accuracy of ±1m.

SLLS931–AUGUST 2009

To do this, the TLK100 uses a RAM with up to 256 samples to record all the input sampled data (Equals to max possible measured cable length of over 200m). The TLK100 also uses soft data averaging to reduce noise and improve accuracy. The TLK100 is capable of recording up to five reflections within the tester pair. In case more than 5 reflections were recorded the TLK100 will save the last 5 of them.

For all TDR measurements, the transformation between time of arrival and physical distance is done by the external host using minor computations (such as multiplication/addition and lookup tables). The host must know the expected propagation delay of the cable, which depends, among other things, on the cable category (e.g. CAT5/CAT5e/CAT6).

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TLK100

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3.7.2 ALCD

The TLK100 also supports Active Link Cable Diagnostic (ALCD). The ALCD offers a passive method to estimate the cable length during active link. It uses passive digital signal processing based on adapted data thus enabling measurement of cable length with an active link partner.

The ALCD also uses pre-defined parameters according to the cable properties (e.g. CAT5/CAT5e/CAT6) in order to achieve higher accuracy in the estimated cable length. The ALCD Cable length measurement accuracy is +/-5m for the pair used in the Rx path (due to the passive nature of the test we measure only the pair on the Rx path).

3.7.3 DSA

The TLK100 also offers a unique capability of Digital Spectrum Analyzer (DSA). The DSA enables a very detailed analysis of the channel frequency response (Magnitude only). The DSA has the following capabilities:

• Produce channel frequency response in resolution of 119.2Hz.

• Save up to 512 bins per DSA run.

• Full control in the analyzed frequency bins location and resolution.

• Programmable options for input data for the DSA: – Use raw data taken directly from the channel – Use adapted data that passed digital signal processing

• Use additional filtering for smoothing the total channel frequency response.

• Build in averaging for more accurate results

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NOTE: For an example of the DSA output please see appendix A

To reset the cable diagnostic registers, set bit 14 of RAMCR2 register (0x0D01) to '1'. Writing software global reset 0x001F bit 15 does not reset the cable diagnostic registers.

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4 Reset and Power Down Operation

At power up it is recommended to have the external reset pin (RESETN) active (low). The RESETN pin should be de-asserted 200μs after the power is ramped up to allow the internal circuits to settle and for the internal regulators to be stabilized. If required during normal operation, the device can be reset by a hardware or software reset.

4.1 Hardware Reset

A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1μs, to the RESETN. This will reset the device such that all registers will be reinitialized to default values and the hardware configuration values will be re-latched into the device (similar to the power-up/reset operation).

4.2 Software Reset

A software reset is accomplished by setting the reset bit (bit 15) of the BMCR register (0x00h). This bit only resets the IEEE defined standard registers in the address space 0x00h to 0x07h. The software global reset is accomplished by setting bit 15 of register PDN (0x001F) to ‘1’. This bit resets IEEE defined registers (0x00h to 0x07h) and all the extended registers except for the cable-diagnostic registers and RAM registers. For resetting the cable diagnostics and RAM registers, bit 14 of register RAMCR2 (0x0D01) should be set to ‘1’. The time from the point when the reset bit is set to the point the when software reset has concluded is approximately 1.3 μs.

The software global reset resets the device such that all registers are reset to default values and the hardware configuration values are maintained. Software driver code must wait 3 μs following a software reset before allowing further serial MII operations with the TLK100.

SLLS931–AUGUST 2009

4.3 Power Down/Interrupt

The Power Down and Interrupt functions are multiplexed on pin 42 of the device. By default, this pin functions as a power down input and the interrupt function is disabled. This pin can be configured as an interrupt output pin by setting bit 15 (INTN_OE) to ‘1’ and bit 12 (INTN_OEN) to ‘0’ of the MINTCR (0x14h) register. Bit 13 of the same MINTCR register is used to set the polarity of the interrupt.

4.3.1 Power Down Control Mode

The PWRDNN/INT pin can be asserted low to put the device in a Power Down mode. An external control signal can be used to drive the pin low, overcoming the weak internal pull-up resistor. Alternatively, the device can be configured to initialize into a Power Down state by use of an external pulldown resistor on the PWRDNN/INT pin.

4.3.2 Interrupt Mechanisms

The interrupt function is controlled via register access. All interrupt sources are disabled by default. The MINTMR register provides independent interrupt enable bits for the different interrupts supported by TLK100. The PWRDNN/INT pin is asynchronously asserted low when an interrupt condition occurs. The source of the interrupt can be determined by reading the interrupt status register MINTSR (0x13h). One or more bits in the MINTSR will be set, denoting all currently pending interrupts. Reading of the MINTSR clears ALL pending interrupts.

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TLK100

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4.4 Power Down Modes

TLK100 supports four types of power saving modes. The lowest power consumption is in the "Extreme Low Power" mode (ELP). To enter into the ELP mode the PWRDNN/INT pin is pulled LOW.

To enable the power-down modes described below, set bit 11 of register BMCR (0x00h) to '1'. In all power-down modes, the entire PHY is powered down except for the SMI interface; the PHY stays in that condition as long as the value of bit 11 of register BMCR (0x00h) remains '1'. When this bit is cleared, the PHY powers up and returns to the last state it was in before it was powered down.

In General Power Down mode, bits 9 and 8 of the PHYCR register (0x10h) should be set to "01". Additionally, bit 4 of the PHYCR register (0x10h) should be set to '1' so as to power down the internal PLL. The SMI would operate on the reference clock.

In Active sleep mode, or Energy-Detect mode, every 1.4 seconds a Normal Link Pulse (NLP) is sent to wake up the link-partner. To enter into the active sleep mode, bits 9 and 8 of register PHYCR (0x10h) is set to "10". Automatic powerup is done when the link partner is detected.

In passive sleep mode, all core blocks are powered down. Automatic power-up is done when the link partner is detected. To enter into the passive sleep mode, bits 9 and 8 of register PHYCR (0x10h) is set to "11".

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RD–

RD+ RD+

49.9 W

Vdd

0.1 Fm

0.1 F*m

TD– TD–

TD+

49.9 W

Vdd

0.1 Fm

0.1 F*m

1:1

RJ45

Placeresistorsandcapacitorsclosetothedevice.

Common-modechokes

mayberequired.

Note:CentertapisconnectedtoVdd

*Placecapacitorsclosetothe

transformercentertaps

Allvaluesaretypicalandare 1%±

S0339-01

TLK100

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5 Design Guidelines

5.1 TPI Network Circuit

Figure 5-1 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. Below is a partial list

of recommended transformers. It is important that the user realize that variations with PCB and component characteristics require that the application be tested to verify that the circuit meets the requirements of the intended application.

• Pulse H1102

• Pulse HX1188

SLLS931–AUGUST 2009

Figure 5-1. 10/100 Mb/s Twisted Pair Interface

5.2 Clock In (XI) Requirements

The TLK100 supports an external CMOS-level oscillator source or an internal oscillator with an external crystal.

5.2.1 Oscillator

If an external clock source is used, XI should be tied to the clock source and XO should be left floating. The amplitude of the oscillator should be a nominal voltage of 1.8V.

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+ 51 hidden pages

TEXAS INSTRUMENTS TLK100 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

1.1 Features

1.2 Applications

1.3 General Description

1.4 System Diagram

1.5 Pin Layout

2 Pin Descriptions

2.1 Serial Management Interface

2.2 MAC Data Interface

2.3 Clock Interface

2.4 LED Interface

2.5 JTAG Interface

2.6 Reset and Power Down

2.7 Jumper Options

2.8 10 Mb/s and 100 Mb/s PMD Interface

2.9 Power and Bias Connections

2.10 Power Supply Configuration

3 Configuration

3.1 Auto-Negotiation

3.2 Auto-MDIX

3.3 PHY Address

3.4 LED Interface

3.5 Loopback Functionality

3.5.1 Near-End Loopback

3.5.2 Far-End Loopback

3.6 BIST

3.7 Cable Diagnostics

3.7.1 TDR

3.7.2 ALCD

3.7.3 DSA

4 Reset and Power Down Operation

4.1 Hardware Reset

4.2 Software Reset

4.3 Power Down/Interrupt

4.3.1 Power Down Control Mode

4.3.2 Interrupt Mechanisms

4.4 Power Down Modes

5 Design Guidelines

5.1 TPI Network Circuit

5.2 Clock In (XI) Requirements

5.2.1 Oscillator