TLC7628C, TLC7628E, TLC7628I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS063A – APRIL 1989 – REVISED MA Y 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Easy Microprocessor Interface
D
On-Chip Data Latches
D
Digital Inputs Are TTL-Compatible With
10.8-V to 15.75-V Power Supply
D
Monotonic Over the Entire A/D Conversion
Range
D
Fast Control Signaling for Digital Signal
Processor (DSP) Applications Including
Interface With TMS320
D
CMOS Technology
KEY PERFORMANCE SPECIFICATIONS
Resolution
Linearity Error
Power Dissipation
Settling Time
Propagation Delay Time
8 bits
1/2 LSB
20 mW
100 ns
80 ns
description
The TLC7628C, TLC7628E, and TLC7628I are
dual, 8-bit, digital-to-analog converters (DACs)
designed with separate on-chip data latches and
feature exceptionally close DAC-to-DAC
matching. Data is transferred to either of the two
DAC data latches through a common, 8-bit input
port. Control input DACA
/DACB determines
which DAC is loaded. The load cycle of these
devices is similar to the write cycle of a
random-access memory, allowing easy interface
to most popular microprocessor buses and output ports. Segmenting the high-order bits minimizes glitches
during changes in the most significant bits, where glitch impulse is typically the strongest.
The TLC7628C operates from a 10.8-V to 15.75-V power supply and is TTL-compatible over this range. 2- or
4-quadrant multiplying makes these devices a sound choice for many microprocessor-controlled gain-setting
and signal-control applications.
The TLC7628C is characterized for operation from 0°C to 70°C. The TLC7628I is characterized for operation
from –25°C to 85°C. The TLC7628E is characterized for operation from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
PLASTIC DIP
(DW)
PLASTIC CHIP
CARRIER
(FN)
PLASTIC DIP
(N)
0°C to 70°C TLC7628CDW TLC7628CFN TLC7628CN
–25°C to 85°C TLC7628IDW TLC7628IFN TLC7628IN
–40°C to 85°C TLC7628EDW TLC7628EFN TLC7628EN
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AGND
OUTA
RFBA
REFA
DGND
DACA
/DACB
(MSB) DB7
DB6
DB5
DB4
OUTB
RFBB
REFB
V
DD
WR
CS
DB0 (LSB)
DB1
DB2
DB3
DW OR N PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
REFB
V
DD
WR
CS
DB0 (LSB)
REFA
DGND
DACA
/DACB
(MSB) DB7
DB6
FN PACKAGE
(TOP VIEW)
RFBA
OUTA
AGND
DB2
DB1
OUTB
RFBB
DB5
DB4
DB3
TLC7628C, TLC7628E, TLC7628I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS063A – APRIL 1989 – REVISED MA Y 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
DACA/DACB
REFB
18
OUTB
20
RFBB
19
AGND
1
OUTA
2
RFBA
3
REFA
4
DACA
Input
Buffer
Logic
Control
DACB
DB0
DB7
CS
WR
15
16
6
Data
Inputs
7
8
9
10
11
12
13
14
8
8
8
8
Latch A
Latch B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
DD
(to AGND or DGND) –0.3 V to 17 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage between AGND and DGND V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(to DGND) –0.3 V to V
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference voltage range, V
refA
or V
refB
(to AGND) ±25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feedback voltage range, V
RFBA
or V
RFBB
(to AGND) ±25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
OA
or VOB (to AGND) ±25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak input current 10 µA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
: TLC7628C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC7628I –25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC7628E –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 10 seconds, T
C
: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package 260°C. . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
TLC7628C, TLC7628E, TLC7628I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS063A – APRIL 1989 – REVISED MA Y 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
DD
10.8 15.75 V
Reference voltage, V
refA
or V
refB
±10 V
High-level input voltage, V
IH
2.4 V
Low-level input voltage, V
IL
0.8 V
CS setup time, t
su(CS)
50 ns
CS hold time, t
h(CS)
(see Figure 1) 0 ns
DAC select setup time, t
su(DAC)
(see Figure 1) 60 ns
DAC select hold time, t
h(DAC)
(see Figure 1) 10 ns
Data bus input setup time t
su(D)
(see Figure 1) 25 ns
Data bus input hold time t
h(D)
(see Figure 1) 10 ns
Pulse duration, WR low, t
w(WR)
(see Figure 1) 50 ns
TLC7628C 0 70
Operating free-air temperature, T
A
TLC7628I –25 85
°C
TLC7628E –40 85
electrical characteristics over recommended ranges of operating free-air temperature and VDD,
V
refA
= V
refB
= 10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
p
Full range 10
IIHHigh-level input current
V
I
=
V
DD
25°C 1
µ
A
p
Full range –10
IILLow-level input current
V
I
=
0
25°C –1
µ
A
Reference input impedance REFA or REFB to
AGND
5 20 kΩ
DAC data latch loaded with 00000000,
Full range ±200
p
OUTA
,
V
refA
= ±10 V
25°C ±50
IkgOutput leakage current
DAC data latch loaded with 00000000,
Full range ±200
nA
OUTB
,
V
refB
= ±10 V
25°C ±50
Input resistance match (REFA to REFB) ±1%
pp
Full range 0.02
DC supply sensitivity ∆gain/∆V
DD
∆V
DD
=
± 5 %
25°C 0.01
%/%
Quiescent All digital inputs at VIHmin or VILmax 2
I
DD
Supply current
p
Full range 0.5
mA
Standb
y
All digital inputs at 0 V or V
DD
25°C 0.1
DB0–DB7 10
C
i
Input capacitance
WR
, CS,
DACA
/DACB
15
pF
p
p
DAC data latches loaded with 00000000 25
p
CoOutput capacitance (OUTA, OUTB)
DAC data latches loaded with 11111111 60
pF
TLC7628C, TLC7628E, TLC7628I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS063A – APRIL 1989 – REVISED MA Y 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics over recommended ranges of operating free-air temperature and VDD,
V
refA
= V
refB
= 10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Linearity error ±1/2 LSB
Settling time (to 1/2 LSB) See Note 1 100 ns
Full range ±3
Gain error
See Note 2
25°C ±2
LSB
REFA to OUTA
Full range –65
AC feedthrough
REFB to OUTB
See Note 3
25°C –75
dB
Temperature coefficient of gain ±0.0035 %FSR/°C
Propagation delay (from digital input to
90% of final analog output current)
See Note 4 80 ns
Channel-to-channel
REFA to OUTB See Note 5 25°C 80
isolation
REFB to OUTA See Note 6 25°C 80
dB
Digital-to-analog glitch impulse area
Measured for code transition from 00000000 to 11111111,
TA = 25°C
330 nV•s
Digital crosstalk
Measured for code transition from 00000000 to 11111111,
TA = 25°C
60 nV•s
Harmonic distortion Vi = 6 V, f = 1 kHz, TA = 25°C –85 dB
NOTES: 1. OUTA, OUTB load = 100 Ω, C
ext
= 13 pF; WR and CS at 0 V; DB0–DB7 at 0 V to VDD or VDD to 0 V.
2. Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = V
ref
– 1 LSB. Both DAC latches are
loaded with 1 1111111.
3. V
ref
= 20 V peak-to-peak, 10-kHz sine wave
4. V
refA
= V
refB
= 10 V; OUTA/OUTB load = 100 Ω, C
ext
= 13 pF; WR
and CS at 0 V; DB0–DB7 at 0 V to VDD or VDD to 0 V.
5. V
refA
= 20 V peak-to-peak, 10-kHz sine wave; V
refB
= 0
6. V
refB
= 20 V peak-to-peak, 10-kHz sine wave; V
refA
= 0
t
h(DAC)
t
h(CS)
t
su(CS)
t
su(DAC)
t
w(WR)
t
h(D)
t
su(D)
Data In Stable
DB0–DB7
WR
CS
DACA/DACB
1.3 V
1.3 V
3.5 V
0.3 V
3.5 V
3.5 V
3.5 V
0.3 V
0.3 V
0.3 V
For all input signals, tr = tf = 5 ns (10% to 90% points).
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
Figure 1. Setup and Hold Times
TLC7628C, TLC7628E, TLC7628I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS063A – APRIL 1989 – REVISED MA Y 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant and 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and bipolar
operation are summarized in Tables 2 and 3, respectively.
17
DGND
5
16
15
6
7
14
V
DD
Input
Buffer
Control
Logic
WR
CS
DACB
DACA
/
DB7
DBO
V
I(B)
±10 V
R3 (see Note A)
REFB
8
8
88
REFA
RFBA
OUTA
AGND
AGND
OUTB
RFBB
C1 (see Note B)
A1
R4 (see Note A)
C2 (see Note B)
AGND
A3
V
OA
R2 (see Note A)
R1 (see Note A)
±10 V
V
I(A)
+
–
+
–
V
OB
RECOMMENDED TRIM
RESISTOR VALUES
R1, R3
R2, R4
500 Ω
150 Ω
Latch
DACA
Latch
DACB
NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment with
digital input of 255.
B. C1 and C2 phase compensation capacitors (10 pF to 15 pF) are required when using high-speed amplifiers to prevent ringing or
oscillation.
Figure 2. Unipolar Operation (2-Quadrant Multiplication)
TLC7628C, TLC7628E, TLC7628I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS063A – APRIL 1989 – REVISED MA Y 1995
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
8
17
DGND
5
16
15
6
7
14
V
DD
WR
CS
DACB
DACA
/
DB7
DBO
V
I(B)
±10 V
R3 (see Note A)
REFB
8
88
REFA RFBA
OUTA
AGND
OUTB
RFBA
C1(see Note C)
A1
R4 (see Note A)
C2
(see Note C)
AGND
A3
5 kΩ
R12
R10
20 kΩ
(see Note B)
(see
Note B)
R9
10 kΩ
R8
20 kΩ
A4
V
OB
(see
Note B)
5 kΩ
R11
10 kΩ
R7
A2
V
OA
20 kΩ
R5
20 kΩ
R6 (see Note B)
R2 (see Note A)
R1 (see Note A)
±10 V
V
I(A)
+
–
+
–
+
–
+
–
RECOMMENDED TRIM
RESISTOR VALUES
R1, R3
R2, R4
500 Ω
150 Ω
Control
Logic
Input
Buffer
Latch
DACA
Latch
DACB
NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Adjust R1 for VOA = 0 V with
code 10000000 in DACA latch. Adjust R3 for VOB = 0 V with 10000000 in DACB latch.
B. Matching and tracking are essential for resistor pairs R6, R7, R9, and R10.
C. C1 and C2 phase compensation capacitors (10 pF to 15 pF) may be required if A1 and A3 are high-speed amplifiers.
Figure 3. Bipolar Operation (4-Quadrant Operation)
A + 1
A
A8–A15
CPU
8051
WR
ALE
TLC7628
DACA/
DACB
CS
WR
DB0
DB7
AD0–AD7
Data Bus
Address Bus
Latch
Address
Decode
Logic
NOTE D: A = decoded address for TLC7628 DACA
A + 1 = decoded address for TLC7628 DACB
Figure 4. TLC7628 — Intel 8051 Interface
TLC7628C, TLC7628E, TLC7628I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS063A – APRIL 1989 – REVISED MA Y 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
φ 2
Address
Decoder
Logic
Address Bus
Data BusD0–D7
DB7
DB0
WR
CS
DACA/DACB
TLC7628
VMA
CPU
6800
A8–A15
A
A + 1
NOTE D: A = decoded address for TLC7628 DACA
A + 1 = decoded address for TLC7628 DACB
Figure 5. TLC7628 – 6800 Interface
voltage-mode operation
The current-multiplying DAC in these devices can be operated in a voltage mode. In the voltage mode, a fixed
voltage is placed on the current output terminal. The analog output voltage is then available at the reference
voltage terminal. An example of a current-multiplying DAC operating in voltage mode is shown in Figure 6. The
relationship between the fixed input voltage and the analog output voltage is given by the following equation:
Analog output voltage = fixed input voltage (D/256)
where D = the digital input. In voltage-mode operation, these devices meet the following specification:
LINEARITY ERROR TEST CONDITIONS MIN MAX UNIT
Analog output voltage for REFA, REFB VDD = 12 V, OUTA or OUTB at 5 V, TA = 25°C 1 LSB
2R 2R 2R
“0” “1”
2R
RRR
R
OUT (Fixed input voltage)
AGND
REF
(Analog output voltage)
Figure 6. Current-Multiplying DAC Operating in Voltage Mode
TLC7628C, TLC7628E, TLC7628I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS063A – APRIL 1989 – REVISED MA Y 1995
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
These devices contain two, identical, 8-bit, multiplying DACs: DACA and DACB. Each DAC consists of an
inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched between
the DAC output and AGND, thus maintaining a constant current in each ladder leg independent of the switch
state. Most applications require only the addition of an external operational amplifier and voltage reference. A
simplified D/A circuit for DACA or DACB with all digital inputs low is shown in Figure 7.
Figure 8 shows the DACA or DACB equivalent circuit. Both DACs share the analog ground terminal 1 (AGND).
With all digital inputs high, the reference current flows to OUTA. A small leakage current (I
Ikg
) flows across
internal junctions, and as with most semiconductor devices, doubles every 10°C. The C
o
is caused by the
parallel combination of the NMOS switches and has a value that depends on the number of switches connected
to the output. The range of C
o
is 25 pF to 60 pF maximum. The equivalent output resistance (ro) varies with the
input code from 0.8R to 3R where R is the nominal value of the ladder resistor in the R-2R network.
These devices interface to a microprocessor through the data bus, CS
, WR, and DACA/DACB control signals.
When CS
and WR are both low, the analog output on these devices, specified by the DACA /DACB control line,
responds to the activity on the DB0–DB7 data bus inputs. In this mode, the input latches are transparent and
input data directly affects the analog output. When either the CS
signal or WR signal goes high, the data on the
DB0–DB7 inputs is latched until the CS
and WR signals go low again. When CS is high, the data inputs are
disabled, regardless of the state of the WR
signal.
The digital inputs of these devices provide TTL compatibility when operated from a supply voltage of 10.8 V to
15.75 V.
DACA Data Latches and Drivers
REF
AGND
OUT
RFB
R
RRR
2R
2R
S8
2R
S3
2R
S2
S1
2R
Figure 7. Simplified Functional Circuit for DACA or DACB
R
REF
OUTA
RFB
R
COUT
1/256
Latch A or Latch B Loaded With 11111111
I
lkg
AGND
Figure 8. TLC7628 Equivalent Circuit for DACA or DACB
TLC7628C, TLC7628E, TLC7628I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS
SLAS063A – APRIL 1989 – REVISED MA Y 1995
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 1. Mode Selection Table
DACA/DACB CS WR DACA DACB
L
H
X
X
L
L
H
X
L
L
X
H
Write
Hold
Hold
Hold
Hold
Write
Hold
Hold
L = low level, H = high level, X = don’t care
Table 2. Unipolar Binary Code Table 3. Bipolar (Offset Binary) Code
DAC LATCH CONTENTS
(see Note 7)
ANALOG OUTPUT
DAC LATCH CONTENTS
(see Note 8)
ANALOG OUTPUT
MSB LSB MSB LSB
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
–VI (255/256)
–VI (129/256)
–VI (128/256) = –Vi/2
–VI (127/256)
–VI (1/256)
–VI (0/256) = 0
1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
VI (127/128)
VI (1/128)
0 V
–VI (1/128)
–VI (127/128)
–VI (128/128)
NOTES: 7. 1 LSB = (2 – 8)V
I
8. 1 LSB = (2 – 7)V
I
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1998, Texas Instruments Incorporated
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