Datasheet TLC7528EN, TLC7528EDWR, TLC7528EDW, TLC7528CN, TLC7528CFNR Datasheet (Texas Instruments)

TLC7528C, TLC7528E, TLC7528I

DUAL 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Easily Interfaced to Microprocessors

D

On-Chip Data Latches

D

Monotonic Over the Entire A/D Conversion
Range

D

Interchangeable With Analog Devices
AD7528 and PMI PM-7528

D

Fast Control Signaling for Digital Signal
Processor (DSP) Applications Including
Interface With TMS320

D

Voltage-Mode Operation

D

CMOS T echnology

KEY PERFORMANCE SPECIFICATIONS

Resolution
Linearity Error
Power Dissipation at VDD = 5 V
Settling Time at VDD = 5 V
Propagation Delay Time at VDD = 5 V

8 bits

1/2 LSB

20 mW
100 ns

80 ns

description

The TLC7528C, TLC7528E, and TLC7528I are
dual, 8-bit, digital-to-analog converters designed
with separate on-chip data latches and feature
exceptionally close DAC-to-DAC matching. Data
is transferred to either of the two DAC data latches
through a common, 8-bit, input port. Control input
DACA

/DACB determines which DAC is to be
loaded. The load cycle of these devices is similar
to the write cycle of a random-access memory , allowing easy interface to most popular microprocessor buses
and output ports. Segmenting the high-order bits minimizes glitches during changes in the most significant bits,
where glitch impulse is typically the strongest.

These devices operate from a 5-V to 15-V power supply and dissipates less than 15 mW (typical). The 2- or
4-quadrant multiplying makes these devices a sound choice for many microprocessor-controlled gain-setting
and signal-control applications. It can be operated in voltage mode, which produces a voltage output rather than
a current output. Refer to the typical application information in this data sheet.

The TLC7528C is characterized for operation from 0°C to 70°C. The TLC7528I is characterized for operation
from –25°C to 85°C. The TLC7528E is characterized for operation from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

T

A

SMALL OUTLINE

(DW)

CHIP CARRIER

(FN)

PLASTIC DIP

(N)

0°C to 70°C TLC7528CDW TLC7528CFN TLC7528CN
–25°C to 85°C TLC7528IDW TLC7528IFN TLC7528IN
–40°C to 85°C TLC7528EDW TLC7528EFN TLC7528EN

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

AGND

OUTA
RFBA

REFA

DGND

DACA

/DACB

(MSB) DB7

DB6
DB5
DB4

OUTB
RFBB
REFB
V

DD

WR
CS
DB0 (LSB)
DB1
DB2
DB3

DW OR N PACKAGE

(TOP VIEW)

3212019

910111213

4
5
6
7
8

18
17
16
15
14

REFB
V

DD

WR
CS
DB0 (LSB)

REFA

DGND

DACA/DACB

(MSB) DB7

DB6

FN PACKAGE

(TOP VIEW)

RFBA

OUTA

AGND

DB2

DB1

OUTB

RFBB

DB5

DB4

DB3

TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

8

8

8

8

DACA

/DACB

REFB

18

OUTB

20

RFBB

19

AGND

1

OUTA

2

RFBA

3

REFA

4

Input

Buffer

Logic

Control

DB0

DB7

CS

WR

15

16

6

Data

Inputs

7

8

9

10

11

12

13

14

DACA

DACB

Latch B

Latch A

operating sequence

t

h(DAC)

t

h(CS)

t

su(CS)

t

su(DAC

)

t

w(WR)

t

h(D)

t

su(D)

Data In Stable

DB0–DB7

WR

CS

DACA/DACB

TLC7528C, TLC7528E, TLC7528I

DUAL 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VDD (to AGND or DGND) –0.3 V to 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage between AGND and DGND ±V

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (to DGND) –0.3 V to VDD + 0.3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference voltage, V

refA

or V

refB

(to AGND) ±25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Feedback voltage V

RFBA

or V

RFBB

(to AGND) ±25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage (voltage mode out A, out B to AGND) –0.3 V to VDD + 0.3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage, VOA or VOB (to AGND) ±25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak input current 10 µA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLC7528C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC7528I –25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC7528E –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 10 seconds, TC: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package 260°C. . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

VDD = 4.75 V to 5.25 V VDD = 14.5 V to 15.5 V

MIN NOM MAX MIN NOM MAX

UNIT

Reference voltage, V

refA

or V

refB

±10 ±10 V

High-level input voltage, V

IH

2.4 13.5 V

Low-level input voltage, V

IL

0.8 1.5 V

CS setup time, t

su(CS)

50 50 ns

CS hold time, t

h(CS)

0 0 ns

DAC select setup time, t

su(DAC)

50 50 ns

DAC select hold time, t

h(DAC)

10 10 ns

Data bus input setup time t

su(D)

25 25 ns

Data bus input hold time t

h(D)

10 10 ns

Pulse duration, WR low, t

w(WR)

50 50 ns

TLC7628C 0 70 0 70

Operating free-air temperature, T

A

TLC7628I –25 85 –25 85

°C

TLC7628E –40 85 –40 85

TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range,
V

refA

= V

refB

= 10 V, VOA and VOB at 0 V (unless otherwise noted)

VDD = 5 V VDD = 15 V

PARAMETER

TEST CONDITIONS

MIN TYP†MAX MIN TYP†MAX

UNIT

I

IH

High-level input current VI = V

DD

10 10 µA

I

IL

Low-level input current VI = 0 5 12 –10 5 12 –10 µA
Reference input impedance

REFA or REFB to AGND

20 20 kΩ

p

OUTA

DAC data latch loaded with
00000000, V

refA

= ±10 V

±400 ±200

I

Ikg

Output leakage current

OUTB

DAC data latch loaded with
00000000, V

refB

= ±10 V

±400 ±200

nA

Input resistance match
(REFA to REFB)

±1% ±1%

DC supply sensitivity, ∆gain/∆V

DD

∆VDD = ±10% 0.04 0.02 %/%

I

DD

Supply current (quiescent)

All digital inputs at VIHmin or
VILmax

2 2 mA

I

DD

Supply current (standby) All digital inputs at 0 V or V

DD

0.5 0.5 mA

DB0–DB7 10 10 pF

C

i

Input capacitance

WR

, CS,

DACA

/DACB

15 15 pF

p

p

DAC data latches loaded with
00000000

50 50

p

CoOutput capacitance (OUTA, OUTB)

DAC data latches loaded with
11111111

120 120

pF

†

All typical values are at TA = 25°C.

TLC7528C, TLC7528E, TLC7528I

DUAL 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics over recommended operating free-air temperature range,
V

refA

= V

refB

= 10 V, VOA and VOB at 0 V (unless otherwise noted)

VDD = 5 V VDD = 15 V

PARAMETER

TEST CONDITIONS

MIN TYP MAX MIN TYP MAX

UNIT

Linearity error ±1/2 ±1/2 LSB
Settling time (to 1/2 LSB) See Note 1 100 100 ns
Gain error See Note 2 2.5 2.5 LSB

REFA to OUTA

–65 –65

AC feedthrough

REFB to OUTB

See Note 3

–65 –65

dB

Temperature coefficient of gain See Note 4 0.007 0.0035 %FSR/°C
Propagation delay (from digital input to

90% of final analog output current)

See Note 5 80 80 ns

Channel-to-channel

REFA to OUTB See Note 6 77 77

isolation

REFB to OUTA See Note 7 77 77

dB

Digital-to-analog glitch impulse area

Measured for code transition
from 00000000 to 11111111,
TA = 25°C

160 440 nV•s

Digital crosstalk

Measured for code transition
from 00000000 to 11111111,
TA = 25°C

30 60 nV•s

Harmonic distortion Vi = 6 V, f = 1 kHz, TA = 25°C –85 –85 dB

NOTES: 1. OUTA, OUTB load = 100 Ω, C

ext

= 13 pF; WR and CS at 0 V; DB0–DB7 at 0 V to VDD or VDD to 0 V.

2. Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = V

ref

– 1 LSB.

3. V

ref

= 20 V peak-to-peak, 100-kHz sine wave; DAC data latches loaded with 00000000.

4. Temperature coefficient of gain measured from 0°C to 25°C or from 25°C to 70°C.

5. V

refA

= V

refB

= 10 V; OUTA/OUTB load = 100 Ω, C

ext

= 13 pF; WR

and CS at 0 V; DB0–DB7 at 0 V to VDD or VDD to 0 V.

6. Both DAC latches loaded with 11111111; V

refA

= 20 V peak-to-peak, 100-kHz sine wave; V

refB

= 0; TA = 25°C.

7. Both DAC latches loaded with 11111111; V

refB

= 20 V peak-to-peak, 100-kHz sine wave; V

refA

= 0; TA = 25°C.

PRINCIPLES OF OPERATION

These devices contain two identical, 8-bit-multiplying D/A converters, DACA and DACB. Each DAC consists
of an inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched
between DAC output and AGND, thus maintaining a constant current in each ladder leg independent of the
switch state. Most applications require only the addition of an external operational amplifier and voltage
reference. A simplified D/A circuit for DACA with all digital inputs low is shown in Figure 1.

Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for DACB. Both DACs
share the analog ground terminal 1 (AGND). With all digital inputs high, the entire reference current flows to
OUT A. A small leakage current (I

Ikg

) flows across internal junctions, and as with most semiconductor devices,

doubles every 10°C. C

o

is due to the parallel combination of the NMOS switches and has a value that depends
on the number of switches connected to the output. The range of Co is 50 pF to 120 pF maximum. The equivalent
output resistance (ro) varies with the input code from 0.8R to 3R where R is the nominal value of the ladder
resistor in the R-2R network.

These devices interface to a microprocessor through the data bus, CS, WR, and DACA/DACB control signals.
When CS and WR are both low, the TLC7528 analog output, specified by the DACA/DACB control line,
responds to the activity on the DB0–DB7 data bus inputs. In this mode, the input latches are transparent and
input data directly affects the analog output. When either the CS signal or WR signal goes high, the data on the
DB0–DB7 inputs is latched until the CS

and WR signals go low again. When CS is high, the data inputs are

disabled regardless of the state of the WR signal.

TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

The digital inputs of these devices provide TTL compatibility when operated from a supply voltage of 5 V . These
devices can operate with any supply voltage in the range from 5 V to 15 V; however, input logic levels are not
TTL compatible above 5 V.

DACA Data Latches and Drivers

REFA

AGND

OUTA

RFBA

R

FB

RRR

2R

2R

S8

2R

S3

2R

S2

S1

2R

Figure 1. Simplified Functional Circuit for DACA

R

I

256

OUTA

RFBA

R

FB

C

OUT

I

Ikg

AGND

REFA

Figure 2. TLC7528 Equivalent Circuit, DACA Latch Loaded With 11111111

MODE SELECTION TABLE

DACA

/DACB CS WR DACA DACB

L
H
X
X

L
L
H
X

L
L
X
H

Write

Hold
Hold
Hold

Hold

Write

Hold
Hold

L = low level, H = high level, X = don’t care

TLC7528C, TLC7528E, TLC7528I

DUAL 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant and 4-quadrant multiplication are shown in Figures 3 and 4. T ables 1 and 2 summarize input coding
for unipolar and bipolar operation.

DGND

V

OB

V

OA

V

I(B)

±10 V

R3 (see Note A)

R1 (see Note A)

AGND

+

–

C1
(see Note B)

C2
(see Note B)

R2 (see Note A)

R4 (see Note A)

+

–

AGND

OUTB

RFBB

AGND

OUTA

5

V

DD

17

7

14

DACA

/DACB

DB0

DB7

Input

Buffer

8

8

8

8

REFB

RFBA

REFA

Latch

Control

Logic

CS

WR

16

15

6

RECOMMENDED TRIM

RESISTOR VALUES

R1, R3
R2, R4

500 Ω
150 Ω

DACA

DACB

Latch

V

I(A)

±10 V

NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment with

digital input of 255.

B. C1 and C2 phase compensation capacitors (10 pF to 15 pF) are required when using high-speed amplifiers to prevent ringing or

oscillation.

Figure 3. Unipolar Operation (2-Quadrant Multiplication)

TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

+

–

R11

5 kΩ

A2

V

OA

DACB

R6

20 kΩ

(see Note B)

V

OB

+

–

AGND

A1

DGND

A4

R3

(see Note A)

R1

(see Note A)

AGND

+

–

C1
(see Note C)

C2
(see Note C)

R2 (see Note A)

R4 (see Note A)

+

–

AGND

OUTB

RFBB

AGND

OUTA

5

V

DD

17

7

14

DACA

/

DACB

DB0

DB7

88

88

REFB

RFBA

DACA

CS

WR

16

15

6

A3

R10

20 kΩ

(see Note B)

Latch

Input

Buffer

Control

Logic

Latch

R8

20 kΩ

R7

10 kΩ

(see Note B)

R9

10 kΩ

(see Note B)

R11
5 kΩ

R5

20 kΩ

V

I(A)

±10 V

V

I(B)

±10 V

NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table in Figure 3 for recommended values. Adjust R1 for

VOA = 0 V with code 10000000 in DACA latch. Adjust R3 for VOB = 0 V with 10000000 in DACB latch.
B. Matching and tracking are essential for resistor pairs R6, R7, R9, and R10.
C. C1 and C2 phase compensation capacitors (10 pF to 15 pF) may be required if A1 and A3 are high-speed amplifiers.

Figure 4. Bipolar Operation (4-Quadrant Operation)

Table 1. Unipolar Binary Code Table 2. Bipolar (Offset Binary) Code

DAC LATCH CONTENTS

DAC LATCH CONTENTS

MSB LSB

†

ANALOG OUTPUT

MSB LSB

‡

ANALOG OUTPUT

1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0

–VI (255/256)
–VI (129/256)

–VI (128/256) = –Vi/2

–VI (127/256)

–VI (1/256)

–VI (0/256) = 0

1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0

VI (127/128)

VI (1/128)

0 V

–VI (1/128)
–VI (127/128)
–VI (128/128)

†

1 LSB = (2–8)V

I

‡

1 LSB = (2–7)V

I

TLC7528C, TLC7528E, TLC7528I

DUAL 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

microprocessor interface information

A + 1

A

A8–A15

CPU
8051

WR

ALE

TLC7528

DACA/DACB

CS

WR
DB0

DB7

AD0–AD7

Data Bus

Address Bus

Latch

Address

Decode

Logic

NOTE A: A = decoded address for TLC7528 DACA

A + 1 = decoded address for TLC7528 DACB

8

8

Figure 5. TLC7528 – Intel 8051 Interface

φ2

Address

Decode

Logic

Address Bus

Data Bus

AD0–AD7

DB7

DB0

WR

CS

DACA/DACB

TLC7528

VMA

CPU
6800

A8–A15

A

A + 1

NOTE A: A = decoded address for TLC7528 DACA

A + 1 = decoded address for TLC7528 DACB

8

8

Figure 6. TLC7528 – 6800 Interface

TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

WR

Address

Decode

Logic

Address Bus

Data Bus

D0–D7

DB7

DB0

WR

CS

DACA

/DACB

TLC7528

IORQ

CPU

Z80-A

A8–A15

A

A + 1

NOTE A: A = decoded address for TLC7528 DACA

A + 1 = decoded address for TLC7528 DACB

8

8

Figure 7. TLC7528 To Z-80A Interface

programmable window detector

The programmable window comparator shown in Figure 8 determines if voltage applied to the DAC feedback
resistors are within the limits programmed into the data latches of these devices. Input signal range depends
on the reference and polarity , that is, the test input range is 0 to –V

ref

. The DACA and DACB data latches are

programmed with the upper and lower test limits. A signal within the programmed limits drives the output high.

TLC7528C, TLC7528E, TLC7528I

DUAL 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

REFB

19

RFBB

OUTB

AGND

TLC7528

REFA

DB0–DB7

CS
WR

DACA

/DACB

DGND

V

ref

Data Inputs

4

5

18

6

16

15

14–7

Test Input

0 to –V

ref

RFBA

3

V

DD

17

OUTA 2

1

20

PASS/FAIL

Output

1 kΩ

V

CC

+

–

+

–

DACB

DACA

8

Figure 8. Digitally-Programmable Window Comparator (Upper- and Lower-Limit Tester)

digitally controlled signal attenuator

Figure 9 shows a TLC7528 configured as a two-channel programmable attenuator. Applications include stereo
audio and telephone signal level control. Table 3 shows input codes vs attenuation for a 0 to 15.5 dB range.

OutputA1

A2

VOB

V

DD

TLC7528

DGND

AGND

REFB

DACA/DACB

WR

CS

DB0–DB7

OUTA

RFBA

REFA

RFBB

OUTB

Data Bus

3
2

15
16
6

18
1
5

19

17

4

20

DACA

DACB

Attenuation dB = –20 log10 D/256, D = digital input code

8

14–7

VIA

Figure 9. Digitally Controlled Dual Telephone Attenuator

TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Table 3. Attenuation vs DACA, DACB Code

ATTN (dB) DAC INPUT CODE

CODE IN

DECIMAL

ATTN (dB) DAC INPUT CODE

CODE IN

DECIMAL

0 1 1 1 1 1 1 1 1 255 8.0 0 1 1 0 0 1 1 0 102

0.5 1 1 1 1 0 0 1 0 242 8.5 0 1 1 0 0 0 0 0 96

1.0 1 1 1 0 0 1 0 0 228 9.0 0 1 0 1 1 0 1 1 91

1.5 1 1 0 1 0 1 1 1 215 9.5 0 1 0 1 0 1 1 0 86

2.0 1 1 0 0 1 0 1 1 203 10.0 0 1 0 1 0 0 0 1 81

2.5 1 1 0 0 0 0 0 0 192 10.5 0 1 0 0 1 1 0 0 76

3.0 1 0 1 1 0 1 0 1 181 11.0 0 1 0 0 1 0 0 0 72

3.5 1 0 1 0 1 0 1 1 171 11.5 0 1 0 0 0 1 0 0 68

4.0 1 0 1 0 0 0 1 0 162 12.0 0 1 0 0 0 0 0 0 64

4.5 1 0 0 1 1 0 0 0 152 12.5 0 0 1 1 1 1 0 1 61

5.0 1 0 0 1 1 1 1 1 144 13.0 0 0 1 1 1 0 0 1 57

5.5 1 0 0 0 1 0 0 0 136 13.5 0 0 1 1 0 1 1 0 54

6.0 1 0 0 0 0 0 0 0 128 14.0 0 0 1 1 0 0 1 1 51

6.5 0 1 1 1 1 0 0 1 121 14.5 0 0 1 1 0 0 0 0 48

7.0 0 1 1 1 0 0 1 0 114 15.0 0 0 1 0 1 1 1 0 46

7.5 0 1 1 0 1 1 0 0 108 15.5 0 0 1 0 1 0 1 1 43

programmable state-variable filter

This programmable state-variable or universal filter configuration provides low-pass, high-pass, and bandpass
outputs, and is suitable for applications requiring microprocessor control of filter parameters.

As shown in Figure 10, DACA1 and DACB1 control the gain and Q of the filter while DACA2 and DACB2 control
the cutoff frequency. Both halves of the DACA2 and DACB2 must track accurately in order for the
cutoff-frequency equation to be true. With the TLC7528, this is easy to achieve.

fc+

1

2pR1C1

The programmable range for the cutoff or center frequency is 0 to 15 kHz with a Q ranging from 0.3 to 4.5. This
defines the limits of the component values.

256 (DAC ladder resistance)

DAC digital code

TLC7528C, TLC7528E, TLC7528I

DUAL 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

Bandpass Out

High Pass
Out

30 kΩ

47 pF

C3

R5

R4

R3

Low Pass Out

1000 pF

C2

C1

1000 pF

+

–

DACA

(R1)

(R2)

DACB

TLC7528

+

–

OUTA

RFBA

AGND

OUTB

REFB

RFBB

2

3
1

20
19

18

REFA

V

DD

CS
WR
DGND

DACA/DACB

DACA2 and DACB2

A3

+

–

A2

A1

DACA1 AND DACB1

Data In

V

I

DACA

/DACB

6

DGND

5

WR

16

CS

15

DB0–DB7

14–7

17

V

DD

REFA

4

18

19

20

1

3

2

RFBB

REFB

OUTB

AGND

RFBA

OUTA

+

–

TLC7528

DACB

(RF)

(RS)

DACA

Q

+

R

3

R

4

·

R

F

R

fb(DACB1)

C1 = C2, R1 = R2, R4 = R

5

G+–

R

F

R

S

30 kΩ

10 kΩ

A4

14–7

DB0–DB7

8

8

Data In

6

5

16

15

17

4

Rfbis the internal resistor connected between OUTB and RFBB

Where:

Circuit Equations:

NOTES: A. Op-amps A1, A2, A3, and A4 are TL287.

B. CS

compensates for the op-amp gain-bandwidth limitations.

C. DAC equivalent resistance equals

Figure 10. Digitally Controlled State-Variable Filter

TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

voltage-mode operation

It is possible to operate the current multiplying D/A converter of these devices in a voltage mode. In the voltage
mode, a fixed voltage is placed on the current output terminal. The analog output voltage is then available at
the reference voltage terminal. Figure 1 1 is an example of a current multiplying D/A, that operates in the voltage
mode.

2R 2R 2R

“0” “1”

2R

RRR

R

Out (Fixed Input Voltage)

AGND

REF

(Analog Output Voltage)

Figure 11. Voltage-Mode Operation

The following equation shows the relationship between the fixed input voltage and the analog output voltage:

V

O

= VI (D/256)

Where:

VO = analog output voltage
VI = fixed input voltage (must not be forced below 0 V.)
D = digital input code converted to decimal

In voltage-mode operation, these devices meet the following specification:

PARAMETER TEST CONDITIONS MIN MAX UNIT

Linearity error at REFA or REFB VDD = 5 V, OUTA or OUTB at 2.5 V, TA = 25°C 1 LSB

TLC7528C, TLC7528E, TLC7528I

DUAL 8-BIT MULTIPLYING

DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

16 PINS SHOWN

4040000/D 01/00

Seating Plane

0.400 (10,15)

0.419 (10,65)

0.104 (2,65) MAX

1

0.012 (0,30)

0.004 (0,10)

A

8

16

0.020 (0,51)

0.014 (0,35)

0.291 (7,39)

0.299 (7,59)

9

0.010 (0,25)

0.050 (1,27)

0.016 (0,40)

(15,24)

(15,49)

PINS **

0.010 (0,25) NOM

A MAX

DIM

A MIN

Gage Plane

20

0.500

(12,70)

(12,95)

0.510

(10,16)

(10,41)

0.400

0.410

16

0.600

24

0.610

(17,78)

28

0.700

(18,03)

0.710

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013

TLC7528C, TLC7528E, TLC7528I
DUAL 8-BIT MULTIPLYING
DIGITAL-TO-ANALOG CONVERTERS

SLAS062B – JANUARY 1987 – REVISED MARCH 2000

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

0.325 (8,26)

0.300 (7,62)

0.010 (0,25) NOM

Gauge Plane

0.015 (0,38)

0.430 (10,92) MAX

20

0.975

(24,77)

0.940

(23,88)

18

0.920

0.850

14

0.775

0.745

(19,69)

(18,92)

16

0.775

(19,69)

(18,92)

0.745

A MIN

DIM

A MAX

PINS **

(23,37)

(21,59)

Seating Plane

14/18 PIN ONL Y

4040049/D 02/00

9

8

0.070 (1,78) MAX

A

0.035 (0,89) MAX

0.020 (0,51) MIN

16

1

0.015 (0,38)

0.021 (0,53)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.240 (6,10)

0.260 (6,60)

M

0.010 (0,25)

0.100 (2,54)

16 PINS SHOWN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001).

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