Texas Instruments TLC7226IN, TLC7226IDWR, TLC7226IDW, TLC7226CN, TLC7226CDW Datasheet

TLC7226C, TLC7226E

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS060B – JANUARY 1995 – REVISED AUGUST 1996

features

D

Four 8-Bit D/A Converters

D

Microprocessor Compatible

D

TTL/CMOS Compatible

D

Single Supply Operation Possible

D

CMOS Technology

applications

D

Process Control

D

Automatic Test Equipment

D

Automatic Calibration of Large System
Parameters, e.g. Gain/Offset

DW OR N PACKAGE

(TOP VIEW)

OUTB

OUTA

AGND
DGND

V

SS

REF

DB7
DB6
DB5
DB4

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

OUTC
OUTD
V

DD

A0
A1
WR
DB0
DB1
DB2
DB3

description

The TLC7226C and TLC7226E consist of four 8-bit voltage-output digital-to-analog converters (DACs) with
output buffer amplifiers and interface logic on a single monolithic chip.

Separate on-chip latches are provided for each of the four DACs. Data is transferred into one of these data
latches through a common 8-bit TTL/CMOS-compatible 5-V input port. Control inputs A0 and A1 determine
which DAC is loaded when WR

Each DAC includes an output buffer amplifier capable of sourcing up to 5 mA of output current.

goes low. The control logic is speed compatible with most 8-bit microprocessors.

The TLC7226 performance is specified for input reference voltages from 2 V to V

– 4 V with dual supplies.

DD

The voltage mode configuration of the DACs allows the TLC7226 to be operated from a single power supply
rail at a reference of 10 V.

The TLC7226 is fabricated in a LinBiCMOS process that has been specifically developed to allow high-speed
digital logic circuits and precision analog circuits to be integrated on the same chip. The TLC7226 has a common
8-bit data bus with individual DAC latches. This provides a versatile control architecture for simple interface to
microprocessors. All latch-enable signals are level triggered.

Combining four DACs, four operational amplifiers, and interface logic into either a 0.3-inch wide, 20-terminal
dual-in-line IC (DIP) or a small 20-terminal small-outline IC (SOIC) allows a dramatic reduction in board space
requirements and offers increased reliability in systems using multiple converters. The pinout is aimed at
optimizing board layout with all of the analog inputs and outputs at one end of the package and all of the digital
inputs at the other.

The TLC7226C is characterized for operation from 0°C to 70°C. The TLC7226E is characterized for operation
from –25°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

T

A

0°C to 70°C TLC7226CDW TLC7226CN

–25°C to 85°C TLC7226EDW TLC7226EN

SMALL OUTLINE

(DW)

PLASTIC DIP

(N)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinBiCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1996, Texas Instruments Incorporated

1

TLC7226C, TLC7226E
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS060B – JANUARY 1995 – REVISED AUGUST 1996

functional block diagram

4

REF

8

Latch

A

8

DAC A

_

+

2

OUTA

DB0–DB7

WR

A0
A1

schematic of outputs

7–14

15
17
16

8

Control

Logic

8

Latch

B

8

Latch

C

8

Latch

D

EQUIVALENT ANALOG OUTPUT

V

DD

8

8

8

DAC B

DAC C

DAC D

_
+

_

+

_
+

1

20

19

OUTB

OUTC

OUTD

Output

450 µA

V

SS

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

TLC7226C, TLC7226E

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS060B – JANUARY 1995 – REVISED AUGUST 1996

Terminal Functions

TERMINAL

NAME NO.

AGND 5 Analog ground. AGND is the reference and return terminal for the analog signals and supply.
A0, A1 16, 17 I DAC select inputs. The combination of high or low levels select either DACA, DACB, DACC, or DACD.
DGND 6 Digital ground. DGND is the reference and return terminal for the digital signals and supply.
DB0–DB7 7–14 I Digital DAC data inputs. DB0–DB7 are the input digital data used for conversion.
OUTA 2 O DACA output. OUTA is the analog output of DACA.
OUTB 1 O DACB output. OUTB is the analog output of DACB.
OUTC 20 O DACC output. OUTC is the analog output of DACC.
OUTD 19 O DACD output. OUTD is the analog output of DACD.
REF 4 I Voltage reference input. The voltage level on REF determines the full scale analog output.
V

DD

V

SS

WR 15 I Write input. WR selects DAC transparency or latch mode. The selected input latch is transparent when WR

†

Terminal numbers shown are for the DW and N packages.

†

18 Positive supply voltage input terminal

3 Negative supply voltage input terminal

is low.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TLC7226C, TLC7226E

Operating free-air temperature, T

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS060B – JANUARY 1995 – REVISED AUGUST 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Supply voltage range, V

: AGND or DGND –0.3 V to 17 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

SS

‡

V

–0.3 V to 24 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SS

: AGND or DGND –7 V to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Voltage range between AGND and DGND –17 V to 17 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V
Reference voltage range: V

Output voltage range, V
Continuous total power dissipation at (or below) T
Operating free-air temperature range, T

(to DGND) –0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

O

(to AGND) –0.3 V to V

ref

V

(to VSS) –0.3 V to 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ref

(to AGND) (see Note 1) VSS to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

= 25°C (see Note 2) 500 mW. . . . . . . . . . . . . . . . . . . . . . .

: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

A

DD

DD

E suffix –25°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N packages 260°C. . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡

The VSS terminal is connected to the substrate and must be tied to the most negative supply voltage applied to the device.

NOTES: 1. Output voltages may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically sh ort circuit

current to AGND is 60 mA.

2. For operation above TA = 75°C, derate linearly at the rate of 2 mW/°C.

recommended operating conditions

MIN MAX UNIT

Supply voltage, V
Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Reference voltage, V
Load resistance, R
Setup time, address valid before WR↓, t
Setup time, data valid before WR↑, t
Hold time, address valid before WR↑, t
Hold time, data valid before WR↑, t
Pulse duration, WR low, tw (see Figure 6)

p

DD
SS

IH

IL

ref

L

su(DW)

h(AW)

h(DW)

p

A

(see Figure 6) VDD = 11.4 V to 16.5 V 0 ns

su(AW)

(see Figure 6)

(see Figure 6)

(see Figure 6)

VDD = 11.4 V to 16.5 V 45 ns
VDD = 11.4 V to 16.5 V 0 ns
VDD = 11.4 V to 16.5 V 10 ns
VDD = 11.4 V to 16.5 V 50 ns
C suffix 0 70 °C

E suffix –25 85 °C

11.4 16.5 V

–5.5 0 V

2 V

0.8 V
0 VDD–4 V
2 kΩ

4

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REF input

Settling time to 1/2 LSB

V

V

s

V

±5%

V

V

Temperature coefficient of gain

Settling time to 1/2 LSB

s

Temperature coefficient of gain

TLC7226C, TLC7226E

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS060B – JANUARY 1995 – REVISED AUGUST 1996

electrical characteristics over recommended operating free-air temperature range

dual power supply over recommended power supply and reference voltage ranges, AGND = DGND = 0 V
(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

I

I

DD

I

SS

r

i(ref)

C

i

operating characteristics over recommended operating free-air temperature range

dual power supply over recommended power supply and reference voltage ranges, AGND = DGND = 0 V
(unless otherwise noted)

Slew rate 2.5 V•µs

Resolution 8 bits
Total unadjusted error ±2 LSB
Linearity error Differential/integral
Full-scale error
Gain error ±0.25 LSB

Zero-code error ±20 ±80 mV
Digital crosstalk glitch impulse area V

Input current, digital VI = 0 V or V
Supply current
Supply current VI = 0.8 V or 2.4 V, No load 4 10 mA

Reference input resistance 2 4 kΩ
Power supply sensitivity ∆VDD = ±5% 0.01 %/%

Input capacitance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

p

Digital inputs 8

Positive full scale
Negative full scale

Full scale VDD = 14 V to 16.5 V, V
Zero-code error ±50 µV/°C

VI = 0.8 V or 2.4 V,
VSS = – 5 V,

All 0s loaded 65
All 1s loaded 300

= 10

ref

DD

= 0 50 nV•s

ref

= 15 V

DD

VDD = 16.5 V,
No load

,

6 16 mA

= 10

ref

= 10 V ±20 ppm/°C

ref

±1 µA

pF

5

µ

7

±1 LSB
±2 LSB

single power supply , VDD = 14.25 V to 15.75 V , VSS = AGND = DGND = 0 V , V

Supply current, I
Slew rate 2 V•µs

Resolution 8 bits
Total unadjusted error ±2 LSB
Full-scale error ±2 LSB

p

Linearity error Differential ±1 LSB
Digital crosstalk-glitch impulse area 50 nV•s

DD

= 10 V (unless otherwise noted)

ref

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VI = 0.8 V or 2.4 V, No load 5 13 mA

Positive full scale 5
Negative full scale 20

Full scale VDD = 14 V to 16.5 V, V
Zero-code error ±50 µV/°C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

= 10 V ±20 ppm/°C

ref

µ

5

TLC7226C, TLC7226E
QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS060B – JANUARY 1995 – REVISED AUGUST 1996

PARAMETER MEASUREMENT INFORMATION

t

su(DW)

Data

Address

t

su(AW)

WR

NOTES: A. tr = tf = 20 ns over VDD range.

B. The timing measurement reference level is equal to VIH + V

divided by 2.

C. The selected input latch is transparent while WR

data during this time can cause erroneous outputs.

Figure 1. Write-Cycle Voltage Waveforms

t

w

t

h(DW)

t

h(AW)

is low. Invalid

V

0 V

V

0 V

V

0 V

DD

DD

DD

IL

6

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