Delay
x0
12−Bit Grayscale
PWM Control
DC Register
GS Register
DC EEPROM
Constant Current
Driver
LED Open Detection
Temperature
Error Flag
(TEF)
Max. OUTn
Current
Delay
x1
12−Bit Grayscale
PWM Control
DC Register
GS Register
DC EEPROM
Constant Current
Driver
LED Open Detection
Delay
x15
6−Bit Dot
12−Bit Grayscale
PWM Control
DC Register
GS Register
DC EEPROM
Constant Current
Driver
LED Open Detection
OUT0
OUT1
OUT15
SOUT
SINSCLK
IREF
XERR
XLAT
GSCLK
BLANK
DCPRG
DCPRG
DCPRG
VPRG
VPRG
VPRG
GNDVCC
VPRG
Input
Shift
Register
Input
Shift
Register
VPRG
110
2312
191180
9590
116
5
VPRG
0
0
95
96
191
LED Open
Detection
(LOD)
5
9590
6 11
DCPRG
0
192
96
0
1
01 0
1
01
GS Counter
CNT
CNT
CNT
CNT
96
96
Status
Information:
LOD,
TED,
DC DATA
192
0
191
1
0
0
1
V
REF
=1.24 V
Correction
6−Bit Dot
Correction
6−Bit Dot
Correction
01
Blank
SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005
16 CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL
FEATURES APPLICATIONS
• 16 Channels
• 12 bit (4096 Steps) Grayscale PWM Control
• Dot Correction
– 6 bit (64 Steps)
– Storable in Integrated EEPROM
• Drive Capability (Constant Current Sink)
– 0 mA to 60 mA (V
– 0 mA to 120 mA (V
< 3.6 V)
CC
> 3.6 V)
CC
• LED Power Supply Voltage up to 17 V
• V
= 3 V to 5.5 V
CC
• Serial Data Interface, SPI comp.
• Controlled In-Rush Current
• 30-MHz Data Transfer Rate
• CMOS Level I/O
• Error Information
– LOD: LED Open Detection
– TEF: Thermal Error Flag
• Monocolor, Multicolor, Fullcolor LED Displays
• LED Signboards
• Display Backlighting
• General, High-Current LED Drive
DESCRIPTION
The TLC5940 is a 16-channel constant-current sink
LED driver. Each channel has an individually adjustable 4096-step grayscale PWM brightness control
and a 64-step constant-current sink (dot correction).
The dot correction adjusts the brightness variations
between LED channels and other LED drivers. The
dot correction data is stored in an integrated
EEPROM. Both grayscale control and dot correction
are accessible via a serial interface. A single external
resistor sets the maximum current value of all 16
channels.
The TLC5940 features two error information circuits.
The LED open detection (LOD) indicates a broken or
disconnected LED at an output terminal. The thermal
error flag (TEF) indicates an overtemperature condition.
TLC5940
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2004–2005, Texas Instruments Incorporated
TLC5940
SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
T
A
PACKAGE
-40 ° C to 85 ° C 28-pin HTSSOP PowerPAD™ TLC5940PWP
-40 ° C to 85 ° C 32-pin 5 mm x 5 mm QFN TLC5940RHB
-40 ° C to 85 ° C 28-pin PDIP TLC5940NT
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com .
ABSOLUTE MAXIMUM RATINGS.
over operating free-air temperature range (unless otherwise noted)
V
Input voltage range
I
I
Output current (dc) 130 mA
O
V
Input voltage range V
I
V
Output voltage range
O
EEPROM program range V
EEPROM write cycles 50
ESD rating
T
Storage temperature range –55 ° C to 150 ° C
stg
T
Operating ambient temperature range –40 ° C to 85 ° C
A
Package thermal impedance
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) With PowerPAD soldered on PCB with 2 oz. trace of copper. See SLMA002 for further information.
(2)
VCC –0.3 V to 6 V
, V
(BLANK)
V
, V
(SOUT)
V
to V
(OUT0)
(PRG)
, V
(DCPRG)
(XERR)
(OUT15)
, V
(SCLK)
HBM (JEDEC JESD22-A114, Human Body Model) 2 kV
CBM (JEDEC JESD22-C101, Charged Device Model) 500 V
HTSSOP (PWP)
(3)
QFN (RHB) 35.9 ° C/W
(4)
PDIP (NP) 48 ° C/W
(1)
(1)
PART NUMBER
UNIT
(XLAT)
–0.3 V to V
–0.3 V to V
–0.3 V to 18 V
–0.3 V to 24 V
31.58 ° C/W
+0.3 V
CC
+0.3 V
CC
2
RECOMMENDED OPERATING CONDITIONS
DC CHARACTERISTICS
V
CC
V
O
V
IH
V
IL
I
OH
I
OL
I
OLC
V
(PRG)
T
A
AC CHARACTERISTICS V
f
(SCLK)
f
(GSCLK)
t
wh0
t
wh1
t
wh2
t
wh3
t
su0
t
su1
t
su2
t
su3
t
su4
t
su5
t
h0
t
h1
t
h2
t
h3
t
h4
t
h5
t
prog
Supply Voltage 3 5.5 V
Voltage applied to output (OUT0–OUT15) 17 V
High-level input voltage 0.8 V
Low-level input voltage GND 0.2 V
High-level output current V
Low-level output current V
Constant output current
EEPROM program voltage 20 22 23 V
Operating free-air temperature range -40 85 ° C
Data shift clock frequency SCLK 30 MHz
Grayscale clock frequency GSCLK 30 MHz
/t
SCLK pulse duration SCLK = H/L (see Figure 8 ) 16 ns
wl0
/t
GSCLK pulse duration GSCLK = H/L (see Figure 13 ) 16 ns
wl1
XLAT pulse duration XLAT = H (see Figure 11 ) 20 ns
BLANK pulse duration BLANK = H (see Figure 13 ) 20 ns
Setup time
Hold Time
= 5 V at SOUT –1 mA
CC
= 5 V at SOUT, XERR 1 mA
CC
OUT0 to OUT15, V
OUT0 to OUT15, V
= 3 V to 5.5 V, TA= –40 ° C to 85 ° C (unless otherwise noted)
CC
< 3.6 V 60 mA
CC
> 3.6 V 120 mA
CC
SIN–SCLK (see Figure 11 ) 10 ns
SCLK–XLAT (see Figure 11 ) 10 ns
VPRG–SCLK (see Figure 6 ) 10 ns
VPRG–XLAT (see Figure 6 ) 10 ns
BLANK–GSCLK (see Figure 13 ) 10 ns
VPRG–DCPRG 1 ms
SCLK–SIN (see Figure 11 ) 10 ns
XLA–SCLK (see Figure 11 ) 10 ns
SCLK–VPRG (see Figure 6 ) 10 ns
XLAT–VPRG (see Figure 6 ) 10 ns
BLANK–GSCLK (see Figure 13 ) 10 ns
DCPRG–VPRG 1 ms
Programming time for EEPROM 20 ms
TLC5940
SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005
MIN NOM MAX UNIT
CC
V
CC
CC
V
V
DISSIPATION RATINGS
PACKAGE
28-pin HTSSOP with
PowerPAD™
(1)
soldered
28-pin HTSSOP with PowerPAD™ un- 2026 mW 16.21 mW/ ° C 1296 mW 1053 mW
soldered
32-pin QFN
(1)
28-pin PDIP 2456 mW 19.65 mW/ ° C 1572 mW 1277 mW
(1) The PowerPAD is soldered to the PCB with a 2 oz. copper trace. See SLMA002 for further information.
POWER RATING DERATING FACTOR POWER RATING POWER RATING
TA< 25 ° C ABOVE TA= 25 ° C TA= 70 ° C TA= 85 ° C
3958 mW 31.67 mW/ ° C 2533 mW 2058 mW
3482 mW 27.86 mW/ ° C 2228 mW 1811 mW
3
TLC5940
SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005
ELECTRICAL CHARACTERISTICS
V
= 3 V to 5.5 V, TA= –40 ° C to 85 ° C (unless otherwise noted)
CC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
V
I
I
I
CC
I
O(LC)
I
lkg
∆ I
∆ I
∆ I
∆ I
∆ I
T
V
V
(1) Not tested. Specified by design
High-level output voltage IOH= -1 mA, SOUT VCC– 0.5 V
OH
Low-level output voltage IOL= 1 mA, SOUT 0.5 V
OL
VI= V
XLAT
Input current
VI= GND; VPRG –1 1
VI= VCC; VPRG 50
VI= 22 V; VPRG; DCPRG = V
No data transfer, all output OFF,
VO= 1 V, R
No data transfer, all output OFF,
Supply current mA
VO= 1 V, R
Data transfer 30 MHz, all output ON,
VO= 1 V, R
Data transfer 30 MHz, all output ON,
VO= 1 V, R
Constant output current All output ON, VO= 1 V, R
Leakage output current 0.1 µ A
All output OFF, VO= 15 V, R
OUT0 to OUT15
All output ON, VO= 1 V, R
OUT0 to OUT15, –20 ° C to 85 ° C
All output ON, VO= 1 V, R
Constant current error %
O(LC0)
OUT0 to OUT15
All output ON, VO= 1 V, R
OUT0 to OUT15, –20 ° C to 85 ° C
All output ON, VO= 1 V, R
V
CC
Constant current error ± 4 %
O(LC1)
Constant current error ± 4 %
O(LC2)
Device to device, Averaged current from OUT0 to –2
OUT15, R
Device to device, Averaged current from OUT0 to –2.7
OUT15, R
All output ON, VO= 1 V, R
Power supply rejection ratio,
O(LC3)
PSRR
OUT0 to OUT15
All output ON, VO= 1 V, R
OUT0 to OUT15
All output ON, VO= 1 V to 3 V, R
Load regulation
O(LC4)
OUT0 to OUT15
All output ON, VO= 1 V to 3 V, R
OUT0 to OUT15
Thermal error flag threshold Junction temperature
(TEF)
LED open detection threshold 0.3 0.4 V
(LED)
Reference voltage
(IREF)
output
R
I(REF)
or GND; BLANK, DCPRG, GSCLK, SCLK, SIN,
CC
= 10 k Ω
(IREF)
= 1.3 k Ω
(IREF)
= 1.3 k Ω
(IREF)
= 640 Ω
(IREF)
= 4.5 V to 5.5 V, OUT0 to OUT15
= 1920 Ω (20 mA) +0.4
(IREF)
= 480 Ω (80 mA) +2
(IREF)
(1)
CC
= 640 Ω 54 61 69 mA
(IREF)
= 640 Ω ,
(IREF)
= 640 Ω ,
(IREF)
= 640 Ω ,
(IREF)
= 320 Ω ,
(IREF)
= 320 Ω ,
(IREF)
= 640 Ω
(IREF)
= 320 Ω ,
(IREF)
= 640 Ω ,
(IREF)
= 320 Ω ,
(IREF)
–1 1
4 10 mA
0.9 6
5.2 12
16 25
30 60
± 1 ± 4
± 1 ± 8
± 1 ± 6
± 1 ± 8
± 1 ± 4 %/V
± 1 ± 6 %/V
± 2 ± 6 %/V
± 2 ± 8 %/V
150 170 ° C
= 640 Ω 1.20 1.24 1.28 V
µ A
4
SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005
SWITCHING CHARACTERISTICS
V
= 3 V to 5.5 V, TA= -40 ° C to 85 ° C (unless otherwise noted)
CC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
r0
Rise time ns
t
r1
t
f0
Fall time ns
t
f1
t
pd0
t
pd1
t
pd2
Propagation delay time
t
pd3
t
pd4
t
pd5
t
Output delay time OUTn–OUT(n+1) (see Figure 13 ) 20 30 ns
d
SOUT 16
OUTn, V
= 5 V, TA= 60 ° C, DCx = 3F 10 30
CC
SOUT 16
OUTn, V
= 5 V, TA= 60 ° C, DCx = 3F 10 30
CC
SCLK–SOUT (see Figure 11 ) 30 ns
DCPRG–OUT0 30 ns
BLANK–OUT0 (see Figure 13 ) 60 ns
OUTn - XERR (see Figure 13 ) 1000 ns
GSCLK–OUT0 (see Figure 13 ) 60 ns
XLAT–I
(dot correction) 1000 ns
OUT
TLC5940
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
BLANK
XLAT
SCLK
SIN
VPRG
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
VCC
IREF
DCPRG
GSCLK
SOUT
XERR
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
PWP PACKAGE
(TOP VIEW)
Thermal
PAD
THERMAL
PAD
GSCLK24
SOUT23
XERR22
OUT1521
OUT1420
OUT1319
OUT1218
OUT1117
OUT1016
OUT915
OUT814
NC13
NC12
OUT711
OUT610
OUT59
OUT4 8
OUT3 7
OUT2 6
OUT1 5
OUT0 4
VPRG 3
SIN 2
SCLK 1
DCPRG 25
IREF 26
VCC 27
NC 28
NC 29
GND 30
BLANK 31
XLAT 32
RHB PACKAGE
(TOP VIEW)
NC − No internal connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
17
16
15
22
21
20
19
26
25
24
23
28
27
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
GND
VCC
IREF
DCPRG
GSCLK
SOUT
XERR
OUT15
SCLK
XLAT
BLANK
OUT0
VPRG
SIN
NT PACKAGE
(TOP VIEW)
TLC5940
SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005
DEVICE INFORMATION
6
SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005
DEVICE INFORMATION (continued)
TERMINAL FUNCTION
TERMINAL
NAME
BLANK 23 2 31 I
DCPRG 19 26 25 I DC is connected to the DC register.
GND 22 1 30 G Ground
GSCLK 18 25 24 I Reference clock for grayscale PWM control
IREF 20 27 26 I Reference current terminal
NC – – No connection
OUT0 28 7 4 O Constant current output
OUT1 1 8 5 O Constant current output
OUT2 2 9 6 O Constant current output
OUT3 3 10 7 O Constant current output
OUT4 4 11 8 O Constant current output
OUT5 5 12 9 O Constant current output
OUT6 6 13 10 O Constant current output
OUT7 7 14 11 O Constant current output
OUT8 8 15 14 O Constant current output
OUT9 9 16 15 O Constant current output
OUT10 10 17 16 O Constant current output
OUT11 11 18 17 O Constant current output
OUT12 12 19 18 O Constant current output
OUT13 13 20 19 O Constant current output
OUT14 14 21 20 O Constant current output
OUT15 15 22 21 O Constant current output
SCLK 25 4 1 I Serial data shift clock
SIN 26 5 2 I Serial data input
SOUT 17 24 23 O Serial data output
VCC 21 28 27 I Power supply voltage
VPRG 27 6 3 I device is in DC mode. When VPRG = V
XERR 16 23 22 O Error output. XERR is an open-drain terminal. XERR goes L when LOD or TEF is detected.
XLAT 24 3 32 I
DIP PWP RHB
NO. I/O DESCRIPTION
Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF. GS counter is also
reset. When BLANK = L, OUTn are controlled by grayscale PWM control.
Switch DC data input. When DCPRG = L, DC is connected to EEPROM. When DCPRG = H,
DCPRG is also controls EEPROM writing, when VPRG = V
12, 13,
28, 29
Multifunction input pin. When VPRG = GND, the device is in GS mode. When VPRG = VCC, the
EEPROM with DCPRG=HIGH.
Data latch. Note that the internal connections are switched by VPRG. At XLAT ↑ (VPRG =
GND), GS register gets new data. At XLAT ↑ (VPRG = VCC), DC register gets new data.
(PRG)
, DC register data can programmed into DC
(PRG)
TLC5940
7
VCC
INPUT
GND
400 W
INPUT EQUIVALENT CIRCUIT
(BLANK, XLAT, SCLK, SIN, GSCLK, DCPRG)
23 W
23 W
SOUT
GND
OUTPUT EQUIVALENT CIRCUIT (SOUT)
_
+
Amp
400 W
100 W
VCC
INPUT
GND
INPUT EQUIVALENT CIRCUIT (IREF)
XERR
GND
OUTPUT EQUIVALENT CIRCUIT (XERR)
23 W
INPUT
INPUT
GND
GND
INPUT EQUIVALENT CIRCUIT (VCC)
INPUT EQUIVALENT CIRCUIT (VPRG)
OUT
GND
OUTPUT EQUIVALENT CIRCUIT (OUT)
TLC5940
SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005
PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
Resistor values are equivalent resistances, and they are not tested.
Figure 1. Input and Output Equivalent Circuits
8