TEXAS INSTRUMENTS TLC5940 Technical data

PWP RHB NT

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Delay

x0

12−Bit Grayscale

PWM Control

DC Register

GS Register

DC EEPROM

Constant Current

Driver

LED Open Detection

Temperature

Error Flag

(TEF)

Max. OUTn

Current

Delay

x1

12−Bit Grayscale

PWM Control

DC Register

GS Register

DC EEPROM

Constant Current

Driver

LED Open Detection

Delay

x15

6−Bit Dot

12−Bit Grayscale

PWM Control

DC Register

GS Register

DC EEPROM

Constant Current

Driver

LED Open Detection

OUT0

OUT1

OUT15

SOUT

SINSCLK

IREF

XERR

XLAT

GSCLK

BLANK

DCPRG

VPRG

GNDVCC

VPRG

Input

Shift

Register

Input Shift

Register

VPRG

110

2312

191180

9590

116

5

VPRG

0

95

96

191

LED Open

Detection

(LOD)

5

9590

6 11

DCPRG

0

192

96

0

1

01 0

1

01

GS Counter

CNT

96

Status

Information:

LOD,

TED,

DC DATA

192

0

191

1 0

0

1

V

REF

=1.24 V

Correction

6−Bit Dot Correction

01

Blank

SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

16 CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL

FEATURES APPLICATIONS

• 16 Channels

• 12 bit (4096 Steps) Grayscale PWM Control

• Dot Correction

– 6 bit (64 Steps) – Storable in Integrated EEPROM

• Drive Capability (Constant Current Sink)

– 0 mA to 60 mA (V – 0 mA to 120 mA (V

< 3.6 V)

CC

> 3.6 V)

CC

• LED Power Supply Voltage up to 17 V

• V

= 3 V to 5.5 V

CC

• Serial Data Interface, SPI comp.

• Controlled In-Rush Current

• 30-MHz Data Transfer Rate

• CMOS Level I/O

• Error Information

– LOD: LED Open Detection – TEF: Thermal Error Flag

• Monocolor, Multicolor, Fullcolor LED Displays

• LED Signboards

• Display Backlighting

• General, High-Current LED Drive

DESCRIPTION

The TLC5940 is a 16-channel constant-current sink LED driver. Each channel has an individually adjustable 4096-step grayscale PWM brightness control and a 64-step constant-current sink (dot correction). The dot correction adjusts the brightness variations between LED channels and other LED drivers. The dot correction data is stored in an integrated EEPROM. Both grayscale control and dot correction are accessible via a serial interface. A single external resistor sets the maximum current value of all 16 channels.

The TLC5940 features two error information circuits. The LED open detection (LOD) indicates a broken or disconnected LED at an output terminal. The thermal error flag (TEF) indicates an overtemperature condition.

TLC5940

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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TLC5940

SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T

A

PACKAGE

-40 ° C to 85 ° C 28-pin HTSSOP PowerPAD™ TLC5940PWP

-40 ° C to 85 ° C 32-pin 5 mm x 5 mm QFN TLC5940RHB

-40 ° C to 85 ° C 28-pin PDIP TLC5940NT

(1) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI website at www.ti.com .

ABSOLUTE MAXIMUM RATINGS.

over operating free-air temperature range (unless otherwise noted)

V

Input voltage range

I

Output current (dc) 130 mA

O

V

Input voltage range V

I

V

Output voltage range

O

EEPROM program range V EEPROM write cycles 50

ESD rating

T

Storage temperature range –55 ° C to 150 ° C

stg

T

Operating ambient temperature range –40 ° C to 85 ° C

A

Package thermal impedance

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. (3) The package thermal impedance is calculated in accordance with JESD 51-7. (4) With PowerPAD soldered on PCB with 2 oz. trace of copper. See SLMA002 for further information.

(2)

VCC –0.3 V to 6 V

, V

(BLANK)

V

, V

(SOUT)

V

to V

(OUT0) (PRG)

, V

(DCPRG)

(XERR)

(OUT15)

, V

(SCLK)

HBM (JEDEC JESD22-A114, Human Body Model) 2 kV CBM (JEDEC JESD22-C101, Charged Device Model) 500 V

HTSSOP (PWP)

(3)

QFN (RHB) 35.9 ° C/W

(4)

PDIP (NP) 48 ° C/W

(1)

PART NUMBER

UNIT

(XLAT)

–0.3 V to V –0.3 V to V

–0.3 V to 18 V –0.3 V to 24 V

31.58 ° C/W

+0.3 V

CC

+0.3 V

CC

2

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RECOMMENDED OPERATING CONDITIONS

DC CHARACTERISTICS

V

CC

V

O

V

IH

V

IL

I

OH

I

OL

I

OLC

V

(PRG)

T

A

AC CHARACTERISTICS V

f

(SCLK)

f

(GSCLK)

t

wh0

t

wh1

t

wh2

t

wh3

t

su0

t

su1

t

su2

t

su3

t

su4

t

su5

t

h0

t

h1

t

h2

t

h3

t

h4

t

h5

t

prog

Supply Voltage 3 5.5 V Voltage applied to output (OUT0–OUT15) 17 V High-level input voltage 0.8 V Low-level input voltage GND 0.2 V High-level output current V Low-level output current V

Constant output current

EEPROM program voltage 20 22 23 V Operating free-air temperature range -40 85 ° C

Data shift clock frequency SCLK 30 MHz Grayscale clock frequency GSCLK 30 MHz

/t

SCLK pulse duration SCLK = H/L (see Figure 8 ) 16 ns

wl0

/t

GSCLK pulse duration GSCLK = H/L (see Figure 13 ) 16 ns

wl1

XLAT pulse duration XLAT = H (see Figure 11 ) 20 ns BLANK pulse duration BLANK = H (see Figure 13 ) 20 ns

Setup time

Hold Time

= 5 V at SOUT –1 mA

CC

= 5 V at SOUT, XERR 1 mA

CC

OUT0 to OUT15, V OUT0 to OUT15, V

= 3 V to 5.5 V, TA= –40 ° C to 85 ° C (unless otherwise noted)

CC

< 3.6 V 60 mA

CC

> 3.6 V 120 mA

CC

SIN–SCLK (see Figure 11 ) 10 ns SCLK–XLAT (see Figure 11 ) 10 ns VPRG–SCLK (see Figure 6 ) 10 ns VPRG–XLAT (see Figure 6 ) 10 ns BLANK–GSCLK (see Figure 13 ) 10 ns VPRG–DCPRG 1 ms SCLK–SIN (see Figure 11 ) 10 ns XLA–SCLK (see Figure 11 ) 10 ns SCLK–VPRG (see Figure 6 ) 10 ns XLAT–VPRG (see Figure 6 ) 10 ns BLANK–GSCLK (see Figure 13 ) 10 ns DCPRG–VPRG 1 ms Programming time for EEPROM 20 ms

TLC5940

SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

MIN NOM MAX UNIT

CC

V

CC CC

V V

DISSIPATION RATINGS

PACKAGE

28-pin HTSSOP with

PowerPAD™

(1)

soldered

28-pin HTSSOP with PowerPAD™ un- 2026 mW 16.21 mW/ ° C 1296 mW 1053 mW

soldered

32-pin QFN

(1)

28-pin PDIP 2456 mW 19.65 mW/ ° C 1572 mW 1277 mW

(1) The PowerPAD is soldered to the PCB with a 2 oz. copper trace. See SLMA002 for further information.

POWER RATING DERATING FACTOR POWER RATING POWER RATING

TA< 25 ° C ABOVE TA= 25 ° C TA= 70 ° C TA= 85 ° C

3958 mW 31.67 mW/ ° C 2533 mW 2058 mW

3482 mW 27.86 mW/ ° C 2228 mW 1811 mW

3

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TLC5940

SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

ELECTRICAL CHARACTERISTICS

V

= 3 V to 5.5 V, TA= –40 ° C to 85 ° C (unless otherwise noted)

CC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V V

I

CC

I

O(LC)

I

lkg

∆ I

T V

V

(1) Not tested. Specified by design

High-level output voltage IOH= -1 mA, SOUT VCC– 0.5 V

OH

Low-level output voltage IOL= 1 mA, SOUT 0.5 V

OL

VI= V XLAT

Input current

VI= GND; VPRG –1 1 VI= VCC; VPRG 50 VI= 22 V; VPRG; DCPRG = V No data transfer, all output OFF,

VO= 1 V, R No data transfer, all output OFF,

Supply current mA

VO= 1 V, R Data transfer 30 MHz, all output ON,

VO= 1 V, R

Constant output current All output ON, VO= 1 V, R Leakage output current 0.1 µ A

All output OFF, VO= 15 V, R OUT0 to OUT15

All output ON, VO= 1 V, R OUT0 to OUT15, –20 ° C to 85 ° C

All output ON, VO= 1 V, R

Constant current error %

O(LC0)

OUT0 to OUT15 All output ON, VO= 1 V, R

OUT0 to OUT15, –20 ° C to 85 ° C All output ON, VO= 1 V, R

V

CC

Constant current error ± 4 %

O(LC1)

Constant current error ± 4 %

O(LC2)

Device to device, Averaged current from OUT0 to –2 OUT15, R

Device to device, Averaged current from OUT0 to –2.7 OUT15, R

All output ON, VO= 1 V, R

Power supply rejection ratio,

O(LC3)

PSRR

OUT0 to OUT15 All output ON, VO= 1 V, R

OUT0 to OUT15 All output ON, VO= 1 V to 3 V, R

Load regulation

O(LC4)

OUT0 to OUT15 All output ON, VO= 1 V to 3 V, R

OUT0 to OUT15

Thermal error flag threshold Junction temperature

(TEF)

LED open detection threshold 0.3 0.4 V

(LED)

Reference voltage

(IREF)

output

R

I(REF)

or GND; BLANK, DCPRG, GSCLK, SCLK, SIN,

CC

= 10 k Ω

(IREF)

= 1.3 k Ω

(IREF)

= 1.3 k Ω

(IREF)

= 640 Ω

(IREF)

= 4.5 V to 5.5 V, OUT0 to OUT15

= 1920 Ω (20 mA) +0.4

(IREF)

= 480 Ω (80 mA) +2

(IREF)

(1)

CC

= 640 Ω 54 61 69 mA

(IREF)

= 640 Ω ,

(IREF)

= 640 Ω ,

(IREF)

= 640 Ω ,

(IREF)

= 320 Ω ,

(IREF)

= 320 Ω ,

(IREF)

= 640 Ω

(IREF)

= 320 Ω ,

(IREF)

= 640 Ω ,

(IREF)

= 320 Ω ,

(IREF)

–1 1

4 10 mA

0.9 6

5.2 12

16 25

30 60

± 1 ± 4

± 1 ± 8

± 1 ± 6

± 1 ± 8

± 1 ± 4 %/V

± 1 ± 6 %/V

± 2 ± 6 %/V

± 2 ± 8 %/V

150 170 ° C

= 640 Ω 1.20 1.24 1.28 V

µ A

4

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SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

SWITCHING CHARACTERISTICS

V

= 3 V to 5.5 V, TA= -40 ° C to 85 ° C (unless otherwise noted)

CC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

r0

Rise time ns

t

r1

t

f0

Fall time ns

t

f1

t

pd0

t

pd1

t

pd2

Propagation delay time

t

pd3

t

pd4

t

pd5

t

Output delay time OUTn–OUT(n+1) (see Figure 13 ) 20 30 ns

d

SOUT 16 OUTn, V

= 5 V, TA= 60 ° C, DCx = 3F 10 30

CC

SOUT 16 OUTn, V

= 5 V, TA= 60 ° C, DCx = 3F 10 30

CC

SCLK–SOUT (see Figure 11 ) 30 ns DCPRG–OUT0 30 ns BLANK–OUT0 (see Figure 13 ) 60 ns OUTn - XERR (see Figure 13 ) 1000 ns GSCLK–OUT0 (see Figure 13 ) 60 ns XLAT–I

(dot correction) 1000 ns

OUT

TLC5940

5

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1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

GND

BLANK

XLAT

SCLK

SIN

VPRG

OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7

VCC IREF DCPRG GSCLK SOUT XERR OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8

PWP PACKAGE

(TOP VIEW)

Thermal

PAD

THERMAL

PAD

GSCLK24

SOUT23

XERR22

OUT1521

OUT1420

OUT1319

OUT1218

OUT1117

OUT1016 OUT915 OUT814 NC13 NC12 OUT711 OUT610 OUT59

OUT4 8

OUT3 7

OUT2 6

OUT1 5

OUT0 4

VPRG 3

SIN 2

SCLK 1

DCPRG 25

IREF 26

VCC 27

NC 28 NC 29

GND 30

BLANK 31

XLAT 32

RHB PACKAGE

(TOP VIEW)

NC − No internal connection

1 2 3 4 5 6 7 8

9 10 11 12 13 14

18 17 16 15

22 21 20 19

26 25 24 23

28 27

OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8

OUT9 OUT10 OUT11 OUT12 OUT13 OUT14

GND VCC IREF DCPRG GSCLK SOUT XERR OUT15

SCLK XLAT BLANK

OUT0 VPRG SIN

NT PACKAGE

(TOP VIEW)

TLC5940

SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

DEVICE INFORMATION

6

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SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

DEVICE INFORMATION (continued)

TERMINAL FUNCTION

TERMINAL

NAME

BLANK 23 2 31 I

DCPRG 19 26 25 I DC is connected to the DC register.

GND 22 1 30 G Ground GSCLK 18 25 24 I Reference clock for grayscale PWM control IREF 20 27 26 I Reference current terminal

NC – – No connection OUT0 28 7 4 O Constant current output

OUT1 1 8 5 O Constant current output OUT2 2 9 6 O Constant current output OUT3 3 10 7 O Constant current output OUT4 4 11 8 O Constant current output OUT5 5 12 9 O Constant current output OUT6 6 13 10 O Constant current output OUT7 7 14 11 O Constant current output OUT8 8 15 14 O Constant current output OUT9 9 16 15 O Constant current output OUT10 10 17 16 O Constant current output OUT11 11 18 17 O Constant current output OUT12 12 19 18 O Constant current output OUT13 13 20 19 O Constant current output OUT14 14 21 20 O Constant current output OUT15 15 22 21 O Constant current output SCLK 25 4 1 I Serial data shift clock SIN 26 5 2 I Serial data input SOUT 17 24 23 O Serial data output VCC 21 28 27 I Power supply voltage

VPRG 27 6 3 I device is in DC mode. When VPRG = V

XERR 16 23 22 O Error output. XERR is an open-drain terminal. XERR goes L when LOD or TEF is detected. XLAT 24 3 32 I

DIP PWP RHB

NO. I/O DESCRIPTION

Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF. GS counter is also reset. When BLANK = L, OUTn are controlled by grayscale PWM control.

Switch DC data input. When DCPRG = L, DC is connected to EEPROM. When DCPRG = H, DCPRG is also controls EEPROM writing, when VPRG = V

12, 13,

28, 29

Multifunction input pin. When VPRG = GND, the device is in GS mode. When VPRG = VCC, the EEPROM with DCPRG=HIGH.

Data latch. Note that the internal connections are switched by VPRG. At XLAT ↑ (VPRG = GND), GS register gets new data. At XLAT ↑ (VPRG = VCC), DC register gets new data.

(PRG)

, DC register data can programmed into DC

(PRG)

TLC5940

7

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VCC

INPUT

GND

400 W

INPUT EQUIVALENT CIRCUIT

(BLANK, XLAT, SCLK, SIN, GSCLK, DCPRG)

23 W

SOUT

GND

OUTPUT EQUIVALENT CIRCUIT (SOUT)

_

+

Amp

400 W

100 W

VCC

INPUT

GND

INPUT EQUIVALENT CIRCUIT (IREF)

XERR

GND

OUTPUT EQUIVALENT CIRCUIT (XERR)

23 W

INPUT

GND

INPUT EQUIVALENT CIRCUIT (VCC)

INPUT EQUIVALENT CIRCUIT (VPRG)

OUT

GND

OUTPUT EQUIVALENT CIRCUIT (OUT)

TLC5940

SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

PARAMETER MEASUREMENT INFORMATION

PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

Resistor values are equivalent resistances, and they are not tested.

Figure 1. Input and Output Equivalent Circuits

8

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Testpoint

CL = 15 pF

SOUT

V

(LED)

= 4 V

RL = 51 

CL = 15 pF

OUTn Testpoint

_

+

VCC = 0 V ~ 7 V

V

(LED)

=

1 V

OUT0

OUTn

OUT15

Testpoint

R

IREF

= 640 

IREF

IOLC, IOLC3, IOLC4, IOUT/IREF

t

who

, t

wIO

, t

wh1

, t

wl1

, t

su0

t

su4,

t

h4

PARAMETER MEASUREMENT INFORMATION (continued)

TLC5940

SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

Figure 2. Parameter Measurement Circuits

9

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100

1 k

100 k

10 k

I − Output Current − mA

O

0 20 60 100

Reference Resistor, R -

(IREF)

W

40

80

120

0

1 k

3 k

4 k

2 k

T − Free-Air Temperature − C

A

o

0-20 20 100

Power Dissipation Rate - mA

-40

80

6040

TLC5940PWP PowerPAD Soldered

TLC5940PWP PowerPAD Unsoldered

TLC5940RHB

TLC5940NT

0

70

60

50

40

30

20

10

90

100

80

I - Output Current - mA

O

V − Output Voltage − V

O

0.6

0.9

1.2

1.5

1.8

2.1 2.4 2.7

30.30

I = 60 mA

max

I = 30 mA

max

I = 5 mA

max

TLC5940

SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

TYPICAL CHARACTERISTICS

REFERENCE RESISTOR POWER DISSIPATION RATE

vs vs

OUTPUT CURRENT FREE-AIR TEMPERATURE

Figure 3. Figure 4.

OUTPUT CURRENT

vs

OUTPUT VOLTAGE

10

Figure 5.

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SCLK

SOUT

SIN

VPRG

Vcc

DC n MSB

GS

MSB

X

1 1

XLAT

DC n LSB

96

192

GS

LSB

193

DC n+1

MSB

DC n+1

MSB−1

1

DC n

MSB

DC n

LSB

DC

MSB

GS

MSB

SID

MSB

X

2

t

h3

t

su3

t

h3

t

su2

t

h2

t

su2

t

h2

DC Mode Data

Input Cycle

GS Mode Data

Input Cycle

DC Mode Data

Input Cycle

X

TLC5940

SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

PRINCIPLES OF OPERATION

SERIAL INTERFACE

The TLC5940 includes a flexible serial interface, which can be connected to microcontrollers or digital signal processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK signal shifts the data from the SIN pin to the internal register. After all data is clocked in, a rising edge of XLAT latches the serial data to the internal registers. All data are clocked in with the MSB first. Multiple TLC5940 devices can be cascaded by connecting the SOUT pin of one device with the SIN pin of the following device. The SOUT pin can also be connected to the controller to receive status information from TLC5940. The serial data format is 96-bit or 192-bit wide, depending on programming mode of the device.

Figure 6. Serial Data Input Timing Chart

ERROR INFORMATION OUTPUT

The open-drain output XERR is used to report both of the TLC5940 error flags, TEF and LOD. During normal operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is pulled up to V on, and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together and pulled up to V (see Figure 14 ).

To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH.

TEMPERATURE OUTn VOLTAGE TEF LOD BLANK XERR

TJ< T TJ> T

TJ< T

TJ> T

through an external pullup resistor. If TEF or LOD is detected, the internal transistor is turned

CC

with a single pullup resistor. This reduces the number of signals needed to report a system error

CC

Table 1. XERR Truth Table

ERROR CONDITION ERROR INFORMATION SIGNALS

(TEF) (TEF)

Don't Care L X H H Don't Care H X L

OUTn > V

(TEF)

OUTn < V OUTn > V

(TEF)

OUTn < V

(LED) (LED) (LED) (LED)

L L H L H L H L L H H L

L

11

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I

max



V

(IREF)

R

(IREF)

 31.5

TLC5940

SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

TEF: THERMAL ERROR FLAG

The TLC5940 provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC. If the junction temperature exceeds the threshold temperature (160 ° C typical), the TEF circuit trips and pulls XERR to ground. TEF status can also be read out from the TLC5940 status register.

LOD: LED OPEN DETECTION

The TLC5940 provides an LED open-detection circuit (LOD). This circuit reports an error if any one of the 16 LEDs is open or disconnected from the circuit. The LOD circuit trips when the following two conditions are met simultaneously:

1. BLANK is set to LOW

2. When the voltage at OUTn is less than V 1 µ s after being turned on).

The LOD circuit also pulls XERR to GND when tripped. The LOD status of each channel can also be read out from the TLC5940 status information data (SID) in GS data input cycle.

DELAY BETWEEN OUTPUTS

The TLC5940 has graduated delay circuits between outputs. These circuits can be found in the constant current driver block of the device (see the functional block diagram). The fixed-delay time is 20 ns (typical), OUT0 has no delay, OUT1 has 20 ns delay, and OUT2 has 40 ns delay, etc. The maximum delay is 300 ns from OUT0 to OUT15. The delay works during switch on and switch off of each output channel. These delays prevent large inrush currents which reduces the bypass capacitors when the outputs turn on.

of 0.3 V (typical) (Note: the voltage at each OUTn is sampled

(LED)

OUTPUT ENABLE

All OUTn channels of TLC5940 can switched off with one signal. When BLANK is set to high, all OUTn are disabled, regardless of logic operations of the device. The grayscale counter is also reset. When BLANK is set to low, all OUTn work under normal conditions.

Table 2. BLANK Signal Truth Table

BLANK OUT0 - OUT15

LOW Normal condition

HIGH Disabled

SETTING MAXIMUM CHANNEL CURRENT

The maximum output current per channel is programmed by a single resistor, R IREF pin and GND pin. The voltage on IREF is set by an internal band gap V

1.24 V. The maximum channel current is equivalent to the current flowing through R

31.5. The maximum output current can be calculated by Equation 1 :

where:

V

= 1.24 V

(IREF)

R

Figure 3 shows the maximum output current IOversus R

= User selected external resistor.

(IREF)

. R

(IREF)

is the value of the resistor between IREF

(IREF)

terminal to GND, and IOis the constant output current of OUT0 to OUT15.

(IREF)

(IREF) (IREF)

, which is placed between

with a typical value of multiplied by a factor of

(1)

12

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P = V x I +

D CC CC

V x I

OUT MAX

x

DC

n

63

x d

PWM

x N

(

)

I

OUTn

 I

max



DCn

63

TLC5940

SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

POWER DISSIPATION CALCULATION

The device power dissipation needs to be below the power dissipation rate of the device package to ensure correct operation. Equation 2 calculates the power dissipation of device:

where:

V

: device supply voltage

CC

ICC: device supply current V

: TLC5940 OUTn voltage when driving LED current

OUT

I

: LED current adjusted by R

MAX

DC

: maximum dot correction value for OUTn

n

N: number of OUTn driving LED at the same time d

: duty cycle defined by BLANK pin or GS PWM value

PWM

OPERATING MODES

The TLC5940 has different operating modes depending on the signals VPRG and DCPRG. Table 3 shows the available operating modes. The TLC5940 GS operating mode (see Figure 11 ) and shift register values are not defined after power up. One solution to solve this is to set dot correction data after TLC5940 power up and switch back to GS PWM mode. The other solution is to overflow the input shift register with 193 bits of dummy data and latch it while TLC5940 is in GS PWM mode.

Resistor

(IREF)

(2)

Table 3. TLC5940 Operating Modes Truth Table

SIGNAL

DCPRG VCPRG

L EEPROM

H DC Register

L EEPROM

H DC Register

L EEPROM

H Write dc register value to EEPROM

GND 192 bit Grayscale PWM Mode

V

CC

V

(PRG)

INPUT SHIFT REGISTER MODE DC VALUE

96 bit Dot Correction Data Input Mode

X EEPROM Programming Mode

SETTING DOT CORRECTION

The TLC5940 has the capability to fine adjust the output current of each channel OUT0 to OUT15 independently. This is also called dot correction. This feature is used to adjust the brightness deviations of LEDs connected to the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit word. The channel output can be adjusted in 64 steps from 0% to 100% of the maximum output current I determines the output current for each output n:

where:

I

= the maximum programmable output current for each output.

max

DCn = the programmed dot correction value for output n (DCn = 0 to 63). n = 0 to 15

Dot correction data are entered for all channels at the same time. The complete dot correction data format consists of 16 x 6-bit words, which forms a 96-bit wide serial data packet. The channel data is put one after another. All data is clocked in with MSB first. Figure 7 shows the DC data format.

. Equation 3

max

(3)

13

www.ti.com

DC 15.5

95

DC 14.5

79

DC 0.5

5

DC 0.0

0

DC 15.0

90

DC 1.0

6

LSB MSB

DC OUT0 DC OUT15

DC OUT2 − DC OUT14

DC n

MSB

DC n

MSB−1

DC n

MSB−2

DC n

LSB+1

DC n

LSB

DC n

MSB

DC n+1

MSB

DC n+1

MSB−1

DC n

MSB−1

DC n

MSB−2

DC n−1

LSB

DC n−1

LSB+1

DC n−1

MSB

DC n−1

MSB−1

DC n−1

MSB−2

1 2 3 95 96 1 2

SCLK

SOUT

SIN

MODE

XLAT

DC Mode Data

Input Cycle n

DC Mode Data

Input Cycle n+1

V

CC

t

su1

t

h1

wh0

t

wl0

t

wh2

DCPRG

VPRG

V

(PRG)

t

su5

t

prog

t

h5

DC EEPROM Write Timing

0 V or V

CC

TLC5940

SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

Figure 7. Dot Correction Data Packet Format

To input data into the dot correction register, VPRG must be set to V

. The internal input shift register is then

CC

set to 96-bit width. After all serial data are clocked in, a rising edge of XLAT is used to latch the data into the dot correction register. Figure 8 shows the dc data input timing chart.

Figure 8. Dot Correction Data Input Timing Chart

The TLC5940 has also an EEPROM to store dot correction data. To store data from the dot correction register to EEPROM, DCPRG is set to high after applying V

to VPRG pin. Figure 9 shows the EEPROM programming

PRG

timings.

Figure 9. EEPROM Programming Timing Chart

14

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Brightness in % 

GSn

4095

 100

GS 15.11

191

GS 14.11

178

GS 0.11

11

GS 0.0

0

GS15.0

180

GS 0.0

12

LSB MSB

GS OUT0 GS OUT15GS OUT2 − GS OUT14

t

su2

SCLK

SOUT

SIN

MODE

GS

MSB

1

Following GS Mode Data

Input Cycle

XLAT

DC

LSB

96

DC Mode Data

Input Cycle

192 193

GS + 1

MSB

1

DC n

LSB

DC

MSB

GS

MSB

SID

MSB

SID

MSB−1

First GS Mode Data

Input Cycle After DC Data Input Cycle

192

SID n + 1

MSB

GS + 1

LSB

t

h3

t

su3

t

h2

t

h3

XX

SID

LSB

t

pd0

GS

LSB

t

wh2

t

h1

t

su1

TLC5940

SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

SETTING GRAYSCALE

The TLC5940 can adjust the brightness of each channel OUTn using a PWM control scheme. The use of 12-bit per channel results in 4096 different brightness steps, respective 0% to 100% brightness. Equation 4 determines the brightness level for each output n:

where:

GSn = the programmed grayscale value for output n (GSn = 0 to 4095) n = 0 to 15 Grayscale data for all OUTn

The input shift register enters grayscale data into grayscale register for all channels simultaneously. The complete grayscale data format consists of 16 x 12 bit words, which forms a 192-bit wide data packet (see

Figure 10 ). The data packet must be clocked in with the MSB first.

(4)

Figure 10. Grayscale Data Packet Format

When VPRG is set to GND, TLC5940 enters the grayscale data input mode. The device switches the input shift register to 192-bit width. After all data is clocked in, a rising edge of XLAT signal latches the data into the grayscale register (see Figure 11 ). The first GS data input cycle after dot correction requires an additional SCLK pulse after the XLAT signal to complete the grayscale update cycle. All GS data in the input shift register is replaced with status information data (SID) after latching into grayscale register.

Figure 11. Grayscale Data Input Timing Chart

15

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LOD 15LOD 0TEFXXDC15.5DC 0.0XX

19117617516816772710

MSBLSB

LOD DataTEFDC ValuesReserved

GSCLK

BLANK

GS PWM

Cycle n

1 2 3 1

GS PWM

Cycle n+1

OUT0

OUT1

OUT15

XERR

n x t

d

t

pd2

t

pd2

+ t

d

t

pd2

+ 14 x t

d

t

pd3

t

pd4

t

wh1

t

wl1

t

wl1

t

pd4

4096

t

h4

t

wh3

t

pd4

+ n x t

d

t

su4

(Current)

TLC5940

SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

STATUS INFORMATION OUTPUT

The TLC5940 does have a status information register, which can be accessed in grayscale mode (VPRG = GND). After the XLAT signal latches the data into GS register the input shift register data will be replaced with status information data (SID) of the device (see Figure 11 ). LOD, TEF and dot correction EEPROM data (DCPRG=LOW) or dot correction register data (DCPRG=HIGH) can be read out at the SOUT pin. The status information data packet is 192-bit wide. Bit 176 - bit 191 contains the LOD status of each channel. Bit 175 contains the TEF status. If DCPRG is low, bit 72 - bit 167 contains the value of the dot correction EEPROM. If DCPRG is high, bit 72 - bit 167 contains the data of the dot correction register. The remaining bits are reserved. The complete status information data packet is shown in Figure 12 .

Figure 12. Status Information Data Packet Format

GRAYSCALE PWM OPERATION

The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK increases the grayscale counter by one and switches on all OUTn with grayscale value not zero. Each following rising edge of GSCLK increases the grayscale counter by one. The TLC5940 compares the grayscale value of each output OUTn with the grayscale counter value. All OUTn with grayscale values equal to counter values are switched off. A BLANK=H signal after 4096 GSCLK pulses resets the grayscale counter to zero and completes the grayscale PWM cycle (see Figure 13 ).

16

Figure 13. Grayscale PWM Cycle Timing Chart

www.ti.com

f

(GSCLK)

 4096  f

(update)

f

(SCLK)

 193  f

(update)

 n

TLC5940

SIN SOUT

OUT0 OUT15

SCLK

GSCLK

XLAT

VPRG

BLANK

IREF

XERR

DCPRG

TLC5940

SIN SOUT

OUT0 OUT15

SCLK

GSCLK

XLAT

VPRG

BLANK

IREF

XERR

DCPRG

IC 0 IC n

7

SIN

SCLK

GSCLK

XLAT

BLANK

XERR

DCPRG

Controller

SOUT

VPRG_D VPRG_OE

W_EEPROM

100 k

50 k

VPRG

100 nF

V

(LED)

V

(LED)

V

(LED)

V

(LED)

V

CC

100 nF

V

(22V)

V

(22V)

V

CC

V

CC

TLC5940

SLVS515A – DECEMBER 2004 – REVISED AUGUST 2005

SERIAL DATA TRANSFER RATE

Figure 14 shows a cascading connection of n TLC5940 devices connected to a controller, building a basic

module of an LED display system. The maximum number of cascading TLC5940 devices depends on the application system and is in the range of 40 devices. Equation 5 calculates the minimum frequency needed:

where:

f f f n: number cascaded of TLC5940 device

APPLICATION EXAMPLE

: minimum frequency needed for GSCLK

(GSCLK)

: minimum frequency needed for SCLK and SIN

(SCLK)

: update rate of whole cascading system

(update)

(5)

Figure 14. Cascading Devices

17

PACKAGE OPTION ADDENDUM

www.ti.com

8-Aug-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

TLC5940NT ACTIVE PDIP NT 28 13 TBD Call TI Level-NA-NA-NA

TLC5940PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS &

no Sb/Br)

TLC5940PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS &

no Sb/Br)

TLC5940PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS &

no Sb/Br)

TLC5940PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS &

no Sb/Br)

TLC5940RHB ACTIVE QFN RHB 32 73 Green (RoHS &

no Sb/Br)

TLC5940RHBR ACTIVE QFN RHB 32 3000 Green (RoHS &

no Sb/Br)

TLC5940RHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

25-Sep-2006

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

TLC5940NT ACTIVE PDIP NT 28 13 Green (RoHS &

no Sb/Br)

TLC5940NTG4 ACTIVE PDIP NT 28 13 Green (RoHS &

no Sb/Br)

TLC5940PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS &

no Sb/Br)

TLC5940PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS &

no Sb/Br)

TLC5940PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS &

no Sb/Br)

TLC5940PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS &

no Sb/Br)

TLC5940RHB ACTIVE QFN RHB 32 TBD Call TI Call TI

TLC5940RHBG4 ACTIVE QFN RHB 32 TBD Call TI Call TI

TLC5940RHBR ACTIVE QFN RHB 32 3000 Green (RoHS &

no Sb/Br)

TLC5940RHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-2-260C-1 YEAR

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MPDI004 – OCTOBER 1994

NT (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

24 PINS SHOWN

24

DIM

A MAX

A MIN

B MAX

B MIN

PINS **

24

1.260

(32,04)

1.230

(31,24)

0.310

(7,87)

0.290 (7,37)

0°–15°

28

1.425

(36,20)

1.385

(35,18)

0.315

(8,00)

0.295

(7,49)

B

A

13

0.280 (7,11)

0.250 (6,35)

1

0.070 (1,78) MAX

0.020 (0,51) MIN

0.100 (2,54)

0.021 (0,53)

0.015 (0,38)

0.010 (0,25)

M

12

0.200 (5,08) MAX Seating Plane

0.125 (3,18) MIN

0.010 (0,25) NOM

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

4040050/B 04/95

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TEXAS INSTRUMENTS TLC5940 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES APPLICATIONS

DESCRIPTION

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ABSOLUTE MAXIMUM RATINGS.

RECOMMENDED OPERATING CONDITIONS

DISSIPATION RATINGS

ELECTRICAL CHARACTERISTICS

SWITCHING CHARACTERISTICS

DEVICE INFORMATION

PARAMETER MEASUREMENT INFORMATION

PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

TYPICAL CHARACTERISTICS

PRINCIPLES OF OPERATION

SERIAL INTERFACE

ERROR INFORMATION OUTPUT

TEF: THERMAL ERROR FLAG

LOD: LED OPEN DETECTION

DELAY BETWEEN OUTPUTS

OUTPUT ENABLE

SETTING MAXIMUM CHANNEL CURRENT

POWER DISSIPATION CALCULATION

OPERATING MODES

SETTING DOT CORRECTION

SETTING GRAYSCALE

STATUS INFORMATION OUTPUT

GRAYSCALE PWM OPERATION

SERIAL DATA TRANSFER RATE

APPLICATION EXAMPLE