TEXAS INSTRUMENTS TLC5930 Technical data

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SLLS528 – MARCH 2002

FEATURES

0.2-mA to 40-mA (Constant-Current Sink)

D

Drive Capability x 12 Bits Output Count into
24-Pin HTSSOP Package

D 1024 Gray-Scale Display (PWM Control 1024

Steps) with Max 25-MHz Clock Frequency

D 3-Way Brightness Adjustment

– Plane Brightness Adjustment for 64 Steps

(40% to 100%)

– Frequency Division for 16 Steps

(6.3% to 100%)

– Dot Correction for 256 Steps (0% to 100%)

D DS–Link Data Input/Output (Data Rate Max

20 Mbps) with Packet Operation

D 5 Error Information Types and 2 Gray–Scale

Clock Modes

D 3.3-V V

and LVTTL Interface

CC

APPLICATION

Full- or Multi-Color LED Display

D

DESCRIPTION

The TLC5930 is a constant-current sink driver
with an adjustable current value, and 1024 gray
scale display that uses pulse width control. The
output current is 0.2 mA to 40 mA with 12 bits of
RGBx4. The maximum current value of the
constant-current output can be set by one external
resistor.

The TLC5930 includes three kinds of brightness
adjustment functions: one adjusts the plane
brightness between devices, changing the current
values of all outputs uniformly. The second adjusts
the frequency division to controls overall panel
brightness, and the third adjusts the dot correction
per LED, changing the current values of
independent output.

The TLC5930 also includes color–tone correction
function for correcting color per dot (pixel) and
OVM function for constant-current output
terminals used for LED failure detection.

Other features include the thermal error flag
(TEF). The active wire-check (AWC) to check the
communication between the controller and the
device. The LED leakage-detect (LKD) to detect
the reverse leakage on the LED. The GCLK error
flag (GEF) and the HSYNC error flag (HEF) by
monitoring the gray-scale clock count, and the
dual source gray-scale clock (DSG) function to
switch the gray-scale clock to the external input
clock or to switch the internally-generated clock.

PowerPAD is a trademark of Texas Instruments Incorporated.

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The TLC5930 requires three signals for standard
operation: data input and gray-scale clock. Only
three-signal line and 24-pin HTSSOP package
reduce board area and total cost.

Copyright  2002, Texas Instruments Incorporated

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SLLS528 – MARCH 2002

PWP PACKAGE

(TOP VIEW)

OUT0
OUT1
OUT2

GND
OUT3
OUT4
OUT5

GND

DTIN
STIN

GCLK

GND

1
2
3
4
5
6
7
8
9
10
11
12

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

24
23
22
21
20
19
18
17
16
15
14
13

OUT11
OUT10
OUT9
GND
OUT8
OUT7
OUT6
DTOUT
STOUT
XRST
IREF
VCC

AVAILABLE OPTIONS

T

A

–20°C to 85°C

PACKAGE

PowerPad TSSOP

(PWP)

TLC5930PWP

†

Supply voltage, VCC –0.3 V to 4.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current (dc), I
Input voltage range, V
Output voltage range, V

Storage temperature range, T
Power dissipation rating at (or above) T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltages values are with respsect to GND terminal.

2. At operating temperature range over 25°C, dependent on derating factor of 41 mW/°C.

O(LC)

IN
DTOUT

V

OUT0 –

V

OUT0 –

stg

, V

V
V

STOUT

, (when off) –0.3 V to 17 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OUT11

, (when on) –0.3 V to 10 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OUT11

= 25°C 3.7 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

–0.3 V to (VCC – 0.2 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.3 V to VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

45 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

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Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

t

Á

P

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

Á

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SLLS528 – MARCH 2002

electrical characteristics, MIN/MAX: V
TA = 25°C (unless otherwise noted)

PARAMETER

V

OH

V

OL

I

I

I

CC

ÁÁ

I

O(LC)

I

LKG

∆I

OLC

ÁÁ

∆I

OLC1

∆I

ÁÁ

OLC2

∆I

OLC3

ÁÁ

T

TSD

V

IREF

High-level output voltage
Low-level output voltage
Input current

Supply current

БББББББББ

Constant-current output current
Output leakage current

Constant-current outout error between

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bits
Changes in constant output current

depend on supply voltage
Changes in constant output current

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depend on output voltage
Changes in constant output current

depend on brightness data

БББББББББ

TEF detection temperature
Reference voltage

= 3.0 V to 3.6 V, T

CC

= – 20°C to 85°C, TYP: V

A

TEST CONDITIONS

IOH = – 1 mA
IOL = 1 mA
VIN = VCC or GND
Input signal is static, V

R

= 5.1 kΩ, LL output bits off

IREF

Input signal is static, V

ББББББББББ

R

= 5.1 kΩ, LL output bits on

IREF

V

= 1.0 V, R

OUTn

LL output bits on
OUT0 to OUT11 (V
OUT0 to OUT11 (V

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R

= 5.1 kΩ

IREF

V

= 1.23 V

REF

V

= 1 V to 3 V, R

OUT

ББББББББББ

V

= 1.23 V, 1 bit light on

IREF

V

= 1.3 V, R

OUT

V

= 1.23 V, 1 bit light on

IREF

ББББББББББ

OUT

OUT

IREF

(OUTn)
(OUTn)

IREF

IREF

= 1 V,

= 1 V,

= 5.1 kΩ,

= 15 V)
= 1 V),

= 5.1 kΩ,

= 5.1 kΩ,

Junction temperature
R

= 5.1 kΩ

IREF

CC

MIN

TYP

MAX

2.4

16

35

40

40

160

1.23

Á

± 4%

170

ÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

ÁÁÁÁÁ

150

= 3.3 V,

0.4
± 1

21

50

45

0.1

± 3

± 1

± 2

UNIT

µA

mA

Á

mA

µA

Á

%/V

Á

Á

°C

V

V

switching characteristics, CL = 15 pF

PARAMETER

t

R

t

F

Rise time

Fall time

DTOUT, STOUT
DTOUT, STOUT
OUTn, See Figure 1
GCLK – OUT0 on
GCLK – OUT0 off
[(OUTn + 1) – OUTn]

PD

Á

p

ropagation delay time

ББББББББББ

DTIN – OUT0, STIN – OUT0
DTIN – DTOUT, DTIN, STOUT

ББББББББББ

STIN – DTOUT, STIN, STOUT
Operation mode setting (all output force off)

– OUT0 off

t

EDGE

Duty deviation between edge of DTIN and

Á

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STIN

DTOUT/STOUT, STOUT/DTOUT

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(1) This specification shows the delay of edge for DATA/STROBE, but data appears in the output with 2 bits delay. (Data propagation delay time
is 2 bits + tD

[D/STIN – D/STOUT]

)

TEST CONDITIONS

(1)

ÁÁÁ

Á

MIN

–10

TYP

Á

12
10
15
90
35
25

18

60

± 1

MAX

110

Á

Á

15
13
40

60
40
60

25

90

10

UNIT

ns

Á

Á

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V

mA

SLLS528 – MARCH 2002

recommended operating conditions

dc characteristics

PARAMETER

Supply voltage, V

Voltage applied to constant-current output, V
High-level input voltage, V

Low-level input voltage, V
High-level output current, I
Low-level output current, I
Constant output current, I
Operating free-air temperature range, T

CC

O

IH

IL

OH

OL

O(LC)

A

CONDITIONS

OUT0 to OUT11 off
OUT0 to OUT11 on

VCC = 3.1 V @ DTOUT, STOUT
VCC = 3.1 V @ DTOUT, STOUT
OUT0 to OUT11

MIN

GND

3.0

2.0

– 20

MAX

VCC

– 1.0

3.6
15
10

0.8

1.0
40
85

UNIT

V

mA

°C

ac characteristics, V

PARAMETER

f

(GCLK)

t

(EDGE)

t

w(H)/tw(L)

t

w(L)

t

(DATA)

t

SU

(1) This is the frequency when any output is obtailed at two or more than gray-scale entered.

GCLK clock frequency
Time between edges
GCLK pulse duration
XRST reset pulse duration
Data transfer rate
Setup time

= 3.1 V to 3.5 V, T

CC

(1)

= –20°C to 85°C (unless otherwise noted)

A

CONDITIONS

2 gray scale inputs I
DTIN – STIN, STIN – DTIN

HSYNC – GCLK

O(LC)

= 40 mA

MIN

30
20

MAX

1

25

20

6.5

UNIT

MHz

ns

ms

Mb/s

ns

4

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functional block diagram

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SLLS528 – MARCH 2002

VCC

DTIN

STIN

GCLK

XRST

330 kΩ

D/S

Link

Decoder

CLR

Communication Logic

CLK

Packet

Interface

BLANK, FON, FOF, INHSW, INHCS

Packet

Shift

Register

GSCLK

Packet

Data

Latch

GS, BCP

PWM

Controller

Packet

Interface

DMDATA

D/S

Link

Decoder

DTOUT

STOUT

IREF

GND

Bandgap
Reference
Generator

BG, IBC

BG

Reference

Voltage

&

Bias Current

Generator

GND = DGND, AGND, LGND

ITEF

IOVM

BC

IDC,ICC

Analog Converter

Trimming

Circuit

Digital to Analog Converter

12-Bit Constant Current Driver

OUT2

OUT1

OUT0

OUT4

OUT3

&

OUT5

DC, CC

OUT6

OUT7

OUT9

OUT8

SW, CSW

OUT11

OUT10

Thermal

Error

Flag

Output
Voltage
Monitor

&

LED Leak

Detector

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SLLS528 – MARCH 2002

Terminal Functions

TERMINAL
NAME NO.

DTIN 9 I DS–link data input
DTOUT 17 O DS–link data output

GCLK 11 I
GND 4, 8, 12, 21 – Ground

IREF 14 I/O

OUT0 1
OUT1 2
OUT2 3
OUT3 5
OUT4 6
OUT5 7
OUT6 18
OUT7 19
OUT8 20
OUT9 22
OUT10 23
OUT11 24
STIN 10 I DS–link strobe input
STOUT 16 O DS–link strobe output
VCC 13 I Power supply

XRST 15 I

I/O

Clock input for gray scale. The gray scale display is accomplished by lighting the LED until the
number of the gray-scale clock counted is equal to the data latched.

Constant-current value setting. LED current is set to the desired value by connecting an external
resistor between IREF and GND. The 168 times current compared to current across the external
resistor flows through the constant-current output terminals.

Constant-current output.

O

Reset signal. This signal is used to initialize the device reset is accomplished by pulling this pin low
(internally pulled up with a 330-kΩ resistor). If not used, this terminal should be left open or connect
to VCC.

DESCRIPTION

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PIN EQUIVALENT INPUT AND OUTPUT SCHEMA TIC DIAGRAMS

DTIN, STIN, GCLK

PAD

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SLLS528 – MARCH 2002

VCC

DTOUT, STOUT

OUTn

XRST

GND

VCC

PAD

GND

PAD

GND

VCC

PAD

330 k

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GND

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SLLS528 – MARCH 2002

TIMING DIAGRAMS

VCC

VIL

Figure 1. Rise Time and Fall Time Test Circuit for OUTn

VIH

tR tF

5.1 kΩ

90%

10%

VCC

IREF OUTn

GND

56 Ω

15 pF

VIH or VOH
50%
50%

VIL or VOL

txxxx

VIH or VOH
50%
50%

VIL or VOL

Figure 2. Timing Requirements

PRINCIPLES OF OPERATION

setting for constant output current value

On the constanct current output terminals (OUT0 to OUT11), approximately 168 times the current that flows
through the external resistor, R
is calculated using the following equation:

R

where R

(IREF)

(IREF)

(W) +

168 1.23 V

I

O(LC)

should be ≤ 4.88 kΩ

Note that more current flows if IREF is connected directly to GND.

, (connected between IREF and GND) can flow. The external resistor value

IREF

(A)

(1)

8

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NO. OF

NO. OF

SLLS528 – MARCH 2002

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PRINCIPLES OF OPERATION

command packet list

ID COMMAND

FUNCTION

Internal reset 00 X 00 00000000 8(03h) 24 Write
Gray scale data setting 00or01.FF X X 02 00000010 10x12 output 136 Write
Dot correction data setting 00or01.FF X X 04 00000100 8x12 output 112 Write
Color tone correction data setting 00or01.FF X X 08 00001000 8x4set 48 Write
Plane brightness adjustment data setting 00or01.FF X X 10 00010000 16 32 Write
Color tone correction control setting 00or01.FF X X 20 00100000 8 24 Write
Operation mode setting 00or01.FF X X 40 01000000 16 32 Write
OVM information read 00or01.FF X X 50 01010000 16 32 Read
Failure monitor information read 00or01.FF X X 60 01100000 8 24 Read
Automatical ID setting 00 X 70 01110000 16(min) 32(min) Write
HSYNC synchronization 00 X 80 10000000 16 32 Wr/Rd

NOTE Common control is applied to all the devices connected. Indidual control is applied to the device specified by ID.

HEX

CONTROL

COMMON INDIVIDUAL

HEX BIN

DATA

BITS BITS

PACKET MODE

basic packet configuration

MSB LSB

ID (8 bit)

MSB

data configuration

DATA

GCLK

LSB

CMD (8 bit)

MSB

LSB

DATA (0 to 120 bit)

MSB

DQ

Q

DQ

Q

Figure 3. DS LINK Configuration

LSB

DTIN

STIN

UDG–02058

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SLLS528 – MARCH 2002

PRINCIPLES OF OPERATION

packet operation

Data output is performed with delay of two bits from input. In other words, by using the edge of the input, data
before two b i t s appear in the output terminal. Figure 4 shows the concept for data transfer when some TLC5930s
are connected in a cascade, where data A–Z indicates valid data, and the asterisk (*) marks invalid data. Also,
data A is a first data input from controller, and there is assumed to be no data transition for DATA/STROBE
between [H and I] and [S and T] in the IC1 input data.

Invalid data is clocked out corresponding to the input edge to ensure that no data exists before data A. After
that, data A is clocked out with a time delay of two bits plus t

D(D/STIN–D/STOUT)

Once data output is started, data before two bits from current input is sequentially clocked out using the input
edge. It should be noted that data output stays during no transition of DATA/STROBE, since no input edge
makes the out p u t edge. Figure 4 shows that the output of IC1 remains in data F and does not go to data G until
the edge of input data I is entered (after IC1 clocked out data F , although the input data of IC1 is continued from
A to H.)

If data A to H are included in one packet, the data output for each output of the device in data H, (which indicates
the completion of packet operation), is performed out at the edge establishing data J for IC1, data L for IC2, data
O for IC3, and data Q for IC4 from the view of controller. In other words, in order to complete the packet operation
for all the devices connected in cascades, additional bit data equivalent to two times the number of devices
cascaded is needed to be clocked in.

using the input edge for data C.

Additionally , s i n c e e a c h d evice has the time delay, T

D(D/STIN–D/STOUT)

, from input to output, the controller views
that output having a time delay exceeding two bits against a virtual input to IC1. In this example, while, in
practice, the output data H for IC4 is established by the input edge of data Q, it appears to be synchronized with
data S for IC1.

A B C D E F G H I J K L M O P Q R S T U V W X Y Z

IC1 INPUT DATA

t

D(D/STIN–D/STOUT)

M O P Q R SI J K LGC DA B

M O P QI J K LGC DA B F

IC2 INPUT DATA

IC1 OUTPUT DATA

IC3 INPUT DATA

IC2 OUTPUT DATA

IC4 INPUT DATA

IC3 OUTPUT DATA

IC4 OUTPUT DATA

2 bit+t

D(D/STIN–D/STOUT)

A B C D E G H F I J L MK O P Q R S T U V W X

**

* * **

* * **

* * **

A B C D E G H F I J L MK O P Q R S T U V

F

**

* *

**

E

2-bit + tD

(D/STIN – D/STOUT)

H

E

H

UDG–02032

10

Figure 4. Data Transfer Concept in Cascade Connection

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SLLS528 – MARCH 2002

PRINCIPLES OF OPERATION

As shown in Figure 4, in order for all the cascade-connected devices to complete one packet operation,
additional bit data to input to the first stage equivalent to two times the number of devices cascaded is required
to be clocked in. But, in practice, sending just any data is not acceptable, and some packets with bits
corresponding to two times the number of devices connected are needed for synchronization to be successful.
For example, in the case that 16 ICs are connected in cascade, since 16 x 2 = 32 bits are needed to complete
the packet operation of sixteenth IC, OVM information reading packet as a dummy, which does not write any
data to the device, is desirable. Or, an alternative method to send any packet such as use of unused ID (e.g.
FFh) is available.

Figure 5 shows the concept for normal lighting-ON operation (based on pulse-width control method). Internal
BLANK goes high on the falling edge of the 21st bit in the HSYNC packet. If the constant-current output is ON
at that time, it is turned off (except for force on mode), and the data for which the latch flag is set in the HSYNC
packet is la t ched during internal BLANK high-level. Internal BLANK goes low on the rising edge of the gray-scale
clock (GCLK) after the edge of LSB (32nd bit) for HSYNC packet, and the TLC5930 goes into the status that
can be turned on by the constant-current output. The constant-current output is turned on by the next rising edge
of the gray-scale clock.

During power up, the initial value of BLANK is at a high level, therefore, operation for BLANK and
constant-current output when HSYNC packet is entered for the first time as a normal operation is dif ferent from
the example shown in Figure 5.



In addition, since BLANK and the gray-scale clock are ignored in the force-ON mode, the timing to be lighted
on is also different from the example shown in Figure 5.

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SLLS528 – MARCH 2002

PRINCIPLES OF OPERATION

HSYNC packet

DATA INPUT

1

INTERNAL CLOCK

When Gray Scale Clock is Not Sequential

INTERNAL BLANK

GCLK

CONSTANT
CURRENT OUTPUT

When Gray Scale Clock Is Sequential
INTERNAL BLANK

GCLK

CONSTANT
CURRENT OUTPUT

10

20

DATA

Next PacketID CMD

30

LSB of HSYNC Packet

Light ON

Light ON

When Internal Gray Scale Clock Is Used

INTERNAL BLANK

CONSTANT
CURRENT OUTPUT

12

Light ON

Figure 5. Normal Lighting-ON Operation

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