Datasheet TLC5904PZP Datasheet (Texas Instruments)

Drive Capability and Output Counts – 80 mA (Current Sink) x 16 Bits – 120 mA (Current Sink) x 8 Bits

Constant Current Output Range – 5 to 80 mA/10 to 120mA (Selectable by

MODE Terminal) (C urrent Value Setting f or All Output Terminals Using External Resistor and Internal Brightness Control Register)

Constant Current Accuracy – ±4% (Maximum Error Between Bits)

Voltage Applied to Constant Current Output Terminals – Minimum 0.4 V (Output Current 5 mA to

40 mA)

– Minimum 0.7 V (Output Current 40 to

80 mA)

256 Gray Scale Display – Pulse Width Control 256 Steps

Brightness Adjustment – Output Current Adjustment for 32 Steps

(Adjustment for Brightness Deviation Between LED Modules)

– 8 Steps Brightness Control by 8 Times

Speed Gray Scale Control Clock (Brightness Adjustment for Panel)

Error Output Signal Check – Check Error Output Signal Line Such as

Protection Circuit When Operating

description

LED DRIVER

SLLS391 – NOVEMBER 1999

Data Output Timing Selectable – Select Data Output Timing for Shift

OVM (Output Voltage Monitor) – Monitor Voltage on Constant Current

Output Terminals (Detect LED Disconnection and Short Circuit)

WDT (Watchdog Timer) – Turn Output Off When Scan Signal

Stopped

TSD (Thermal ShutDown) – Turn Output Off When Junction

T emperature Exceeds Limit

Data Input – Clock Synchronized 8 Bit Parallel Input

(Schmitt-Triggered Input)

Data Output – Clock Synchronized 8 Bit Parallel Output

(3-State Output)

Input Signal Level . . . CMOS Level

Power Supply Voltage . . . 4.5 V to 5.5 V

Maximum Output Voltage . . . 17 V (Max)

Data Transfer Rate . . . 15 MHz (Max)

Gray Scale Clock Frequency 8 MHz (Max)

Operating Free-Air Temperature Range –20_C to 85_C

100-Pin HTQFP Package (PD=4.7 W, T

= 25°C)

TLC5904

The TLC5904 is a constant current driver incorporating shift register, data latch, and constant current circuitry with current value adjustable and a 256 gray scale display using pulse width control. The output current can be selected as maximum 80 mA with 16 bits or 120 mA with 8 bits, and the current value of constant current output can be set by one external resistor. After this device is mounted on a PCB, the brightness deviation between LED modules (ICs) can be adjusted by external data input, and the brightness control for the panel can be accomplished by the brightness adjustment circuitry . Also, the device incorporates the output voltage monitor (OVM) used for LED open detection (LOD) by monitoring the constant current output. Moreover, the device incorporates watchdog time (WDT) circuitry , which turns the constant current output of f when a scan signal is stopped at the dynamic scanning operation, and thermal shutdown (TSD) circuitry, which turns the constant current output off when the junction temperature exceeds the limit.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5904 LED DRIVER

SLLS391 – NOVEMBER 1999

PZP PACKAGE

(TOP VIEW)

NC NC

OUT4

GNDLED

NC OUT5 OUT6

GNDLED

NC OUT7 OUT8

GNDLED

NC OUT9

OUT10

GNDLED

OUT11

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

OUT3

NCNCNC

100

GNDLEDNCOUT2

OUT1NCNC

GNDLEDNCNC

OUT0NCBCENA

GNDLOG

MODENCVCCLOG

TSENA

DIN7

DIN6

DIN5

DIN4

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

TEST2 DOMODE DIN3 DIN2 DIN1 DIN0 GSCLK BLANK RSEL1 RSEL0 DCLK XENABLE XOE WDTRG XLA TCH XDOWN1 XDOWN2 TEST1 BOUT GSOUT DOUT0 DOUT1 DOUT2 DOUT3 DOUT4

OUT12

GNDLED

OUT13

OUT14

GNDLED

OUT15

IREF

VCCLED

WDCAP

GNDANA

DOUT7

MCENA

VCCANA

DOUT6

DOUT5

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functional block diagram

TLC5904

LED DRIVER

SLLS391 – NOVEMBER 1999

Shift Register and Data Latch

MCENA

BCENA

RSEL0 RSEL1

DIN<0:7>

XENABLE

DCLK

DOMODE

XOE

XLATCH

MODE

GSCLK

BLANK

TSENA

Gray Scale

TSD

8 bits

Counter

DCLK

Controller

OVM

Shift Register

Data Latch

Brightness Control

Shift Register

Data Latch

Gray Scale Control

Shift Register

Data Latch

DELEY

DELEY BOUT

16 x 8 bits

Comparator

DOUT<0:7>

GSOUT

XDOWN1

WDTRG WDCAP

IREF

NOTE: All the input terminals are with Schmitt-triggered inverter except IREF and WDCAP.

WDT

Current Reference

Circuit

Constant Current Driver

16 bits

OUT0 OUT15

16 bits

OVM Comp

XDOWN2

LATCH

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TLC5904 LED DRIVER

SLLS391 – NOVEMBER 1999

functional block diagram for shift register and data latch

MCENA

DIN<0:7>

BCENA

XLATCH

XENABLE

DCLK

Controller

OVM Data Latch

(1 x 8 bit)

OVM Shift Register

(1 x 8 bit)

Brightness Control Data Latch

(1 x 8 bit)

Brightness Control Shift Register

(1 x 8 bit)

Gray Scale Control Data Latch

(16 x 8 bit)

Gray Scale Control Shift Register

(16 x 8 bit / 8 x 8 bit)

16 bit OVM Comparator XDOWN1, 2 Output Driver

Constant Current Driver Control Gray Scale Clock Counter

16 x 8 bit Data Comparator

MODE

RSEL<0:1>

DOMODE

XOE

Note: Enclosed in () is dependent on MODE pin selection.

1 bit

S/R

DOUT<0:7>

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equivalent input and output schematic diagrams

TLC5904

LED DRIVER

SLLS391 – NOVEMBER 1999

Input

DOUT0–7, GSOUT, BOUT

XDOWN1, XDOWN2

VCCLOG

INPUT

GNDLOG

VCCLOG

OUTPUT

GNDLOG

XDOWN1, XDOWN2

OUTn

GNDLOG

OUTn

GNDLED

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5904

I/O

DESCRIPTION

LED DRIVER

SLLS391 – NOVEMBER 1999

TERMINAL

NAME NO.

ÁÁÁÁ

BCENA

ÁÁÁÁ

BLANK

ÁÁÁÁ

BOUT

DCLK

ÁÁÁÁ

DIN0 – DIN7

ÁÁÁÁ

DOMODE

ÁÁÁÁ

DOUT0 – DOUT7

ÁÁÁÁ

GNDANA GNDLOG

GNDLED

ÁÁÁÁ

GSCLK

ÁÁÁÁ

GSOUT

IREF

ÁÁÁÁ

MCENA

ÁÁÁÁ

MODE

ÁÁÁÁ

OUT0 – OUT15

ÁÁÁÁ

RSEL0 RSEL1

ÁÁÁÁ

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1,2,4,6,9,11,14,16,

БББББ

19,21,23,24,25,27, 28,30,31,34,35,37,

БББББ

38,44,50,82,86,88,

БББББ

89,91,92,95,97,98,

БББББ

70,71,72,73,

76,77,78,79

55,54,53,52,

51,49,48,47

43 84

5,10,15,20,

29,36,90,96

69 56

87,93,94,100,

3,7,8,12,13,

17,18,22,26,

32,33,39

66 67

Terminal Functions

Brightness control enable. When BCENA is low, the brightness control latch is set to the

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default value. The output current value in this status is 100% of the setting value by an

external resistor. The frequency division ratio of GSCLK is1/1. When BCENA is high,

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writing to brightness control latch is enabled. Blank(light off). When BLANK is high, all the output of the constant current driver is turned

off. The constant current output, which the gray scale data is not zero, is turned on (LED

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on) synchronizing to the falling edge of GSCLK after the next rising edge of GSCLK when

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BLANK goes from high to low.

Blank signal delay. BOUT is the output with addition of delay time to BLANK. Clock input for data transfer. The input data is from DIN. All data on the shift register is

selected by RSEL0 and RSEL1, and output data at DOUT is shifted by 1 bit synchronizing

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to DCLK. The data except for DOUT is synchronized to the rising edge, and the edge for data from DOUT is determined by the level of DOMODE.

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Input for 8 bit parallel data. These terminals are inputs to the shift register for gray scale

data, brightness control, and OVM. The register selected is determined by RSEL0, 1. Timing select for data output. When DOMODE is low , DOUT0–7 is changed synchronizing

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to the rising edge of DCLK. When DOMODE is high, DOUT0–7 is changed synchronizing to the falling edge of DCLK.

Output for 8 bit parallel data with 3-state. These terminals are outputs to the shift register

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for gray scale data, brightness control, and OVM. The register selected is determined by

RSEL0, 1.

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Analog ground (internally connected to GNDLOG and GNDLED) Logic ground (internally connected to GNDANA and GNDLED)

LED driver ground (internally connected to GNDANA and GNDLOG)

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Clock input for gray scale. The gray scale display is accomplished by lighting LEDs until the number of GSCLK counted is equal to data latched.

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Clock delay for gray scale. GSOUT is the output with the addition of delay time to GSCLK. Constant current value setting. LED current is set to the desired value by connecting an

external resistor between IREF and GND. The 37 times current compares current across

I/O

the external resistor sink on the output terminal.

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OVM enable. When MCENA is low, the OVM latch is set to the default value. The comparison voltage in this status is 0.3V. When MCENA is high, writing to the OVM latch

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is enabled. 8/16 bits select. When MODE is high, 16 bits output is selected. When MODE is low, 8 bits

output is selected.

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No internal connection

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Constant current output

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Shift register data latch switching. When RSEL1 is low, gray scale data shift register latch

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is selected at RSEL0 low, and the brightness control register latch is selected at RSEL0

high. When RSEL1 is high, the OVM register latch is selected at RSEL0 low, and no

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

TERMINAL

NAME NO.

TSENA

ÁÁÁÁ

TEST1 TEST2

THERMAL PAD VCCANA VCCLOG VCCLED

WDTRG

ÁÁÁÁ

WDCAP

ÁÁÁÁ

XDOWN1

ÁÁÁÁ

XDOWN2

ÁÁÁÁ

XENABLE

ÁÁÁÁ

XLATCH

ÁÁÁÁ

XOE

ÁÁÁÁ

58 75

package bottom

45 81 41

ÁÁÁÁ

LED DRIVER

SLLS391 – NOVEMBER 1999

Terminal Functions (Continued)

TSD(thermal shutdown) enable. When TSENA is high, TSD is enabled. When TSENA is

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low, TSD is disabled. TEST. Factory test terminal. TEST1 and TEST2 should be connected to GND for normal

operation. Heat sink pad. This pad is connected to the lowest potential IC or thermal layer. Analog power supply voltage Logic power supply voltage LED driver power supply voltage WDT (watchdog timer) trigger input. By applying a scan signal to this terminal, the scan

signal can be monitored by turning the constant current output off to protect the LED from

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damage if the scan signal stops during the constant period designed. WDT (watchdog timer) detection time adjustment. WDT detection time is adjusted by

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connecting a capacitor between WDCAP and GND. When WDCAP is directly connected

to GND, WDT function is disabled. In this case, WDTRG should be tied to a high or a low

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level. Shutdown. XDOWN1 is configured as open collector. It goes low when constant current

output is shut down by WDT or TSD function.

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OVM comparator output. XDOWN2 is configured as an open collector. It monitors terminal voltage when constant current output is turned on. XDOWN2 goes low when this voltage

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is lower than the level selected by OVM latch. When BLANK is set high, the previous level is held.

DCLK enable. When XENABLE is low, data transfer is enabled. Data transfer starts on the

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rising edge of DCLK after XENABLE goes low. During XENABLE high, no data is

transferred.

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Latch. When XLATCH is high, data on the shift register goes through latch. When XLA TCH is low, data is latched. Accordingly , if data on the shift register is changed during XLA TCH

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high, this new value is latched (level latch). Data output enable. When XOE is low, DOUT0–7 terminals are drived. When XOE is high,

DOUT0–7 terminals go to a high

-impedance state.

TLC5904

absolute maximum ratings (see Note 1)

†

Logic supply voltage, VCC(LOG) – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage for constant current circuit, VCC(LED) – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog supply voltage, VCCANA – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current (dc), I

90 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O(LC)

Input voltage range – 0.3 V to VCCLOG + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V Output voltage range, V

O(DOUTn) O(OUTn)

Storage temperature range, T Continuous total power dissipation at (or below) T

, V

O(BOUT)

and V

–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

and V

O(DOWNn)

O(GSOUT)

– 0.3 V to VCCLOG + 0.3 V. . . . . . . . . . . . . .

– 0.3 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

= 25°C 4.7 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power dissipation rating at (or above) TA = 25°C 38.2m W/°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to the GNDLOG terminal.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5904

DCLK clock frequenc

LED DRIVER

SLLS391 – NOVEMBER 1999

recommended operating conditions

dc characteristics

PARAMETER

Logic supply voltage, VCCLOG Supply voltage for constant current

circuit, VCCLED Analog power supply, VCCANA

Voltage between VCC, V

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Voltage between GND, V

DIFF1

DIFF2

Voltage applied to constant current output, V

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High-level input voltage, V Low-level input voltage, V

High-level output current, I

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Low-level output current, I

Constant output current, I

OUTn

O(LC)

Operating free-air temperature range, T

DIFF1

VCCLOG – VCCLED, VCCANA – VCCLED

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DIFF2

GNDLOG – GNDLED, GNDANA – GNDLED OUT0 to OUT15 off

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VCCLOG = 4.5V, DOUT0 to DOUT7, BOUT, GSOUT

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VCCLOG = 4.5V, XDOWN1, XDOWN2 OUT0 to OUT15

TEST CONDITIONS

= VCCLOG – VCCANA

= GNDLOG – GNDANA

MIN

ÁÁÁ

ÁÁÁÁÁÁÁÁÁ

0.8 VCCLOG GNDLOG

4.5

– 0.3

NOM

5 5 5 0

ÁÁÁ

0.2 VCCLOG

MAX

5.5

0.3

VCCLOG

–1

ÁÁÁÁÁÁÁÁÁ

–20

80 85

UNIT

V V V V

V V

mA mA

°C

ac characteristics, VC C LOG = VCCANA = VCCLED = 4. 5 V to 5.5 V, T

DCLK

twh/t

GSCLK

twh/t

WDT

twh/t

tr/t

PARAMETER

DCLK pulse duration (high or low level) GSCLK clock frequency GSCLK pulse duration (high or low level) WDTRG clock frequency WDTRG pulse duration (high or low level) XLATCH pulse duration (high) Rise/fall time

Setup time

Hold time

TEST CONDITIONS

At single operation At cascade operation (DOMODE = L)

Frequency division ratio 1/1

DINn – DCLK BLANK – GSCLK XENABLE – DCLK XLATCH – DCLK XLATCH – GSCLK RSEL – DCLK↑ RSEL – XLATCH DINn – DCLK

XENABLE – DCLK XLATCH – DCLK RSEL – DCLK↓ RSEL – XLATCH

= – 20 to 85°C (unless otherwise noted)

MIN

TYP

MAX

UNIT

15 10

8 40 50

100 10 20 15 15 15 10 20 15 20 30 20 20

MHz

ns ns ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Supply current (logic)

Supply current (analog)

OLK

Constant out ut leakage current

electrical characteristics, MIN/MAX: VCCLOG= VCCANA TYP: VCCLOG = VCCANA = VCCLED = 5 V, TA = 25°C (unless otherwise noted)

PARAMETER

ÁÁ

LOG

ÁÁ

ANA

LED

ÁÁ

OLC1

OLC2

ÁÁ

∆I

OLC

ÁÁ

I∆

OLC1

ÁÁ

I∆

OLC2

tsd

wdt

IREF

High-level output voltage

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Low-level output voltage

Input current

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Supply current (constant current driver)

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Constant output current (includes error

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between bits) Constant output current (includes error

between bits)

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Constant output current error between bit

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Changes in constant output current depend on supply voltage

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Changes in constant output current depend on output voltage

TSD detection temperature WDT detection temperature Voltage reference

= VCCLED = 4.5 V to 5.5 V, TA = – 20 to 85°C

TEST CONDITIONS

DOUTn, GSOUT, BOUT, IOH = – 1.0mA

DOUTn, GSOUT, BOUT,

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IOL = 1.0mA, XDOWN1, XDOWN2, IOL = 5 mA VIN = VCCLOG or GNDLOG Input signal is static,T SENA = H,

WDCAP = OPEN Data transfer,D CLK = 15 MHz,

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GSCLK = 8 MHz LED turnon, R LED turnoff R LED turnoff, R LED turnoff, R V

= 1 V. R

OUT

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All output bits turn on V

= 1, R

OUT

All output bits turn on V

= 1 V, R

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OUT

= 1 V, R

OUT

ББББББББ

OUT0 to OUT15 (V XDOWN1,2 (V DOUTn,

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OUTn

XDOWNn

= VCCLOG or GND)

VCCLOG=VCCANA=VCCLED=5 V, V

= 1 V, R

OUT

ББББББББ

All output bits turn on V

= 1 V, R

OUT

= 1.24 V, 1 bit output turn on

ББББББББ

IREF

= 1 V to 3 V, R

OUT

= 1.24 V, 1 bit output turn on

IREF

Junction temperature No external capacitor BCENA = L, R

IREF IREF IREF IREF IREF

IREF

OUTn

IREF

= 590 Ω = 590 Ω

= 1180 Ω =590 Ω = 1180 Ω

= 590 Ω

= 1180 Ω

= 590 Ω

= 15 V)

= 590 Ω

= 1180 Ω,

= 590 Ω

MIN

VCCLOG

– 0.5

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁ

150

TLC5904

LED DRIVER

SLLS391 – NOVEMBER 1999

TYP

±1%

1.24

15 30

±1

160

MAX

0.5

0.5 ±1

20 40

0.1

±4%

±4

±2

170

UNIT

µA

5 5

µA

%/V

°C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5904 LED DRIVER

SLLS391 – NOVEMBER 1999

switching characteristics, CL = 15pF, MIN/MAX: VCCLOG= VCCANA

= VCCLED = 4.5 V to 5.5, T

TYP: VCCLOG = VCCANA = VCCLED = 5 V, TA = 25°C (unless otherwise noted)

= –20 to 85°C

PARAMETER

Rise time

Fall time

Propagation delay time

NOTE 2: Until DOUT will be turned on (drive) or turned off (Hi-Z).

TEST CONDITIONS

DOUTn GSOUT, BOUT OUTn (see Figure 1) DOUTn GSOUT, BOUT OUTn (see Figure 1) OUTn+1 – OUTn BLANK↑ – OUT0 BLANK – BOUT GSCLK↓ – OUT0 GSCLK – GSOUT DCLK – DOUTn XOE↓ – DOUTn (see Note 2) XOE↑ – DOUTn (see Note 2) GSCLK – XDOWN2 (∆0.1 V)

MIN

20 15 10 10

TYP

250

200

350

12 13

40 30 20 15

MAX

5000

30 30

20 25

500

70 50 35 25

UNIT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5904

LED DRIVER

SLLS391 – NOVEMBER 1999

PARAMETER MEASUREMENT INFORMATION

90%

10%

100%

50%

51 Ω

15 pF

590 Ω

IREF OUTn

GND

Figure 1. Rise Time and Fall Time Test Circuit for OUTn

100%

50%

100%

50%

VIH or V

VIL or V

VIH or V

VIL or V

Figure 2. Timing Requirements

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5904 LED DRIVER

SLLS391 – NOVEMBER 1999

PRINCIPLES OF OPERATION

constant current output selection by user (80 mA × 16 bits or 120 mA × 8 bits)

When the MODE terminal is set to high, output is selected as 80 mA × 16 bits. When the MODE terminal is set to low, output is selected as 120 mA × 8 bits. By this setting, the shift register latch for gray scale data is changed to the configuration corresponding to the bit selected. Note that two constant output terminals should be tied to an LED such as OUT0-to-OUT1 and OUT2-to-OUT3 because they operate in a pair when the 8 bits output mode is selected. Also, in this case, the current value of the constant current output is the same as the 16 bits output mode. Therefore, when an output current of 120 mA is desired, the resister connected to the IREF terminal should be selected to the same value as the output current of 60 mA.

Table 1. Operation Mode Selection

MODE

80 mA × 16 bits 120 mA × 8 bits

OUTPUT

On the constant current output terminals (OUT0–15), approximately 37 times the current which flows through external resistor, R

(connected between IREF and GND), can flow. The external resistor value is calculated

IREF

using the following equation:

(Ω) ≅ 37 × 1.24 (V)/I

IREF

(A) where BCENA is low.

O(LC)

Note that more current flows if IREF is connect to GND directly.

constant output current operation

The constant current output turns on the sink constant current if all the gray scale data in the gray scale latch is not zero on the falling edge of the gray scale clock after the next rising edge of the gray scale clock when BLANK goes from high to low . After that, the number of the falling edge is counted by the 8-bit gray scale counter. Then, the output counted corresponding to gray scale data is turned off (stop to sink constant current). If the shift register for gray scale is updated during XLA TCH high, data on the gray scale data latch is also updated affecting the constant current output number of the gray scale. Accordingly, during the on-state of constant current output, the XLA TCH should be kept to a low level and the gray scale data latch should be held. If there are constant current output terminals unconnected (includes LED disconnection), the LED should be turned on after writing zero to the gray scale data latch corresponding to output unconnected. Unless this action is taken, the supply current on the constant current driver will increase resulting in the influence of the current value for the constant current output light on.

shift register latch

The device provides three kinds of shift register latchs including the gray scale data, brightness control, and OVM. T o write data into a shift register , DCLK and DIN are utilized. The selection of a shift register will be done by RSEL0 and RSEL1 as shown in below table. Note that RSEL0 and RSEL1 should be changed when both DCLK and XLA TCH are low.

Table 2. Shift Register Latch Selection

RSEL0

L L

H H

RSEL1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SHIFT REGISTER LATCH SELECTED

Shift register latch for gray scale data Shift register latch for brightness control

Shift register latch for OVM N/A (DOUTn is tied to low level)

LED DRIVER

SLLS391 – NOVEMBER 1999

PRINCIPLES OF OPERATION

shift register latch for gray scale data

The shift register latch for the gray scale data is set as an 8 × 1 byte configuration at the 8 bit mode, and as a 16 × 1 byte configuration at the 16 bit mode. The gray scale data, configured as 8 bits, represents the time when constant current output is being turned on, and the data range is 0 to 255 (00h to FFh). When the gray scale data is 0, the time is shortest, and the output is not turned on(light off). On the other hand, when the gray scale data is 255, the time is longest, and it turns on during the time of the 255 clocks from GSCLK. The configuration of the shift register and latch for gray scale data is shown below.

Latch for Gray Scale Data

TLC5904

XLATCH

DOUT0 to 7

XLATCH

DOUT0 to 7

OUT15

Data

(8 bits)

Shift Register for Gray Scale Data

16th byte

DIN7 MSB

DIN0 LSB

Latch for Gray Scale Data

OUT15, 14

Data

(8 bits)

Shift Register for Gray Scale Data

8th byte

DIN7 MSB

DIN0 LSB

OUT14

Data

(8 bits)

15th byte

DIN7 MSB

DIN0 LSB

16 Bit Mode (MODE=H, RSEL0 and RSEL1=L)

OUT13, 12

Data

(8 bits)

7th byte

DIN7 MSB

DIN0 LSB

OUT1

Data

(8 bits)

2nd byte

DIN7 MSB

DIN0 LSB

OUT3, 2

Data

(8 bits)

2nd byte

DIN7 MSB

DIN0 LSB

OUT0

Data

(8 bits)

1st byte

DIN7 MSB

DIN0 LSB

OUT1, 0

Data

(8 bits)

1st byte

DIN7 MSB

DIN0 LSB

DCLK

DIN0 to 7

DCLK

DIN0 to 7

8 Bit Mode (MODE=L, RSEL0 and RSEL1=L)

Figure 3. Relationship Between Shift Register and Latch for Gray Scale Data

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC5904 LED DRIVER

SLLS391 – NOVEMBER 1999

PRINCIPLES OF OPERATION

shift register latch for brightness control and OVM

The shift register latch for both brightness control and OVM (Output Voltage Monitor) is configured with a 1 x 1 byte. In the shift register latch for brightness control, the division ratio of GSCLK can be set and the output current value on the constant current output can be adjusted. In the shift register latch for OVM, the comparison voltage at OVM comparator on the constant current output terminals (OUT0 to OUT15) can be set and the output signal for both XDOWN1 and XDOWN2 can be forced to low level. When power up, the latch data is indeterminate and the shift register is not initialized. Data should be written to the shift register latch prior to turning the constant current output on (BLANK=L) when these functions are used. Also, it is inhibited to rewrite the latch value for brightness control when the constant current output is turned on. When these functions are not used, the latch value can be set to the default value setting BCENA or MCENA to low level (tied to GND). The configuration of the shift register and the latch for brightness control and monitor control is shown in below.

Latch for Brightness Control

GSCLK Division Ratio Data Set Current Data Adjusted On Constant Current Output

GSCLK Division Ratio Data Set

XLATCH

00011111

MSB LSB MSB LSB

(Note A)

Shift Register for Brightness Control

DOUT0 to 7

XLATCH

DOUT0 to 7

DIN7

DATA

Latch for OVM

Shift Register for OVM

DIN7

DATA

Note A: Indicates default value at the BCENA terminal = 0 if the brightness control latch = 1 Note B: Indicates default value at the MCENA terminal = 0 if the OVM latch =1

DIN6

DATA

DIN6

DATA

N/A

DIN5

DATA

DIN5

DATA

DIN4

DATA

DIN4

DATA

DIN3

DATA

0001

MSB LSB

DIN3

DATA

DIN2

DATA

Monitor Control Data

DIN2

DATA

DIN1

DATA

DIN1

DATA

DIN0

DATA

DIN0

DATA

(Note B)

DIN0 to 7

Figure 4. Relationship Between Shift Register and Latch for Brightness Control and OVM

write data to shift register latch

The shift register latch written to is selected using the RSEL0 and RSEL1 terminals. The data is applied to the DIN data input terminal and is clocked into the shift register synchronizing to the rising edge of DCLK after XENABLE is pulled low . The shift register for the gray scale data is 8 bits length at 8 bit mode resulting in eight times DCLK, and 16 bit length at 16 bit mode resulting in sixteen times DCLK, and as for the brigtness control and monitor control resulting one times DCLK input. At the number of DCLK input for each case, data can be written into the shift register. In this condition, when XLATCH is pulled high, data in the shift register is clocked into the latch (data through), and when XLATCH is pulled low, the data is held (latch).

DCLK DIN0 to 7

DCLK

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LED DRIVER

SLLS391 – NOVEMBER 1999

PRINCIPLES OF OPERATION

brightness control function

By writting data into the brightness control latch, the current on all constant current outputs can be adjusted to control the variation of brightness between ICs and the division ratio for the gray scale clock can be set to control the variation of brigtness for the total panel system.

output current adjustment on all constant current outputs – brightness adjustment between ICs

By using the lower 5 bits of the brightness control latch, the output current can be adjusted to 32 steps. 1 step is 1.6% of the current ratio between 100% and 51.6% when the set output current is 100% by an external resistor. By using this function, the brightness control between modules (ICs) can be adjusted sending desired data externally even if ICs are mounted on print-circuit board. When BCENA is pulled low, output current is set to 100%.

Table 3. Relative Current Ratio For Total Constant Current Output

TLC5904

CODE

MSB 00000 LSB

БББББ

. . .

11110

†

11111

†

BCENA is low.

CURRENT RATIO (%)

51.6 .

БББББ

. . .

98.4

100

20 (mA)

10.3 .

ÁÁ

. .

ÁÁ

19.7

20.0

80 (mA)

41.3 .

ÁÁ

. .

ÁÁ

78.7

80.0

(TYP)

IREF

0.63 .

ÁÁÁ

. .

ÁÁÁ

1.22

1.24

frequency division ratio setting for gray scale clock – panel brightness adjustment

By using the upper 3 bits of the brightness control latch, the gray scale clock can be divided into a frequency division ratio of 1/1 to 1/8. If the gray scale clock is set to 8 times the speed (256x8=2048) of frequency during horizontal scanning time, the brightness can be adjusted to 8 steps selecting the frequency division ratio. By using this function, the total panel brightness can be adjusted at once, and it applies to the brightness of day or night circumstances. When BCENA is pulled low, the gray scale clock is not divided. When BCENA is pulled high, the brightness can be adjusted (see Table 4).

Table 4. Relative Brightness Ratio For Total Constant Current Output

CODE

ÁÁÁÁ

MSB 000 LSB

ÁÁÁÁ

. .

. 110 111

†

BCENA is low.

FREQUENCY

БББББ

DIVISION RATIO

†

БББББ

1/1

. . .

. 1/7 1/8

RELATIVE BRIGHTNESS RATIO

ББББББББ

(%)

12.5 .

ББББББББ

. . .

87.5

100

OVM (output voltage monitor) function

By writing data into the OVM latch, the comparison voltage for the voltage comparator of OUT0 to OUT15 can be set, and the output signal for XDOWN1 and XDOWN2 can be checked.

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TLC5904 LED DRIVER

SLLS391 – NOVEMBER 1999

PRINCIPLES OF OPERATION

OVM comparator

The OVM comparator compares the voltage on the constant current output terminal during turnon with comparison voltage set by the OVM latch. When the voltage on the constant current output terminal is lower, XDOWN2 goes low. As shown in Figure 5, the comparator is provided in every output portion, and the comparison result corresponding to the output to be turned on appears in the XDOWN2 terminal. Since the XDOWN2 terminal is an open-collector output, outputs of multiple ICs are brought together.

The output terminal for comparison result is only XDOWN2. The voltage on all the constant current output can be checked to monitor XDOWN2 turning output on in turn. The voltage on the constant current output, when turned on, can be also measured changing the comparison voltage set by the OVM latch. Using this function, sensing (LOD function) an LED disconnection (output voltage is below 0.3 V) and short circuit (output voltage is extremely high) can be detected and specifies which LED encountered this failure. Also, by monitoring the output voltage and controlling the voltage across anode of the LED to minimize the voltage on the constant current output (approximately 0.7 V at I Furthermore, by setting BLANK to low during LED on, the comparison result immediately before can be held. Thus, synchronizing timing to check XDOWN2 from the system to the LED lighting timing is not required. Note that the gray scale data being turned on should be a minimum of 5 µs since XDOWN2 output is required approximately 5 µs after the constant current output is turned on. The comparison result is also required approximately 5 µs after the changed latch data.

= 80 mA), the temperature rising of the chip can be minimized.

OUT0

Internal OUT0

Turn ON Signal

OUT1

Internal OUT1

Turn ON Signal

OUT14

Internal OUT014

Turn ON Signal

OUT15

Internal OUT015

Turn ON Signal

– +

Comparison Voltage

XDOWN2

LATCH

BLANK When BLANK is high, hold the data

When BLANK is low, data is out.

Figure 5. OVM functional diagram

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VOLTAGE

LED DRIVER

SLLS391 – NOVEMBER 1999

PRINCIPLES OF OPERATION

output signal check for XDOWN1, XDOWN2

XDOWN1 or XDOWN2 can be forced to low level by setting the appropriate latch value for OVM. This allows the investigation of the correct connection of XDOWN1 or XDOWN2 to the external system.

OVM comparator setting

Setting the OVM latch is shown in Table 5. Note that the comparison voltage is set to the default value of 0.3 V when MCENA is tied to the low level.

Table 5. OVM Setting

MONITOR CONTROL

ББББББ

MSB

DATA

LSB

0000

†

0001

0010 0011 0100 0101 0110 0111

1000 1001 1010 1011 1100 1101

1110

1111

†

MCENA is low.

ÁÁÁÁ

COMPARISON

NO COMPARISON

0.3 V

0.4 V

0.5 V

0.6 V

0.7 V

0.8 V

0.9 V

1.0 V

1.1 V

1.2 V 1/3 × VCCANA 1/2 × VCCANA 2/3 × VCCANA

0.3 V

ББББББ

XDOWN1

DEPEND ON TSD/WDT DEPEND ON TSD/WDT DEPEND ON TSD/WDT DEPEND ON TSD/WDT DEPEND ON TSD/WDT DEPEND ON TSD/WDT DEPEND ON TSD/WDT DEPEND ON TSD/WDT

DEPEND ON TSD/WDT DEPEND ON TSD/WDT DEPEND ON TSD/WDT DEPEND ON TSD/WDT DEPEND ON TSD/WDT DEPEND ON TSD/WDT

DEPEND ON TSD/WDT

ББББББББ

XDOWN2

HI–Z DEPEND ON OVM COMPARATOR DEPEND ON OVM COMPARATOR DEPEND ON OVM COMPARATOR DEPEND ON OVM COMPARATOR DEPEND ON OVM COMPARATOR DEPEND ON OVM COMPARATOR DEPEND ON OVM COMPARATOR

DEPEND ON OVM COMPARATOR DEPEND ON OVM COMPARATOR DEPEND ON OVM COMPARATOR DEPEND ON OVM COMPARATOR DEPEND ON OVM COMPARATOR DEPEND ON OVM COMPARATOR

DEPEND ON OVM COMPARATOR

TLC5904

DOUT output timing selection

The timing for the DOUT output change can be switched by selecting the DOMODE level. When DOMODE is low, the DOUT is changed synchronizing to the rising edge of DCLK. When DOMODE is high, the DOUT is changed synchronizing to the falling edge of DCLK. When the shift operation with DOMODE is high, data can be protected from a shift error even if the DCLK signal is buffered externally in serial. In this case, when ICs are connected in cascade, the maximum data transfer speed at will be slower than the case of DOMODE low.

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TLC5904 LED DRIVER

SLLS391 – NOVEMBER 1999

PRINCIPLES OF OPERATION

protection

This device incorporates WDT and TSD functions. If WDT or TSD functions, constant current output is stopped and XDOWN1 goes low. Therefore, by monitoring the XDOWN1 terminal, these failures can be detected immediately . Since the XDOWN1 output is configured as an open collector , outputs of multiple ICs are brought together.

WDT (watchdog timer)

The constant current output is forced to turn off and XDOWN1 goes low when the fixed period elapsed after the signal applied to WDTRG has not been changed. Therefore, by connecting a scan signal (signal to control line displayed) to WDTRG, the stop of the scan signal can be detected and the constant current output is turned off. This prevents the LED from burning and damage caused by continuous LED turnon at the dynamic scanning operation. The detection time can be set using an external capacitor, Cext. The typical value is approximately 10 ms without a capacitor, 160 ms with a 1000 pF capacitor and 1500 ms with a 0.01 µF capacitor . During static operation, the WDT function is disabled connecting WDCAP to GND (high or low level should be applied to WDTRG). Note that normal operations will resume changing the WDTRG level when WDT functions.

WDT operational time: T (ms) ≅ 10 + 0.15 × Cext (pF)

t – Time – ms

1500

160

0 0.001 0.01

Cext – External Capacitor – µF

Scan Signal

Cext

TLC5904

WDTRG

WDCAP

Figure 6. WDT Operational Time and Usage Example

TSD (thermal shutdown)

When the junction temperature exceeds the limit, TSD starts to function and turns the constant current output off, and XDOWN1 goes low . When TSD is used, TSENA should be pulled high. When TSD is not used, TSENA should be pulled low. To recover from the constant current output off-state to normal operations, the power supply should be turned off or TSENA should be pulled low once.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

LED DRIVER

SLLS391 – NOVEMBER 1999

PRINCIPLES OF OPERATION

noise reduction

concurrent switching noise reduction

The concurrent switching noise has a potential to occur when multiple outputs turn on or off at the same time. T o prevent this noise, the device has delay output terminals such as XGSOUT and BOUT for GSCLK (gray scale clock) and BLANK (blanking signal) respectively. By connecting these outputs to the GSCLK and BLANK terminals of next stage IC, it allows differences in the switching time between ICs. When GSCLK is output to GSOUT through the device, duty will be changed between input and output, and the number of stages to be connected will be limited depending on frequency.

output slope

When the output current is 80 mA, the time to change constant current output to turnon and turnoff is approximately 150 ns and 250 ns respectively . This allows reduced concurrent switching noise when multiple outputs turn on or off at the same time.

delay between constant current output

The constant current output has a delay time of approximately 30 ns between outputs. This means approximately 450 ns delay time exists between OUT0 and OUT15. This time differences by delay allows reduced concurrent switching noise as well as the output slope previously described. This delay time has the same value at the 8 bits or 16 bits operation mode.

TLC5904

power supply

The followings should be taken into consideration:

1) VCCLOG, VCCANA, and VCCLED should be supplied by a single power supply to minimize voltage differences between these terminals.

2) The bypass capacitor should be located between the power supply and GND to eliminate the variation of power supply voltage.

GND

Although GNDLOG, GNDANA, and GNDLED are internally tied together, these terminals should be externally connected to reduce noise influence.

thermal pad

The thermal pad should be connected to GND to eliminate the noise influence when it is connected to the bottom side of IC chip. Also, the desired thermal effect will be obtained by connecting this pad to the PCB pattern with better thermal conductivity.

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TLC5904 LED DRIVER

SLLS391 – NOVEMBER 1999

power rating – free-air temperature

PRINCIPLES OF OPERATION

†

4.7

2.4

– Total Power Dissipation – W

0 25 85–20

TA – Free–Air Temperature – °C

†

VCCLOG=VCCANA=VCCLED=5.0V, I

NOTES: A. IC is mounted on PCB. PCB size: 102 x 76 × 1.6 [mm3], four layers with the internal two layer being plane. The thermal pad is soldered

to the PCB pattern of 10 × 10 [mm2]. For operation above 25°C free-air temperature, derate linearly at the rate of 38.2 mW/°C.

B. The thermal impedance will be varied depending on mounting conditions. Since the PZP package established low thermal

impedance by radiating heat from the thermal pad, the thermal pad should be soldered to the pattern with low a thermal impedance.

C. Consider thermal characteristics when selecting the material for the PCB, since the temperature will rise around the thermal pad.

= 80 mA, ICC is typical value.

OLC

3.2

1.48

Output Voltage (Constant Current) – V

Figure 7. Power Rating

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constant output current

– mA

OLC

TLC5904

LED DRIVER

SLLS391 – NOVEMBER 1999

PRINCIPLES OF OPERATION

0.1 R

– kΩ

IREF

NOTE: Conditions: V

(mA)

OLC

(kW)

IREF

NOTE: Shows the output current at the 16 bit mode. and at the 8 bit mode (MODE=L). Output current is the sum of both outputs. This sum current

should be set from 10 mA to 120 mA. The resistor, R influence.

≅

OUT

≅

= 1.0V, V

IREF

(mA)

OLC

(V) (kW)

IREF

= 1.24V

, should be located as close to the IREF terminal as possible to avoid the noise

IREF

10.01.0

Figure 8. Current on Constant Current Output vs External Resistor

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T l

R l

7 11

RSEL0

TLC5904

LED DRIVER

SLLS391 – NOVEMBER 1999

emp ate

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

RSEL1

XOE

XENABLE

DCLK

DIN0

DIN7

XLATCH

th (DIN–DCLK)

tsu (XENABLE–DCLK)

tsu (DIN–DCLK)

D00_A D01_A D02_A D0F_A D00_B D0D_B D0E_B D0F_B D00_C D01_CD0E_A

D70_A D71_A D72_A D7F_A D70_B D7D_B D7E_B D7F_B D70_C D71_CD7E_A

1/f

DCLK

twl (DCLK) twh (DCLK)

th (XLATCH–DCLK)

th (XENABLE–DCLK)

tsu (XLATCH–DCLK)

e ease

ate:

– –

DOUT0

DOUT7

HI–Z

NOTE: MODE = H

td (XOE↓–DOUT)

twh (XLATCH)

D00_A D01_A D0E_A D0F_A D00_B

D70_A D71_A D7E_A D7F_A D70_B

td (DCLK–DOUT)

Figure 9. Timing Diagram (Shift Register for Gray Scale Data)

td (XOE↑–DOUT)

MCENA

RSEL0

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• 23

RSEL1

XOE

XENABLE

DCLK

DIN0

DIN7

XLATCH

MCL_0

MCL_1–3

DOUT0

Default Value “1”

(Monitor Control Latch Internal Signal)

Default Value “0”

td (XOE↓–DOUT)

HI–Z

tsu (RSEL–XLATCH) th (RSEL–XLATCH)

tsu (RSEL–DCLK)

D0_A D0_C D0_J D0_K D0_L D0_M D0_N D0_OD0_B

D7_A D7_C D7_J D7_K D7_L D7_M D7_N D7_OD7_B

td (DCLK–DOUT)

th (XLATCH–DCLK)

twh (XLATCH)

D<0>_A

D<1:3>_A

D0_E D0_G D0_H D0_I

D0_FD0_A D0_C

tsu (RSEL–DCLK)

Default Value “1”

Default Value “0”

td (XOE↑–DOUT)

SLLS391 – NOVEMBER 1999

LED DRIVER

DOUT7

HI–Z

TLC5904

D7_FD7_A D7_C D7_E D7_G D7_H D7_I

Figure 10. Timing Diagram (Shift Register for Monitor Control)

T l

R l

7 11

BCENA

RSEL0

RSEL1

tsu (RSEL–XLATCH) th (RSEL–XLATCH)

TLC5904

LED DRIVER

SLLS391 – NOVEMBER 1999

emp ate

e ease

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

XOE

XENABLE

tsu (RSEL–DCLK)

DCLK

DIN0

DIN7

XLATCH

BCL_0–4

BCL_5–7

Default Value “1”

(Brightness Control Latch Internal Signal)

Default Value “0”

td (XOE↓–DOUT)

D0_A D0_C D0_J D0_K D0_L D0_M D0_N D0_OD0_B

D7_A D7_C D7_J D7_K D7_L D7_M D7_N D7_OD7_B

td (DCLK–DOUT)

th (XLATCH–DCLK)

twh (XLATCH)

D<0:4>_A

D<5:7>_A

tsu (RSEL–DCLK)

Default Value “1”

Default Value “0”

td (XOE↑–DOUT)

ate:

– –

DOUT0

DOUT7

HI–Z

D0_E D0_G D0_H D0_I

D0_FD0_A D0_C

D7_FD7_A D7_C D7_E D7_G D7_H D7_I

Figure 11. Timing Diagram (Shift Register for Brightness Control)

XLATCH

BLANK

GSCLK

1/f

WDT

tsu (XLATCH–GSCLK)

tsu (BLANK–GSCLK)

td (BLANK–OUT0)

1/f

GSCLK

twl (GSCLK)

twh (GSCLK)

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• 25

WDTRG

twl (WDTRG)

OUT0

OUT1

OUT15

XDOWN1

XDOWN2

BOUT

twh (WDTRG)

td (BLANK–OUT0)

td (OUTn+1–OUTn)

td (GSCLK–XDOWN2)

td (BLANK–BOUT)

td (GSCLK–GSOUT)

td (GSCLK–OUT0)

OFF OFFON(Note A)

OFF OFF

OFF OFF OFF

ON(Note A)

NOTE A: ON or OFF, or ON time is varied dpend on the gray scale data and BLANK.

HI–Z

td (GSCLK–OUT0)

(Note A) (Note A)OFF

td (OUTn+1–OUTn)

OFF

......

(Note B) (Note B)

NOTE B: LED disconnection

(Note A)

wdt

(Note A)

SLLS391 – NOVEMBER 1999

LED DRIVER

TLC5904

GSOUT

Figure 12. Timing Diagram (Constant Current Output)

TLC5904 LED DRIVER

SLLS391 – NOVEMBER 1999

MECHANICAL DATA

PZP (S-PQFP-G100) PowerPAD PLASTIC QUAD FLATPACK

100

1,05

0,95

0,50

12,00 TYP

14,20

13,80 16,20

15,80

0,27 0,17

0,08

Thermal Pad (see Note D)

0,15 0,05

0,13 NOM

Gage Plane

0,25

0°–7°

0,75 0,45

1,20 MAX

NOTES: A. All linear dimensions are in millimeters.

PowerPAD is a trademark of Texas Instruments Incorporated.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.

This pad is electrically and thermally connected to the backside of the die and possibly selected leads. The demensions of the thermal pad are 5 mm x 5 mm. The pad is centered on the bottom of the package.

E. Falls within JEDEC MS-026

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Seating Plane

0,08

4146929/A 04/99

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Datasheet TLC5904PZP Datasheet (Texas Instruments)

Specifications and Main Features

Frequently Asked Questions

User Manual