Texas Instruments TLC5904PZP Datasheet
D
Drive Capability and Output Counts
– 80 mA (Current Sink) x 16 Bits
– 120 mA (Current Sink) x 8 Bits
D
Constant Current Output Range
– 5 to 80 mA/10 to 120mA (Selectable by
MODE Terminal) (C urrent Value Setting f or
All Output Terminals Using External
Resistor and Internal Brightness Control
Register)
D
Constant Current Accuracy
– ±4% (Maximum Error Between Bits)
D
Voltage Applied to Constant Current Output
Terminals
– Minimum 0.4 V (Output Current 5 mA to
40 mA)
– Minimum 0.7 V (Output Current 40 to
80 mA)
D
256 Gray Scale Display
– Pulse Width Control 256 Steps
D
Brightness Adjustment
– Output Current Adjustment for 32 Steps
(Adjustment for Brightness Deviation
Between LED Modules)
– 8 Steps Brightness Control by 8 Times
Speed Gray Scale Control Clock
(Brightness Adjustment for Panel)
D
Error Output Signal Check
– Check Error Output Signal Line Such as
Protection Circuit When Operating
description
LED DRIVER
SLLS391 – NOVEMBER 1999
D
Data Output Timing Selectable
– Select Data Output Timing for Shift
Register Relative to Clock
D
OVM (Output Voltage Monitor)
– Monitor Voltage on Constant Current
Output Terminals (Detect LED
Disconnection and Short Circuit)
D
WDT (Watchdog Timer)
– Turn Output Off When Scan Signal
Stopped
D
TSD (Thermal ShutDown)
– Turn Output Off When Junction
T emperature Exceeds Limit
D
Data Input
– Clock Synchronized 8 Bit Parallel Input
(Schmitt-Triggered Input)
D
Data Output
– Clock Synchronized 8 Bit Parallel Output
(3-State Output)
D
Input Signal Level . . . CMOS Level
D
Power Supply Voltage . . . 4.5 V to 5.5 V
D
Maximum Output Voltage . . . 17 V (Max)
D
Data Transfer Rate . . . 15 MHz (Max)
D
Gray Scale Clock Frequency
8 MHz (Max)
D
Operating Free-Air Temperature Range
–20_C to 85_C
D
100-Pin HTQFP Package (PD=4.7 W,
T
= 25°C)
A
TLC5904
The TLC5904 is a constant current driver incorporating shift register, data latch, and constant current circuitry
with current value adjustable and a 256 gray scale display using pulse width control. The output current can be
selected as maximum 80 mA with 16 bits or 120 mA with 8 bits, and the current value of constant current output
can be set by one external resistor. After this device is mounted on a PCB, the brightness deviation between
LED modules (ICs) can be adjusted by external data input, and the brightness control for the panel can be
accomplished by the brightness adjustment circuitry . Also, the device incorporates the output voltage monitor
(OVM) used for LED open detection (LOD) by monitoring the constant current output. Moreover, the device
incorporates watchdog time (WDT) circuitry , which turns the constant current output of f when a scan signal is
stopped at the dynamic scanning operation, and thermal shutdown (TSD) circuitry, which turns the constant
current output off when the junction temperature exceeds the limit.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
TLC5904
LED DRIVER
SLLS391 – NOVEMBER 1999
PZP PACKAGE
(TOP VIEW)
NC
NC
OUT4
NC
GNDLED
NC
OUT5
OUT6
NC
GNDLED
NC
OUT7
OUT8
NC
GNDLED
NC
OUT9
OUT10
NC
GNDLED
NC
OUT11
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
OUT3
NCNCNC
99
100
27
26
98
28
97
29
GNDLEDNCOUT2
96
30
95
31
OUT1NCNC
93
94
33
32
92
34
GNDLEDNCNC
90
91
36
35
OUT0NCBCENA
87
88
89
38
39
37
86
40
85
41
GNDLOG
MODENCVCCLOG
81
82
83
84
45
44
43
42
TSENA
DIN7
DIN6
78
79
80
48
47
46
DIN5
DIN4
76
77
50
49
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
TEST2
DOMODE
DIN3
DIN2
DIN1
DIN0
GSCLK
BLANK
RSEL1
RSEL0
DCLK
XENABLE
XOE
WDTRG
XLA TCH
XDOWN1
XDOWN2
TEST1
BOUT
GSOUT
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
NC
NC
OUT12
NC
NC
GNDLED
NC
OUT13
OUT14
NC
GNDLED
NC
NC
OUT15
IREF
VCCLED
NC
WDCAP
GNDANA
DOUT7
MCENA
VCCANA
NC
DOUT6
DOUT5
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
TLC5904
LED DRIVER
SLLS391 – NOVEMBER 1999
Shift Register and Data Latch
MCENA
BCENA
RSEL0
RSEL1
DIN<0:7>
XENABLE
DCLK
DOMODE
XOE
XLATCH
MODE
GSCLK
BLANK
TSENA
Gray Scale
TSD
8
8 bits
Counter
DCLK
Controller
OVM
Shift Register
Data Latch
8
Brightness Control
Shift Register
Data Latch
Gray Scale Control
Shift Register
Data Latch
DELEY
DELEY BOUT
16 x 8 bits
Comparator
DOUT<0:7>
GSOUT
XDOWN1
WDTRG
WDCAP
IREF
NOTE: All the input terminals are with Schmitt-triggered inverter except IREF and WDCAP.
WDT
Current Reference
Circuit
Constant Current Driver
16 bits
OUT0 OUT15
16 bits
OVM Comp
XDOWN2
LATCH
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TLC5904
LED DRIVER
SLLS391 – NOVEMBER 1999
functional block diagram for shift register and data latch
MCENA
DIN<0:7>
BCENA
XLATCH
XENABLE
DCLK
DCLK
Controller
OVM Data Latch
(1 x 8 bit)
OVM Shift Register
(1 x 8 bit)
Brightness Control Data Latch
(1 x 8 bit)
Brightness Control Shift Register
(1 x 8 bit)
Gray Scale Control Data Latch
(16 x 8 bit)
Gray Scale Control Shift Register
(16 x 8 bit / 8 x 8 bit)
16 bit OVM Comparator
XDOWN1, 2 Output Driver
88
Constant Current Driver Control
Gray Scale Clock Counter
8
16 x 8 bit Data Comparator
8
8
MODE
RSEL<0:1>
DOMODE
XOE
Note: Enclosed in () is dependent
on MODE pin selection.
1 bit
S/R
8
8
DOUT<0:7>
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
equivalent input and output schematic diagrams
TLC5904
LED DRIVER
SLLS391 – NOVEMBER 1999
Input
DOUT0–7, GSOUT, BOUT
XDOWN1, XDOWN2
VCCLOG
INPUT
GNDLOG
VCCLOG
OUTPUT
GNDLOG
XDOWN1, XDOWN2
OUTn
GNDLOG
OUTn
GNDLED
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TLC5904
I/O
DESCRIPTION
Á
Á
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Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
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Á
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Á
LED DRIVER
SLLS391 – NOVEMBER 1999
TERMINAL
NAME NO.
ÁÁÁÁ
BCENA
ÁÁÁÁ
ÁÁÁÁ
BLANK
ÁÁÁÁ
BOUT
DCLK
ÁÁÁÁ
ÁÁÁÁ
DIN0 – DIN7
ÁÁÁÁ
DOMODE
ÁÁÁÁ
DOUT0 – DOUT7
ÁÁÁÁ
GNDANA
GNDLOG
GNDLED
ÁÁÁÁ
GSCLK
ÁÁÁÁ
GSOUT
IREF
ÁÁÁÁ
MCENA
ÁÁÁÁ
MODE
ÁÁÁÁ
ÁÁÁÁ
NC
ÁÁÁÁ
ÁÁÁÁ
OUT0 – OUT15
ÁÁÁÁ
ÁÁÁÁ
RSEL0
RSEL1
ÁÁÁÁ
БББББ
БББББ
БББББ
БББББ
БББББ
БББББ
БББББ
БББББ
БББББ
БББББ
БББББ
БББББ
БББББ
1,2,4,6,9,11,14,16,
БББББ
19,21,23,24,25,27,
28,30,31,34,35,37,
БББББ
38,44,50,82,86,88,
БББББ
89,91,92,95,97,98,
БББББ
БББББ
БББББ
БББББ
85
68
57
65
70,71,72,73,
76,77,78,79
74
55,54,53,52,
51,49,48,47
43
84
5,10,15,20,
29,36,90,96
69
56
40
46
83
99
87,93,94,100,
3,7,8,12,13,
17,18,22,26,
32,33,39
66
67
Terminal Functions
Brightness control enable. When BCENA is low, the brightness control latch is set to the
Á
ББББББББББББББББББББ
default value. The output current value in this status is 100% of the setting value by an
I
external resistor. The frequency division ratio of GSCLK is1/1. When BCENA is high,
Á
ББББББББББББББББББББ
writing to brightness control latch is enabled.
Blank(light off). When BLANK is high, all the output of the constant current driver is turned
off. The constant current output, which the gray scale data is not zero, is turned on (LED
Á
ББББББББББББББББББББ
I
on) synchronizing to the falling edge of GSCLK after the next rising edge of GSCLK when
Á
ББББББББББББББББББББ
BLANK goes from high to low.
O
Blank signal delay. BOUT is the output with addition of delay time to BLANK.
Clock input for data transfer. The input data is from DIN. All data on the shift register is
selected by RSEL0 and RSEL1, and output data at DOUT is shifted by 1 bit synchronizing
I
Á
ББББББББББББББББББББ
to DCLK. The data except for DOUT is synchronized to the rising edge, and the edge for
data from DOUT is determined by the level of DOMODE.
Á
ББББББББББББББББББББ
Input for 8 bit parallel data. These terminals are inputs to the shift register for gray scale
I
data, brightness control, and OVM. The register selected is determined by RSEL0, 1.
Timing select for data output. When DOMODE is low , DOUT0–7 is changed synchronizing
ÁIББББББББББББББББББББ
to the rising edge of DCLK. When DOMODE is high, DOUT0–7 is changed synchronizing
to the falling edge of DCLK.
Output for 8 bit parallel data with 3-state. These terminals are outputs to the shift register
Á
ББББББББББББББББББББ
for gray scale data, brightness control, and OVM. The register selected is determined by
O
RSEL0, 1.
Á
ББББББББББББББББББББ
Analog ground (internally connected to GNDLOG and GNDLED)
Logic ground (internally connected to GNDANA and GNDLED)
LED driver ground (internally connected to GNDANA and GNDLOG)
Á
ББББББББББББББББББББ
Clock input for gray scale. The gray scale display is accomplished by lighting LEDs until
the number of GSCLK counted is equal to data latched.
ÁIББББББББББББББББББББ
O
Clock delay for gray scale. GSOUT is the output with the addition of delay time to GSCLK.
Constant current value setting. LED current is set to the desired value by connecting an
external resistor between IREF and GND. The 37 times current compares current across
I/O
the external resistor sink on the output terminal.
Á
ББББББББББББББББББББ
OVM enable. When MCENA is low, the OVM latch is set to the default value. The
comparison voltage in this status is 0.3V. When MCENA is high, writing to the OVM latch
ÁIББББББББББББББББББББ
is enabled.
8/16 bits select. When MODE is high, 16 bits output is selected. When MODE is low, 8 bits
I
output is selected.
Á
ББББББББББББББББББББ
Á
ББББББББББББББББББББ
No internal connection
Á
ББББББББББББББББББББ
Á
ББББББББББББББББББББ
Constant current output
ÁOББББББББББББББББББББ
Shift register data latch switching. When RSEL1 is low, gray scale data shift register latch
Á
ББББББББББББББББББББ
is selected at RSEL0 low, and the brightness control register latch is selected at RSEL0
I
high. When RSEL1 is high, the OVM register latch is selected at RSEL0 low, and no
Á
ББББББББББББББББББББ
register latch is selected at RSEL0 high.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
I/O
DESCRIPTION
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Á
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Á
Á
Á
TERMINAL
NAME NO.
TSENA
ÁÁÁÁ
TEST1
TEST2
THERMAL PAD
VCCANA
VCCLOG
VCCLED
WDTRG
ÁÁÁÁ
ÁÁÁÁ
WDCAP
ÁÁÁÁ
XDOWN1
ÁÁÁÁ
XDOWN2
ÁÁÁÁ
ÁÁÁÁ
XENABLE
ÁÁÁÁ
XLATCH
ÁÁÁÁ
XOE
80
ÁÁÁÁ
58
75
package bottom
45
81
41
62
ÁÁÁÁ
ÁÁÁÁ
42
ÁÁÁÁ
60
ÁÁÁÁ
59
ÁÁÁÁ
ÁÁÁÁ
64
ÁÁÁÁ
61
ÁÁÁÁ
63
LED DRIVER
SLLS391 – NOVEMBER 1999
Terminal Functions (Continued)
TSD(thermal shutdown) enable. When TSENA is high, TSD is enabled. When TSENA is
I
Á
Á
Á
Á
Á
Á
Á
Á
Á
БББББББББББББББББББ
low, TSD is disabled.
TEST. Factory test terminal. TEST1 and TEST2 should be connected to GND for normal
I
operation.
Heat sink pad. This pad is connected to the lowest potential IC or thermal layer.
Analog power supply voltage
Logic power supply voltage
LED driver power supply voltage
WDT (watchdog timer) trigger input. By applying a scan signal to this terminal, the scan
signal can be monitored by turning the constant current output off to protect the LED from
I
БББББББББББББББББББ
damage if the scan signal stops during the constant period designed.
WDT (watchdog timer) detection time adjustment. WDT detection time is adjusted by
БББББББББББББББББББ
connecting a capacitor between WDCAP and GND. When WDCAP is directly connected
I
to GND, WDT function is disabled. In this case, WDTRG should be tied to a high or a low
БББББББББББББББББББ
level.
Shutdown. XDOWN1 is configured as open collector. It goes low when constant current
O
output is shut down by WDT or TSD function.
БББББББББББББББББББ
OVM comparator output. XDOWN2 is configured as an open collector. It monitors terminal
voltage when constant current output is turned on. XDOWN2 goes low when this voltage
O
БББББББББББББББББББ
is lower than the level selected by OVM latch. When BLANK is set high, the previous level
is held.
DCLK enable. When XENABLE is low, data transfer is enabled. Data transfer starts on the
БББББББББББББББББББ
rising edge of DCLK after XENABLE goes low. During XENABLE high, no data is
I
transferred.
БББББББББББББББББББ
Latch. When XLATCH is high, data on the shift register goes through latch. When XLA TCH
is low, data is latched. Accordingly , if data on the shift register is changed during XLA TCH
I
БББББББББББББББББББ
high, this new value is latched (level latch).
Data output enable. When XOE is low, DOUT0–7 terminals are drived. When XOE is high,
I
DOUT0–7 terminals go to a high
-impedance state.
TLC5904
absolute maximum ratings (see Note 1)
†
Logic supply voltage, VCC(LOG) – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage for constant current circuit, VCC(LED) – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog supply voltage, VCCANA – 0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current (dc), I
90 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O(LC)
Input voltage range – 0.3 V to VCCLOG + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
Output voltage range, V
O(DOUTn)
O(OUTn)
Storage temperature range, T
Continuous total power dissipation at (or below) T
, V
O(BOUT)
and V
–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
and V
O(DOWNn)
O(GSOUT)
– 0.3 V to VCCLOG + 0.3 V. . . . . . . . . . . . . .
– 0.3 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
= 25°C 4.7 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
Power dissipation rating at (or above) TA = 25°C 38.2m W/°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GNDLOG terminal.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TLC5904
Á
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Á
mA
,
OL
f
DCLK clock frequenc
MH
LED DRIVER
SLLS391 – NOVEMBER 1999
recommended operating conditions
dc characteristics
PARAMETER
Logic supply voltage, VCCLOG
Supply voltage for constant current
circuit, VCCLED
Analog power supply, VCCANA
V
Voltage between VCC, V
ББББББББББ
Voltage between GND, V
DIFF1
DIFF2
Voltage applied to constant current
output, V
ББББББББББ
High-level input voltage, V
Low-level input voltage, V
High-level output current, I
ББББББББББ
Low-level output current, I
Constant output current, I
OUTn
IH
IL
OH
O(LC)
Operating free-air temperature range, T
DIFF1
VCCLOG – VCCLED, VCCANA – VCCLED
ББББББББББ
V
DIFF2
GNDLOG – GNDLED, GNDANA – GNDLED
OUT0 to OUT15 off
ББББББББББ
VCCLOG = 4.5V, DOUT0 to DOUT7,
BOUT, GSOUT
VCCLOG = 4.5V, DOUT0 to DOUT7,
BOUT, GSOUT
ББББББББББ
VCCLOG = 4.5V, XDOWN1, XDOWN2
OUT0 to OUT15
A
TEST CONDITIONS
= VCCLOG – VCCANA
= GNDLOG – GNDANA
MIN
ÁÁÁ
ÁÁÁÁÁÁÁÁÁ
0.8 VCCLOG
GNDLOG
4.5
4.5
4.5
– 0.3
– 0.3
NOM
Á
5
5
5
0
ÁÁÁ
0
0.2 VCCLOG
MAX
5.5
5.5
5.5
0.3
0.3
17
VCCLOG
–1
ÁÁÁÁÁÁÁÁÁ
5
–20
80
85
UNIT
V
V
V
V
Á
V
V
Á
V
V
1
Á
5
mA
mA
°C
ac characteristics, VC C LOG = VCCANA = VCCLED = 4. 5 V to 5.5 V, T
DCLK
twh/t
wl
f
GSCLK
twh/t
wl
f
WDT
twh/t
wl
t
wh
tr/t
f
t
su
t
h
PARAMETER
y
DCLK pulse duration (high or low level)
GSCLK clock frequency
GSCLK pulse duration (high or low level)
WDTRG clock frequency
WDTRG pulse duration (high or low level)
XLATCH pulse duration (high)
Rise/fall time
Setup time
Hold time
TEST CONDITIONS
At single operation
At cascade operation (DOMODE = L)
Frequency division ratio 1/1
DINn – DCLK
BLANK – GSCLK
XENABLE – DCLK
XLATCH – DCLK
XLATCH – GSCLK
RSEL – DCLK↑
RSEL – XLATCH
DINn – DCLK
XENABLE – DCLK
XLATCH – DCLK
RSEL – DCLK↓
RSEL – XLATCH
= – 20 to 85°C (unless otherwise noted)
A
MIN
TYP
MAX
UNIT
15
10
20
8
40
8
40
50
100
10
20
15
15
15
10
20
15
20
30
20
20
z
ns
MHz
ns
MHz
ns
ns
ns
ns
ns
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Á
Á
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OL
g
Á
I
Á
Supply current (logic)
Á
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I
Supply current (analog)
mA
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Á
Á
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Á
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Á
Á
Á
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Á
Á
I
OLK
Á
Constant out ut leakage current
Á
Á
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Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
electrical characteristics,
MIN/MAX: VCCLOG= VCCANA
TYP: VCCLOG = VCCANA = VCCLED = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
V
OH
ÁÁ
V
I
I
LOG
ÁÁ
ANA
I
LED
ÁÁ
I
ÁÁ
OLC1
I
OLC2
ÁÁ
ÁÁ
∆I
OLC
ÁÁ
I∆
OLC1
ÁÁ
I∆
OLC2
T
tsd
T
wdt
V
IREF
High-level output voltage
ББББББББББ
Low-level output voltage
Input current
pp
ББББББББББ
pp
Supply current (constant current driver)
ББББББББББ
Constant output current (includes error
ББББББББББ
between bits)
Constant output current (includes error
between bits)
ББББББББББ
p
ББББББББББ
Constant output current error between bit
ББББББББББ
Changes in constant output current depend
on supply voltage
ББББББББББ
Changes in constant output current depend
on output voltage
TSD detection temperature
WDT detection temperature
Voltage reference
= VCCLED = 4.5 V to 5.5 V, TA = – 20 to 85°C
TEST CONDITIONS
DOUTn, GSOUT, BOUT,
IOH = – 1.0mA
DOUTn, GSOUT, BOUT,
ББББББББ
IOL = 1.0mA,
XDOWN1, XDOWN2, IOL = 5 mA
VIN = VCCLOG or GNDLOG
Input signal is static,T SENA = H,
WDCAP = OPEN
Data transfer,D CLK = 15 MHz,
ББББББББ
GSCLK = 8 MHz
LED turnon, R
LED turnoff R
LED turnoff, R
LED turnoff, R
V
= 1 V. R
OUT
ББББББББ
All output bits turn on
V
= 1, R
OUT
All output bits turn on
V
= 1 V, R
ББББББББ
OUT
V
= 1 V, R
OUT
ББББББББ
OUT0 to OUT15 (V
XDOWN1,2 (V
DOUTn,
ББББББББ
(V
OUTn
XDOWNn
= VCCLOG or GND)
VCCLOG=VCCANA=VCCLED=5 V,
V
= 1 V, R
OUT
ББББББББ
All output bits turn on
V
= 1 V, R
OUT
V
= 1.24 V, 1 bit output turn on
ББББББББ
IREF
V
= 1 V to 3 V, R
OUT
V
= 1.24 V, 1 bit output turn on
IREF
Junction temperature
No external capacitor
BCENA = L, R
IREF
IREF
IREF
IREF
IREF
IREF
IREF
IREF
OUTn
IREF
IREF
IREF
IREF
= 590 Ω
= 590 Ω
= 1180 Ω
=590 Ω
= 1180 Ω
= 590 Ω
= 1180 Ω
= 590 Ω
= 15 V)
= 15 V)
= 590 Ω
= 1180 Ω,
= 1180 Ω,
= 590 Ω
MIN
VCCLOG
– 0.5
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
35
ÁÁ
70
ÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
150
5
TLC5904
LED DRIVER
SLLS391 – NOVEMBER 1999
TYP
Á
Á
±1%
1.24
18
15
30
25
50
40
80
±1
±1
160
10
MAX
Á
3
3
Á
Á
Á
Á
Á
0.5
0.5
±1
30
20
40
35
70
45
90
0.1
±4%
±4
±2
170
15
UNIT
V
Á
V
µA
1
mA
mA
Á
5
5
mA
Á
mA
Á
mA
Á
µA
1
µA
1
µA
Á
Á
%/V
Á
%/V
°C
ms
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
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