Texas Instruments TLC5733AIPM Datasheet

T

20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER

WITH HIGH-PRECISION CLAMP

SLAS104A – JULY 1995 – REVISED NOVEMBER 1996

D

3-Channel CMOS ADC

D

5-V Single-Supply Operation or 5-V Analog
Supply with Digital Supply from

2.7 V to 5.25 V

D

8-Bit Resolution

D

Differential Linearity Error...±0.5 LSB Max

D

Linearity Error...±0.75 LSB Max

D

Maximum Conversion Rate

20 Megasamples per Second
(MSPS) Min

D

Analog Input Voltage Range

2 V

D

64-Pin Shrink QFP Package

I(PP)

Min

description

The TLC5733A is a 3-channel 8-bit semiflash analog-to-digital converter (ADC) that operates from a single 5-V
power supply. It converts a wide-band analog signal (such as a video signal) to digital data at sampling rates
up to 20 MSPS minimum. The TLC5733A contains a feed-back type high-precision clamp circuit for each ADC
channel for video (YUV) applications and a clamp pulse generator that detects COMPOSITE SYNC
automatically . A clamp pulse can also be supplied externally . The output-data format multiplexer selects a ratio
of Y:U:V of 4:4:4, 4:1:1, or 4:2:2. For RGB applications, the 4:4:4 output format without clamp function can be
used. The TLC5733A is characterized for operation from –20°C to 75°C.

D

Analog Input Bandwidth...>14 MHz

D

Suitable for YUV or RGB Applications

D

Digital Clamp Optimized for NTSC or PAL
YUV Component

D

High-Precision Clamp...±1 LSB

D

Automatic Clamp Pulse Generator

D

Output-Data Format Multiplexer

D

Low Power Consumption

TLC5733A

†

pulses

AVAILABLE OPTIONS

A

–20°C to 75°C TLC5733AIPM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

COMPOSITE SYNC refers to the externally generated synchronizing signal that is a combination of vertical and horizontal sync information
used in display and TV systems.

PACKAGE

QUAD FLATPACK

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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Copyright  1996, Texas Instruments Incorporated

1

TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP

SLAS104A – JULY 1995 – REVISED NOVEMBER 1996

PM PACKAGE

(TOP VIEW)

RB A

A

OE

NT/PAL

TEST

QA DGND

AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1

QA DV

DD

DGND

QB DV

DD

CC
AV
A

GND A

AIN

63 62 61 60 5964 58

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

18 19

17

BD6

BD8

BD7

RT A

CLPV A

21 22 23 24

20

BD5

BD4

CLP OUT A

BD3

INIT

CLPEN

CLK

56 55 5457

25 26 27 28 29

BD2

BD1

QB DGND

CLP OUT B

EXTCLP

53 52

DD

DV

CLP OUT C

CLPV B

RT B

51 50 49

30 31 32

RT C

CLPV C

C A V

CC

AVB

CC

BIN

CIN

GND B

RB B

48

OE

47

MODE0

46

MODE1

45

QC DGND

44

CD1

43

CD2

42

CD3

41

CD4

40

CD5

39
38

CD6

37

CD7

36

CD8

35

QC DV

34

OE C

33

RB C

GND C

B

DD

2

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functional block diagram

CLK A

TLC5733A

20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER

WITH HIGH-PRECISION CLAMP

SLAS104A – JULY 1995 – REVISED NOVEMBER 1996

AIN

RT A

RB A

CLPV A

CLP OUT A

BIN

RT B

RB B

CLPV B

CLP OUT B

CIN

RT C

RB C

CLPV C

CLP OUT C

ADC

(Sampling

Comparators)

Clamp
Circuit

CLK B

ADC

(Sampling

Comparators)

Clamp
Circuit

CLK C

ADC

(Sampling

Comparators)

Clamp

Circuit

8

8

8

8

Multiplexer

For

Output Format

8

8

8

Output Data

Latch

OE A

8

Output Data

Latch

OE B

8

Output Data

Latch

OE C

8

8

8

AD1–8

BD1–8

CD1–8

EXTCLP

CLPEN

NT/PAL

Control For

INT/EXT

Clamp Circuit

Clock

Generator

CLK INIT

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Output

Format
Selector
and Test

MODE0
MODE1
TEST

3

TLC5733A

I/O

DESCRIPTION

20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP

SLAS104A – JULY 1995 – REVISED NOVEMBER 1996

Terminal Functions

TERMINAL

NAME NO.

A AV

CC

AD8–AD1 6–13 O Data output of ADC A (LSB: AD1, MSB:AD8)
AIN 63 I Analog input of ADC A
B AV

CC

BD8–BD1 17–24 O Data output of ADC B (LSB: BD1, MSB:BD8)
BIN 50 I Analog input of ADC B
C AV

CC

CD8–CD1 36–43 O Data output of ADC C (LSB:CD1, MSB: CD8)

CIN 31 I Analog input of ADC C
CLK 56 I Clock input. The clock frequency is normally 4 × the frequency subcarrier (fsc) for most video systems (see

CLPEN 57 I Clamp enable. When using an internal clamp pulse, CLPEN should be high. When using an external clamp

CLP OUT A 59 O Clamping bias current of ADC A. A resistor-capacitor combination that sets the clamp timing.
CLP OUT B 54 O Clamping bias current of ADC B. A resistor-capacitor combination that sets the clamp timing.
CLP OUT C 27 O Clamping bias current of ADC C. A resistor-capacitor combination that sets the clamp timing.
CLPV A 60 O Clamping level of ADC A. A capacitor is connected to CLPV A to set the clamp timing. The clamp level at

CLPV B 53 O Clamping level of ADC B. A capacitor is connected to CLPV B to set the clamp timing. The clamp level at

CLPV C 28 O Clamping level of ADC C. A capacitor is connected to CLPV C to set the clamp timing. The clamp level at

DGND 15 I Digital ground
DV

DD

EXTCLP 55 I External clamp pulse input. When EXTCLP and CLPEN are low, the internal clamp circuit cannot be used.

GND A 64 I Ground of ADC A
GND B 49 I Ground of ADC B
GND C 32 I Ground of ADC C
INIT 58 I Output initialized. The output data is synchronous when INIT is taken high from low. INIT is a control terminal

MODE0 46 I Output format mode selector 0. When MODE1 is low and MODE0 is low, output data format1 is selected.

MODE1 45 I Output format mode selector 1. When MODE1 is low and MODE0 is low, output data format1 is selected.

NT/PAL 3 I NTSC/PAL control. NTSC/PAL should be low for NTSC and high for PAL.
OE A 2 I Output enable A. OE A enables the output of ADC A.
OE B 47 I Output enable B. OE B enables the output of ADC B.

62 I Analog supply voltage of ADC A

51 I Analog supply voltage of ADC B

30 I Analog supply voltage of ADC C

When MODE0 = L, MODE1 = L, CD8 outputs MSB flag of BD8–BD5
When MODE0 = L, MODE1 = L, CD7 outputs MSB flag of BD8–BD5
When MODE0 = L, MODE1 = H, CD8 outputs B channel flag of CD8–BD1
When MODE0 = L, MODE1 = H, CD8 outputs B channel flag of CD8–BD1

T able 3). The nominal clock frequency is 14.31818 MHz for National T elevision System Committee (NTSC)
and 17.745 MHz for phase alteration line (PAL).

pulse, CLPEN should be low.

CLPV A is connected to an output code of 16 (0010000).

CLPV B is connected to an output code of 128 (1000000).

CLPV C is connected to an output code of 128 (1000000).

26 I Digital supply voltage

The external clamp pulse when used is active high.

that allows the external system to initialize the TLC5733A data conversion cycle. INIT is usually used at
power up or system reset.

When MODE1 is low and MODE0 is high, output data format2 is selected. When MODE1 is high and
MODE0 is low, output data format3 is selected. A high level on MODE1 and a high level on MODE0 is not
used.

When MODE1 is low and MODE0 is high, output data format2 is selected. When MODE1 is high and
MODE0 is low, output data format3 is selected. A high level on MODE1 and a high level on MODE0 is not
used.

4

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I/O

DESCRIPTION

TLC5733A

20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER

WITH HIGH-PRECISION CLAMP

SLAS104A – JULY 1995 – REVISED NOVEMBER 1996

Terminal Functions (Continued)

TERMINAL

NAME NO.

OE C 34 I Output enable C. OE C enables the output of ADC C.
QA DGND 5 I Digital ground for output of ADC A
QA DV

DD

QB DGND 25 I Digital ground for output of ADC B
QB DV

DD

QC DGND 44 I Digital ground for output of ADC C
QC DV

DD

RB A 1 I Bottom reference voltage of ADC A. The nominal externally applied dc voltage between RT A and RB A is

RB B 48 I Bottom reference voltage of ADC B. The nominal externally applied dc voltage between RT B and RB B is

RB C 33 I Bottom reference voltage of ADC C. The nominal externally applied dc voltage between RT C and RB C

RT A 61 I Top reference voltage of ADC A. The nominal externally applied dc voltage between RT A and RB A is 2

RT B 52 I Top reference voltage of ADC B. The nominal externally applied dc voltage between RT B and RB B is 2

RT C 29 Top reference voltage of ADC C. The nominal externally applied dc voltage between RT C and RB C is 2

TEST 4 I Test. TEST should be tied low when using this device.

14 I Digital supply voltage for output of ADC A

16 I Digital supply voltage for output of ADC B

35 I Digital supply voltage for output of ADC C

2 V for video signals.

2 V for video signals.

is 2 V for video signals.

V for video signals.

V for video signals.

V for video signals.

absolute maximum ratings

Supply voltage, V
Reference voltage input range,V

V

ref(RB B)

Analog input voltage range AGND to V
Digital input voltage range, V
Digital output voltage range, V
Operating free-air temperature range, T
Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

, V

ref(RB C)

CC

†

, VDD 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGND to V

ref(RT A)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

, V

ref(RT B)

, V

ref(RT C)

, V

ref(RB A)

,

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGND to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

DGND to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

–20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

CC
CC
DD
DD

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5

TLC5733A

‡

V

A

V

A

20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP

SLAS104A – JULY 1995 – REVISED NOVEMBER 1996

recommended operating conditions

MIN NOM MAX UNIT

VCC–AGND 4.75 5 5.25

Supply voltage

Reference input voltage, V
Reference input voltage, V
Analog input voltage, V
High-level input voltage, V
Low-level input voltage, V
High-level pulse duration, t
Low-level pulse duration, t
Setup time for INIT input, t
Operating free-air temperature range, T

‡

Within the electrical and operating characteristics table, when the term VDD is used, all XDVDD terminals are tied together, and when the term
VCC is used, all XAVCC terminals are tied together.

VDD–DGND 2.7 5 5.25
AGND–DGND –100 0 100 mV

ref(RT A)
ref(RB A)

I

IH

IL

w(H)
w(L)
su1

, V

ref(RT B)

, V

ref(RB B)

, V

ref(RT C)

, V

ref(RB C)

A

V

+2 V

ref(RB)

0 V
0 V
2 V

25 ns
25 ns

5 ns

–20 75 °C

CC

ref(RT)

ref(RT)

0.8 V

–2 V

V

V

electrical characteristics at VDD = 2.7 V to 5.25 V, V
f

†

= 20 MHz, TA = 25°C (unless otherwise noted)

(CLK)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Clamp level accuracy ±1 LSB

R

ref

C

i

I

IH

I

IL

V

OH

V

OL

I

OH(lkg)

I

OL(lkg)

I

CC
Conditions marked MIN or MAX are as stated in recommended operating conditions.

Reference voltage resistor Measured between RT and RB 160 220 350 Ω
Analog input capacitance VI = 1.5 V + 0.07 V

High-level input current

Low-level input current

High-level output voltage

Low-level output voltage

High-level output leakage current

Low-level output leakage current

Supply current

VDD = MAX†,
VCC = 5V

VDD = MAX†,
VCC = 5V

All DVDD terminals = 2.7 V to 5.25 V,
IOH = –1 mA

All DVDD terminals = 2.7 V to 5.25 V,
IOL = 2 mA

VDD = MAX†,
VCC = 5V

VDD = MIN†,
VCC = 5V

fc = 20 MSPS,
NTSC ramp wave input

CC

rms

= 5 V, V

ref(RT)

VIH = VDD,

VIL = 0,

VOH = VDD,

VOL = 0,

= 2.5 V, V

DVDD –0.7 V

ref(BB)

= 0.5 V,

16 pF

50 75 mA

5

µ

5

0.8

16

µ

16

6

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TLC5733A

20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER

WITH HIGH-PRECISION CLAMP

SLAS104A – JULY 1995 – REVISED NOVEMBER 1996

operating characteristics at VDD = 2.7 V to 5.25 V, V
f

‡

= 20 MHz, TA = 25°C (unless otherwise noted)

(CLK)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

E

Zero-scale error V

ZS

E

Full-scale error V

FS

E

Linearity error

L

E

Linearity error, differential

D

f

Maximum conversion rate VI = 0.5 V – 2.5 V, fI = 1-kHz ramp waveform 20 MSPS

c

BW Analog input bandwidth At – 1 dB 14 MHz
t

Digital output delay time CL = 10 pF 18 30 ns

pd

Differential gain NTSC 40 IRE‡ modulation wave, fc = 14.3 MSPS 1%
Differential phase NTSC 40 IRE‡ modulation wave, fc = 14.3 MSPS 0.7 deg
Aperture jitter time 30 ps
Sampling delay time 4 ns

Institute of Radio Engineers

= REFT – REFB = 2 V –18 –43 –68 mV

ref

= REFT – REFB = 2 V –20 0 20 mV

ref

f

= 20 MHz, VI = 0.5 V to 2.5 V ±0.4 ±0.75

(CLK)

f

= 20 MHz,

(CLK)

TA = –20°C to 75°C
f

= 20 MHz, VI = 0.5 V to 2.5 V ±0.3 ±0.5

(CLK)

f

= 20 MHz,

(CLK)

TA = –20°C to 75°C

= 5 V, V

CC

VI = 0.5 V to 2.5 V

VI = 0.5 V to 2.5 V

ref(RT)

= 2.5 V, V

ref(RB)

= 0.5 V,

±0.4 ±1

±0.3 ±0.75

LSB

LSB

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7

TLC5733A

CHANNEL OF ADC

OUTPUT CODE

APPLICATION

L

H

COMPOSITE SYNC input

20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP

SLAS104A – JULY 1995 – REVISED NOVEMBER 1996

detailed description

clamp function

The clamp function is optimized for a YUV video signal and has two clamp modes. The first mode uses the
COMPOSITE SYNC signal as the input to the EXTCLP terminal to generate an internal clamp pulse and the
second mode uses an externally generated clamp pulse as the input to the EXTCLP terminal.

In the first mode, the device detects false pulses in the COMPOSITE SYNC signal by monitoring the rising and
falling edges of the COMPOSITE SYNC signal pulses. This monitoring prevents faulty operation caused by
disturbances and missing pulses of the COMPOSITE SYNC signal input on EXTCLP and external spike noise.
When fault pulses are detected, the device internally generates a train of clamp pulses at the proper positions
(1H) by an internal 910-counter for NTSC and a 1 136-counter for P AL. The device checks clamp pulses for 1H
time and generates clamp pulses at correct positions when COMPOSITE SYNC pulses are in error in time.

The internal counter continually produces a horizontal sync period (1H) that is NTSC or PAL compatible as
selected by the condition of the NT/PAL terminal.

clamp voltages and selection

T able 1 shows the clamping level during the clamp interval. T able 2 shows the selection of the internal or external
clamp pulse. With either NTSC or PAL, the internal clamp pulse is always used.

Table 1. Clamp Level (Internal Connection Level)

ADC A • V
ADC B • V
ADC C • V

I(A)
I(B)
I(C)

00010000 Y
10000000 (U, V)
10000000 (U, V)

Table 2. Clamp Level (Internal Connection Level)

CONDITION FUNCTION (EACH ADC)

CLPEN EXTCLP NT/PAL INTERNAL CLAMP CLAMP PULSE

Don’t Care Inactive External clamp pulse

L Don’t Care Inactive No clamping

p

L Active Synchronous with NTSC
H Active Synchronous with P AL

The clamp circuit is shown in Figure 6. The clamp voltage is stored on capacitor C2 during the back porch of
the horizontal blanking period.

During the clamp pulse the input to channel A is clamped to:

V

(A) = (16/256) × (voltage difference from terminal RT A to RB A)

C

V

(B) = (128/256) × (voltage difference from terminal RT B to RB B)

C

V

(C) = (128/256) × (voltage difference from terminal RT C to RB C)

C

COMPOSITE SYNC time monitoring

When CLPEN is high, COMPOSITE SYNC generates an internal clamp pulse on the horizontal blanking interval
back porch. The TLC5733A has a timing window into which the horizontal sync tip must occur. There is a noise
time window for the falling edge and one for the rising edge (see Figure 1, Figure 2, and Table 3).

8

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