Datasheet TLC5615C, TLC5615I Datasheet (TEXAS INSTRUMENTS)

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1
2
3
4

8
7
6
5

DIN

SCLK

CS

DOUT

V

DD

OUT
REFIN
AGND

TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

10-BIT DIGITAL-TO-ANALOG CONVERTERS

FEATURES • Settling Time to 0.5 LSB . . . 12.5 µs Typ

• 10-Bit CMOS Voltage Output DAC in an
8-Terminal Package

• 5-V Single Supply Operation

• 3-Wire Serial Interface

• High-Impedance Reference Inputs

• Voltage Output Range . . . 2 Times the Refer-
ence Input Voltage • Battery Operated/Remote Industrial Controls

• Internal Power-On Reset • Machine and Motion Control Devices

• Low Power Consumption . . . 1.75 mW Max • Cellular Telephones

• Update Rate of 1.21 MHz

D, P, OR DGK PACKAGE

(TOP VIEW)

• Monotonic Over Temperature

• Pin Compatible With the Maxim MAX515

APPLICATIONS

• Battery-Powered Test Instruments

• Digital Offset and Gain Adjustment

DESCRIPTION

The TLC5615 is a 10-bit voltage output digital-to-analog converter (DAC) with a buffered reference input (high
impedance). The DAC has an output voltage range that is two times the reference voltage, and the DAC is
monotonic. The device is simple to use, running from a single supply of 5 V. A power-on-reset function is
incorporated to ensure repeatable start-up conditions.

Digital control of the TLC5615 is over a three-wire serial bus that is CMOS compatible and easily interfaced to
industry standard microprocessor and microcontroller devices. The device receives a 16-bit data word to produce
the analog output. The digital inputs feature Schmitt triggers for high noise immunity. Digital communication
protocols include the SPI™, QSPI™, and Microwire™ standards.

The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications. The
TLC5615C is characterized for operation from 0°C to 70°C. The TLC5615I is characterized for operation from -40°C
to 85°C.

AVAILABLE OPTIONS

PACKAGE

T

A

0°C to 70°C TLC5615CD TLC5615CDGK TLC5615CP

40°C to 85°C TLC5615ID TLC5615IDGK TLC5615IP

(1)

Available in tape and reel as the TLC5615CDR and the TLC5615IDR

SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform tospecifications per the terms ofTexas Instruments
standard warranty. Production processing does not necessarily in­cludetestingof allparameters.

SMALL OUTLINE PLASTIC SMALL OUTLINE PLASTIC DIP

(1)

(D) (DGK) (P)

Copyright © 1996 – 2003, Texas Instruments Incorporated

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_

+

DAC

10-Bit DAC Register

Power-ON

Reset

Control

Logic

16-Bit Shift Register

4

Dummy

Bits

2

0s

10 Data Bits

(LSB) (MSB)

REFIN

AGND

CS

SCLK

DIN

OUT
(Voltage Output)

_

+

DOUT

R R

2

TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

FUNCTIONAL BLOCK DIAGRAM

Terminal Functions

TERMINAL

NAME NO.

DIN 1 I Serial data input

SCLK 2 I Serial clock input

CS 3 I Chip select, active low

DOUT 4 O Serial data output for daisy chaining

AGND 5 Analog ground

REFIN 6 I Reference input

OUT 7 O DAC analog voltage output

V

DD

8 Positive power supply

I/O DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage (VDDto AGND) 7 V

Digital input voltage range to AGND - 0.3 V to VDD+ 0.3 V

Reference input voltage range to AGND - 0.3 V to VDD+ 0.3 V

Output voltage at OUT from external source VDD+ 0.3 V

Continuous current at any terminal ±20 mA

Operating free-air temperature range, T

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

(1)

Stresses beyond those listed under,, absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2

stg

A

TLC5615C 0°C to 70°C

TLC5615I -40°C to 85°C

(1)

-65°C to 150°C

UNIT

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TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

Supply voltage, V

High-level digital input voltage, V

Low-level digital input voltage, V

Reference voltage, V

Load resistance, R

Operating free-air temperature, T

DD

IH

IL

to REFIN terminal 2 2.048 VDD-2 V

ref

L

TLC5615C 0 70 °C

A

TLC5615I 40 85 °C

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range, VDD= 5 V ± 5%, V

STATIC DAC SPECIFICATIONS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 10 bits

Integral nonlinearity, end point adjusted (INL) V

Differential nonlinearity (DNL) V

E

Zero-scale error (offset error at zero scale) V

ZS

Zero-scale-error temperature coefficient V

E

Gain error V

G

Gain-error temperature coefficient V

PSRR Power-supply rejection ratio See

Zero scale 80

Gain 80

Analog full scale output RL= 100 kΩ 2V

(1)

The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text). Tested from code 3 to code

1024.

(2)

The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB
amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code. Tested from code 3 to code 1024.

(3)

Zero-scale error is the deviation from zero-voltage output when the digital input code is zero (see text).

(4)

Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(T

(5)

Gain error is the deviation from the ideal output (V

(6)

Gain temperature coefficient is given by: EGTC = [EG(T

(7)

Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDDfrom 4.5 V to 5.5 V dc and measuring the proportion of this
signal imposed on the zero-code output voltage.

(8)

Gain-error rejection ratio (EG-RR) is measured by varying the VDDfrom 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero-scale change.

= 2.048 V, See

ref

= 2.048 V, See

ref

= 2.048 V, See

ref

= 2.048 V, See

ref

= 2.048 V, See

ref

= 2.048 V, See

ref

(7) (8)

) - EZS(T

min

max

)]/V

- 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-scale error.

ref

max

) - EG(T

= 2.048 V (unless otherwise noted)

ref

(1)

(2)

(3)

(4)

(5)

(6)

)]/V

× 106/(T

min

ref

× 106/(T

ref

max

- T

min

).

4.5 5 5.5 V

2.4 V

2 kΩ

±1 LSB

±0.1 ±0.5 LSB

±3 LSB

3 ppm/°C

±3 LSB

1 ppm/°C

(1023/1024) V

ref

- T

min

).

max

0.8 V

dB

VOLTAGE OUTPUT(OUT)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

I

OSC

V

OL(low)

V

OH(high)

REFERENCE INPUT (REFIN)

V

I

r

i

Voltage output range RL= 10 kΩ 0 VDD-0.4 V

Output load regulation accuracy V

Output short circuit current OUT to VDDor AGND 20 mA

Output voltage, low-level I

Output voltage, high-level I

Input voltage 0 VDD-2 V

Input resistance 10 MΩ

= 2 V, RL= 2 kΩ 0.5 LSB

O(OUT)

≤ 5 mA 0.25 V

O(OUT)

≤ -5 mA 4.75 V

O(OUT)

3

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TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

VOLTAGE OUTPUT(OUT) (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

C

i

DIGITAL INPUTS (DIN, SCLK, CS)

V

IH

V

IL

I

IH

I

IL

C

i

DIGITAL OUTPUT (DOUT)

V

OH

V

OL

POWER SUPPLY

V

DD

I

DD

ANALOG OUTPUT DYNAMIC PERFORMANCE

(1)

Input capacitance 5 pF

High-level digital input voltage 2.4 V

Low-level digital input voltage 0.8 V

High-level digital input current VI= V

DD

Low-level digital input current VI= 0 ±1 µA

Input capacitance 8 pF

Output voltage, high-level IO= -2 mA VDD-1 V

Output voltage, low-level IO= 2 mA 0.4 V

Supply voltage 4.5 5 5.5 V

VDD= 5.5 V, No load,

Power supply current

All inputs = 0 V or V

VDD= 5.5 V, No load,
All inputs = 0 V or V

V

= 1 Vppat 1 kHz + 2.048 Vdc,

Signal-to-noise + distortion, S/(N+D) code = 11 1111 1111, 60 dB

ref

See

(1)

DD

DD

The limiting frequency value at 1 Vpp is determined by the output-amplifier slew rate.

±1 µA

V

= 0 150 250 µA

ref

V

= 2.048 V 230 350 µA

ref

DIGITAL INPUT TIMING REQUIRMENTS (SEE FIGURE 1)

PARAMETER MIN NOM MAX UNIT

t

su(DS)

t

h(DH)

t

su(CSS)

t

su(CS1)

t

h(CSH0)

t

h(CSH1)

t

w(CS)

t

w(CL)

t

w(CH)

Setup time, DIN before SCLK high 45 ns

Hold time, DIN valid after SCLK high 0 ns

Setup time, CS low to SCLK high 1 ns

Setup time, CS high to SCLK high 50 ns

Hold time, SCLK low to CS low 1 ns

Hold time, SCLK low to CS high 0 ns

Pulse duration, minimum chip select pulse width high 20 ns

Pulse duration, SCLK low 25 ns

Pulse duration, SCLK high 25 ns

OUTPUT SWITCHING CHARACTERISTICS

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

t

pd(DOUT)

Propagation delay time, DOUT CL= 50 pF 50 ns

OPERATING CHARACTERISTICS

over recommended operating free-air temperature range, VDD= 5 V ±5%, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG OUTPUT DYNAMIC PERFORMANCE

SR Output slew rate RL= 10 kΩ, 0.3 0.5 V/µs

CL= 100 pF,
TA= 25°C

= 2.048 V (unless otherwise noted)

ref

4

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t

h(CSH0)

t

su(CSS)

t

w(CH)

t

w(CL)

t

h(CSH1)

t

su(CS1)

t

w(CS)

t

pd(DOUT)

CS

SCLK

DIN

DOUT

t

su(DS)

t

h(DH)

NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough.

See Note A See Note A

See Note B

MSB LSB

B. Data input from preceeding conversion cycle.

See Note C

Previous LSB

C. Sixteenth SCLK falling edge

TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

OPERATING CHARACTERISTICS (continued)

over recommended operating free-air temperature range, VDD= 5 V ±5%, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG OUTPUT DYNAMIC PERFORMANCE

t

Output settling time 12.5 µs

s

To 0.5 LSB, CL= 100 pF,
RL= 10 kΩ, See

(1)

Glitch energy DIN = All 0s to all 1s 5 nV•s

REFERENCE INPUT (REFIN)

Reference feedthrough REFIN = 1 Vppat 1 kHz + 2.048 Vdc (see

Reference input
bandwidth (f-3dB)

(1)

Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of

REFIN = 0.2 Vpp+ 2.048 Vdc 30 kHz

000 hex to 3FF hex or 3FF hex to 000 hex.

(2)

Reference feedthrough is measured at the DAC output with an input code = 000 hex and a V

PARAMETER MEASURMENT INFORMATION

= 2.048 V (unless otherwise noted)

ref

(2)

input = 2.048 Vdc + 1 Vppat 1 kHz.

ref

-80 dB

Figure 1. Timing Diagram

5

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15

10

5

0

20

25

30

5

4.8 4.6 4.4 4.2 4

3.8 3.6 3.4 3.2 3

VDD = 5 V
V

REFIN

= 2.048 V

TA = 25°C

- Output Source Current - mA
I

O

VO - Output Pullup Voltage - V

8
6

2

0

0.1 0.2 0.4 0.6

- Output Sink Current - mA

10

14

16

0.8 1

4

12

18

20

0.3 0.5 0.7 0.9 1.1

1.2

VDD = 5 V
V

REFIN

= 2.048 V

TA = 25°C

I

O

VO - Output Pulldown Voltage - V

80

- Supply Current -

200

280

240

160

120

40

0

- 60 - 40 - 20 0 20 40 60 80 100 120 140

Aµ

t - Temperature - °C

VDD = 5 V
V

REFIN

= 2.048 V

TA = 25°C

I

DD

1 100 1 k 10 k 100 k

G - Relative Gain - dB

4

2

0

- 2

- 4

- 6

- 8

- 10

- 12

- 14

VDD = 5 V
V

REFIN

= 0.2 V

PP

+ 2.048 V dc

TA = 25°C

fI - Input Frequency - Hz

TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

OUTPUT SINK CURRENT OUTPUT SOURCE CURRENT

vs vs

OUTPUT PULLDOWN VOLTAGE OUTPUT PULLUP VOLTAGE

TYPICAL CHARACTERISTICS

SUPPLY CURRENT RELATIVE GAIN

TEMPERATURE INPUT FREQUENCY

6

Figure 2.

V

REFIN

vs vs

Figure 4.

Figure 3.

TO V

(OUT)

Figure 5.

www.ti.com

40

50

1 k

Signal-To-Noise + Distortion - dB

70

30

Frequency - Hz

20

10

0

60

10 k 100 k 300 k

VDD = 5 V
T

A

= 25°C

V

REFIN

= 4 V

PP

Differential Nonlinearity – LSB

–0.2

0.2

0.1

0

–0.05

0.15

0.05

–0.1

–0.15

Input Code

255 511 767 10230

Integral Nonlinearity – LSB

–0.6

Input Code

1

0

–0.2

255 511 767 10230

0.8

0.6

0.4

0.2

–0.4

–0.8

–1

TYPICAL CHARACTERISTICS (continued)

TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

SIGNAL-TO-NOISE + DISTORTION

vs

INPUT FREQUENCY AT REFIN

Figure 6.

Figure 7 Differential Nonlinearity With Input Code

Figure 8 Integral Nonlinearity With Input Code

7

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_

+

Resistor

String

DAC

5 V

0.1 µF

AGND V

DD

OUT

REFIN

DIN SCLK CS

DOUT

R

R

_

+

2V

REFIN



1023
1024

2V

REFIN



513

1024

2V

REFIN



512

1024

 V

REFIN

2V

REFIN



511

1024

2V

REFIN



1

1024

TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

APPLICATION INFORMATION

GENERAL FUNCTION

The TLC5615 uses a resistor string network buffered with an op amp in a fixed gain of 2 to convert 10-bit digital
data to analog voltage levels (see functional block diagram and Figure 9). The output of the TLC5615 is the
same polarity as the reference input (see Table 1).

An internal circuit resets the DAC register to all zeros on power up.

Figure 9. TLC5615 Typical Operating Circuit

Table 1. Binary Code Table (0 V to 2 V

(1)

INPUT

1111 1111 11(00)

: :

1000 0000 01(00)

1000 0000 00(00)

0111 1111 11(00)

: :

0000 0000 01(00)

0000 0000 00(00) 0 V

(1)

A 10-bit data word with two bits below the LSB bit (sub-LSB) with 0 values must be written since the DAC input latch is 12 bits wide.

BUFFER AMPLIFIER

Output),Gain = 2

REFIN

OUTPUT

The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-kΩ load with a 100-pF
load capacitance. Settling time is 12.5 µs typical to within 0.5 LSB of final value.

8

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f

(SCLK)max



1

t

wCH



 t

wCL



t

p(CS)

 16t

wCH



 t

wCL





 t

wCS



10 Data Bits x x

12 Bits

MSB LSB 2 Extra (Sub-LSB) Bits

x = don’t care

10 Data Bits x x

16 Bits

MSB LSB 2 Extra (Sub-LSB) Bits

4 Upper Dummy Bits

x = don’t care

TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

EXTERNAL REFERENCE

The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore,
the REFIN input resistance is 10 MΩ and the REFIN input capacitance is typically 5 pF independent of input
code. The reference voltage determines the DAC full-scale output.

LOGIC INTERFACE

The logic inputs function with either TTL or CMOS logic levels. However, using rail-to-rail CMOS logic achieves
the lowest power dissipation. The power requirement increases by approximately 2 times when using TTL logic
levels.

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the TLC5615 timing. The maximum serial clock rate is:

or approximately 14 MHz. The digital update rate is limited by the chip-select period, which is:

and is equal to 820 ns which is a 1.21 MHz update rate. However, the DAC settling time to 10 bits of 12.5 µs
limits the update rate to 80 kHz for full-scale input step transitions.

SERIAL INTERFACE

When chip select (CS) is low, the input data is read into a 16-bit shift register with the input data clocked in most
significant bit first. The rising edge of the SLCK input shifts the data into the input register.

The rising edge of CS then transfers the data to the DAC register. When CS is high, input data cannot be
clocked into the input register. All CS transitions should occur when the SCLK input is low.

If the daisy chain (cascading) function (see daisy-chaining devices section) is not used, a 12-bit input data
sequence with the MSB first can be used as shown in Figure 10:

Figure 10. 12-Bit Input Data Sequence

or 16 bits of data can be transferred as shown in Figure 11 with the 4 upper dummy bits first.

Figure 11. 16-Bit Input Data Sequence

9

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SCLK

DIN

CS

DOUT

TLC5615

SK

SO

I/O

SI

Microwire

Port

NOTE A: The DOUT -SI connection is not required for writing to

the TLC5615 but may be used for verifying data
transfer if desired.

SCLK

DIN

CS

DOUT

TLC5615

SCK

MOSI

I/O

MISO

SPI/QSPI

Port

NOTE A: The DOUT -MISO connection is not required for writing to the

TLC5615 but may be used for verifying data transfer.

CPOL = 0, CPHA = 0

TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

The data from DOUT requires 16 falling edges of the input clock and, therefore, requires an extra clock width.
When daisy chaining multiple TLC5615 devices, the data requires 4 upper dummy bits because the data transfer
requires 16 input-clock cycles plus one additional input-clock falling edge to clock out the data at the DOUT
terminal (see Figure 1).

The two extra (sub-LSB) bits are always required to provide hardware and software compatibility with 12-bit data
converter transfers.

The TLC5615 three-wire interface is compatible with the SPI, QSPI†, and Microwire serial standards. The
hardware connections are shown in Figure 12 and Figure 13.

The SPI and Microwire interfaces transfer data in 8-bit bytes, therefore, two write cycles are required to input
data to the DAC. The QSPI interface, which has a variable input data length from 8 to 16 bits, can load the DAC
input register in one write cycle.

Figure 12. Microwire Connection

Figure 13. SPI/QSPI Connection

DAISY-CHAINING DEVICES

DACs can be daisy-chained by connecting the DOUT terminal of one device to the DIN of the next device in the
chain, providing that the setup time, t
t

, plus the propagation delay time, t

su(DS)

The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. DOUT is a totem-poled
output for low power. DOUT changes on the SCLK falling edge when CS is low. When CS is high, DOUT
remains at the value of the last data bit and does not go into a high-impedance state.

, (CS low to SCLK high) is greater than the sum of the setup time,

su(CSS)

pd(DOUT)

, for proper timing (see digital input timing requirements section).

10

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DAC Code

Output

Voltage

0 V

Negative

Offset

TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

LINEARITY, OFSET, AND GAIN ERROR USING SINGLE ENDED SUPPLIES

When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage
may not change with the first code depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to
overcome the negative offset voltage, resulting in the transfer function shown in Figure 14.

Figure 14. Effect of Negative Offset (Single Supply)

This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.

For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is
measured between full-scale code and the lowest code that produces a positive output voltage. For the
TLC5615, the zero-scale (offset) error is plus or minus 3 LSB maximum. The code is calculated from the
maximum specification for the negative offset.

POWER-SUPPLY BYPASSING AND GROUND MANAGEMENT

Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane making sure that analog ground currents
are well managed and there are negligible voltage drops across the ground plane.

A 0.1-µF ceramic-capacitor bypass should be connected between VDDand AGND and mounted with short leads
as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the
digital power supply.

Figure 15 shows the ground plane layout and bypassing technique.

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0.1 µF

Analog Ground Plane

1
2
3
4

8
7
6
5

TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

Figure 15. Power-Supply Bypassing

SAVING POWER

Setting the DAC register to all 0s minimizes power consumption by the reference resistor array and the output
load when the system is not using the DAC.

AC CONSIDERATIONS

Digital Feedthrough

Even with CS high, high-speed serial data at any of the digital input or output terminals may couple through the
DAC package internal stray capacitance and appear at the DAC analog output as digital feedthrough. Digital
feedthrough is tested by holding CS high and transmitting 0101010101 from DIN to DOUT.

Analog Feedthrough

Higher frequency analog input signals may couple to the output through internal stray capacitance. Analog
feedthrough is tested by holding CS high, setting the DAC code to all 0s, sweeping the frequency applied to
REFIN, and monitoring the DAC output.

12

MECHANICAL DATA

MPDI001A – JANUARY 1995 – REVISED JUNE 1999

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE

0.400 (10,60)

0.355 (9,02)

8

5

0.260 (6,60)

0.240 (6,10)

1

0.021 (0,53)

0.015 (0,38)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001

4

0.070 (1,78) MAX

0.020 (0,51) MIN

0.200 (5,08) MAX

0.125 (3,18) MIN

0.100 (2,54)

0.010 (0,25)

Seating Plane

M

0.325 (8,26)

0.300 (7,62)

0.015 (0,38)

Gage Plane

0.010 (0,25) NOM

0.430 (10,92)
MAX

4040082/D 05/98

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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deems necessary to support this warranty . Except where mandated by government requirements, testing of all
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security

Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless

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