TEXAS INSTRUMENTS TLC5615C, TLC5615I Technical data

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1
2
3
4

8
7
6
5

DIN

SCLK

CS

DOUT

V

DD

OUT
REFIN
AGND

TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

10-BIT DIGITAL-TO-ANALOG CONVERTERS

FEATURES • Settling Time to 0.5 LSB . . . 12.5 µs Typ

• 10-Bit CMOS Voltage Output DAC in an
8-Terminal Package

• 5-V Single Supply Operation

• 3-Wire Serial Interface

• High-Impedance Reference Inputs

• Voltage Output Range . . . 2 Times the Refer-
ence Input Voltage • Battery Operated/Remote Industrial Controls

• Internal Power-On Reset • Machine and Motion Control Devices

• Low Power Consumption . . . 1.75 mW Max • Cellular Telephones

• Update Rate of 1.21 MHz

D, P, OR DGK PACKAGE

(TOP VIEW)

• Monotonic Over Temperature

• Pin Compatible With the Maxim MAX515

APPLICATIONS

• Battery-Powered Test Instruments

• Digital Offset and Gain Adjustment

DESCRIPTION

The TLC5615 is a 10-bit voltage output digital-to-analog converter (DAC) with a buffered reference input (high
impedance). The DAC has an output voltage range that is two times the reference voltage, and the DAC is
monotonic. The device is simple to use, running from a single supply of 5 V. A power-on-reset function is
incorporated to ensure repeatable start-up conditions.

Digital control of the TLC5615 is over a three-wire serial bus that is CMOS compatible and easily interfaced to
industry standard microprocessor and microcontroller devices. The device receives a 16-bit data word to produce
the analog output. The digital inputs feature Schmitt triggers for high noise immunity. Digital communication
protocols include the SPI™, QSPI™, and Microwire™ standards.

The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications. The
TLC5615C is characterized for operation from 0°C to 70°C. The TLC5615I is characterized for operation from -40°C
to 85°C.

AVAILABLE OPTIONS

PACKAGE

T

A

0°C to 70°C TLC5615CD TLC5615CDGK TLC5615CP

40°C to 85°C TLC5615ID TLC5615IDGK TLC5615IP

(1)

Available in tape and reel as the TLC5615CDR and the TLC5615IDR

SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform tospecifications per the terms ofTexas Instruments
standard warranty. Production processing does not necessarily in­cludetestingof allparameters.

SMALL OUTLINE PLASTIC SMALL OUTLINE PLASTIC DIP

(1)

(D) (DGK) (P)

Copyright © 1996 – 2003, Texas Instruments Incorporated

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_

+

DAC

10-Bit DAC Register

Power-ON

Reset

Control

Logic

16-Bit Shift Register

4

Dummy

Bits

2

0s

10 Data Bits

(LSB) (MSB)

REFIN

AGND

CS

SCLK

DIN

OUT
(Voltage Output)

_

+

DOUT

R R

2

TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

FUNCTIONAL BLOCK DIAGRAM

Terminal Functions

TERMINAL

NAME NO.

DIN 1 I Serial data input

SCLK 2 I Serial clock input

CS 3 I Chip select, active low

DOUT 4 O Serial data output for daisy chaining

AGND 5 Analog ground

REFIN 6 I Reference input

OUT 7 O DAC analog voltage output

V

DD

8 Positive power supply

I/O DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage (VDDto AGND) 7 V

Digital input voltage range to AGND - 0.3 V to VDD+ 0.3 V

Reference input voltage range to AGND - 0.3 V to VDD+ 0.3 V

Output voltage at OUT from external source VDD+ 0.3 V

Continuous current at any terminal ±20 mA

Operating free-air temperature range, T

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

(1)

Stresses beyond those listed under,, absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2

stg

A

TLC5615C 0°C to 70°C

TLC5615I -40°C to 85°C

(1)

-65°C to 150°C

UNIT

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TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

Supply voltage, V

High-level digital input voltage, V

Low-level digital input voltage, V

Reference voltage, V

Load resistance, R

Operating free-air temperature, T

DD

IH

IL

to REFIN terminal 2 2.048 VDD-2 V

ref

L

TLC5615C 0 70 °C

A

TLC5615I 40 85 °C

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range, VDD= 5 V ± 5%, V

STATIC DAC SPECIFICATIONS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 10 bits

Integral nonlinearity, end point adjusted (INL) V

Differential nonlinearity (DNL) V

E

Zero-scale error (offset error at zero scale) V

ZS

Zero-scale-error temperature coefficient V

E

Gain error V

G

Gain-error temperature coefficient V

PSRR Power-supply rejection ratio See

Zero scale 80

Gain 80

Analog full scale output RL= 100 kΩ 2V

(1)

The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text). Tested from code 3 to code

1024.

(2)

The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB
amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code. Tested from code 3 to code 1024.

(3)

Zero-scale error is the deviation from zero-voltage output when the digital input code is zero (see text).

(4)

Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(T

(5)

Gain error is the deviation from the ideal output (V

(6)

Gain temperature coefficient is given by: EGTC = [EG(T

(7)

Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDDfrom 4.5 V to 5.5 V dc and measuring the proportion of this
signal imposed on the zero-code output voltage.

(8)

Gain-error rejection ratio (EG-RR) is measured by varying the VDDfrom 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero-scale change.

= 2.048 V, See

ref

= 2.048 V, See

ref

= 2.048 V, See

ref

= 2.048 V, See

ref

= 2.048 V, See

ref

= 2.048 V, See

ref

(7) (8)

) - EZS(T

min

max

)]/V

- 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-scale error.

ref

max

) - EG(T

= 2.048 V (unless otherwise noted)

ref

(1)

(2)

(3)

(4)

(5)

(6)

)]/V

× 106/(T

min

ref

× 106/(T

ref

max

- T

min

).

4.5 5 5.5 V

2.4 V

2 kΩ

±1 LSB

±0.1 ±0.5 LSB

±3 LSB

3 ppm/°C

±3 LSB

1 ppm/°C

(1023/1024) V

ref

- T

min

).

max

0.8 V

dB

VOLTAGE OUTPUT(OUT)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

I

OSC

V

OL(low)

V

OH(high)

REFERENCE INPUT (REFIN)

V

I

r

i

Voltage output range RL= 10 kΩ 0 VDD-0.4 V

Output load regulation accuracy V

Output short circuit current OUT to VDDor AGND 20 mA

Output voltage, low-level I

Output voltage, high-level I

Input voltage 0 VDD-2 V

Input resistance 10 MΩ

= 2 V, RL= 2 kΩ 0.5 LSB

O(OUT)

≤ 5 mA 0.25 V

O(OUT)

≤ -5 mA 4.75 V

O(OUT)

3

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TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

VOLTAGE OUTPUT(OUT) (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

C

i

DIGITAL INPUTS (DIN, SCLK, CS)

V

IH

V

IL

I

IH

I

IL

C

i

DIGITAL OUTPUT (DOUT)

V

OH

V

OL

POWER SUPPLY

V

DD

I

DD

ANALOG OUTPUT DYNAMIC PERFORMANCE

(1)

Input capacitance 5 pF

High-level digital input voltage 2.4 V

Low-level digital input voltage 0.8 V

High-level digital input current VI= V

DD

Low-level digital input current VI= 0 ±1 µA

Input capacitance 8 pF

Output voltage, high-level IO= -2 mA VDD-1 V

Output voltage, low-level IO= 2 mA 0.4 V

Supply voltage 4.5 5 5.5 V

VDD= 5.5 V, No load,

Power supply current

All inputs = 0 V or V

VDD= 5.5 V, No load,
All inputs = 0 V or V

V

= 1 Vppat 1 kHz + 2.048 Vdc,

Signal-to-noise + distortion, S/(N+D) code = 11 1111 1111, 60 dB

ref

See

(1)

DD

DD

The limiting frequency value at 1 Vpp is determined by the output-amplifier slew rate.

±1 µA

V

= 0 150 250 µA

ref

V

= 2.048 V 230 350 µA

ref

DIGITAL INPUT TIMING REQUIRMENTS (SEE FIGURE 1)

PARAMETER MIN NOM MAX UNIT

t

su(DS)

t

h(DH)

t

su(CSS)

t

su(CS1)

t

h(CSH0)

t

h(CSH1)

t

w(CS)

t

w(CL)

t

w(CH)

Setup time, DIN before SCLK high 45 ns

Hold time, DIN valid after SCLK high 0 ns

Setup time, CS low to SCLK high 1 ns

Setup time, CS high to SCLK high 50 ns

Hold time, SCLK low to CS low 1 ns

Hold time, SCLK low to CS high 0 ns

Pulse duration, minimum chip select pulse width high 20 ns

Pulse duration, SCLK low 25 ns

Pulse duration, SCLK high 25 ns

OUTPUT SWITCHING CHARACTERISTICS

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

t

pd(DOUT)

Propagation delay time, DOUT CL= 50 pF 50 ns

OPERATING CHARACTERISTICS

over recommended operating free-air temperature range, VDD= 5 V ±5%, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG OUTPUT DYNAMIC PERFORMANCE

SR Output slew rate RL= 10 kΩ, 0.3 0.5 V/µs

CL= 100 pF,
TA= 25°C

= 2.048 V (unless otherwise noted)

ref

4

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t

h(CSH0)

t

su(CSS)

t

w(CH)

t

w(CL)

t

h(CSH1)

t

su(CS1)

t

w(CS)

t

pd(DOUT)

CS

SCLK

DIN

DOUT

t

su(DS)

t

h(DH)

NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough.

See Note A See Note A

See Note B

MSB LSB

B. Data input from preceeding conversion cycle.

See Note C

Previous LSB

C. Sixteenth SCLK falling edge

TLC5615C, TLC5615I

SLAS142D–OCTOBER 1996 – REVISED AUGUST 2003

OPERATING CHARACTERISTICS (continued)

over recommended operating free-air temperature range, VDD= 5 V ±5%, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ANALOG OUTPUT DYNAMIC PERFORMANCE

t

Output settling time 12.5 µs

s

To 0.5 LSB, CL= 100 pF,
RL= 10 kΩ, See

(1)

Glitch energy DIN = All 0s to all 1s 5 nV•s

REFERENCE INPUT (REFIN)

Reference feedthrough REFIN = 1 Vppat 1 kHz + 2.048 Vdc (see

Reference input
bandwidth (f-3dB)

(1)

Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of

REFIN = 0.2 Vpp+ 2.048 Vdc 30 kHz

000 hex to 3FF hex or 3FF hex to 000 hex.

(2)

Reference feedthrough is measured at the DAC output with an input code = 000 hex and a V

PARAMETER MEASURMENT INFORMATION

= 2.048 V (unless otherwise noted)

ref

(2)

input = 2.048 Vdc + 1 Vppat 1 kHz.

ref

-80 dB

Figure 1. Timing Diagram

5