Datasheet TLC555CP, TLC555CDR, TLC555CD, TLC555QDR, TLC555MP Datasheet (Texas Instruments)

TLC555, TLC555Y

LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Very Low Power Consumption

1 mW Typ at VDD = 5 V

D

Capable of Operation in Astable Mode

D

CMOS Output Capable of Swinging Rail
to Rail

D

High Output-Current Capability

Sink 100 mA Typ
Source 10 mA Typ

D

Output Fully Compatible With CMOS, TTL,
and MOS

D

Low Supply Current Reduces Spikes
During Output Transitions

D

Single-Supply Operation From 2 V to 15 V

D

Functionally Interchangeable With the
NE555; Has Same Pinout

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015.2

description

The TLC555 is a monolithic timing circuit
fabricated using the TI LinCMOS process. The
timer is fully compatible with CMOS, TTL, and
MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses
smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations
are possible. Power consumption is low across the full range of power supply voltage.

Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a
threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of
the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is
set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the
threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs
and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low.
Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and
GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering.

While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC555 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE555.

The TLC555C is characterized for operation from 0°C to 70°C. The TLC555I is characterized for operation from
– 40°C to 85°C. The TLC555M is characterized for operation over the full military temperature range of – 55°C
to 125°C.

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either supply voltage or ground. Specific guidelines for handling devices of this type are contained in the publication

Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies

available from Texas Instruments.

LinCMOS is a trademark of Texas Instruments Incorporated.

Copyright  1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

3212019

910111213

4
5
6
7
8

18
17
16
15
14

NC
DISCH
NC
THRES
NC

NC

TRIG

NC

OUT

NC

FK PACKAGE

(TOP VIEW)

NC

GND

NC

CONT

NC

V

NC

RESET

NC

NC

DD

D, DB, JG, P, OR PW PACKAGE

(TOP VIEW)

1
2
3
4

8
7
6
5

GND

TRIG

OUT

RESET

V

DD

DISCH
THRES
CONT

NC – No internal connection

TLC555, TLC555Y
LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

V

DD

RANGE

SMALL

OUTLINE

(D)

SSOP

(DB)

CHIP

CARRIER

(FK)

CERAMIC

DIP

(JG)

PLASTIC

DIP

(P)

TSSOP

(PW)

CHIP

FORM

(Y)

0°C to

70°C

2 V to 15 V TLC555CD TLC555CDBLE — — TLC555CP TLC555CPWLE

–40°C to

85°C

3 V to 15 V TLC555ID — — — TLC555IP —

TLC555Y

–55°C to

125°C

5 V to 15 V TLC555MD — TLC555MFK TLC555MJG TLC555MP —

The D package is available taped and reeled. Add the R suffix to device type (e.g., TLC555CDR). The DB and PW packages are only available
left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TLC555CDBLE). Chips are tested at 25°C.

FUNCTION TABLE

RESET

VOLTAGE

†

TRIGGER

VOLTAGE

†

THRESHOLD

VOLTAGE

†

OUTPUT

DISCHARGE

SWITCH

<MIN Irrelevant Irrelevant L On
>MAX <MIN Irrelevant H Off
>MAX >MAX >MAX L On
>MAX >MAX <MIN As previously established

†

For conditions shown as MIN or MAX, use the appropriate value specified under
electrical characteristics.

functional block diagram

GND

RESET

CONT

V

DD

1

THRES

TRIG

R

R

R

DISCH

OUT

S

R

R1

Pin numbers are for all packages except the FK package.
RESET can override TRIG, which can override THRES.

5

6

2

1

7

3

4

8

TLC555, TLC555Y

LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC555Y chip information

This chip, when properly assembled, displays characteristics similar to the TLC555. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

50

64

RESET can override TRIG, which can override THRES.

CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
PIN (1) IS INTERNALLY CONNECTED

TO BACKSIDE OF CHIP.

GND

RESETCONT

V

DD

1

THRES

TRIG

R

R

R

DISCH

OUT

S

R

R1

(5)

(6)

(2)

(1)

(7)

(3)

(8)

(4)

TLC555, TLC555Y

LinCMOS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

Template Release Date: 7–11–94

TIMERS

4

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

equivalent schematic (each channel)

THRES

CONT

TRIG RESET

V

DD

DISCH

OUT

GND

Transistors

COMPONENT COUNT

Resistors

39

5

TLC555, TLC555Y

LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, VDD (see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (any input) –0.3 to V

DD

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Sink current, discharge or output 150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Source current, output, I

O

15 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: C-suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I-suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

M-suffix –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package 300°C. . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, DB, P, or PW package 260°C. . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to network GND.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

TA = 125°C

POWER RATING

D
DB
FK
JG

P

PW

725 mW

525 mW
1375 mW
1050 mW
1000 mW

525 mW

5.8 mW/°C

4.2 mW/°C

11.0 mW/°C

8.4 mW/°C

8.0 mW/°C

4.2 mW/°C

464 mW
336 mW
880 mW
672 mW
640 mW
336 mW

377 mW
273 mW
715 mW
546 mW
520 mW
273 mW

145 mW
105 mW
275 mW
210 mW
200 mW
105 mW

recommended operating conditions

MIN MAX UNIT

Supply voltage, V

DD

2 15 V

TLC555C 0 70

Operating free-air temperature range, T

A

TLC555I –40 85

°C

TLC555M –55 125

TLC555, TLC555Y
LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, VDD = 2 V for TLC555C, VDD = 3 V for
TLC555I

TEST

TLC555C TLC555I

PARAMETER

CONDITIONS

T

A

†

MIN TYP MAX MIN TYP MAX

UNIT

25°C 0.95 1.33 1.65 1.6 2.4

VITThreshold voltage

Full range 0.85 1.75 1.5 2.5

V

25°C 10 10

p

IITThreshold current

MAX 75 150

pA

25°C 0.4 0.67 0.95 0.71 1 1.29

V

I(TRIG)

Trigger voltage

Full range 0.3 1.05 0.61 1.39

V

25°C 10 10

p

I

I(TRIG)

Trigger current

MAX 75 150

pA

25°C 0.4 1.1 1.5 0.4 1.1 1.5

V

I(RESET)

Reset voltage

Full range 0.3 2 0.3 1.8

V

25°C 10 10

p

I

I(RESET)

Reset current

MAX 75 150

pA

Control voltage (open circuit) as
a percentage of supply voltage

MAX 66.7% 66.7%

Discharge switch on-stage

25°C 0.03 0.2 0.03 0.2

gg

voltage

I

OL

= 1

mA

Full range 0.25 0.375

V

Discharge switch off-stage

25°C 0.1 0.1

gg

current

MAX 0.5 120

nA

p

25°C 1.5 1.9 1.5 1.9

VOHHigh-level output voltage

I

OH

= –

300 µA

Full range 1.5 2.5

V

p

25°C 0.07 0.3 0.07 0.3

VOLLow-level output voltage

I

OL

= 1

mA

Full range 0.35 0.4

V

pp

25°C 250 250

IDDSupply current

See Note 2

Full range 400 500

µ

A

†

Full range is 0°C to 70°C for the TLC555C and – 40°C to 85°C for the TLC555I. For conditions shown as MAX, use the appropriate value specified
in the recommended operating conditions table.

NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.

TLC555, TLC555Y

LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, VDD = 5 V

TEST

TLC555C TLC555I TLC555M

PARAMETER

CONDITIONS

T

A

†

MIN TYP MAX MIN TYP MAX MIN TYP MAX

UNIT

25°C

2.8 3.3 3.8 2.8 3.3 3.8 2.8 3.3 3.8

V

IT

Threshold voltage

Full range 2.7 3.9 2.7 3.9 2.7 3.9

V

25°C

10 10 10

p

I

IT

Threshold current

MAX 75 150 5000

pA

25°C

1.36 1.66 1.96 1.36 1.66 1.96 1.36 1.66 1.96

V

I(TRIG)

Trigger voltage

Full range 1.26 2.06 1.26 2.06 1.26 2.06

V

25°C

10 10 10

p

I

I(TRIG)

Trigger current

MAX 75 150 5000

pA

25°C

0.4 1.1 1.5 0.4 1.1 1.5 0.4 1.1 1.5

V

I(RESET)

Reset voltage

Full range 0.3 1.8 0.3 1.8 0.3 1.8

V

25°C

10 10 10

p

I

I(RESET)

Reset current

MAX 75 150 5000

pA

Control voltage (open
circuit) as a
percentage of supply
voltage

MAX 66.7% 66.7% 66.7%

Discharge switch

25°C

0.14 0.5 0.14 0.5 0.14 0.5

g

on-state voltage

I

OL

=

10 mA

Full range 0.6 0.6 0.6

V

Discharge switch

25°C

0.1 0.1 0.1

g

off-state current

MAX 0.5 120 120

nA

High-level output

25°C

4.1 4.8 4.1 4.8 4.1 4.8

V

OH

g

voltage

I

OH

= –

1 mA

Full range 4.1 4.1 4.1

V

25°C

0.21 0.4 0.21 0.4 0.21 0.4

I

OL

=

8 mA

Full range 0.5 0.5 0.6

Low-level output

25°C

0.13 0.3 0.13 0.3 0.13 0.3

V

OL

voltage

I

OL

=

5 mA

Full range 0.4 0.4 0.45

V

25°C

0.08 0.3 0.08 0.3 0.08 0.3

I

OL

=

3.2 mA

Full range 0.35 0.35 0.4

pp

25°C

170 350 170 350 170 350

IDDSupply current

See Note 2

Full range 500 600 700

µ

A

†

Full range is 0°C to 70°C the for TLC555C, – 40°C to 85°C for the TLC555I, and – 55°C to 125°C for the TLC555M. For conditions shown as
MAX, use the appropriate value specified in the recommended operating conditions table.

NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

TLC555, TLC555Y
LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics at specified free-air temperature, VDD = 15 V

TEST

TLC555C TLC555I TLC555M

PARAMETER

CONDITIONS

T

A

†

MIN TYP MAX MIN TYP MAX MIN TYP MAX

UNIT

25°C 9.45 10 10.55 9.45 10 10.55 9.45 10 10.55

VITThreshold voltage

Full range 9.35 10.65 9.35 10.65 9.35 10.65

V

25°C 10 10 10

p

IITThreshold current

MAX 75 150 5000

pA

25°C 4.65 5 5.35 4.65 5 5.35 4.65 5 5.35

V

I(TRIG)

Trigger voltage

Full range 4.55 5.45 4.55 5.45 4.55 5.45

V

25°C 10 10 10

p

I

I(TRIG)

Trigger current

MAX 75 150 5000

pA

25°C 0.4 1.1 1.5 0.4 1.1 1.5 0.4 1.1 1.5

V

I(RESET)

Reset voltage

Full range 0.3 1.8 0.3 1.8 0.3 1.8

V

25°C 10 10 10

p

I

I(RESET)

Reset current

MAX 75 150 5000

pA

Control voltage (open
circuit) as a
percentage of supply
voltage

MAX 66.7% 66.7% 66.7%

Discharge switch

25°C 0.77 1.7 0.77 1.7 0.77 1.7

g

on-state voltage

I

OL

=

100 mA

Full range 1.8 1.8 1.8

V

Discharge switch

25°C 0.1 0.1 0.1

g

off-state current

MAX 0.5 120 120

nA

25°C 12.5 14.2 12.5 14.2 12.5 14.2

I

OH

= –

10 mA

Full range 12.5 12.5 12.5

High-level output

25°C 13.5 14.6 13.5 14.6 13.5 14.6

V

OH

g

voltage

I

OH

= –

5 mA

Full range 13.5 13.5 13.5

V

25°C 14.2 14.9 14.2 14.9 14.2 14.9

I

OH

= –

1 mA

Full range 14.2 14.2 14.2

25°C 1.28 3.2 1.28 3.2 1.28 3.2

I

OL

=

100 mA

Full range 3.6 3.7 3.8

Low-level output

25°C 0.63 1 0.63 1 0.63 1

V

OL

voltage

I

OL

=

50 mA

Full range 1.3 1.4 1.5

V

25°C 0.12 0.3 0.12 0.3 0.12 0.3

I

OL

=

10 mA

Full range 0.4 0.4 0.45

pp

25°C 360 600 360 600 360 600

IDDSupply current

See Note 2

Full range 800 900 1000

µA

†

Full range is 0°C to 70°C for TLC555C, – 40°C to 85°C for TLC555I, and – 55°C to 125°C for TLC555M. For conditions shown as MAX, use the
appropriate value specified in the recommended operating conditions table.

NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

TLC555, TLC555Y

LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS MIN TYP MAX UNIT

Initial error of timing interval

‡

V

= 5 V to 15 V, R

= R

= 1 kΩ to 100 kΩ,

1% 3%

Supply voltage sensistivity of timing interval

DD

,

CT = 0.1 µF,

AB

,

See Note 3

0.1 0.5 %/V

t

r

Output pulse rise time

p

20 75

t

f

Output pulse fall time

R

L

=

10 MΩ

,

C

L

=

10 pF

15 60

ns

f

max

Maximum frequency in astable mode

RA = 470 Ω,
CT = 200 pF,

RB = 200 Ω,
See Note 3

1.2 2.1 MHz

‡

Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process
run.

NOTE 3: RA, RB, and CT are as defined in Figure 1.

electrical characteristics at VDD = 5 V, TA = 25°C

PARAMETER

TEST CONDITIONS MIN TYP MAX UNIT

V

IT

Threshold voltage 2.8 3.3 3.8 V

I

IT

Threshold current 10 pA

V

I(TRIG)

Trigger voltage 1.36 1.66 1.96 V

I

I(TRIG)

Trigger current 10 pA

V

I(RESET)

Reset voltage 0.4 1.1 1.5 V

I

I(RESET)

Reset current 10 pA
Control voltage (open circuit) as a percentage of supply voltage 66.7%
Discharge switch on-state voltage IOL = 10 mA 0.14 0.5 V
Discharge switch off-state current 0.1 nA

V

OH

High-level output voltage IOH = – 1 mA 4.1 4.8 V

IOL = 8 mA 0.21 0.4

V

OL

Low-level output voltage

IOL = 5 mA 0.13 0.3

V

IOL = 3.2 mA 0.08 0.3

I

DD

Supply current See Note 2 170 350 µA

NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

TLC555, TLC555Y
LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 1

2

1
–75 – 50 – 25 0 25 75 125

Discharge Switch On-State Resistance –

DISCHARGE SWITCH ON-STATE RESISTANCE

vs

FREE-AIR TEMPERATURE

50 100

10

4

20

100

40

7

70

Ω

TA – Free-Air Temperature – °C

VDD = 2 V, IO = 1 mA

VDD = 5 V, IO = 10 mA

VDD = 15 V, IO = 100 mA

Figure 2

100

0

0 2 4 6 8 12 16

PROPAGATION DELAY TIMES TO DISCHARGE

OUTPUT FROM TRIGGER AND THRESHOLD

SHORTED TOGETHER

vs

SUPPLY VOLTAGE

10 14

400

200

500

600

300

VDD – Supply Voltage – V

2018

PHL

t,

PLH

t – Propagation Delay Times – ns

t

PLH

†

I

O(on)

≥ 1 mA

CL ≈ 0
TA = 25°C

†

The effects of the load resistance on these values must be
taken into account separately.

t

PHL

TLC555, TLC555Y

LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

0.1 µF

0.1 µF

C

T

C

L

R

L

Output

R

B

R

A

GND

TRIG

THRES

RESET
DISCH

CONT V

DD

OUT

V

DD

2/3 V

DD

1/3 V

DD

GND

t

PHL

t

PLH

t

c(H)

t

c(L)

CIRCUIT

TRIGGER AND THRESHOLD VOLTAGE WAVEFORM

TLC555

6

1

3

85
4
7

2

Pin numbers shown are for all packages except the
FK package.

Figure 3. Astable Operation

Connecting TRIG to THRES, as shown in Figure 3, causes the timer to run as a multivibrator. The capacitor C

T

charges through RA and RB to the threshold voltage level (approximately 0.67 VDD) and then discharges through R

B

only to the value of the trigger voltage level (approximately 0.33 VDD). The output is high during the charging cycle
(t

c(H)

) and low during the discharge cycle (t

c(L)

). The duty cycle is controlled by the values of RA, RB, and CT as shown

in the equations below.

t

c(H)

[

CT(RA)

RB)In2 (In2+0.693)

t

c(L)

[

CTRBIn 2

Period+t

c(H)

)

t

c(L)

[

CT(RA)

2RB)In2

Output driver duty cycle

+

t

c(L)

t

c(H)

)

t

c(L)

[

1–

R

B

RA)

2R

B

Output waveform duty cycle

+

t

c(H)

t

c(H)

)

t

c(L)

[

R

B

RA)

2R

B
The 0.1-µF capacitor at CONT in Figure 3 decreases the period by about 10%.
The formulas shown above do not allow for any propagation delay times from the TRIG and THRES inputs to DISCH.

These delay times add directly to the period and create differences between calculated and actual values that
increase with frequency. In addition, the internal on-state resistance ron during discharge adds to RB to provide
another source of timing error in the calculation when RB is very low or ron is very high.

TLC555, TLC555Y
LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

The equations below provide better agreement with measured values.

t

c(H)

+

CT(RA)

RB)Inƪ3–exp

ǒ

–t

PLH

CT(RB)

ron)

Ǔ

ƫ

)

t

PHL

t

c(L)

+

CT(RB)

ron)In

ƪ

3–exp

ǒ

–t

PHL

CT(RA)

RB)

Ǔ

ƫ

)

t

PLH

These equations and those given earlier are similar in that a time constant is multiplied by the logarithm of a number
or function. The limit values of the logarithmic terms must be between In 2 at low frequencies and In 3 at extremely
high frequencies. For a duty cycle close to 50%, an appropriate constant for the logarithmic terms can be substituted

with good results. Duty cycles less than 50%

t

c(H)

t

c(H)

)

t

c(L)

require that

t

c(H)

t

c(L)

< 1 and possibly RA ≤ ron. These

conditions can be difficult to obtain.
In monostable applications, the trip point on TRIG can be set by a voltage applied to CONT . An input voltage between

10% and 80% of the supply voltage from a resistor divider with at least 500-µA bias provides good results.

TLC555, TLC555Y

LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047/D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394

(10,00)

0.386

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

TLC555, TLC555Y
LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL INFORMATION

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040065 /C 10/95

28 PIN SHOWN

Gage Plane

8,20
7,40

0,15 NOM

0,63

1,03

0,25

38

12,90

12,30

28

10,50

24

8,50

Seating Plane

9,907,90

30

10,50

9,90

0,38

5,60
5,00

15

0,22

14

A

28

1

2016

6,50

6,50

14

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65

M

0,15

0°–8°

0,10

3,30

8

2,70

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

TLC555, TLC555Y

LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL INFORMATION

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

4040140/D 10/96

28 TERMINAL SHOWN

B

0.358
(9,09)

MAX

(11,63)

0.560

(14,22)

0.560

0.458

0.858
(21,8)

1.063
(27,0)

(14,22)

A

NO. OF

MINMAX

0.358

0.660

0.761

0.458

0.342

(8,69)

MIN

(11,23)

(16,26)

0.640

0.739

0.442

(9,09)

(11,63)

(16,76)

0.962

1.165

(23,83)

0.938

(28,99)

1.141

(24,43)

(29,59)

(19,32)(18,78)

**

20

28

52

44

68

84

0.020 (0,51)

TERMINALS

0.080 (2,03)

0.064 (1,63)

(7,80)

0.307

(10,31)

0.406

(12,58)

0.495

(12,58)

0.495

(21,6)

0.850

(26,6)

1.047

0.045 (1,14)

0.045 (1,14)

0.035 (0,89)

0.035 (0,89)

0.010 (0,25)

12

1314151618 17

11

10

8

9

7

5

432

0.020 (0,51)

0.010 (0,25)

6

12826 27

19

21

B SQ

A SQ

22

23

24

25

20

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004

TLC555, TLC555Y
LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL INFORMATION

JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE PACKAGE

0.310 (7,87)

0.290 (7,37)

0.014 (0,36)

0.008 (0,20)

Seating Plane

4040107/C 08/96

5

4

0.065 (1,65)

0.045 (1,14)

8

1

0.020 (0,51) MIN

0.400 (10,20)

0.355 (9,00)

0.015 (0,38)

0.023 (0,58)

0.063 (1,60)

0.015 (0,38)

0.200 (5,08) MAX

0.130 (3,30) MIN

0.245 (6,22)

0.280 (7,11)

0.100 (2,54)

0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.

E. Falls within MIL-STD-1835 GDIP1-T8

TLC555, TLC555Y

LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE

4040082/B 03/95

0.310 (7,87)

0.290 (7,37)

0.010 (0,25) NOM

0.400 (10,60)

0.355 (9,02)

58

41

0.020 (0,51) MIN

0.070 (1,78) MAX

0.240 (6,10)

0.260 (6,60)

0.200 (5,08) MAX

0.125 (3,18) MIN

0.015 (0,38)

0.021 (0,53)

Seating Plane

M

0.010 (0,25)

0.100 (2,54)

0°–15°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001

TLC555, TLC555Y
LinCMOS TIMERS

SLFS043C – SEPTEMBER 1983 – REVISED SEPTEMBER 1997

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL INFORMATION

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040064/E 08/96

14 PIN SHOWN

Seating Plane

0,05 MIN

1,20 MAX

1

A

7

14

0,19

4,50
4,30

8

6,20

6,60

0,30

0,75
0,50

0,25

Gage Plane

0,15 NOM

0,65

M

0,10

0°–8°

0,10

PINS **

A MIN

A MAX

DIM

2,90

3,10

8

4,90

5,10

14

6,60

6,404,90

5,10

16

7,70

20

7,90

24

9,60

9,80

28

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1998, Texas Instruments Incorporated