Page 1
TLC5540/TLC5510/TLC5510A/
TLV5540/TLV5510
Evaluation Module
User’s Guide
1999 Mixed-Signal Products
SLAU007C
Page 2
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Page 3
About This Manual
Information About Cautions and Warnings
Preface
Read This First
The purpose of this user’s guide is to serve as a reference book for the
TLC5540/TLC5510/TLC5510A/TLV5510/TLV5540 devices. This document
provides information to assist managers and hardware/software engineers in
application development.
How to Use This Manual
This document contains the following chapters:
-
Chapter 1 Overview
-
Chapter 2 Circuit Description
-
Chapter 3 Physical Description
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you
.
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
Read This First
iii
Page 4
Related Documentation From Texas Instruments
Related Documentation From Texas Instruments
The following documents may be ordered by contacting the T exas Instruments
Product Information Center at one of the numbers listed on the next page, or,
they may be downloaded at:
http://www–s.ti.com/sc/docs/psheets/pids2.htm
CE/FCC Warnings
TLC5510/TLC5510A Data Sheet
(literature number SLAS095) contains
electrical specifications, available temperature options, general overview of the device, and application information.
TLC5540 Data Sheet
(literature number SLAS105) contains electrical
specifications, available temperature options, general overview of the
device, and application information.
TLV5510 Data Sheet
(literature number SLAS124) contains electrical
specifications, available temperature options, general overview of the
device, and application information.
TLV5540 Data Sheet
(literature number SLAS192) contains electrical
specifications, available temperature options, general overview of the
device, and application information.
This equipment is intended for use in a laboratory test environment only . It generates, uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules.This device has been tested and found to comply with the
limits for a CISPRII Group 1 and the following directives: EMC Directive
89/336/EEC amending directive 92/31/EEC and 93/68/EEC as per
ENV50204:1995, EN55011: 1995 Class A, EN61000–4–4: 1995, and
EN6100–4–3: 1993. Operation of this equipment in other environments may
cause interference with radio communications, in which case the user at his
own expense will be required to take whatever measures may be required to
correct this interference.
iv
Page 5
Running Title—Attribute Reference
Contents
1 Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Purpose 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Power Supply Requirements 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Circuit Description 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 EVM Analog Input 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 Direct Input 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 Amplifier Input, DC Coupled 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3 Amplifier Input, AC Coupled 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4 Input Bias Operational Range 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5 Test Points 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.6 User Supplied Input Circuit 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Digital Output 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Clock Circuit 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Board Schematic 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Physical Description 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Board Layout 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Board Layers 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Part Descriptions 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter Title—Attribute Reference
v
Page 6
Running Title—Attribute Reference
Figures
2–1 Board Schematic 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 EVM Board Layout 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 EVM Board Layer 1 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 EVM Board Layer 2 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 EVM Board Layer 3 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 EVM Board Layer 4 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T ables
1–1 Power Supplies 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 Amplifier Input Coupling 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Input Voltage Setting 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 Test Points 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Part Descriptions 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
Page 7
Chapter 1
Overview
This chapter gives an overview of the TLC5540/TLC5510/TLC5510A/
TLV5540/TLV5510 evaluation module (EVM).
Topic Page
1.1 Power Supply Requirements 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 EVM Analog Input 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview
1-1
Page 8
Purpose
1.1 Purpose
The TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 evaluation module
(EVM) provides a platform for lab prototype evaluation of the Texas Instruments TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 8-bit, high-speed
analog-to-digital converters.
Since practical operation can be acheived in excess of 40 MHz, the circuit
layout is critical and does not lend itself to classic breadboarding techniques.
In fact, proper operation requires use of surface-mount components.
1-2
Overview
Page 9
Power Supply Requirements
1.2 Power Supply Requirements
The TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 EVM is designed to
be powered by regulated lab power supplies. Three lab supplies are required
for the best performance.
Table 1–1.Power Supplies
If Amp Used By-pass Amp
Connector Supply
J2 Positive analog supply 5 V ±10% 3.6 V MIN 5 V ±10% 3.6 V – 2.7 V
J3 Negative analog supply –5 V ±10% –3.6 MIN N/A N/A
J8 Digital supply 5 V ±10% 3.6 V – 3.3 V 5 V ±10% 3.6 V – 2.7 V
TLC5540/5510/
5510A
TL V5540/5510
The 5 V/3.6 V and –5 V/–3.6 V analog supplies share an analog ground plane.
The digital supply uses an isolated ground plane.
The two ground planes can be easily connected by soldering jumpers from
E21 to E22 or from E13 to E14. This allows the user to adapt the EVM to
various grounding conditions that can exist in an evaluation circuit interface.
TLC5510/
5540/5510A
TL V5510/5540
Overview
1-3
Page 10
1-4
Overview
Page 11
Chapter 2
Circuit
Description
This chapter describes the EVM circuit and its operation.
Topic Page
2.1 EVM Analog Input 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Digital Output 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Clock Circuit 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Board Schematic 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Circuit Description
2-1
Page 12
EVM Analog Input
2.1 EVM Analog Input
The EVM analog input signal is applied to BNC connector J4 by one of four
methods:
-
-
-
-
2.1.1 Direct Input
To route the signal directly to the TLC5540/TLC5510/TLC5510A/
TL V5540/TLV5510 input, solder jumpers from E7 to E8 and from E23 to E12.
This provides a 50-Ohm load (R5) at input connector J4. The input signal must
be dc biased to the specifications defined by the data sheet. The
TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 is connected using its internal bias resistors. Jumper J6 bypasses one of the internal bias resistors and
thus alters the input bias range required by the input signal. With J6 installed,
the voltage range of the TLC5540/TLC5510 is 0 V – 2.28 V and
TLV5540/TLV5510 is 0 V – 2.74 V (at 3.3 V
Direct
Amplifier input (dc coupled)
Amplifier input (ac coupled)
User supplied input
DDA
).
The TLC5510A uses only the center internal bias resistor with an externallyapplied regulated 4-V reference to generate the device reference voltage.
Hence the input signal range applied to J4 can be between 0 V – 4 V.
The input signal is bandlimited to 12 MHz by the LC filter consisting of FB5,
R15, and C5. For a bandwidth of 20 MHz, select a value for C5 in the 15 pF
to 33 pF range.
2-2
Circuit Description
Page 13
2.1.2 Amplifier Input, DC Coupled
A THS3001 high-speed transconductance operational amplifier provides buffering for dc-coupled amplifier-input signals. The amplifier circuit provides a flat
response to 300 MHz with a gain of two. It can drive a low impedance load.
The values of R6 and R8 set the amplifier gain to two.
The gain can be reduced to one by removing R6. Since the inverting input is
a low-impedance current-controlled input, R8 must remain in the circuit, and
its value must be changed to 1 kΩ. This resistance value is critical because it
controls the high frequency response of the circuit. The TLC5510A amplifier
gain is set to one.
The output roll-off filter , consisting of R4 and C14, provides a small amount of
filtering against frequencies in excess of 20 MHz (f
be altered to change the filter characteristics, or C14 can be removed entirely .
In most cases, R4 should be retained to lower the direct capacitive load on the
operational amplifier, thereby avoiding high frequency peaking of the output
signal.
Resistor R7 also provides isolation against a direct capacitive load (such as
a scope probe) on the test point terminal.
EVM Analog Input
/2). The value of C14 can
s
The amplifier output circuit is connected to the TLC5540/TLC5510/
TLC5510A/TLV5540/TLV5510 by soldering a jumper between terminals E10
and E12.
The amplifier input can be either dc coupled or ac coupled to the input.
T able 2–1 shows the jumpers required to select either input coupling method.
Table 2–1.Amplifier Input Coupling
Coupling Jumper Terminals
dc E3 to E4
ac E1 to E2
2.1.3 Amplifier Input, AC Coupled
Potentiometer R2 controls the dc input bias for amplifier ac-coupled inputs.
This allows the bias to be varied from near ground to near 5 V/3.6 V (analog).
With an amplifier gain of two, the output approaches the positive power supply
when the bias potentiometer approaches 2.5 V for the TLC5510/TLC5560 and
1.8 V for the TLV5510/TLV5540.
For a 4-V input and a gain of 1 (R6 removed and R8 set to 1 kΩ for optimum
settling time and minimum ringing) bias potentiometer R2 is adjusted such that
E1 is at 2 V and the amplifier output swing is 0 V to 4 V at TP2. With an amplifier
supply voltage of +5 V the output positive peak will be distorted slightly; therefore, it is necessary to adjust the 5-V supply to 5.56 V in order to prevent clipping of the amplifier output voltage.
Circuit Description
2-3
Page 14
EVM Analog Input
The low frequency response pole is dominated by the 4.7-µF capacitor (C6)
and the resistance setting of the potentiometer.
2.1.4 Input Bias Operational Range
Jumper J6 determines the signal input range (0 to full scale) at the analog input
of the TLC5540/TLC5510/TLC5510A/TLV5570/TLV5540. Table 2–2 shows
the effects of J6.
Table 2–2.Input Voltage Setting
2.1.5 Test Points
Table 2–3.Test Points
TLC5540/TLC5510
Jumper J6
Removed 0.6 V to 2.6 V 0.66 V to 2.87 V
Installed 0 V to 2.28 V 0 V to 2.74 V
Input Voltage
Range
@ 5 V
DDA
TLV5540/TLV5510
Input Voltage
Range
@ 3.3 V
DDA
TLC5510A
Input V oltage Range
@ 5 V
DDA
0 V to 4 V (J11 and J16
installed)
0 V to 4 V (J11 and J16
installed)
Other output ranges can be configured. See the TLC5540/TLC5510/
TLC5510A/TLV5540/TLV5510 data sheets.
Test points TP1 and TP2 provide an oscilloscope connection to monitor the
output of the analog input conditioning amplifier stage as follows:
Test Point Connection
TP1 Analog ground
TP2 Analog output of THS3001
2.1.6 User Supplied Input Circuit
A breadboarding area allows the use of custom input filters or other signal
conditioning circuits. To route the input signal to the breadboarding area
(terminal E24), solder a jumper between terminals E5 and E6.
To route the signal from the breadboard area (terminal E25) to the
TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 input, solder a jumper
between terminals E11 and E12.
Only one of the above configurations should be used at one time to prevent
excessive capacitance on the signal path. This excessive capacitance can degrade the input signal quality at high frequencies.
2-4
Circuit Description
Page 15
2.2 Digital Output
Digital Output
An octal high-speed latch (U4) provides buffered digital data. The factory configuration uses this latch as a buffer to drive the 22-ohm line damping resistors.
Pin 24 on the output connector (J5) can be used to drive the U4 output to a high
impedance (3-state) allowing a bus interface to external circuitry . T o do so, the
jumper between terminals E17 and E18 must be removed to remove the
ground connection. Logic 1 applied to J5 pin 24 makes the latch output a
3-state output.
This latch can be transparent by using external circuitry to drive the strobe
input (pin 1 1). The jumper at E19 and E20 must be removed and the external
drive be connected to E19. A logic 0 on this input captures and holds the input
data on the output. A logic 1 allows the outputs to follow the inputs.
Circuit Description
2-5
Page 16
Clock Circuit
2.3 Clock Circuit
An external clock of up to 40 MHz is required for operation. The clock source
is required to drive the 50-ohm BNC input J1. If the clock signal comes from
a DSP or microcontroller, resistor R1 should be removed from the circuit. The
clock is buffered by inverters (U1) and provides a true (noninverted) output to
the TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510 and a true equivalent
output at pin 22 of the output connector J5. This provides the user a buffered
reference clock output for external circuitry.
2-6
Circuit Description
Page 17
2.4 Board Schematic
Figure 2–1 shows the EVM board schematic.
Board Schematic
Circuit Description
2-7
Page 18
Board Schematic
R10
912
U1E
74AC11004B
C4
5 VD
J1
U1A
15 16
R1
BNC
CLOCK IN
E20
See Note 4
1
2
5 VD
U1F
1
74AC11004B
20
ANALOG OUT
TP2
R7
+
5 VA
R2 POT
R11
5 VA
E19
1011
GND
R12
74AC11004B
4567
TP1
R4
U2
C7
C8
JP1
C6
IN
ANALOG
6
THS3001
7
_
+
3
2
See Note C
E1 E2
+
J4
BNC
J5
GND
D1
GNDD2GNDD3GNDD4GND
123456789
D1D2D3D4D5D6D7
R13F
R13H
R13G
89
710
611
121314151617181920
10
Q8Q7Q6Q5Q4Q3Q2
GND
U4
74AC573
GND
D8D7D6D5D4D3D2
C
OC
9876543
11
10
1
12345678910
D1D2D3D4D5D6D7
CLOCK
U3
TLV5540/TLV5510
ANALOG IN
TLC5540/TLC5510/TLC5510A/
19
141518
E12
See Note 3
JP2
E11
E10
E23
C14
FB1
R8
4
R6
R15
C16
–
+
C19
–5 VA
E3 E4
R5
FB5
E5 E6
E7 E8
D5
GNDD6GNDD7GNDD8GND
101112131415161718192021222324
R13E
512
VDDA
C5
See Note 6
R13D
413
VDDA
FB2
FB3
Area
Breadboard
E24 E25
R13B
R13C
314
215
Q1
D1
2
D8
VDDA
J9
1
+
+
+
5 VD
D8
R13A
116
VCC
C15
5 VD
1
OE
REFTS
REFT
161723
1
J10
C26C22
C25
C18
C17C10
C9
+
5 VA
C27
+
2
1
J8
GND
5 V dc
X
11
VDD
REFB
1
R3
GND
GND
X
5 VD
+
13224
VDD
222021
J16
1
J11
++
2
J12
CLOCK OUT
GND
OE
C12
C13 C11
DGND
DGND
REFBS
AGND
AGND
C23C24C20C21
4 V
FB4
R9
5 VA
+
1
J2
5 V dc
C1
2
GND
See Note 4
1
See Note 4
1
U1B
See Note 4
1
J7
E17
E18
2
E15
E16
2
E27
219
1
See Note 5
2
1
J6-1
J6-2
U5
2
74AC11004B
J13
R14
OPTION TABLE
JP1, JP2, JP3, JP4, (J6-1–J6-2), J13, J14, J15,
(E15–E16), (E17–E18), (E19–E20),J10, J11, C24, C23
JP1, JP2, JP3, JP4, (J6-1–J6-2), J13, J14, J15,
(E15–E16), (E17–E18), (E19–E20), J10, J11, C24, C23
(E15–E16), (E17–E18), (E19–E20), J11, J7, J12, R14, R9, R3,
U5, J9 AND J16
DEVICE INSTALL
TLV5510
TLV5540
TLC5510
TLC5540
TLC5510A JP1, JP2, JP3, JP4, (J6-1–J6-2), J13, J14, J15,
E30
318
U1C
2
1
See Note 5
JP3
E13 E14
See Note 3
C27
+
2
1
J3
GND
–5 V dc
74AC11004B
J14
See Option Table
–5 VA
E33
813
U1D
74AC11004B
2
1
2
J15
See Note 5
JP4
E21 E22
2) Unless otherwise specified resistors are in ohms, ±5%.
3) JP1, JP2, JP3, JP4 are jumper wires that are installed at the factory.
4) (J6-1–J6-2), (E15-E16), (E17-E18), and (E19-E20) are 1” center headers with removable jumpers.
5) E-26, E28, and E30 inverter inputs should be tied to J13-2, J14-2, and J15-2, respectively, if not being used.
6) FB5, R15 and C5 are optional LP filter components.
Figure 2–1.Board Schematic
2-8
Notes: 1) Unless otherwise specified capacitors are in µF, ±20%, 50 Vdc.
Page 19
Chapter 3
Physical Description
This chapter describes the physical characteristics and PCB layout of the EVM
and lists the components used on the module.
Topic Page
3.1 Board Layout 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Board Layers 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Part Descriptions 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Description
3-1
Page 20
Board Layout
3.1 Board Layout
Figure 3–1 shows the EVM board layout.
Figure 3–1.EVM Board Layout
3-2
Physical Description
Page 21
3.2 Board Layers
Figures 3–2 through 3–5 show the EVM board layers.
Figure 3–2.EVM Board Layer 1
Board Layers
Physical Description
3-3
Page 22
Board Layers
Figure 3–3.EVM Board Layer 2
3-4
Physical Description
Page 23
Figure 3–4.EVM Board Layer 3
Board Layers
Physical Description
3-5
Page 24
Board Layers
Figure 3–5.EVM Board Layer 4
3-6
Physical Description
Page 25
3.3 Part Descriptions
Table 3–1 lists and describes the EVM parts. C2 and E9 are not used.
Table 3–1.Part Descriptions
Quantity Reference Description
11 C4, C7, C11 C13, C15, C16,
C17, C20, C23, C25, C26
0.1 µF capacitor, 50 V, 10%, COG, SMD, size 1206
Part Descriptions
13 C1, C3, C6, C8–C10, C12,
C18, C19, C21, C22, C24, C27
1 C5
1 C14 100 pF (TLC5540)/150 pF(TLC5510/TLC5510A) capacitor,
3 FB1–FB5
2 J1, J4 Connector, BNC, 50 Ω, vertical, PC mount
3 J2, J3, J8 Screw terminal, 2 pin, vertical
1 J5 Header, 2 12, 0.025 inch square pins, 0.1 inch centers
4 J6, (E15, E16), (E17, E18),
4 R1, R4, R5, R7 Resistor, 49.9 Ω, 1/8 W, 1 %, SMD, size 0805
1 R2 Potentiometer, 10 kΩ, multiturn SMD
1 R3 Resistor, 20 Ω, 1/4 W, SMD, size 1210
2 R6, R8 Resistor, 750 Ω, 1/10 W, 1 %, SMD, size 0805
1 R9 Resistor, 15K, 1/10 W, 1%, SMD, size 1210
1 R10 Resistor, 22 Ω, 1/10 W, 5%, SMD, size 0805
†
†
(E19, E20)
4.7 µF capacitor, tantalum electrolytic, SMD, size A
68 pF capacitor, 50 V, 5%, NPO, SMD, size 1210
50 V, 5%, NPO, SMD, size 0805
Ferrite bead, SMD, size 1206, Murata BLM31B601SPT
Header, 1 2, 0.025 inch square pins, 0.1 inch centers
2 R11, R12 Resistor, 1 kΩ, 1/10 W, 5 %, SMD, size 0805
1 R13 Resistor pack, 22 Ω 8, 1/8 W, 5%, SMD, SOIC-16
1 R14 Resistor, 24.9K, 1/10 W, 1%, SMD, size 1210
1 R15
2 TP1, TP2 Test point terminal
4 P6, (P15, P16), (P17, P18),
1 U1 IC, (SN)74AC11004DW inverter, SOIC-16
1 U2 IC, THS3001CD operational amplifier, SOIC-8
1 U3 IC, TLC5540INSLE/TLC5510INSLE/TLC5510AINSLE/
1 U4 IC, SN74AC573DW octal transparent latch, SOIC-20
1 U5 IC, TL431AID or TLV431AIDBV5, SOIC–8, SOT–23
1 PCB1 PCB, TLC5540/TLC5510/TLC5510A/TLV5540/TLV5510
†
C5, FB5 and R15 not on REV C PCB
†
(P19, P20)
Resistor, 10 Ω, 1/10 W, 1%, SMD, size 1210
Jumper, for 0.025 inch, square pins, 0.1 inch centers
TLV5540INSLE/TLV5510INSLE ADC
Physical Description
3-7
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