Texas Instruments TLC2943IDB Datasheet

TLC2943

T

20°C to 75°C

HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK

SLAS249 – NOVEMBER 1999

D

Dual TLC2933 by Multichip Module
(MCM) Technology

D

Voltage-Controlled Oscillators (VCO)
Section

– Complete Oscillator Using Only One

External Bias Resistor (RBIAS)

– Recommended Lock Frequency

Range

– 37 MHz to 60 MHz

= 3.3 V ± 0.15 V, T

(V

DD

to 75°C)

– 43 MHz to 100 MHz

= 5 V ± 0.25 V, TA = –20°C

(V

DD

to 75°C)

D

Includes a High Speed Edge-Triggered
Phase Frequency Detector (PFD) With
Internal Charge Pump

D

Independent VCO, PFD Power-Down
Mode

description

= –20°C

A

LOGIC_1 V

DD

TEST_1

VCO_1 OUT

-A_1

F

IN

F

-B_1

IN

PFD_1 OUT

LOGIC_1 GND

GND

NC
NC
NC

GND

LOGIC_2 V

DD

TEST_2

VCO_2 OUT

F

-A_2

IN

F

-B_2

IN

PFD_2 OUT

LOGIC_2 GND

DB PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

VCO_1 V

38

R

37

BIAS

VCOIN_1

36

VCO_1 GND

35

VCO_1 INHIBIT

34

PFD_1 INHIBIT

33

NC

32

GND

31

NC

30

NC

29

NC

28

GND

27

VCO_2 V

26

R

25

BIAS

VCOIN_2

24

VCO_2 GND

23

VCO_2 INHIBIT

22

PFD_2 INHIBIT

21

NC

20

The TLC2943 is a multichip module product that
uses two TLC2933 chips. The TLC2933 chip is
composed of a voltage-controlled oscillator (VCO) and an edge-triggered-type phase frequency detector
(PFD). The oscillation frequency range of the VCO is set by an external bias resistor (R BIAS ). The high-speed
PFD with internal charge pump detects the phase difference between the reference frequency input and signal
frequency input from the external counter. Both the VCO and the PFD have inhibit functions that can be used
as a power-down mode. The high-speed and stable VCO characteristics of the TLC2933 make the TLC2943
suitable for use in dual high-performance phase-locked loop (PLL) systems.

DD

_1

DD

_2

°

–

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

AVAILABLE OPTIONS

A

°

TLC2943IDBR (Tape and Reel)

PACKAGE

SMALL OUTLINE (DB)

TLC2943IDB

Copyright  1999, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK

SLAS249 – NOVEMBER 1999

functional block diagram

VCOIN_1

FIN-A_1

FIN-B_1

VCO_1 INHIBIT

VCO_1

PFD_1

PFD_1 INHIBIT

VCO_1 OUT

PFD_1 OUT

VCO_2 OUT

PFD_2 OUT

VCO_2 INHIBIT

VCO_2

PFD_2

PFD_2 INHIBIT

VCOIN_2

FIN-A_2

FIN-B_2

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2943

I/O

DESCRIPTION

GND

HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK

SLAS249 – NOVEMBER 1999

Terminal Functions

TERMINAL

NAME NO.

8, 31 Common GND for chip 1

12, 27 Common GND for chip 2

FIN–A_1,
FIN–B_1

FIN–A_2,
FIN–B_2

LOGIC_1 GND 7 Ground for the internal logic of chip 1
LOGIC_2 GND 19 Ground for the internal logic of chip 2

LOGIC_1 V

LOGIC_2 V

NC

PFD_1 INHIBIT 33 I

PFD_2 INHIBIT 21 I
PFD_1 OUT 6 O PFD output of chip 1. When the PFD_1 INHIBIT is high, PFD_1 OUT is in the high-impedance state.

PFD_2 OUT 18 O PFD output of chip 2. When the PFD_2 INHIBIT is high, PFD_2 OUT is in the high-impedance state.
R

BIAS

R

BIAS

TEST_1 2 Test terminal. TEST connects to LOGIC_1 GND for normal operation.
TEST_2 14 Test terminal. TEST connects to LOGIC_2 GND for normal operation.
VCO_1 GND 35 GND for VCO_1
VCO_2 GND 23 GND for VCO_2
VCO_1 INHIBIT 34 I VCO inhibit control for chip 1. When VCO_1 INHIBIT is high, VCO_1 OUT is low (see Table 1).
VCO_2 INHIBIT 22 I VCO inhibit control for chip 2. When VCO_2 INHIBIT is high, VCO_2 OUT is low (see Table 1).
VCO_1 OUT 3 O VCO output of chip 1. When VCO_1 INHIBIT is high, VCO_1 OUT is low.
VCO_2 OUT 15 O VCO output of chip 2. When VCO_2 INHIBIT is high, VCO_2 OUT is low.

VCO_1 V

VCO_2 V

VCOIN_1 36 I

VCOIN_2 24 I

DD

DD

_1 37 I

_2 25 I

DD

DD

4
5

16
17

1

13

9, 10,
11, 20,
28, 29,

30, 32

38

26

Reference frequency signal input and comparison frequency signal input for PFD_1. fREF–IN_1 inputs
to FIN-A_1, and comparison frequency input from external counter logic to FIN–B_1, for a lag-lead filter

I

use as LPF.
Reference frequency signal input and comparison frequency signal input for PFD_2. fREF–IN_2 inputs

to FIN-A_2, and comparison frequency input from external counter logic to FIN-B_2, for a lag-lead filter use

I

as LPF.

Power supply for the internal logic of chip 1. This power supply should be separate from VCO VDD to
reduce cross-coupling between supplies.

Power supply for the internal logic of chip 2. This power supply should be separate from VCO VDD to
reduce cross-coupling between supplies.

No internal connection

PFD inhibit control for chip 1. When PFD_1 INHIBIT is high, PFD_1 OUT is in the high-impedance state,
see Table 2.

PFD inhibit control for chip 2. When PFD_2 INHIBIT is high, PFD_2 OUT is in the high-impedance state,
see Table 2.

Bias supply for VCO_1. An external resistor (R
adjusting the oscillation frequency range of VCO_1.

Bias supply for VCO_2. An external resistor (R
adjusting the oscillation frequency range of VCO_2.

Power supply for VCO_1. This power supply should be separate from LOGIC VDD to reduce
cross-coupling between supplies.

Power supply for VCO_2. This power supply should be separate from LOGIC VDD to reduce
cross-coupling between supplies.

VCO_1 control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency .

VCO_2 control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency .

) between VCO_1 VDD and BIAS_1 supplies bias for

BIAS

) between VCO_2 VDD and BIAS_2 supplies bias for

BIAS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK

SLAS249 – NOVEMBER 1999

detailed description

MCM (multichip module) technology for TLC2943

The TLC2943 is a multichip module (MCM) product that uses two TLC2933 chips. Inside the package, two chips
are completely isolated by a special formed lead-frame. Therefore,when using the TLC2943 in two
asynchronous PLL circuits, there is no performance degradation by electrical interference between chips inside
the package. So, the same performance as TLC2933 can be easily expected by using TLC2943.

The NC terminals in the middle on both sides of the package are to achieve complete isolation inside the
package. To get the best performance from this MCM technology, it is better to make a careful board layout of
the external power supply, ground, and signal lines.

voltage controlled oscillator (VCO)

VCO_1 and VCO_2 have the same typical characteristics. Each VCO oscillation frequency is determined by
an external resistor (R
and range depend on this resistor value. The bias resistor value for the minimum temperature coefficient is
nominally 2.2 kΩ with V
the recommended operating conditions. Figure 1 shows the typical frequency variation and VCO control
voltage.

VCO Oscillation Frequency (f

) connected between the VCO VDD and the BIAS terminals. The oscillation frequency

BIAS

= 3.3 V and nominally 2.4 kΩ with VDD = 5 V . For the lock frequency range, refer to

DD

)

osc

VCO Oscillation Frequency Range

BIAS Resistor (R

VCO Control Voltage (V

BIAS)

COIN

)

Figure 1. VCO_1 and VCO_2 Oscillation Frequency

VCO inhibit function

Each VCO has an externally controlled inhibit function that inhibits the VCO output. The VCO oscillation is
stopped during a high level on VCOINHIBIT, so the high level can also be used as the power-down mode. The
VCO output maintains a low level during the power-down mode (see Table 1 and Table 2).

Table 1. VCO_1 Inhibit Function

VCO_1 INHIBIT VCO_1 OSCILLATOR VCO_1 OUT VCO_1 I

Low Active Active Normal
High Stop Low Power down

DD

Table 2. VCO_2 Inhibit Function

VCO_2 INHIBIT VCO_2 OSCILLATOR VCO_2 OUT VCO_2 I

Low Active Active Normal
High Stop Low Power down

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DD

HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK

SLAS249 – NOVEMBER 1999

detailed description (continued)

phase frequency detector (PFD)

The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN-A and FIN-B as shown in Figure 2. Nominally the
reference is supplied to FIN-A, and the frequency from the external counter output is fed to FIN-B. For clock
recovery PLL systems, other types of phase detectors should be used.

FIN-A_1, 2

FIN-B_1, 2

VOH

PFD_1, 2 OUT

HI-Z

TLC2943

VOL

Figure 2. PFD Function Timing Chart

PFD output control

A high level on PFD INHIBIT places the PFD OUT in the high impedance state and the PFD stops phase
detection as shown in T able 3 and T able 4. A high level on PFD inhibit also can be used as the power-down mode
for the PFD.

Table 3. PFD_1 Inhibit Function

PFD_1 INHIBIT PFD_1 PFD_1 OUT PFD_1 I

Low Active Active Normal

High Stop Hi-Z Power down

DD

Table 4. PFD_2 Inhibit Function

PFD_2 INHIBIT PFD_2 PFD_2 OUT PFD_2 I

Low Active Active Normal

High Stop Hi-Z Power down

DD

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK

SLAS249 – NOVEMBER 1999

internal function block diagram

BIAS

Resistor

VCO Control

V

COIN

FIN-A

FIN-B

BIAS

Circuit

Figure 3. VCO Block Schematic (VCO_1, VCO_2)

Detector

Figure 4. PFD Block Schematic (PFD_1, PFD_2)

Charge Pump

PFD OUT

Output

Buffer

VCO OUT

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2943

HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK

SLAS249 – NOVEMBER 1999

DD

†

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage (each supply), V
Input voltage range (each input), V
Input current (each input), I

I

(se e Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

(se e Note 1) –0.5 to V

I

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current (each output), IO ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation at (or below) T

= 25°C (see Note 2) 1160 mW. . . . . . . . . . . . . . . . . . . . . . . .

A

Operating free-air temperature range, TA –20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 260

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to network ground terminal.

2. For operation above 25°C free-air temperature, derate linearly at the rate of 9.3 mW/

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

°C.

°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions

MIN NOM MAX UNIT

VDD = 3 V 2.85 3 3.15

Supply voltage (each supply, see Notes 3 and 4 ), V

Input voltage range (input except for VCOIN_1, 2), V
Output current (each output), I
Control voltage, VCOIN 1 V

Clock frequency, f

Oscillation frequency range set resistor (each RBIAS), R

Top operating temperature range –20 75

NOTES: 3. It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) be at the same voltage and

separated from each other.

4. Insert bypass capacitors locating the nearest point to each power supply terminal.

O

DD

I

BIAS

VCO

VDD = 3.3 V 3.15 3.3 3.45
VDD = 5 V 4.75 5 5.25

0 V
0 ±2 mA

VDD = 3 V 37 55
VDD = 3.3 V 37 60
VDD = 5 V 43 100
VDD = 3 V 1.8 2.7
VDD = 3.3 V 1.8 3.0
VDD = 5 V 2.2 3.0

DD

DD

V

V

V

MHz

kΩ

_

C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK

SLAS249 – NOVEMBER 1999

electrical characteristics over recommended operating free-air temperature range, VDD = 3 V
(unless otherwise noted)

VCO section

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

V

OH

V

OL

V

(TH+)

I

I

Z

(VCOIN)

I

DD(INH)

I

DD(VCO)

NOTES: 5. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD and PFD INHIBIT is high.

PFD section

V

OH

V

OL

I

OZ

V

IH

V

IL

V

(TH+)

C

I

Z

I

I

DD(PFD)

NOTE 7: The current into LOGIC VDD when FIN–A and FIN–B = 30 MHz (V I(PP) = 3 V , rectangular wave), PFD INHIBIT = GND, PFD OUT open,

High-level output voltage IOH = –2 mA 2.4 V
Low-level output voltage IOL = 2 mA 0.3 V
Positive input threshold voltage 0.9 1.5 2.1 V
Input current VI = VDD or GND ±1 µA
VCOIN input impedance VCOIN = 1/2V
VCO supply current (inhibit) (for one chip) See Note 5 0.01 1 µA
VCO supply current (for one chip) See Note 6 5.1 15 mA

6. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD , R
is high.

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

High-level output voltage IOH = –2 mA 2.7 V
Low-level output voltage IOL = 2 mA 0.2 V
High-impedance state output current PFD INHIBIT = high, VO = VDD or GND ±1 µA
High-level input voltage at FIN–A, FIN–B 2.1 V
Low-level input voltage at FIN–A, FIN–B 0.9 V
Positive input threshold voltage at PFD

INHIBIT
Input capacitance at FIN–A, FIN–B 5 pF
Input impedance at FIN–A, FIN–B 10 MΩ
PFD supply current See Note 7 0.7 4 mA

and VCO OUT is inhibited.

BIAS

DD

= 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT

0.9 1.5 2.1 V

10 MΩ

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2943

HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK

SLAS249 – NOVEMBER 1999

electrical characteristics over recommended operating free-air temperature range, VDD = 3.3 V
(unless otherwise noted) (continued)

VCO section

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

V

OH

V

OL

V

(TH+)

I

I

Z

(VCOIN)

I

DD(INH)

I

DD(VCO)

NOTES: 5. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD and PFD INHIBIT is high.

PFD section

V

OH

V

OL

I

OZ

V

IH

V

IL

V

(TH+)

C

I

Z

I

I

DD(PFD)

NOTE 8: The current into LOGIC VDD when FIN–A and FIN–B = 30 MHz (V I(PP) = 3.3 V , rectangular wave), PFD INHIBIT = GND, PFD OUT

High-level output voltage IOH = –2 mA 2.7 V
Low-level output voltage IOL = 2 mA 0.4 V
Positive input threshold voltage 1 1.65 2.3 V
Input current VI = VDD or GND ±1 µA
VCOIN input impedance VCOIN = 1/2V
VCO supply current (inhibit) (for one chip) See Note 5 0.01 1 µA
VCO supply current (for one chip) See Note 6 6.2 16 mA

6. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD , R
is high.

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

High-level output voltage IOH = –2 mA 3 V
Low-level output voltage IOL = 2 mA 0.2 V
High-impedance state output current PFD INHIBIT = high, VO = VDD or GND ±1 µA
High-level input voltage at FIN–A, FIN–B 2.3 V
Low-level input voltage at FIN–A, FIN–B 1 V
Positive input threshold voltage at PFD

INHIBIT
Input capacitance at FIN–A, FIN–B 5 pF
Input impedance at FIN–A, FIN–B 10 MΩ
PFD supply current See Note 8 0.8 5 mA

open, and VCO OUT is inhibited.

BIAS

DD

= 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT

10 MΩ

1 1.65 2.3 V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9