TEXAS INSTRUMENTS TLC2933 Technical data

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TLC2933

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

D

Voltage-Controlled Oscillator (VCO)
Section:

PW PACKAGE

(TOP VIEW)

†

– Ring Oscillator Using Only One

External Bias Resistor (R

BIAS

)

– Lock Frequency:

43 MHz to 100 MHz (V
T

= –20°C to 75°C, ×1 Output)

A

37 MHz to 55 MHz (V
T

= –20°C to 75°C)

A

D

Phase-Frequency Detector (PFD) Section

= 5 V ±5%,

DD

= 3 V ±5%,

DD

Includes a High-Speed Edge-Triggered
Detector With Internal Charge Pump

D

Independent VCO, PFD Power-Down Mode

D

Thin Small-Outline Package (14 terminal)

D

CMOS Technology

D

Typical Applications:

LOGIC V

LOGIC GND

†

Available in tape and reel only and ordered as the
TLC2933PWLE.

NC – No internal connection

DD

TEST

VCO OUT

FIN–A
FIN–B

PFD OUT

1
2
3
4
5
6
7

14
13
12
11
10

9
8

– Frequency Synthesis
– Modulation/Demodulation
– Fractional Frequency Division

D

CMOS Input Logic Level

description

The TLC2933 is designed for phase-locked-loop (PLL) systems and is composed of a voltage-controlled
oscillator (VCO) and an edge-triggered-type phase frequency detector (PFD). The oscillation frequency range
of the VCO is set by an external bias resistor (R
the phase difference between the reference frequency input and signal frequency input from the external
counter. Both the VCO and the PFD have inhibit functions that can be used as a power-down mode. With the
high-speed and stable VCO characteristics, the TLC2933 is well suited for use in high-performance PLL
systems.

). The high-speed PFD with internal charge pump detects

BIAS

VCO V

DD

BIAS

IN

VCO
VCO GND
VCO INHIBIT
PFD INHIBIT
NC

functional block diagram

4

FIN–A
FIN–B

PFD INHIBIT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

5

Frequency

Detector

9

Phase

VCO IN

6

PFD OUT

AVAILABLE OPTIONS

T

A

–20°C to 75°C TLC2933PWLE

SMALL OUTLINE

BIAS

VCO INHIBIT

TEST

PACKAGE

(PW)

12
13

Voltage-

Controlled

10

Oscillator

2

Copyright  1997, Texas Instruments Incorporated

3

VCO OUT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

TLC2933

I/O

DESCRIPTION

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

Terminal Functions

TERMINAL

NAME NO.

BIAS 13 I Bias supply. An external resistor (R

FIN–A 4 I Input reference frequency f
FIN–B 5 I Input for VCO external counter output frequency f

LOGIC GND 7 Ground for the internal logic.
LOGIC V

NC 8 No internal connection.
PFD INHIBIT 9 I PFD inhibit control. When PFD INHIBIT is high, PFD OUT is in the high-impedance state, see Table 2.
PFD OUT 6 O PFD output. When the PFD INHIBIT is high, PFD OUT is in the high-impedance state.
TEST 2 I Test terminal. TEST connects to ground for normal operation.
VCO GND 11 Ground for VCO.
VCO IN 12 I VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO

VCO INHIBIT 10 I VCO inhibit control. When VCO INHIBIT is high, VCO OUT is low (see Table 1).
VCO OUT 3 O VCO output. When VCO INHIBIT is high, VCO OUT is low.
VCO V

DD

DD

1 Power supply for the internal logic. This power supply should be separate from VCO VDD to reduce

14 Power supply for VCO. This power supply should be separated from LOGIC VDD to reduce cross-coupling

oscillation frequency range.

(REF IN)

counter.

cross-coupling between supplies.

oscillation frequency .

between supplies.

) between VCO VDD and BIAS supplies bias for adjusting the

BIAS

is applied to FIN–A.

(FIN–B)

. FIN–B is nominally provided from the external

detailed description

VCO oscillation frequency

The VCO oscillation frequency is determined by an external resistor (R
and the BIAS terminals. The oscillation frequency and range depends on this resistor value. While all resistor
values within the specified range result in excellent low temperature coefficients, the bias resistor value for the
minimum temperature coefficient is nominally 2.2 kΩ with 3-V V

and nominally 2.4 kΩ with 5-V VDD. For the

DD

lock frequency range refer to the recommended operating conditions. Figure 1 shows the typical frequency
variation and VCO control voltage.

VCO Oscillation Frequency Range

osc

(f )

VCO Oscillation Frequency

1/2 V

VCO Control Voltage (VCO IN)

Bias Resistor (R

DD

BIAS

)

) connected between the VCO V

BIAS

DD

Figure 1. VCO Oscillation Frequency

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

VCO inhibit function

The VCO has an externally controlled inhibit function which inhibits the VCO output. A high level on the VCO
INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during
the power-down mode as shown in Table 1.

Table 1. VCO Inhibit Function

TLC2933

VCO INHIBIT VCO OSCILLATOR VCO OUT I

Low Active Active Normal

High Stopped Low level Power Down

DD(VCO)

PFD operation

The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN–A and FIN–B as shown in Figure 2. Nominally the
reference is supplied to FIN–A, and the frequency from the external counter output is fed to FIN–B. For clock
recovery PLL systems, other types of phase detectors should be used.

FIN–A

FIN–B

V

OH

PFD OUT

Hi-Z

V

OL

Figure 2. PFD Function Timing Chart

PFD inhibit control

A high level on the PFD INHIBIT terminal places PFD OUT in the high-impedance state and the PFD stops
phase detection as shown in Table 2. A high level on the PFD INHIBIT terminal can also be used as the
power-down mode for the PFD.

Table 2. VCO Output Control Function

PFD INHIBIT DETECTION PFD OUT I

Low Active Active Normal

High Stopped Hi-Z Power Down

DD(PFD)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TLC2933
HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

schematics

VCO block schematic

R

BIAS

BIAS

VCO

Output

Buffer

VCO OUT

VCO IN

VCO INHIBIT

Bias

Control

PFD block schematic

Charge Pump

V

DD

FIN–A

Detector

FIN–B

PFD INHIBIT

absolute maximum ratings

Supply voltage (each supply), V
Input voltage range (each input), V
Input current (each input), I
Output current (each output), I

†

(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

(see Note 1) –0.3 V to V

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

I

±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

Continuous total power dissipation at (or below) T
Operating free-air temperature range, T
Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

= 25°C (see Note 2) 700 mW. . . . . . . . . . . . . . . . . . . . . . .

–20°C to 75°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

A

PFD OUT

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to network ground terminal.

2. For operation above 25°C free-air temperature, derate linearly at the rate of 5.6 mW/°C.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Suppl

oltage, V

(each suppl

see Note 3)

V

Lock frequenc

MH

Bias resistor, R

kΩ

TLC2933

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

recommended operating conditions

MIN NOM MAX UNIT

pp

y v

Input voltage, VI (inputs except VCO IN) 0 V
Output current, IO (each output) 0 ±2 mA
VCO control voltage at VCO IN 1 V

NOTE 3: It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) be at the same voltage and

separated from each other.

y

BIAS

DD

pp

y,

electrical characteristics over recommended operating free-air temperature range, VDD = 3 V
(unless otherwise noted)

VCO section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

V

OL

V

IT+

I

I

Z

i(VCO IN)

I

DD(INH)

I

DD(VCO)

NOTES: 4. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD and PFD INHIBIT is high.

High-level output voltage IOH = –2 mA 2.4 V
Low-level output voltage IOL = 2 mA 0.3 V
Positive input threshold voltage at TEST, VCO INHIBIT 0.9 1.5 2.1 V
Input current at TEST, VCO INHIBIT VI = VDD or ground ±1 µA
Input impedance at VCO IN VCO IN = 1/2 V
VCO supply current (inhibit) See Note 4 0.01 1 µA
VCO supply current See Note 5 5.1 15 mA

5. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD, R
is high.

VDD = 3 V 2.85 3 3.15
VDD = 5 V 4.75 5 5.25

DD

DD

VDD = 3 V 37 55
VDD = 5 V 43 100
VDD = 3 V 1.8 2.7
VDD = 5 V 2.2 3

DD

= 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT

BIAS

10 MΩ

V

V

z

PFD section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

V

OL

I

OZ

V

IH

V

IL

V

IT+

C

i

Z

i

I

DD(Z)

I

DD(PFD)

NOTES: 6. The current into LOGIC VDD when FIN–A and FIN–B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.

High-level output voltage IOH = –2 mA 2.7 V
Low-level output voltage IOL = 2 mA 0.2 V

High-impedance-state output current
High-level input voltage at FIN–A, FIN–B 2.1 V

Low-level input voltage at FIN–A, FIN–B 0.9 V
Positive input threshold voltage at PFD INHIBIT 0.9 1.5 2.1 V
Input capacitance at FIN–A, FIN–B 5 pF
Input impedance at FIN–A, FIN–B 10 MΩ
High-impedance-state PFD supply current See Note 6 0.01 1 µA
PFD supply current See Note 7 0.7 4 mA

7. The current into LOGIC VDD when FIN–A and FIN–B = 30 MHz (V
open, and VCO OUT is inhibited.

PFD INHIBIT = high,
VI = VDD or ground

= 3 V , rectangular wave), PFD INHIBIT = GND, PFD OUT

I(PP)

±1 µA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TLC2933

ns

See Figures 4 and 5 and Table 3

ns

C

15 pF

See Figure 4

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

operating characteristics over recommended operating free-air temperature range, VDD = 3 V
(unless otherwise noted)

VCO section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

osc

t

s(fosc)

t

r

t

f

α

(fosc)

k

SVS(fosc)

NOTES: 8. The time period to stabilize the VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.

PFD section

f

max

t

PLZ

t

PHZ

t

PZL

t

PZH

t

r

t

f

Operating oscillation frequency R
Time to stable oscillation (see Note 8) Measured from VCO INHIBIT↓ 10 µs
Rise time, VCO OUT↑ CL = 15 pF, See Figure 3 3.3 10 ns
Fall time, VCO OUT↓ CL = 15 pF, See Figure 3 2 8 ns
Duty cycle at VCO OUT R

Temperature coefficient of oscillation frequency

Supply voltage coefficient of oscillation frequency

Jitter absolute (see Note 9) R

9. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with
a carefully designed printed circuit board (PCB) with no device socket.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Maximum operating frequency 30 MHz
Disable time, PFD INHIBIT↑ to PFD OUT Hi-Z 20 40
Disable time, PFD INHIBIT↑ to PFD OUT Hi-Z
Enable time, PFD INHIBIT↓ to PFD OUT low
Enable time, PFD INHIBIT↓ to PFD OUT high 4.8 18
Rise time, PFD OUT↑
Fall time, PFD OUT↓

= 2.4 kΩ, VCO IN = 1/2 V

BIAS

= 2.4 kΩ, VCO IN = 1/2 V

BIAS

R

= 2.4 kΩ, VCO IN = 1/2 VDD,

BIAS

TA = –20°C to 75°C
R

= 2.4 kΩ, VCO IN = 1.5 V,

BIAS

VDD = 2.85 V to 3.15 V

= 2.4 kΩ 100 ps

BIAS

p

,

=

L

DD

DD

38 48 55 MHz

45% 50% 55%

0.03 %/°C

0.04 %/mV

18 40

4.1 18

3.1 9 ns

1.5 9 ns

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC2933

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

electrical characteristics over recommended operating free-air temperature range, VDD = 5 V
(unless otherwise noted)

VCO section

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

V

OL

V

IT+

I

I

Z

i(VCO IN)

I

DD(INH)

I

DD(VCO)

NOTES: 4. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD, and PFD INHIBIT high.

PFD section

V

OH

V

OL

I

OZ

V

IH

V

IL

V

IT+

C

i

Z

i

I

DD(Z)

I

DD(PFD)

NOTES: 6. The current into LOGIC VDD when FIN–A and FIN–B = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.

High-level output voltage IOH = –2 mA 4.5 V
Low-level output voltage IOL = 2 mA 0.5 V
Positive input threshold voltage at TEST, VCO INHIBIT 1.5 2.5 3.5 V
Input current at TEST, VCO INHIBIT VI = VDD or ground ±1 µA
Input impedance at VCO IN VCO IN = 1/2 V
VCO supply current (inhibit) See Note 4 0.01 1 µA
VCO supply current See Note 5 14 35 mA

5. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD, R
high.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage IOH = 2 mA 4.5 V
Low-level output voltage IOL = 2 mA 0.2 V

High-impedance-state output current
High-level input voltage at FIN–A, FIN–B 3.5 V

Low-level input voltage at FIN–A, FIN–B 1.5 V
Positive input threshold voltage at PFD INHIBIT 1.5 2.5 3.5 V
Input capacitance at FIN–A, FIN–B 7 pF
Input impedance at FIN–A, FIN–B 10 MΩ
High-impedance-state PFD supply current See Note 6 0.01 1 µA
PFD supply current See Note 10 2.6 8 mA

10. The current into LOGIC VDD when FIN–A and FIN–B = 50 MHz (V
open, and VCO OUT is inhibited.

I(PP)

= 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT

BIAS

PFD INHIBIT = high,
VI = VDD or ground

= 3 V , rectangular wave), PFD INHIBIT = ground, PFD OUT

DD

10 MΩ

±1 µA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7