Datasheet TLC1549IP, TLC1549IDR, TLC1549ID, TLC1549CP, TLC1549CDR Datasheet (Texas Instruments)

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

10-Bit-Resolution A/D Converter

D

Inherent Sample and Hold

D

T otal Unadjusted Error...±1 LSB Max

D

On-Chip System Clock

D

T erminal Compatible With TLC549 and
TL V1549

D

CMOS Technology

description

The TLC1549C, TLC1549I, and TLC1549M
are 10-bit, switched-capacitor, successive­approximation analog-to-digital converters.
These devices have two digital inputs and a
3-state output [chip select (CS

), input-output clock
(I/O CLOCK), and data output (DATA OUT)] that
provide a three-wire interface to the serial port of
a host processor.

The sample-and-hold function is automatic. The
converter incorporated in these devices features
differential high-impedance reference inputs that
facilitate ratiometric conversion, scaling, and
isolation of analog circuitry from logic and supply
noise. A switched-capacitor design allows low­error conversion over the full operating free-air
temperature range.

The TLC1549C is characterized for operation from 0°C to 70°C. The TLC1549I is characterized for operation
from –40°C to 85°C. The TLC1549M is characterized for operation over the full military temperature range of
–55°C to 125°C.

AVAILABLE OPTIONS

PACKAGE

T

A

SMALL OUTLINE

(D)

CHIP CARRIER

(FK)

CERAMIC DIP

(JG)

PLASTIC DIP

(P)

0°C to 70°C TLC1549CD — — TLC1549CP

–40°C to 85°C TLC1549ID — — TLC1549IP

–55°C to 125°C — TLC1549MFK TLC1549MJG —

Copyright  1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4

8
7
6
5

REF+

ANALOG IN

REF–

GND

V

CC

I/O CLOCK
DATA OUT
CS

D, JG, OR P PACKAGE

(TOP VIEW)

3212019

910111213

4
5
6
7
8

18
17
16
15
14

NC
I/O CLOCK
NC
DATA OUT
NC

NC

ANALOG IN

NC

REF–

NC

FK PACKAGE

(TOP VIEW)

NC

REF+

NC

CS

NC

NC

NC

GND

NC

NC – No internal connection

CC

V

TLC1549C, TLC1549I, TLC1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Sample and

Hold

10-Bit

Analog-to-Digital

Converter

(switched capacitors)

Output

Data

Register

10-to-1 Data

Selector and

Driver

System Clock,
Control Logic,

and I/O

Counters

10

10

4

REF+ REF–

DATA OUT

ANALOG IN

31

6

7
5

I/O CLOCK

CS

2

Terminal numbers shown are for the D, JG, and P packages only.

typical equivalent inputs

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kΩ TYP

Ci = 60 pF TYP
(equivalent input
capacitance)

5 MΩ TYP

ANALOG IN

ANALOG IN

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL
NAME NO.

I/O

DESCRIPTION

ANALOG IN 2 I Analog signal input. The driving source impedance should be ≤ 1 kΩ. The external driving source to ANALOG IN

should have a current capability ≥ 10 mA.

CS 5 I Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT and

I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. A low-to-high
transition disables I/O CLOCK within a setup time plus two falling edges of the internal system clock.

DATA OUT 6 O This 3-state serial output for the A/D conversion result is in the high-impedance state when CS is high and active

when CS

is low. With a valid chip select, DATA OUT is removed from the high-impedance state and is driven to
the logic level corresponding to the MSB value of the previous conversion result. The next falling edge of I/O
CLOCK drives DATAOUT to the logic level corresponding to the next most significant bit, and the remaining bits
are shifted out in order with the LSB appearing on the ninth falling edge of I/O CLOCK. On the tenth falling edge
of I/O CLOCK, DAT A OUT is driven to a low logic level so that serial interface data transfers of more than ten clocks
produce zeroes as the unused LSBs.

GND 4 The ground return for internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.
I/O CLOCK 7 I Input/output clock. I/O CLOCK receives the serial I/O CLOCK input and performs the following three functions:

1) On the third falling edge of I/O CLOCK, the analog input voltage begins charging the capacitor array and

continues to do so until the tenth falling edge of I/O CLOCK.

2) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.

3) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.

REF+ 1 I The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range is

determined by the difference between the voltage applied to REF+ and the voltage applied to REF–.

REF– 3 I The lower reference voltage value (nominally ground) is applied to REF–.
V

CC

8 Positive supply voltage

detailed description

With chip select (CS) inactive (high), I/O CLOCK is initially disabled and DATA OUT is in the high impedance
state. When the serial interface takes CS

active (low), the conversion sequence begins with the enabling of I/O
CLOCK and the removal of DATA OUT from the high-impedance state. The serial interface then provides the
I/O CLOCK sequence to I/O CLOCK and receives the previous conversion result from DA T A OUT. I/O CLOCK
receives an input sequence that is between 10 and 16 clocks long from the host serial interface. The first ten
I/O clocks provide the control timing for sampling the analog input.

There are six basic serial interface timing modes that can be used with the TLC1549. These modes are
determined by the speed of I/O CLOCK and the operation of CS

as shown in Table 1. These modes are (1) a

fast mode with a 10-clock transfer and CS

inactive (high) between transfers, (2) a fast mode with a 10-clock

transfer and CS

active (low) continuously , (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high)

between transfers, (4) a fast mode with a 16-bit transfer and CS

active (low) continuously , (5) a slow mode with

an 1 1- to 16-clock transfer and CS

inactive (high) between transfers, and (6) a slow mode with a 16-clock transfer

and CS

active (low) continuously.

The MSB of the previous conversion appears on DA T A OUT on the falling edge of CS

in mode 1, mode 3, and
mode 5, within 21 µs from the falling edge of the tenth I/O CLOCK in mode 2 and mode 4, and following the
sixteenth clock falling edge in mode 6. The remaining nine bits are shifted out on the next nine falling edges of
I/O CLOCK. T en bits of data are transmitted to the host serial interface through DA T A OUT . The number of serial
clock pulses used also depends on the mode of operation, but a minimum of ten clock pulses is required for
conversion to begin. On the tenth clock falling edge, the internal logic takes DA TA OUT low to ensure that the
remaining bit values are zero if the I/O CLOCK transfer is more than ten clocks long.

T able 1 lists the operational modes with respect to the state of CS

, the number of I/O serial transfer clocks that

can be used, and the timing on which the MSB of the previous conversion appears at the output.

TLC1549C, TLC1549I, TLC1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

Table 1. Mode Operation

MODES CS

NO. OF

I/O CLOCKS

MSB AT Terminal 6

†

TIMING

DIAGRAM

Mode 1 High between conversion cycles 10 CS falling edge Figure 6
Mode 2 Low continuously 10 Within 21 µs Figure 7

Fast Modes

Mode 3 High between conversion cycles 11 to 16

‡

CS falling edge Figure 8

Mode 4 Low continuously 16

‡

Within 21 µs Figure 9

Mode 5 High between conversion cycles 11 to 16

‡

CS falling edge Figure 10

Slow Modes

Mode 6 Low continuously 16

‡

16th clock falling edge Figure 11

†

This timing also initiates serial interface communication.

‡

No more than 16 clocks should be used.

All the modes require a minimum period of 21 µs after the falling edge of the tenth I/O CLOCK before a new
transfer sequence can begin. During a serial I/O CLOCK data transfer, CS

must be active (low) so that I/O

CLOCK is enabled. When CS

is toggled between data transfers (modes 1, 3, and 5), the transitions at CS are
recognized as valid only if the level is maintained for a minimum period of 1.425 µs after the transition. If the
transfer is more than ten I/O clocks (modes 3, 4, 5, and 6), the rising edge of the eleventh clock must occur within

9.5 µs after the falling edge of the tenth I/O CLOCK; otherwise, the device could lose synchronization with the
host serial interface and CS

has to be toggled to restore proper operation.

fast modes

The TLC1549 is in a fast mode when the serial I/O CLOCK data transfer is completed within 21 µs from the falling
edge of the tenth I/O CLOCK. With a ten-clock serial transfer, the device can only run in a fast mode.

mode 1: fast mode, CS inactive (high) between transfers, 10-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The
falling edge of CS

begins the sequence by removing DA TA OUT from the high-impedance state. The rising edge

of CS

ends the sequence by returning DA T A OUT to the high-impedance state within the specified delay time.

Also, the rising edge of CS

disables I/O CLOCK within a setup time plus two falling edges of the internal system

clock.

mode 2: fast mode, CS active (low) continuously, 10-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After
the initial conversion cycle, CS

is held active (low) for subsequent conversions. Within 21 µs after the falling

edge of the tenth I/O CLOCK, the MSB of the previous conversion appears at DATA OUT.

mode 3: fast mode, CS inactive (high) between transfers, 11- to 16-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 1 1 to 16 clocks
long. The falling edge of CS

begins the sequence by removing DA T A OUT from the high-impedance state. The

rising edge of CS

ends the sequence by returning DA T A OUT to the high-impedance state within the specified

delay time. Also, the rising edge of CS

disables I/O CLOCK within a setup time plus two falling edges of the

internal system clock.

mode 4: fast mode, CS active (low) continuously, 16-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS

is held active (low) for subsequent conversions. Within 21 µs after

the falling edge of the tenth I/O CLOCK, the MSB of the previous conversion appears at DATA OUT.

slow modes

In a slow mode, the serial I/O CLOCK data transfer is completed after 21 µs from the falling edge of the tenth
I/O CLOCK.

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

mode 5: slow mode, CS inactive (high) between transfers, 11- to 16-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 1 1 to 16 clocks
long. The falling edge of CS

begins the sequence by removing DA T A OUT from the high-impedance state. The

rising edge of CS

ends the sequence by returning DA T A OUT to the high-impedance state within the specified

delay time. Also, the rising edge of CS

disables I/O CLOCK within a setup time plus two falling edges of the

internal system clock.

mode 6: slow mode, CS active (low) continuously, 16-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS

is held active (low) for subsequent conversions. The falling edge of
the sixteenth I/O CLOCK then begins each sequence by removing DA T A OUT from the low state, allowing the
MSB of the previous conversion to appear immediately at DA T A OUT. The device is then ready for the next 16
clock transfer initiated by the serial interface.

analog input sampling

Sampling of the analog input starts on the falling edge of the third I/O CLOCK, and sampling continues for seven
I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK.

converter and analog input

The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the S

C

switch and all ST switches simultaneously .

This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector

begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF–)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector
looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF–. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half V

CC

), a bit 0 is placed in the
output register and the 512-weight capacitor is switched to REF–. If the voltage at the summing node is less
than the trip point of the threshold detector, a bit 1 is placed in the register and this 512-weight capacitor remains
connected to REF+ through the remainder of the successive-approximation process. The process is repeated
for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are determined.

With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB.

TLC1549C, TLC1549I, TLC1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

S

C

Threshold

Detector

NODE 512

REF–

REF+

S

T

512

V

I

To Output
Latches

1124816128256

REF+ REF+ REF+ REF+ REF+ REF+

REF– REF– REF– REF– REF– REF – REF – REF–

S

T

S

T

S

T

S

T

S

T

S

T

S

T

S

T

Figure 1. Simplified Model of the Successive-Approximation System

chip-select operation

The trailing edge of CS

starts all modes of operation, and CS can abort a conversion sequence in any mode.

A high-to-low transition on CS

within the specified time during an ongoing cycle aborts the cycle, and the device
returns to the initial state (the contents of the output data register remain at the previous conversion result). Care
should be exercised to prevent CS

from being taken low close to completion of conversion because the output

data may be corrupted.

reference voltage inputs

There are two reference inputs used with the TLC1549: REF+ and REF–. These voltage values establish the
upper and lower limits of the analog input to produce a full-scale and zero reading respectively . The values of
REF+, REF–, and the analog input should not exceed the positive supply or be lower than GND consistent with
the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or
higher than REF+ and at zero when the input signal is equal to or lower than REF–.

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

(see Note 1): TLC1549C, TLC1549I –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . .

TLC1549M –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(any input) –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O

–0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Positive reference voltage, V

ref+

V

CC

+ 0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Negative reference voltage, V

ref–

–0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak input current (any input) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak total input current (all inputs) ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLC1549C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC1549I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC1549M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to ground with REF– and GND wired together (unless otherwise noted).

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

CC

4.5 5 5.5 V

Positive reference voltage, V

ref+

(see Note 2) V

CC

V

Negative reference voltage, V

ref–

(see Note 2) 0 V

Differential reference voltage, V

ref+

– V

ref–

(see Note 2) 2.5 VCCVCC+0.2 V

Analog input voltage (see Note 2) 0 V

CC

V

High-level control input voltage, V

IH

VCC = 4.5 V to 5.5 V 2 V

Low-level control input voltage, V

IL

VCC = 4.5 V to 5.5 V 0.8 V
Clock frequency at I/O CLOCK (see Note 3) 0 2.1 MHz
Setup time, CS low before first I/O CLOCK↑, t

su(CS)

(see Note 4) 1.425 µs

Hold time, CS low after last I/O CLOCK↓, t

h(CS)

0 ns

Pulse duration, I/O CLOCK high, t

wH(I/O)

190 ns

Pulse duration, I/O CLOCK low, t

wL(I/O)

190 ns

Transition time, I/O CLOCK, t

t(I/O)

(see Note 5 and Figure 5) 1 µs

Transition time, CS, t

t(CS)

10 µs

TLC1549C 0 70
Operating free-air temperature, T

A

TLC1549I –40 85

°C

TLC1549M –55 125

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied

to REF– convert as all zeros (0000000000). The TLC1549 is functional with reference voltages down to 1 V (V

ref+

– V

ref–

); however,

the electrical specifications are no longer applicable.

3. For 1 1- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V) at least 1 I/O CLOCK rising edge (≥ 2 V) must occur within

9.5 µs.

4. To minimize errors caused by noise at CS

, the internal circuitry waits for a setup time plus two falling edges of the internal system

clock after CS

↓ before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup

time has elapsed.

5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.

TLC1549C, TLC1549I, TLC1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range,
V

CC

= V

ref+

= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

p

VCC = 4.5 V, IOH = –1.6 mA 2.4

VOHHigh-level output voltage

VCC = 4.5 V to 5.5 V, IOH = –20 µA VCC–0.1

V

p

VCC = 4.5 V, IOL = 1.6 mA 0.4

VOLLow-level output voltage

VCC = 4.5 V to 5.5 V, IOL = 20 µA 0.1

V

p

p

VO = VCC, CS at V

CC

10

IOZOff-state (high-impedance-state) output current

VO = 0, CS at V

CC

–10

µ

A

I

IH

High-level input current VI = V

CC

0.005 2.5 µA

I

IL

Low-level input current VI = 0 –0.005 –2.5 µA

I

CC

Operating supply current CS at 0 V 0.8 2.5 mA

p

VI = V

CC

1

Analog input leakage current

VI = 0 –1

µ

A

Maximum static analog reference
current into REF+

V

ref+

= VCC, V

ref–

= GND 10 µA

TLC1549C, I (Analog) During sample cycle 30 55

p

p

TLC1549M (Analog) During sample cycle 30

p

CiInput capacitance

TLC1549C, I (Control) 5 15

pF

TLC1549M (Control) 5

†

All typical values are at VCC = 5 V, TA = 25°C.

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics over recommended operating free-air temperature range,
V

CC

= V

ref+

= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz

PARAMETER TEST CONDITIONS MIN MAX UNIT

E

L

Linearity error (see Note 6) ±1 LSB

E

ZS

Zero-scale error (see Note 7) See Note 2 ±1 LSB

E

FS

Full-scale error (see Note 7) See Note 2 ±1 LSB
Total unadjusted error (see Note 8) ±1 LSB

t

conv

Conversion time See Figures 6–10 21 µs

t

c

Total cycle time (access, sample, and conversion)

See Figures 6–10,
See Note 9

21
+10 I/O
CLOCK

periods

µs

t

v

Valid time, DATA OUT remains valid after I/O CLOCK↓ See Figure 5 10 ns

t

d(I/O-DATA)

Delay time, I/O CLOCK↓ to DATA OUT valid See Figure 5 240 ns

t

PZH

, t

PZL

Enable time, CS↓ to DATA OUT (MSB driven) See Figure 3 1.3 µs

t

PHZ

, t

PLZ

Disable time, CS↑ to DATA OUT (high impedance) See Figure 3 180 ns

t

r(bus)

Rise time, data bus See Figure 5 300 ns

t

f(bus)

Fall time, data bus See Figure 5 300 ns

t

d(I/O-CS)

Delay time, tenth I/O CLOCK↓ to CS↓ to abort conversion
(see Note10)

9 µs

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied

to REF– convert as all zeros (0000000000). The TLC1549 is functional with reference voltages down to 1 V (V

ref+

– V

ref–

); however,

the electrical specifications are no longer applicable.

6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.

7. Zero error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the dif ference
between 1111111111 and the converted output for full-scale input voltage.

8. Total unadjusted error comprises linearity , zero, and full-scale errors.

9. I/O CLOCK period = 1/(I/O CLOCK frequency). Sampling begins on the falling edge of the third I/O CLOCK, continues for seven
I/O CLOCK periods, and ends on the falling edge of the 10th I/O CLOCK (see Figure 5).

10. Any transitions of CS

are recognized as valid only if the level is maintained for a minimum of a setup time plus two falling edges of

the internal clock (1.425 µs) after the transition.

TLC1549C, TLC1549I, TLC1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

DATA OUT

CL = 100 pF

12 kΩ

Test Point

V

CC

RL = 2.18 kΩ

Figure 2. Load Circuit

CS

DATA

OUT

2.4 V

0.4 V

90%
10%

t

PZH

, t

PZL

t

PHZ

, t

PLZ

0.8 V

2 V

Figure 3. DATA OUT to Hi-Z Voltage Waveforms

Last

Clock

CS

0.8 V

2 V

0.8 V

t

su(CS)

0.8 V

I/O CLOCK

t

h(CS)

First

Clock

Figure 4. CS to I/O CLOCK Voltage Waveforms

0.4 V

2.4 V

0.4 V

2.4 V

2 V

0.8 V

I/O CLOCK

DATA OUT

t

t(I/O)

0.8 V

2 V

t

r(bus)

, t

f(bus)

t

d(I/O-DATA)

t

v

I/O CLOCK Period

t

t(I/O)

0.8 V

Figure 5. I/O CLOCK and DATA OUT Voltage Waveforms

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Sample Cycle B

A/D

Conversion

Interval

Initialize

Initialize

MSB LSB

Previous Conversion Data

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Hi-Z State

12345678910 1

I/O

CLOCK

DATA

OUT

CS

(see Note A)

(≤ 21 µs)

Figure 6. Timing for 10-Clock Transfer Using CS

Sample Cycle B

A/D Conversion

Interval

Initialize

MSB LSB

Previous Conversion Data

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Low Level

12345678910 1

I/O

CLOCK

DATA

OUT

CS

Initialize

(see Note A)

Must Be High on Power Up

(≤ 21 µs)

See Note C

Figure 7. Timing for 10-Clock Transfer Not Using CS

Sample Cycle B

A/D

Conversion

Interval

Initialize

MSB LSB

Previous Conversion Data

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

12345678910 1

I/O

CLOCK

DATA

OUT

CS

Initialize

ÏÏ

Low

Level

Hi-Z

See Note B

11 16

(see Note A)

(≤ 21 µs)

Figure 8. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed Within 21 µs)

NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system

clock after CS

↓ before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup

time has elapsed.

B. A low-to-high transition of CS

disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system

clock.

C. The first I/O CLOCK must occur after the end of the previous conversion.

TLC1549C, TLC1549I, TLC1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Sample Cycle B

A/D Conversion

Interval

(≤ 21 µs)

Initialize

MSB LSB

Previous Conversion Data

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Low Level

12345678910 1

I/O

CLOCK

DATA

OUT

CS

Initialize

Must Be High on Power Up

14 15 16

See Note C

(see Note A)

Figure 9. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Completed Within 21 µs)

Sample Cycle B

Conversion

Interval

Initialize

MSB LSB

Previous Conversion Data

B9

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

12345678910 1

I/O

CLOCK

DATA

OUT

CS

Initialize

11

Hi-Z State

16

Low

Level

(see Note A)

(≤ 21 µs)

A/D

See Note B

Figure 10. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed After 21 µs)

Sample Cycle B

A/D Conversion Interval

Initialize

MSB LSB

Previous Conversion Data

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

12345678910 1

I/O

CLOCK

DATA

OUT

CS

Must Be High on Power Up

14 15 16

See Note C

See Note B

Low Level

(see Note A)

(≤ 21 µs)

Figure 11. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Completed After 21 µs)

NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system

clock after CS

↓ before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup

time has elapsed.

B. A low-to-high transition of CS

disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system

clock.

C. The first I/O CLOCK must occur after the end of the previous conversion.

TLC1549C, TLC1549I, TLC1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

1000000000

0111111111

0000000010

0000000001

0000000000

1111111110

0 0.0096 2.4528 2.4576 2.4624

Digital Output Code

1000000001

1111111101

1111111111

4.9056 4.9104 4.9152

512

511

2

1

0

1022

Step

513

1021

1023

0.0024
VI – Analog Input Voltage – V

VZT =VZS + 1/2 LSB

V

ZS

See Notes A and B

4.9080

0.0048

VFT = VFS – 1/2 LSB

V

FS

NOTES: A. This curve is based on the assumption that V

ref+

and V

ref–

have been adjusted so that the voltage at the transition from digital 0

to 1 (VZT) is 0.0024 V and the transition to full scale (VFT) is 4.908 V. 1 LSB = 4.8 mV.

B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is

the step whose nominal midstep value equals zero.

Figure 12. Ideal Conversion Characteristics

Processor

Control

Circuit

To Source

Ground

5-V DC Regulated

Analog Input ANALOG IN

I/O CLOCK

CS

DATA OUT

REF+

REF–

GND

TLC1549

Figure 13. T ypical Serial Interface

TLC1549C, TLC1549I, TLC1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS059C – DECEMBER 1992 – REVISED MARCH 1995

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

APPLICATION INFORMATION

simplified analog input analysis

Using the equivalent circuit in Figure 14, the time required to charge the analog input capacitance from 0 V to
V

S

within 1/2 LSB can be derived as follows:

The capacitance charging voltage is given by

(1)

where

R

t

= Rs + r

i

VC+

V

S

ǒ

1–e

–tcń

RtC

i

Ǔ

The final voltage to 1/2 LSB is given by

(2)V

C

(1/2 LSB) = VS – (VS/2048)

Equating equation 1 to equation 2 and solving for time t

c

gives

(3)

and

t

c

(1/2 LSB) = Rt × Ci × ln(2048) (4)

VS*ǒVSń

2048Ǔ+

V

S

ǒ

1–e

–tcń

RtC

i

Ǔ

Therefore, with the values given the time for the analog input signal to settle is

(5)

t

c

(1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(2048)

This time must be less than the converter sample time shown in the timing diagrams.

R

s

r

i

V

S

V

C

50 pF MAX

1 kΩ MAX

Driving Source

†

TLC1549

C

i

V

I

VI= Input Voltage at ANALOG IN
VS= External Driving Source Voltage
Rs= Source Resistance
ri= Input Resistance
Ci= Input Capacitance

†

Driving source requirements:

• Noise and distortion for the source must be equivalent to the
resolution of the converter.

• Rs must be real at the input frequency.

Figure 14. Equivalent Input Circuit Including the Driving Source

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