Texas Instruments TLC0832CP, TLC0832CD, TLC0832CDR, TLC0831IP, TLC0831IDR Datasheet

...

8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL

8-Bit Resolution

Easy Microprocessor Interface or Standalone Operation

Operates Ratiometrically or With 5-V Reference

Single Channel or Multiplexed Twin Channels With Single-Ended or Differential Input Options

Input Range 0 to 5 V With Single 5-V Supply

Inputs and Outputs Are Compatible With TTL and MOS

Conversion Time of 32 µs at f

= 250 kHz

clock

Designed to Be Interchangeable With National Semiconductor ADC0831 and ADC0832

Total Unadjusted Error...±1 LSB

description

TLC0831C, TLC0831I TLC0832C, TLC0832I

SLAS107B – JANUARY 1995 – REVISED APRIL 1996

TLC0831 ...D OR P PACKAGE

TLC0832 ...D OR P PACKAGE

CS IN+ IN–

GND

CS CH0 CH1

GND

(TOP VIEW)

1 2 3 4

(TOP VIEW)

8 7 6 5

1 2 3 4

8 7 6 5

CLK DO REF

CLK DO DI

/REF

These devices are 8-bit successive-approximation analog-to-digital converters. The TLC0831 has single input channels; the TLC0832 has multiplexed twin input channels. The serial output is configured to interface with standard shift registers or microprocessors.

The TLC0832 multiplexer is software configured for single-ended or differential inputs. The differential analog voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.

The operation of the TLC0831 and TLC0832 devices is very similar to the more complex TLC0834 and TLC0838 devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum analog input signal value, which gives the highest possible conversion resolution. Typically, REF is set equal to V

(done

internally on the TLC0832). The TLC0831C and TLC0832C are characterized for operation from 0°C to 70°C. The TLC0831I and TLC0832I

are characterized for operation from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

0°C to 70°C TLC0831CD TLC0832CD TLC0831CP TLC0832CP

–40°C to 85°C TLC0831ID TLC0832ID TLC0831IP TLC0832IP

SMALL OUTLINE

(D)

PLASTIC DIP

(P)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC0831C, TLC0831I TLC0832C, TLC0832I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL

SLAS107B – JANUARY 1995 – REVISED APRIL 1996

functional block diagram

CLK

(TLC0832

only)

CH0/IN+ CH1/IN–

(TLC0831

only)

REF

To Internal Circuits

Shift Register

CLK

SGL/DIF

Analog

MUX

Ladder

and

Decoder

ODD/EVEN

Start

Comparator

Bits 0–7

One

Shot

SAR

Logic

and

Latch

MSB First

Bits 0–7

Bit 1

LSB First

Time Delay

CLK

9-Bit Shift

Start

Flip-Flop

CLK

EOC

CLK

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC0831C, TLC0831I TLC0832C, TLC0832I

8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL

SLAS107B – JANUARY 1995 – REVISED APRIL 1996

functional description

The TLC0831 and TLC0832 use a sample-data-comparator structure that converts differential analog inputs by a successive-approximation routine. The input voltage to be converted is applied to an input terminal and is compared to ground (single ended), or to an adjacent input (differential). The TLC0832 input terminals can be assigned a positive (+) or negative (–) polarity . The TLC0831 contains only one differential input channel with fixed polarity assignment; therefore it does not require addressing. The signal can be applied differentially, between IN+ and IN–, to the TLC0831 or can be applied to IN+ with IN– grounded as a single ended input. When the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the converter output is all zeros.

Channel selection and input configuration are under software control using a serial-data link from the controlling processor. A serial-communication format allows more functions to be included in a converter package with no increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter at the analog sensor and communicating serially with the controlling processor. This process returns noise-free digital data to the processor.

A conversion is initiated by setting CS conversion process. A clock input is then received from the processor. An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds, conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock periods, the conversion is complete. When CS output circuits go to the high-impedance state. If another conversion is desired, CS transition followed by address information.

A TLC0832 input configuration is assigned during the multiplexer-addressing sequence. The multiplexer address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog inputs to be enabled and determines whether the input is single ended or differential. When the input is differential, the polarity of the channel input is assigned. In addition to selecting the differential mode, the polarity may also be selected. Either channel of the channel pair may be designated as the negative or positive input.

On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift register. The first logic high on the input is the start bit. A 2-bit assignment word follows the start bit on the TLC0832. On each successive low-to-high transition of the clock input, the start bit and assignment word are shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register, the input channel is selected and conversion starts. The TLC0832 DI terminal to the multiplexer shift register is disabled for the duration of the conversion.

The TLC0832 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. The DI and DO terminals can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the high-impedance state.

low, which enables all logic circuits. CS must be held low for the complete

goes high, all internal registers are cleared. At this time, the

must make a high-to-low

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC0831C, TLC0831I TLC0832C, TLC0832I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL

SLAS107B – JANUARY 1995 – REVISED APRIL 1996

sequence of operation

TLC0831

10987654321

CLK

conv

CLK

(TLC0832

only)

Bit

SGL

DIF

MUX

+Sign Bit

MUX

Settling Time

Start

Settling Time

Hi-Z

ODD

EVEN

MSB

MSB-First Data

conv

MSB-First Data

TLC0832

Don’t Care

1765 243

LSB-First Data

LSB

Hi-Z

21201918141312123456 1011

Hi-Z

MSBLSB

176201267

TLC0832 MUX-ADDRESS CONTROL LOGIC TABLE

MUX ADDRESS

SGL/DIF

L L H H

H = high level, L = low level, – or + = terminal polarity for the selected input channel

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ODD/EVEN CH0 CH1

L H L H

CHANNEL NUMBER

+ – +

– +

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