Texas Instruments TL5001EVM-097 User Manual

TL5001EVM-097

3.3ĆV/5ĆV Selectable Output, 2.5ĆA Buck
Converter Module

User’s Guide

2001 Mixed-Signal Linear Products

SLVU002B

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Copyright  2001, Texas Instruments Incorporated

About This Manual

Related Documentation From Texas Instruments

Preface

Read This First

This user’s guide is a reference manual for the TL5001EVM–097. This docu-
ment provides information to assist managers and hardware engineers in ap­plication development.

How to Use This Manual

This manual provides the information and instructions necessary to design,
construct, operate, and understand the SLVP097. Chapter 1 describes and
lists the hardware requirements; Chapter 2 describes design considerations
and procedures.

Related Documentation From Texas Instruments

The following books describe the TL5001 and related support tools. T o obtain
a copy of any of these TI documents, call the Texas Instruments Literature
Response Center at (800) 477–8924. When ordering, please identify the book
by its title and literature number.

TL5001 Pulse-Width-Modulation Control Circuits Data Sheet (Literature

number SLVS084C).

Designing with the TL5001C PWM Controller Application Report

(Literature number SLVA034).

TPS2816, TPS2817, TPS2818, and TPS2819 Single-Channel High-Speed

MOSFET Driver Data Sheet (Literature number SLVS160)

Read This First

iii

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iv

Running Title—Attribute Reference

Contents

1 Hardware 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Introduction 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Schematic 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Input/Output Connections 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Board Layout 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Bill of Material 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Test Results 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Design Procedure 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Introduction 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Operating Specifications 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Design Procedures 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 Duty Cycle Estimate 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Output Filter 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3 Power Switch 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.4 Rectifier 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.5 Snubber Network 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.6 Controller Functions 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.7 Loop Compensation 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter Title—Attribute Reference

v

Running Title—Attribute Reference

Figures

1–1 Typical Buck Converter Block Diagram 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 SLVP097 Schematic 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–3 I/O Connections 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–4 Board Layout 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–5 Top Layer 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–6 Bottom Layer 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–7 Output Voltage Vs Output Current (3.3-V Mode) 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–8 Output Voltage Vs Output Current (5-V Mode) 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–9 Output Voltage Vs Supply Voltage (3.3-V Mode) 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–10 Output Voltage Vs Supply Voltage (5-V Mode) 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–11 Efficiency Vs Output Current (5-V Mode) 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 Power Stage Response 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Required Compensation Response 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

Chapter 1

Hardware

The TL5001EVM–097 (SL VP097) provides a method for evaluating the perfor­mance of a buck converter using the TL5001 pulse-width-modulation (PWM)
controller coupled with a TPS2817 MOSFET driver. This manual explains how
to construct basic power conversion circuits including the design of the control
chip functions and the basic loop. This chapter includes the following topics:

Topic Page

1.1 Introduction 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Schematic 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Input/Output Connections 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Board Layout 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Bill of Materials 1–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Test Results 1–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter Title—Attribute Reference

1-1

Introduction

1.1 Introduction

Low cost and design simplicity make buck converters popular solutions in dc/
dc step-down applications where lack of isolation from the input source is not
a concern. Loop compensation for the buck converter can be set for high band­widths. This mode is desirable for the low peak-to-average current ratio, eas­ing the component worst-case design parameters.

Figure 1–1 shows a block diagram of a typical buck converter. The converter
passes a duty-cycle modulated waveform through a low-pass output filter. To
maintain the desired output voltage, a controller senses the output voltage,
compares it to an internal reference voltage and adjusts the width of the power
switch (Q1) on time, . A commutating diode (CR1) maintains continuous
current through the inductor when the power switch is turned off.

Figure 1–1.Typical Buck Converter Block Diagram

CR1

L1

R1

R2

+
C2

V

O

Q1

V

I

+
C1

Controller

FB

R3

The SLVP097 buck converter uses the TI TL5001 PWM controller and the
TPS2817 MOSFET driver to give a 0- to 2.5-A output with a selectable output
voltage of either 3.3 V or 5 V. The converter operates over an input voltage
range of 5.5 V to 12 V with a typical efficiency of 90 percent. Chapter 2 lists full
design specifications.

Note: Peak currents in excess of 2.5 A may be obtained from this EVM,
but due to thermal restraints, should not be subtained. This EVM shuts
down when a short circuit is encountered. Input power must be re­cycled to restart the module.

1-2

1.2 Schematic

Figure 1–2 shows the SLVP097 schematic.

Figure 1–2.SLVP097 Schematic

†

4.5 V to 12.6 V
Input

J1

Optional

R8A

W

1–2 = 5 V

1
2

3
4

JP1

231

+

C1

C8

0.1 µF

100
20 V

µF

47 kΩ

TL5001

R2

C2

U2

+

+
GND
GND

Adjustable Output

(Replace JP1 and R8)

VO= 1.36–5 V

1.0 kΩ

CW CCW

2–3 = 3.3 V

0.1

µFC30.1

µF

2

0.1 µF

V

CC

C9

1.8 kΩ

CC

DTC

6

V

V
DD

R4

5

1

GND

2

COMP

3

C12
.047 µF

Q1

IRF7406

30WQ04FN

4

OUT IN

3

1

OUT

FB

4

CR1

U1

TPS2817

5

SCP

GND

RT

7

R3

30.1 kΩ
1%

C11
1000 pF

C10

+

Schematic

3.3/5 V, 2.5 A

1
2

3
4

Output

J2

+

+
GND
GND

L1

µH

33

C4
1000 pF

R1

22 Ω

µF1

8

C5

220 µF

10 V

R5

330 Ω

+

0.018 µF

+

C6

220 µF

10 V

(Optional)

C13

C7

0.1 µF

R8

732 Ω

1%

†

Input voltage range for 3.3 V output. When using 5-V output, minimum input voltage must be greater than 5.5 V .

R7

1.00 kΩ
1%

R6

4.02 kΩ
1%

Notes: 1) Frequency set to 275 kHz by R3.

2) This unit and the components are thermally rated to 2.5 A. The output current should not exceed 2.5 A unless
proper thermal management is put in place.

3) DO NOT change the set output voltage jumper (JP1) while power is applied to the unit.

Hardware

1-3

Input/Output Connections

1.3 Input/Output Connections

Figure 1–3 shows the SLVP097 input and output connections.

Figure 1–3.I/O Connections

–

+

Power Supply

SLVP097

3.3/5 V, 2.5 AMP
Rev. A.1 1997

1

J1
IN

R4

U1

C12

R5

C1

+

.330

C3

C2

CR1

C8

C11

R6

JP1

C13

U2

R7

1.0

Q1
R3
R2

C9

C10

R8

1–2 = 5 V
2–3 = 3.3 V

C4R1

C5

C6

L1

OUT

+

J2

1

C7

+

–

LOAD

+

Notes: 1) The input power supply should be rated at least 3 A with current limit set high enough for proper operation.

2) The load should be rated at least 2.5 A with proper power dissipation. Fixed or variable resistors may be used.

1-4

1.4 Board Layout

Figures 1–4 through 1–6 show the SLVP097 board layout.

Figure 1–4.Board Layout

Board Layout

1

1.6”

Figure 1–5.Top Layer

SLVP097

3.3/5V, 2.5 AMP
Rev. A.1 1997

J1
IN

C12

R4

U1

R5

C1

+

.330

C3

C11

C13

R6

C8

JP1

C2

U2

CR1

Q1
R3
R2

C9

1.0

C10

R8

R7

1

1–2 = 5V
2–3 = 3.3V

C4R1

C5

C6

L1

OUT

+

J2

1

C7

+

2.4”

1.6”

2.4”

Hardware

1-5

Board Layout

Figure 1–6.Bottom Layer

1.6”

2.4”

1-6

Bill of Material

1.5 Bill of Material

Table 1–1 lists materials required for the SLVP097.

Table 1–1.Bill of Materials

Reference Part Number Mfr Description

C1 20SA100M Sanyo Capacitor, Os-Con, 100 mF, 20 V, F-case
C2 Capacitor, Ceramic, 0.1 mF, 50 V, 1206
C3 Capacitor, Ceramic, 0.1 mF, 50 V, 1206
C4 Capacitor, Ceramic, 1000 pF, 50 V, 1206
C5 10SA220M Sanyo Capacitor, Os-Con, 220 mF, 10 V, F-case

*

C6
C7 Capacitor, Ceramic, 0.1 mF, 50 V, 1206
C8 Capacitor, Ceramic, 0.1 mF, 50 V, 1206
C9 Capacitor, Ceramic, 0.1 mF, 50 V, 1206
C10 ECS-T1EY105R Digikey Capacitor, Tantalum, 1.0 mF, 25 V, 1206
C1 1 Capacitor, Ceramic, 1000 pF, 50 V, 1206
C12 Capacitor, Ceramic, 0.047 mF, 50 V, 1206
C13 Capacitor, Ceramic, 0.018 mF, 50 V, 1206
CR1 30WQ04FN IR Diode, Schottky , 3.3 A, 40 V, D-Pak
J1 Header, 4-pin, 0.025” sq  0.100” centers
J2 Header, 4-pin, 0.025” sq  0.100” centers
JP1 Header, 3-pin, 0.025” sq  0.100” centers
L1 SLF12565-330M2R8 TDK Inductor, 33 mH, 2.8 A, 0.041 W, 0.50” square
Q1 IRF7406 MOSFET, P-Ch, 30 V, 0.045 W, 4.7 A, SO-8
R1 Resistor, CF, 22 W, 1/10 W, 5%, 1206
R2 Resistor, CF, 47 kW, 1/10 W, 5%, 0805
R3 Resistor, MF, 30.1 kW, 1/10 W, 1%, 0805
R4 Resistor, CF, 1.8 kW, 1/10 W, 5%, 0805
R5 Resistor, CF, 330 W, 1/10 W, 5%, 0805
R6 Resistor, MF, 4.02 kW, 1/10 W, 1%, 0805
R7 Resistor, MF, 1.00 kW, 1/10 W, 1%, 0805
R8 Resistor, MF, 732 W, 1/10 W, 1%, 0805

*

R8A

U1 TPS2817DBV TI MOSFET driver, noninverting, single channel,

U2 TL5001CD TI PWM controller, SO-8

–– Shunt, standard profile
––

10SA220M Sanyo Capacitor, Os-Con, 220 mF, 10 V, F-case

CT9W102-ND Digikey Potentiometer, 1 kW, 10%, 18-turn, 9mm-

square

SOT-25

SLVP097 TI PCB, TPS2817 EVM, 2.40”  1.60”

* Optional parts not on present board.

Hardware

1-7

Test Results

1.6 Test Results

Figures 1–7 through 1–11 show test results for the the SLVP097.

Figure 1–7.Output Voltage Vs Output Current (3.3-V Mode)

OUTPUT VOLTAGE

vs

OUTPUT CURRENT (3.3-V MODE)

3.45
VCC = 9 V

3.4

3.35

3.3

– Output Voltage – V

3.25

O

V

3.2

3.15

0 0.5 1 1.5

IO – Output Current – A

2 2.5 3

Figure 1–8.Output Voltage Vs Output Current (5-V Mode)

OUTPUT VOLTAGE

vs

OUTPUT CURRENT (5-V MODE)

5.15
VCC = 9 V

5.1

5.05

5

– Output Voltage – VV

4.95

O

4.9

4.85

1-8

01

0.5 1.5 2.5
IO – Output Current – A

23

Figure 1–9.Output Voltage Vs Supply Voltage (3.3-V Mode)

OUTPUT VOLTAGE

vs

SUPPLY VOLTAGE (3.3-V MODE)

3.26

3.255

Test Results

3.25

3.245

– Output Voltage – VV

3.24

O

3.235

3.23
5678910

VCC – Supply Voltage – V

IO = 0.25 A

IO = 2.5 A

11 12 13

Figure 1–10. Output Voltage Vs Supply Voltage (5-V Mode)

OUTPUT VOLTAGE

vs

SUPPLY VOLTAGE (5-V MODE)

4.92

IO = 0.25 A

4.915

4.91

4.905

– Output Voltage – VV

4.9

O

4.895

4.89
5678910

VCC – Supply Voltage – V

IO = 2.5 A

11 12 13

Hardware

1-9

Test Results

Figure 1–11. Efficiency Vs Output Current (5-V Mode)

EFFICIENCY

vs

OUTPUT CURRENT

93
92

Efficiency – %

91
90
89
88
87
86
85

84
83
82
81
80

0 0.5 1 1.5

5 V

3.3 V

IO – Output Current – A

VCC = 9 V

2 2.5

1-10

Chapter 2

Design

Procedure

The SL VP097 evaluation module provides a method for evaluating the perfor­mance of the TPS2817 MOSFET driver and the TL5001 PWM controller. The
TPS2817 contains all of the circuitry necessary to drive large MOSFETs, in­cluding a voltage regulator for higher voltage applications. This section ex­plains how to construct basic power conversion circuits including the design
of the control chip functions and the basic loop. This chapter includes the fol­lowing topics:

Topic Page

2.1 Introduction 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Operating Specifications 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Design Procedure 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Chapter Title—Attribute Reference

2-1

Introduction

2.1 Introduction

The SL VP097 is a dc-dc buck converter module that provides a 5-V or 3.3-V
output at up to 2.5 A with an input voltage range of 5.5 V to 12 V . The controller
is a TL5001 PWM operating at a nominal frequency of 275 kHz. The TL5001
is configured for a maximum duty cycle of 100 percent and has short-circuit
protection built in. Output voltage selection is implemented with jumper JP1.

2-2

2.2 Operating Specifications

Table 2–1 lists the operating specifications for the SLVP097.

Table 2–1.Operating Specifications

Specification Min Typ Max Units

Operating Specifications

Input Voltage Range 4.5
Output Voltage Range

5-V Mode 4.7 5.0 5.3 V

3.3-V Mode 3.1 3.3 3.5 V
Output Current Range 0 2.6 A
Operating Frequency 275 kHz
Output Ripple 50 mV
Efficiency

†

For 3.3 V only, minimum input voltage for 5 V output is 5.5 V.

†

85% 90%

12.6 V

Design Procedure

2-3

Design Procedures

2.3 Design Procedures

Detailed steps in the design of a buck-mode converter may be found in
Designing With the TL5001C PWM Controller (literature number SLVA034)
from Texas Instruments. This section shows the basic steps involved in this
design, using the 3.3-V output mode.

2.3.1 Duty Cycle Estimate

The duty cycle for a continuous-mode step-down converter is approximately:

D

+

VI*

Assuming the commutating diode forward voltage Vd = 0.5 V and the power
switch on voltage V

0.42, and 0.32, respectively.

2.3.2 Output Filter

A buck converter uses a single-stage LC filter. Choose an inductor to maintain
continuous-mode operation down to 6 percent of the rated output load:

D

IO+2

VO)

V

d

V

SAT

0.06 IO+2

= 0.1 V , the duty cycle for Vi = 5.5, 9, and 12 V is 0.70,

SAT

0.06 2.5+0.30 A

2.3.3 Power Switch

The inductor value is:

*

D

+

D

V

O

0.05

0.3

I

VO) D t

O

0.30

+

Ǔ

+

8

0.167

ǒ

275 10

ǒ

3.63 10

W

0.3

–6

Ǔ

+

33.3mH

+

3

Ǔ

0.05

2.73mF

(VI*

V

L

+

(12*0.1*3.3) 0.32

+

Assuming that all of the inductor ripple current flows through the capacitor and
the effective series resistance (ESR) is zero, the capacitance needed is:

C

+

8 f

Assuming the capacitance is very large, the ESR needed to limit the ripple to
50 mV is:

ESR

+

The output filter capacitor should be rated at least ten times the calculated
capacitance and 30–50 percent lower than the calculated ESR. This design
used a 220-mF OS-Con capacitor in parallel with a ceramic to reduce ESR.

SAT

D

I

O

ǒ

D

V

O

D

I

O

Based on the preliminary estimate, r
= 40 mW. The IRF7406 is a 30-V p-channel MOSFET with r
Power dissipation (conduction + switching losses) can be estimated as:

PD+

2-4

DS(ON)

2

ǒ

I

O

r

DS(ON)

DǓ)ǒ0.5 Vi

should be less than 0.10 V  2.5 A

IO

t

r)f

DS(ON)

Ǔ

f

= 40 m

W.

Design Procedures

Assuming total switching time, t
perature, and r

PD+

The thermal impedance R
inch-square pattern, thus:

TJ+

2.3.4 Rectifier

The catch rectifier conducts during the time interval when the MOSFET is off.
The 30WQ04 is a 3.3-A, 40-V rectifier in a D-Pak power surface-mount
package. The power dissipation is:

PD+

2.3.5 Snubber Network

A snubber network is usually needed to suppress the ringing at the node where
the power switch drain, output inductor, and the rectifier connect. This is
usually a trial-and-error sequence of steps to optimize the network; but as a
starting point, select a snubber capacitor with a value that is 4–10 times larger
than the estimated capacitance of the catch rectifier. The 30WQ04 has a
capacitance of 110 pF, resulting in a snubber capacitor of 1000 pF. Then,
measuring a ringing time constant of 20 ns, R is:

R

+

DS(ON)

ƪ

2.52

)ƪ0.5 5.5 2.5

ǒ

IO

C

R

q

V

D

–9

TA)

20 10

adjustment factor (for high temperature) = 1.6, then:

(0.04 1.6) 0.7

JA

ǒ

1*D

+

1000 10

, = 100 ns, a 55°C maximum ambient tem-

r+f

ƫ

*

6

ǒ0.1 10

= 90°C/W for FR-4 with 2-oz. copper and a one-

θJA

Ǔ

P

+55)

D

Ǔ

+

Min

20 10

2.5 0.6 0.68+1.02 W

–9

–12

Ǔ ǒ

275 10

(90 0.41)+92°C

+20W

3

Ǔ

ƫ

+

0.41 W

A 22-Ω resistor is used in the design.

2.3.6 Controller Functions

The controller functions, oscillator frequency, soft-start, dead-time control,
short-circuit protection, and sense-divider network are discussed in this
section.

The oscillator frequency is set by selecting the resistance value from the graph
in Figure 6 of the TL5001 data sheet. For 275 kHz, a value of 30.1 kWis
selected.

Dead-time control provides a minimum off-time for the power switch in each
cycle. Set this time by connecting a resistor between DTC and GND. For this
design, a maximum duty cycle of 100% is chosen. Then R is calculated as:

ǒ

R

R

+

+

(30.1 kW)

OSC

Ǔ

)

1.25 k

1.25 kW)[1(1.4 – 0.6))0.60]+44 kWå

ƪ

W

D(V

0(100%)

– V

))V

0(0%)

Design Procedure

0(0%)

ƫ

47 k

W

2-5

Design Procedures

Soft-start is added to reduce power-up transients. This is implemented by
adding a capacitor across the dead-time resistor. In this design, a soft-start
time of 5 ms is used:

t

C

+

R

The TL5001 has short circuit protection (SCP) instead of a current sense cir­cuit. If not used, the SCP terminal must be connected to ground to allow the
converter to start up. If a timing capacitor is connected to SCP, it should have
a time constant that is greater than the soft-start time constant. This time
constant is chosen to be 75 ms:

R

DT

0.005 s

+

47 k

+

0.1mF

W

C(mF)+12.46 t

2.3.7 Loop Compensation

Loop compensation is necessary to stabilize the converter over the full range
of load, line, and gain conditions. A buck-mode converter has a two-pole LC
output filter with a 40-dB-per-decade rolloff. The total closed-loop response
needed for stability is a 20-dB-per-decade rolloff with a minimum phase margin
of 30 degrees over the full bandwidth for all conditions. In addition, sufficient
bandwidth must be designed into the circuit to assure that the converter has
good transient response. Both of these requirements are met by adding
compensation components around the error amplifier to modify the total loop
response.

The first step in design of the loop compensation network is the design of the
output sense divider. This sets the output voltage and the top resistor
determines the relative size of the rest of the compensation design. Since the
TL5001 input bias current is 0.5 mA (worst case), the divider current should be
at least 0.5 mA. Using a 1-kW resistor for the bottom of the divider gives a
divider current of 1 mA. Since this is a dual-voltage output, the divider must be
selectable. For a 5-V output, the divider was set for 1 kW and 4 kW. The bottom
of the divider is calculated for the 3-V mode as:

R

+

VO*

+

SCP

R

T

V

REF

12.46 0.075 s+0.93mF

4k

+

W

3.3*1

+

1.74 k

W

The pulse-width modulator gain can be approximated as the change in output
voltage divided by the change in PWM input voltage:

A

PWM

The LC filter has a double pole at:

1

Ǹ

2pLC
and rolls off at 40-dB per decade after that until the ESR zero is reached at:

1

2pR

ESR

2-6

+

D

+

1.87 kHz

+

C

D

V

O

V

COMP

2p(0.027)

+

1.4–0.6

1

ǒ

220 10

9–0

+

11.25å21 dB

+

–6

26.8 kHz

Ǔ

This information is enough to calculate the required compensation values.
Figure 2–1 shows the power stage gain and phase plots.

Figure 2–1.Power Stage Response

FREQUENCY RESPONSE

50

Design Procedures

0

40

30

20

10

0

Gain – dB (Solid)

–10

–20

–30

10 10

2

Frequency – Hz

10

3

Figure 2–2 shows the required error amplifier compensation response.

Figure 2–2.Required Compensation Response

BODE PLOT

40

35

10

–45

–90

–135

–180

–225

–270

Phase – Degrees (Dashed)

–315

4

10

5

–360

90

70

30

25

20

15

Gain – dB (Solid)

10

5

0

–5

10 10

2

Frequency – Hz

10

3

10

4

10

This response can be met with the following:

-

A pole at zero to give high dc gain

-

Two zeroes at 1.87 kHz to cancel the LC poles

-

A pole at 26.8 kHz to cancel the ESR zero

-

A final pole to roll off high-frequency gain above 100 kHz

50

30

10

–10

–30

Phase – Degrees (Dashed)

–50

–70

–90

5

Design Procedure

2-7

Design Procedures

The sum of the gains of the modulator, the LC filter, and the error amplifier
needs to be 0 dB at the selected unity-gain frequency of 20 kHz. The modulator
and LC filter gain is –14 dB. The two zeroes at 1.87 kHz in the compensation
network that cancels the LC poles will have a total gain of 41.2 dB at 20 kHz.
Therefore, the pole at zero frequency needs to furnish 0–(–14+41.2) =
–27.2 dB (voltage gain = 0.04365) at 20 kHz. R5 and C12 provide this pole.
R6 is already chosen as 4 kW. Calculate C12 as:

C12)C11

+

(2p)(f)(R6)(Required Gain)

1

In practice C12 is much greater than C11, therefore:

C12

+

(2p)(20 kHz)(4 kW)(0.04365)

1

+

0.045mFUseC12+0.047mF

R4 provides the first zero at the LC break point:

R4

+

(2p)(1.87 kHz)(C12)

1

+

1.89 k

W

Use R4+1.8 k

W

C13 provides the other zero at the LC break point:

C13

(1.87 kHz)

+

1

2p(R6)

*

(20 kHz)

1

+

0.019mFUseC13+0.018mF

R5 provides the compensation for the ESR zero:

R5

+

(2p)(26.8 kHz)(C13)

1

+

330

W

Finally, C11 provides a rolloff filter at high frequency, chosen at 100 kHz:

2-8

C11

+

(2p)(100 kHz)(R4)

1

+

0.00088mFUseC11+1000 pF

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