TEXAS INSTRUMENTS TL16C750 Technical data

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Pin-to-Pin Compatible With the Existing TL16C550B/C

Programmable 16- or 64-Byte FIFOs to Reduce CPU Interrupts

Programmable Auto-RTS and Auto-CTS

In Auto-CTS Mode, CTS Controls Transmitter

In Auto-RTS Mode, Receiver FIFO Contents and Threshold Control RTS

Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment Is on the Same Power Drop

Capable of Running With All Existing TL16C450 Software

After Reset, All Registers Are Identical to the TL16C450 Register Set

Up to 16-MHz Clock Rate for Up to 1-Mbaud Operation

In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data

Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1

to (2 Clock

Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added or Deleted to or From the Serial Data Stream

5-V and 3-V Operation

description

–1) and Generates an Internal 16 ×

TL16C750

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997

Independent Receiver Clock Input

Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts

Fully Programmable Serial Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation

and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (DC to 1 Mbits Per

Second)

False Start Bit Detection

Complete Status Reporting Capabilities

3-State Output CMOS Drive Capabilities for Bidirectional Data Bus and Control Bus

Line Break Generation and Detection

Internal Diagnostic Capabilities: – Loopback Controls for Communications

Link Fault Isolation – Break, Parity, Overrun, Framing Error

Simulation

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR, DTR

, RI, and DCD)

Available in 44-Pin PLCC and 64-Pin SQFP

Industrial T emperature Range Available for 64-Pin SQFP

The TL16C750 is a functional upgrade of the TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), the TL16C750, like the TL16C550C, can be placed in an alternate mode (FIFO mode). This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 64 bytes including three additional bits of error status per byte for the receiver FIFO. The user can choose between a 16-byte FIFO mode or an extended 64-byte FIFO mode. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow through the RTS input signals (see Figure 1).

The TL16C750 performs serial-to-parallel conversion on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE status at any time. The ACE includes complete modem control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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output and the CTS

TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997

description (continued)

The TL16C750 ACE includes a programmable baud rate generator capable of dividing a reference clock by

divisors from 1 to (2

– 1) and producing a 16× reference clock for the internal transmitter logic. Provisions are also included to use this 16 × clock for the receiver logic. The ACE accommodates a 1-Mbaud serial rate (16-MHz input clock) so a bit time is 1 µs and a typical character time is 10 µs (start bit, 8 data bits, stop bit).

Two of the TL16C450 terminal functions have been changed to TXRDY

and RXRDY, which provide signaling

to a direct memory access (DMA) controller.

FN PACKAGE

(TOP VIEW)

DCD

DSR

D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

D4D3D2D1D0NCV

543216

7 8 9 10 11 12 13 14 15 16 17

20 21 22 23

18 19

XIN

WR1

WR2

XOUT

PM PACKAGE

(TOP VIEW)

24 25 26 2728

RD1

RD2

42 41 4043

DDIS

CTS

39 38 37 36 35 34 33 32 31 30 29

ADS

TXRDY

MR OUT1 DTR RTS OUT2 NC INTRPT RXRDY A0 A1 A2

BAUDOUT

CS2NCCS1NCCS0

XIN

XOUT

WR1

WR2

RD1 RD2

DDIS

TXRDY

ADS

63 62 61 60 5964 58

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

18 19

NC–No internal connection

SOUT

21 22 23 24

RXRDY

INTRPT

RCLK

SIN

56 55 5457

25 26 27 28 29

RTS

OUT2

53 52

DTR

D7NCD5

51 50 49

30 31 32

OUT1

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

D4 NC D3 D2 NC D1 D0 NC V

NC RI NC DCD DSR NC CTS

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functional block diagram

Data

Bus

Buffer

Select

and

Control

Logic

Power Supply

D(7–0)

CS0 CS1 CS2

ADS

MR RD1 RD2

WR1 WR2

DDIS

TXRDY

XIN

XOUT

RXRDY

A0 A1 A2

9–2

44 22

31 30

14 15

16 28

39 24

25 20

21 26 27 18 19 32

Internal Data Bus

S e

l e c

Receiver

Buffer

Line

Control

Divisor

Latch (LS)

Divisor

Latch (MS)

Line

Status

Transmitter

Holding

Modem

Control

Modem

Status

Interrupt

Enable

TL16C750

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997

Receiver

FIFO

Generator

Transmitter

FIFO

Interrupt

Control

Logic

Baud

S e

8 8

Receiver

Shift

Receiver

Timing and

Control

Transmitter

Timing and

Control

Transmitter

Shift

Modem

Control

Logic

SIN

RCLK

BAUDOUT

Autoflow Control Enable (AFE)

CTS

DTR

DSR

DCD

OUT1

OUT2

INTRPT

RTS

SOUT

Interrupt

Identification

FIFO

Control

NOTE A: Terminal numbers shown are for the FN package.

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TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997

Terminal Functions

TERMINAL

NAME

A0 A1 A2

ADS 28 15 I Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals

BAUDOUT 17 64 O Baud out. BAUDOUT is a 16× clock signal for the transmitter section of the ACE. The clock rate is established

CS0 CS1 CS2

CTS 40 33 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the

D0 D1 D2 D3 D4 D5 D6 D7

DCD 42 36 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of

DDIS 26 12 O Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS can disable an

DSR 41 35 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the

DTR 37 28 O Data terminal ready . When active (low), DTR informs a modem or data set that the ACE is ready to establish

INTRPT 33 23 O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four

MR 39 32 I Master reset. When active (high), MR clears most ACE registers and sets the levels of various output signals

OUT1 OUT2

RCLK 10 54 I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE.

NO.FNNO.

31 30 29

14 15 16

2 3 4 5 6 7 8 9

38353025O Outputs 1 and 2. These are user-designated output terminals that are set to their active (low) level by setting

I/O

I Register select. A0–A2 are used during read and write operations to select the ACE register to read from 18 17

59 61 62

42 43 45 46 48 50 51 52

or write to. Refer to Table 1 for register addresses and ADS

(CS0, CS1, CS2 signals are held at the logic levels they were in when the low-to-high transition of ADS

by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT

I Chip select. When CS0 and CS1 are high and CS2 is low, the ACE is selected. When any of these inputs

are inactive, the ACE remains inactive. Refer to the ADS

modem status register. Bit 0 (∆CTS) of the modem status register indicates that CTS since the last read from the modem status register. When the modem status interrupt is enabled, CTS changes states, and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the auto-CTS

I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status

information between the ACE and the CPU. As inputs, they use fail safe CMOS compatible input buffers.

the modem status register. Bit 3 (∆DCD) of the modem status register indicates that DCD since the last read from the modem status register. When the modem status interrupt is enabled and DCD changes state, an interrupt is generated.

external transceiver.

modem status register. Bit 1 (∆DSR) of the modem status register indicates DSR the last read from the modem status register. When the modem status interrupt is enabled and the DSR changes states, an interrupt is generated.

communication. DTR DTR

is placed in the inactive condition either as a result of a master reset, during loop mode operation, or

clearing the DTR bit.

conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.

(refer to Table 2).

their respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 inactive (high) level as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR.

) drive the internal select logic directly; when ADS is high, the register select and chip select

can also be used for the receiver section by tying this output to RCLK.

mode to control the transmitter.

is placed in the active state by setting the DTR bit of the modem control register to one.

DESCRIPTION

signal description.

occurred.

signal description.

has changed states

has changed states since

and OUT2 are set to their

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TL16C750

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997

Terminal Functions (Continued)

TERMINAL

I/O

Read inputs. When either RD1 or RD2 is active (low or high respectively) while the ACE is selected, the CPU is allowed to read status information or data from a selected ACE register. Only one of these inputs is required for the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied low or RD1

status register. Bit 2 (TERI) of the modem status register indicates that RI level since the last read from the modem status register. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated.

is set to its active level by setting the RTS MCR bit and is set to its inactive (high) level either as a result of a master reset, during loop mode operations, or by clearing bit 1 (RTS) of the MCR. In the auto-RTS is set to its inactive level by the receiver threshold control logic.

in the FIFO mode, one of two types of DMA signalling can be selected through the FIFO control register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least one character in the receiver FIFO or receiver holding register, RXRDY holding register, RXRDY or the timeout has been reached, RXRDY characters in the FIFO or holding register, it goes inactive (high).

as a result of master reset.

one of two types of DMA signalling can be selected through FCR3. When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled.

allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer data during a write operation; the other input should be tied in its inactive state (i.e., WR2 tied low or WR1

tied high).

is active (low). When RXRDY has been active but there are no characters in the FIFO or

goes inactive (high). In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level

tied high).

NAME

RD1 RD2

RI 43 38 I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem

RTS 36 26 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS

RXRDY 32 21 O Receiver ready. Receiver direct memory access (DMA) signalling is available with RXRDY. When operating

SIN 11 55 I Serial data. SIN is the input from a connected communications device. SOUT 13 58 O Composite serial data output to a connected communication device. SOUT is set to the marking (high) level

TXRDY 27 13 O Transmitter ready. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO mode,

WR1 WR2

XIN XOUT

NO.FNNO.

2425910I

44 40 5-V supply voltage 22 8 Supply common 202146I Write inputs. When either input is active (low or high respectively) and while the ACE is selected, the CPU is

181912I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

DESCRIPTION

has transitioned from a low to a high

mode, RTS

goes active (low); when it has been active but there are no more

detailed description

autoflow control

Auto-flow control is composed of auto-CTS transmit FIFO can emit data (see Figure 1). With auto-RTS or the threshold has not been reached. When RTS unless the receive FIFO has empty space. Thus, overrun errors are eliminated when ACE1 and ACE2 are TLC16C750s with enabled autoflow control. If not, overrun errors occur if the transmit data rate exceeds the receive FIFO read latency.

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and auto-RTS. With auto-CTS, CTS must be active before the

, RTS becomes active when the receiver is empty

is connected to CTS, data transmission does not occur

TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997

autoflow control (continued)

ACE1 ACE2

Serial to

Parallel

RCV

FIFO

Flow

Control

D7–D0

Parallel

to Serial

XMT

FIFO

Flow

Control

SIN SOUT

RTS

SOUT SIN

CTS

RTS

Parallel

to Serial

XMT FIFO

Flow

Control

Serial to

Parallel

RCV FIFO

Flow

Control

Figure 1. Autoflow Control (auto-RTS and auto-CTS) Example

auto-RTS (see Figure 1)

Auto-RTS

data flow control originates in the receiver timing and control block (see functional block diagram) and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of 1, 4, 8, or 14 in 16-byte mode or 1, 16, 32, or 56 in 64-byte mode, RTS

is deasserted. The sending ACE may send an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it may not recognize the deassertion of RTS

until after it has begun sending the additional byte. RTS is automatically reasserted once the receiver FIFO is emptied by reading the receiver buffer register. The reassertion signals the sending ACE to continue transmitting data.

auto-CTS

(see Figure 1)

D7–D0

The transmitter circuitry checks CTS sends the next byte. To stop the transmitter from sending the following byte, CTS middle of the last stop bit that is currently being sent. The auto-CTS system. When flow control is enabled, the CTS device automatically controls its own transmitter. Without auto-CTS

before sending the next data byte. When CTS is active, the transmitter

must be released before the

function reduces interrupts to the host

state changes and does not trigger host interrupts because the

, the transmitter sends any data present in

the transmit FIFO and a receiver overrun error can result.

enabling auto-RTS

and auto-CTS

The auto-RTS and auto-CTS modes of operation are activated by setting bit 5 of the modem control register (MCR) to 1 (see Figure 2).

SOUT

CTS

NOTES: A. When CTS is low, the transmitter keeps sending serial data out.

B. When CTS

C. When CTS

Start Bits 0–7 Start Bits 0–7 Start Bits 0–7

goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but

it does not send the next byte.

goes from high to low, the transmitter begins sending data again.

Stop Stop Stop

Figure 2. CTS Functional Timing

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ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997

enabling auto-RTS and auto-CTS (continued)

The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes for the 16-byte mode and 1, 16, 32, or 56 bytes for 64-byte mode (see Figure 3).

TL16C750

SIN

RTS

(RD RBR)

NOTES: A. N = receiver FIFO trigger level

B. The two blocks in dashed lines cover the case where an additional byte is sent as described in auto-RTS

Start Byte N Start Byte N+1 Start Byte

Stop Stop Stop

N N+1

Figure 3. RTS Functional Timing, Receiver FIFO Trigger Level

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

(see Note 1) –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage range, V Input voltage range, V

Output voltage range, V Input clamp current, I

Output clamp current, I Operating free-air temperature range, T Operating free-air temperature range, T Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. This applies for external input and bidirectional buffers. VI > VCC does not apply to fail safe terminals.

2. This applies for external output and bidirectional buffers. VO > VCC does not apply to fail safe terminals.

: Standard –0.5 V to V

Fail safe –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

: Standard –0.5 V to V

Fail safe –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(VO < 0 or VO > VCC) (see Note 2) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(TL16C750I) –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

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TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997

recommended operating conditions

low voltage (3.3 V nominal)

MIN NOM MAX UNIT

Supply voltage, V Input voltage, V High-level input voltage, VIH (see Note 3) 0.7 V Low-level input voltage, VIL (see Note 3) 0.3 V Output voltage, VO (see Note 4) 0 V High-level output current, IOH (all outputs) 1.8 mA Low-level output current, IOL (all outputs) 3.2 mA Input capacitance, c Operating free-air temperature, T Junction temperature range, TJ (see Note 5) 0 25 115 °C Oscillator/clock speed 14 MHz NOTES: 3. Meets TTL levels, V

= 2 V and V

4. Applies for external output buffers

5. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is responsible for verifying junction temperature.

IHmin

= 0.8 V on nonhysteresis inputs

ILmax

3 3.3 3.6 V 0 V

0 25 70 °C

1 pF

V V V V

standard voltage (5 V nominal)

MIN NOM MAX UNIT

Supply voltage, V Input voltage, V High-level input voltage, V Low-level input voltage, V Output voltage, VO (see Note 4) 0 V High-level output current, IOH (all outputs) 4 mA Low-level output current, IOL (all outputs) 4 mA Input capacitance, c Operating free-air temperature, T Junction temperature range, TJ (see Note 5) 0 25 115 °C Oscillator/clock speed 16 MHz

NOTES: 4. Applies for external output buffers

5. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is responsible for verifying junction temperature.

4.75 5 5.25 V 0 V

0.7 V

0 25 70 °C

0.2 V

1 pF

V V V V

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TL16C750

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

low voltage (3.3 V nominal)

PARAMETER TEST CONDITIONS MIN MAX UNIT

High-level output voltage

Low-level output voltage

High-impedance 3-state output current (see Note 6) VI = VCC or GND ±10 µA

Low-level input current (see Note 7) VI = GND –1 µA

High-level input current (see Note 8) VI = V

†

For all outputs except XOUT

NOTES: 6. The 3-state or open-drain output must be in the high-impedance state.

7. Specifications only apply with pullup termination turned off.

8. Specifications only apply with pulldown termination turned off.

standard voltage (5 V nominal)

High-level output voltage

Low-level output voltage

High-impedance 3-state output current (see Note 6) VI = VCC or GND ±10 µA

Low-level input current (see Note 7) VI = GND –1 µA

High-level input current (see Note 8) VI = V

†

For all outputs except XOUT

NOTES: 6. The 3-state or open-drain output must be in the high-impedance state.

7. Specifications only apply with pullup termination turned off.

8. Specifications only apply with pulldown termination turned off.

†

PARAMETER TEST CONDITIONS MIN MAX UNIT

†

IOH = –1.8 mA VCC–0.55 V IOL = 3.2 mA 0.5 V

IOH = –4 mA VCC–0.8 V IOL = 4 mA 0.5 V

1 µA

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TL16C750 ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997

system timing requirements over recommended ranges of supply voltage and operating free-air temperature

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

Cycle time, read (tw7 + td8 + td9) RC 87 ns

Cycle time, write (tw6 + td5 + td6) WC 87 ns

Pulse duration, clock (XIN) high t

Pulse duration, clock (XIN) low t

Pulse duration, ADS low t

Pulse duration, write strobe t

Pulse duration, read strobe t

Pulse duration, MR t

Setup time, address valid before ADS↑ t

su1

Setup time, CS valid before ADS↑ t

su2

Setup time, data valid before WR1↓

su3

†

Setup time,

su4

Hold time, address low after ADS↑ t

Hold time, CS valid after ADS↑ t

Hold time, CS valid after WR1↑

†

Hold time, address valid after WR1↑

Hold time, data valid after WR1↑

Hold time, CS valid after RD1↑ or RD2↓

†

Hold time, address valid after RD1↑ or RD2↓ t

†

Delay time, CS valid before WR1↓ or WR2↑ t

Delay time, address valid before WR1↓ or WR2↑ t

†

Delay time, write cycle, WR1↑ or WR2↓ to ADS↓ t

†

Delay time, CS valid to RD1↓ or RD2↑ t

†

Delay time, address valid to RD1↓ or RD2↑ t

Delay time, read cycle, RD1↑ or RD2↓ to ADS↓ tRC 6 40 ns

Delay time, RD1↓ or RD2↑ to data valid t

d10

Delay time, RD1↑ or RD2↓ to floating data t

d11

†

Only applies when ADS is low

CTS

↑ before midpoint of stop bit

or WR2

XH XL

ADS

AS CS

↑

↓

AH CH

WCS

RCS

CSW

AW WC

CSR

RVD

4 f = 16 MHz maximum 25 ns 4 f = 16 MHz maximum 25 ns

5, 6 9 ns

5 40 ns 6 40 ns

1 µs 5, 6 8 ns 5, 6 8 ns

5 15 ns

16 10 ns 5, 6 0 ns 5, 6 0 ns

5 10 ns 5 10 ns 5 5 ns 6 10 ns 6 20 ns 5 7 ns 5 7 ns 5 40 ns 6 7 ns 6 7 ns

6 CL = 75 pF 45 ns 6 CL = 75 pF 20 ns

system switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 9)

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

dis(R)

NOTE 9: Charge and discharge times are determined by VOL, VOH, and external loading.

Disable time, RD1↓↑

or RD2

↑↓ to DDIS↑↓ t

RDD

6 CL = 75 pF 20 ns

baud generator switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

t t t t

w3 w4 d1 d2

Pulse duration, BAUDOUT low t Pulse duration, BAUDOUT high t Delay time, XIN↑ to BAUDOUT↑ t Delay time, XIN↑↓ to BAUDOUT↓ t

= 75 pF

BLD

BHD

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4 f = 16 MHz, CLK ÷ 2 50 ns

4 45 ns

ASYNCHRONOUS COMMUNICATIONS ELEMENT

PARAMETER

DELAY

XIN

PARAMETER

DELAY

XIN

WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL

SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997

commercial maximum switching characteristics, VCC = 4.75 V, TJ = 115°C

TL16C750

PLH

PHL

FROM TO

(INPUT) (OUTPUT)

Output rise time, XO 10.86 40.42 69.98 82.65

Output fall time, XO 5.47 20.90 36.34 42.95

INTRINSIC

(ns)

–0.92 0.571 7.65 27.66 47.66 56.23 –0.79 0.312 3.89 14.83 25.76 30.45

DELTA

(ns/pF)

DELAY (ns)

CL = 15 pF CL = 50 pF CL = 85 pF CL = 100 pF

commercial maximum switching characteristics, VCC = 3 V, TJ = 115°C

PLH

PHL

FROM TO

(INPUT) (OUTPUT)

Output rise time, XO 14.39 64.87 115.35 136.98

Output fall time, XO 5.06 26.53 48.01 57.21

INTRINSIC

(ns)

–4.69 1.017 10.57 46.16 81.75 97.00 –3.05 0.442 3.58 19.04 34.51 41.13

DELTA

(ns/pF)

DELAY (ns)

CL = 15 pF CL = 50 pF CL = 85 pF CL = 100 pF

receiver switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 10)

PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

d12

d13

d14

NOTE 10: In the FIFO mode, the read cycle (RC) = 425 ns (minimum) between reads of the receive FIFO and the status registers (interrupt

Delay time, RCLK to sample clock t Delay time, stop to set receiver error inter-

rupt or read RBR to LSI interrupt or stop to RXRDY

↓

Delay time, read RBR/LSR low to reset interrupt low

identification register or line status register).

SCD

SINT

RINT

7 10 ns

7, 8, 9,

10, 11

7, 8, 9,

10, 11

CL = 75 pF 120 ns

RCLK

cycle

transmitter switching characteristics over recommended ranges of supply voltage and operating free-air temperature

PARAMETER

Delay time, INTRPT to transmit start t

d15

Delay time, start to interrupt t

d16

Delay time, WR THR to reset interrupt t

d17

Delay time, initial write to interrupt (THRE) t

d18

Delay time, read IIR to reset interrupt (THRE) t

d19

Delay time, write to TXRDY inactive t

d20

Delay time, start to TXRDY active

d21

†

THRE = transmitter holding register empty, IIR = interrupt identification register.

†

ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT

IRS

STI HR

WXI

SXA

12 8 24

12 8 10 12 CL = 75 pF 50 ns

SI IR

12 16 34 12 CL = 75 pF 70 ns

13, 14 CL = 75 pF 75 ns 13, 14 CL = 75 pF 9

baudout

cycles

baudout

cycles

baudout

cycles

baudout

cycles

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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TEXAS INSTRUMENTS TL16C750 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual